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[deliverable/linux.git] / drivers / dma / ste_dma40.c
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8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
b7f080cf 9#include <linux/dma-mapping.h>
8d318a50
LW		 10#include <linux/kernel.h>
11#include <linux/slab.h>
f492b210 12#include <linux/export.h>
8d318a50
LW		 13#include <linux/dmaengine.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
c95905a6 17#include <linux/log2.h>
7fb3e75e
N		 18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
698e4732 20#include <linux/err.h>
1814a170 21#include <linux/of.h>
fa332de5 22#include <linux/of_dma.h>
f4b89764 23#include <linux/amba/bus.h>
15e4b78d 24#include <linux/regulator/consumer.h>
865fab60 25#include <linux/platform_data/dma-ste-dma40.h>
8d318a50 26
d2ebfb33 27#include "dmaengine.h"
8d318a50
LW		 28#include "ste_dma40_ll.h"
29
30#define D40_NAME "dma40"
31
32#define D40_PHY_CHAN -1
33
34/* For masking out/in 2 bit channel positions */
35#define D40_CHAN_POS(chan) (2 * (chan / 2))
36#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
37
38/* Maximum iterations taken before giving up suspending a channel */
39#define D40_SUSPEND_MAX_IT 500
40
7fb3e75e
N		 41/* Milliseconds */
42#define DMA40_AUTOSUSPEND_DELAY 100
43
508849ad
LW		 44/* Hardware requirement on LCLA alignment */
45#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 46
47/* Max number of links per event group */
48#define D40_LCLA_LINK_PER_EVENT_GRP 128
49#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
50
db72da92
LJ		 51/* Max number of logical channels per physical channel */
52#define D40_MAX_LOG_CHAN_PER_PHY 32
53
508849ad
LW		 54/* Attempts before giving up to trying to get pages that are aligned */
55#define MAX_LCLA_ALLOC_ATTEMPTS 256
56
57/* Bit markings for allocation map */
8a3b6e14
LJ		 58#define D40_ALLOC_FREE BIT(31)
59#define D40_ALLOC_PHY BIT(30)
8d318a50
LW		 60#define D40_ALLOC_LOG_FREE 0
61
a7dacb68
LJ		 62#define D40_MEMCPY_MAX_CHANS 8
63
664a57ec 64/* Reserved event lines for memcpy only. */
a2acaa21
LW		 65#define DB8500_DMA_MEMCPY_EV_0 51
66#define DB8500_DMA_MEMCPY_EV_1 56
67#define DB8500_DMA_MEMCPY_EV_2 57
68#define DB8500_DMA_MEMCPY_EV_3 58
69#define DB8500_DMA_MEMCPY_EV_4 59
70#define DB8500_DMA_MEMCPY_EV_5 60
71
72static int dma40_memcpy_channels[] = {
73 DB8500_DMA_MEMCPY_EV_0,
74 DB8500_DMA_MEMCPY_EV_1,
75 DB8500_DMA_MEMCPY_EV_2,
76 DB8500_DMA_MEMCPY_EV_3,
77 DB8500_DMA_MEMCPY_EV_4,
78 DB8500_DMA_MEMCPY_EV_5,
79};
664a57ec 80
29027a1e 81/* Default configuration for physcial memcpy */
b4a1ccdf 82static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
29027a1e 83 .mode = STEDMA40_MODE_PHYSICAL,
2c2b62d5 84 .dir = DMA_MEM_TO_MEM,
29027a1e 85
43f2e1a3 86 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 87 .src_info.psize = STEDMA40_PSIZE_PHY_1,
88 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
89
43f2e1a3 90 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 91 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
92 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
93};
94
95/* Default configuration for logical memcpy */
b4a1ccdf 96static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
29027a1e 97 .mode = STEDMA40_MODE_LOGICAL,
2c2b62d5 98 .dir = DMA_MEM_TO_MEM,
29027a1e 99
43f2e1a3 100 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 101 .src_info.psize = STEDMA40_PSIZE_LOG_1,
102 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
103
43f2e1a3 104 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 105 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
106 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
107};
108
8d318a50
LW		 109/**
110 * enum 40_command - The different commands and/or statuses.
111 *
112 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
113 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
114 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
115 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
116 */
117enum d40_command {
118 D40_DMA_STOP = 0,
119 D40_DMA_RUN = 1,
120 D40_DMA_SUSPEND_REQ = 2,
121 D40_DMA_SUSPENDED = 3
122};
123
1bdae6f4
N		 124/*
125 * enum d40_events - The different Event Enables for the event lines.
126 *
127 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
128 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
129 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
130 * @D40_ROUND_EVENTLINE: Status check for event line.
131 */
132
133enum d40_events {
134 D40_DEACTIVATE_EVENTLINE = 0,
135 D40_ACTIVATE_EVENTLINE = 1,
136 D40_SUSPEND_REQ_EVENTLINE = 2,
137 D40_ROUND_EVENTLINE = 3
138};
139
7fb3e75e
N		 140/*
141 * These are the registers that has to be saved and later restored
142 * when the DMA hw is powered off.
143 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
144 */
145static u32 d40_backup_regs[] = {
146 D40_DREG_LCPA,
147 D40_DREG_LCLA,
148 D40_DREG_PRMSE,
149 D40_DREG_PRMSO,
150 D40_DREG_PRMOE,
151 D40_DREG_PRMOO,
152};
153
154#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
155
3cb645dc
TL		 156/*
157 * since 9540 and 8540 has the same HW revision
158 * use v4a for 9540 or ealier
159 * use v4b for 8540 or later
160 * HW revision:
161 * DB8500ed has revision 0
162 * DB8500v1 has revision 2
163 * DB8500v2 has revision 3
164 * AP9540v1 has revision 4
165 * DB8540v1 has revision 4
166 * TODO: Check if all these registers have to be saved/restored on dma40 v4a
167 */
168static u32 d40_backup_regs_v4a[] = {
7fb3e75e
N		 169 D40_DREG_PSEG1,
170 D40_DREG_PSEG2,
171 D40_DREG_PSEG3,
172 D40_DREG_PSEG4,
173 D40_DREG_PCEG1,
174 D40_DREG_PCEG2,
175 D40_DREG_PCEG3,
176 D40_DREG_PCEG4,
177 D40_DREG_RSEG1,
178 D40_DREG_RSEG2,
179 D40_DREG_RSEG3,
180 D40_DREG_RSEG4,
181 D40_DREG_RCEG1,
182 D40_DREG_RCEG2,
183 D40_DREG_RCEG3,
184 D40_DREG_RCEG4,
185};
186
3cb645dc
TL		 187#define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
188
189static u32 d40_backup_regs_v4b[] = {
190 D40_DREG_CPSEG1,
191 D40_DREG_CPSEG2,
192 D40_DREG_CPSEG3,
193 D40_DREG_CPSEG4,
194 D40_DREG_CPSEG5,
195 D40_DREG_CPCEG1,
196 D40_DREG_CPCEG2,
197 D40_DREG_CPCEG3,
198 D40_DREG_CPCEG4,
199 D40_DREG_CPCEG5,
200 D40_DREG_CRSEG1,
201 D40_DREG_CRSEG2,
202 D40_DREG_CRSEG3,
203 D40_DREG_CRSEG4,
204 D40_DREG_CRSEG5,
205 D40_DREG_CRCEG1,
206 D40_DREG_CRCEG2,
207 D40_DREG_CRCEG3,
208 D40_DREG_CRCEG4,
209 D40_DREG_CRCEG5,
210};
211
212#define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
7fb3e75e
N		 213
214static u32 d40_backup_regs_chan[] = {
215 D40_CHAN_REG_SSCFG,
216 D40_CHAN_REG_SSELT,
217 D40_CHAN_REG_SSPTR,
218 D40_CHAN_REG_SSLNK,
219 D40_CHAN_REG_SDCFG,
220 D40_CHAN_REG_SDELT,
221 D40_CHAN_REG_SDPTR,
222 D40_CHAN_REG_SDLNK,
223};
224
84b3da14
LJ		 225#define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
226 BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
227
3cb645dc
TL		 228/**
229 * struct d40_interrupt_lookup - lookup table for interrupt handler
230 *
231 * @src: Interrupt mask register.
232 * @clr: Interrupt clear register.
233 * @is_error: true if this is an error interrupt.
234 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
235 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
236 */
237struct d40_interrupt_lookup {
238 u32 src;
239 u32 clr;
240 bool is_error;
241 int offset;
242};
243
244
245static struct d40_interrupt_lookup il_v4a[] = {
246 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
247 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
248 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
249 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
250 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
251 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
252 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
253 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
254 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
255 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
256};
257
258static struct d40_interrupt_lookup il_v4b[] = {
259 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
260 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
261 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
262 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
263 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
264 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
265 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
266 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
267 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
268 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
269 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
270 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
271};
272
273/**
274 * struct d40_reg_val - simple lookup struct
275 *
276 * @reg: The register.
277 * @val: The value that belongs to the register in reg.
278 */
279struct d40_reg_val {
280 unsigned int reg;
281 unsigned int val;
282};
283
284static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
285 /* Clock every part of the DMA block from start */
286 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
287
288 /* Interrupts on all logical channels */
289 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
290 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
291 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
292 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
293 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
294 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
295 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
296 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
297 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
298 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
299 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
300 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
301};
302static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
303 /* Clock every part of the DMA block from start */
304 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
305
306 /* Interrupts on all logical channels */
307 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
308 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
309 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
310 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
311 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
312 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
313 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
314 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
315 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
316 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
317 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
318 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
319 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
320 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
321 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
322};
323
8d318a50
LW		 324/**
325 * struct d40_lli_pool - Structure for keeping LLIs in memory
326 *
327 * @base: Pointer to memory area when the pre_alloc_lli's are not large
328 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
329 * pre_alloc_lli is used.
b00f938c 330 * @dma_addr: DMA address, if mapped
8d318a50
LW		 331 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
332 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
333 * one buffer to one buffer.
334 */
335struct d40_lli_pool {
336 void *base;
508849ad 337 int size;
b00f938c 338 dma_addr_t dma_addr;
8d318a50 339 /* Space for dst and src, plus an extra for padding */
508849ad 340 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 341};
342
343/**
344 * struct d40_desc - A descriptor is one DMA job.
345 *
346 * @lli_phy: LLI settings for physical channel. Both src and dst=
347 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
348 * lli_len equals one.
349 * @lli_log: Same as above but for logical channels.
350 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 351 * @lli_len: Number of llis of current descriptor.
25985edc 352 * @lli_current: Number of transferred llis.
698e4732 353 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 354 * @txd: DMA engine struct. Used for among other things for communication
355 * during a transfer.
356 * @node: List entry.
8d318a50 357 * @is_in_client_list: true if the client owns this descriptor.
7fb3e75e 358 * @cyclic: true if this is a cyclic job
8d318a50
LW		 359 *
360 * This descriptor is used for both logical and physical transfers.
361 */
8d318a50
LW		 362struct d40_desc {
363 /* LLI physical */
364 struct d40_phy_lli_bidir lli_phy;
365 /* LLI logical */
366 struct d40_log_lli_bidir lli_log;
367
368 struct d40_lli_pool lli_pool;
941b77a3 369 int lli_len;
698e4732
JA		 370 int lli_current;
371 int lcla_alloc;
8d318a50
LW		 372
373 struct dma_async_tx_descriptor txd;
374 struct list_head node;
375
8d318a50 376 bool is_in_client_list;
0c842b55 377 bool cyclic;
8d318a50
LW		 378};
379
380/**
381 * struct d40_lcla_pool - LCLA pool settings and data.
382 *
508849ad
LW		 383 * @base: The virtual address of LCLA. 18 bit aligned.
384 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
385 * This pointer is only there for clean-up on error.
386 * @pages: The number of pages needed for all physical channels.
387 * Only used later for clean-up on error
8d318a50 388 * @lock: Lock to protect the content in this struct.
698e4732 389 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 390 */
391struct d40_lcla_pool {
392 void *base;
026cbc42 393 dma_addr_t dma_addr;
508849ad
LW		 394 void *base_unaligned;
395 int pages;
8d318a50 396 spinlock_t lock;
698e4732 397 struct d40_desc **alloc_map;
8d318a50
LW		 398};
399
400/**
401 * struct d40_phy_res - struct for handling eventlines mapped to physical
402 * channels.
403 *
404 * @lock: A lock protection this entity.
7fb3e75e 405 * @reserved: True if used by secure world or otherwise.
8d318a50
LW		 406 * @num: The physical channel number of this entity.
407 * @allocated_src: Bit mapped to show which src event line's are mapped to
408 * this physical channel. Can also be free or physically allocated.
409 * @allocated_dst: Same as for src but is dst.
410 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 411 * event line number.
7407048b 412 * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
8d318a50
LW		 413 */
414struct d40_phy_res {
415 spinlock_t lock;
7fb3e75e 416 bool reserved;
8d318a50
LW		 417 int num;
418 u32 allocated_src;
419 u32 allocated_dst;
7407048b 420 bool use_soft_lli;
8d318a50
LW		 421};
422
423struct d40_base;
424
425/**
426 * struct d40_chan - Struct that describes a channel.
427 *
428 * @lock: A spinlock to protect this struct.
429 * @log_num: The logical number, if any of this channel.
8d318a50
LW		 430 * @pending_tx: The number of pending transfers. Used between interrupt handler
431 * and tasklet.
432 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 433 * @phy_chan: Pointer to physical channel which this instance runs on. If this
434 * point is NULL, then the channel is not allocated.
8d318a50
LW		 435 * @chan: DMA engine handle.
436 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
437 * transfer and call client callback.
438 * @client: Cliented owned descriptor list.
da063d26 439 * @pending_queue: Submitted jobs, to be issued by issue_pending()
8d318a50 440 * @active: Active descriptor.
4226dd86 441 * @done: Completed jobs
8d318a50 442 * @queue: Queued jobs.
82babbb3 443 * @prepare_queue: Prepared jobs.
8d318a50 444 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 445 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 446 * @base: Pointer to the device instance struct.
447 * @src_def_cfg: Default cfg register setting for src.
448 * @dst_def_cfg: Default cfg register setting for dst.
449 * @log_def: Default logical channel settings.
8d318a50 450 * @lcpa: Pointer to dst and src lcpa settings.
ae752bf4 451 * @runtime_addr: runtime configured address.
452 * @runtime_direction: runtime configured direction.
8d318a50
LW		 453 *
454 * This struct can either "be" a logical or a physical channel.
455 */
456struct d40_chan {
457 spinlock_t lock;
458 int log_num;
8d318a50
LW		 459 int pending_tx;
460 bool busy;
461 struct d40_phy_res *phy_chan;
462 struct dma_chan chan;
463 struct tasklet_struct tasklet;
464 struct list_head client;
a8f3067b 465 struct list_head pending_queue;
8d318a50 466 struct list_head active;
4226dd86 467 struct list_head done;
8d318a50 468 struct list_head queue;
82babbb3 469 struct list_head prepare_queue;
8d318a50 470 struct stedma40_chan_cfg dma_cfg;
ce2ca125 471 bool configured;
8d318a50
LW		 472 struct d40_base *base;
473 /* Default register configurations */
474 u32 src_def_cfg;
475 u32 dst_def_cfg;
476 struct d40_def_lcsp log_def;
8d318a50 477 struct d40_log_lli_full *lcpa;
95e1400f
LW		 478 /* Runtime reconfiguration */
479 dma_addr_t runtime_addr;
db8196df 480 enum dma_transfer_direction runtime_direction;
8d318a50
LW		 481};
482
3cb645dc
TL		 483/**
484 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
485 * controller
486 *
487 * @backup: the pointer to the registers address array for backup
488 * @backup_size: the size of the registers address array for backup
489 * @realtime_en: the realtime enable register
490 * @realtime_clear: the realtime clear register
491 * @high_prio_en: the high priority enable register
492 * @high_prio_clear: the high priority clear register
493 * @interrupt_en: the interrupt enable register
494 * @interrupt_clear: the interrupt clear register
495 * @il: the pointer to struct d40_interrupt_lookup
496 * @il_size: the size of d40_interrupt_lookup array
497 * @init_reg: the pointer to the struct d40_reg_val
498 * @init_reg_size: the size of d40_reg_val array
499 */
500struct d40_gen_dmac {
501 u32 *backup;
502 u32 backup_size;
503 u32 realtime_en;
504 u32 realtime_clear;
505 u32 high_prio_en;
506 u32 high_prio_clear;
507 u32 interrupt_en;
508 u32 interrupt_clear;
509 struct d40_interrupt_lookup *il;
510 u32 il_size;
511 struct d40_reg_val *init_reg;
512 u32 init_reg_size;
513};
514
8d318a50
LW		 515/**
516 * struct d40_base - The big global struct, one for each probe'd instance.
517 *
518 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
519 * @execmd_lock: Lock for execute command usage since several channels share
520 * the same physical register.
521 * @dev: The device structure.
522 * @virtbase: The virtual base address of the DMA's register.
f4185592 523 * @rev: silicon revision detected.
8d318a50
LW		 524 * @clk: Pointer to the DMA clock structure.
525 * @phy_start: Physical memory start of the DMA registers.
526 * @phy_size: Size of the DMA register map.
527 * @irq: The IRQ number.
a7dacb68
LJ		 528 * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
529 * transfers).
8d318a50
LW		 530 * @num_phy_chans: The number of physical channels. Read from HW. This
531 * is the number of available channels for this driver, not counting "Secure
532 * mode" allocated physical channels.
533 * @num_log_chans: The number of logical channels. Calculated from
534 * num_phy_chans.
535 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
536 * @dma_slave: dma_device channels that can do only do slave transfers.
537 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
7fb3e75e 538 * @phy_chans: Room for all possible physical channels in system.
8d318a50
LW		 539 * @log_chans: Room for all possible logical channels in system.
540 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
541 * to log_chans entries.
542 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
543 * to phy_chans entries.
544 * @plat_data: Pointer to provided platform_data which is the driver
545 * configuration.
28c7a19d 546 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
8d318a50
LW		 547 * @phy_res: Vector containing all physical channels.
548 * @lcla_pool: lcla pool settings and data.
549 * @lcpa_base: The virtual mapped address of LCPA.
550 * @phy_lcpa: The physical address of the LCPA.
551 * @lcpa_size: The size of the LCPA area.
c675b1b4 552 * @desc_slab: cache for descriptors.
7fb3e75e
N		 553 * @reg_val_backup: Here the values of some hardware registers are stored
554 * before the DMA is powered off. They are restored when the power is back on.
3cb645dc
TL		 555 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
556 * later
7fb3e75e
N		 557 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
558 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
3cb645dc
TL		 559 * @gen_dmac: the struct for generic registers values to represent u8500/8540
560 * DMA controller
8d318a50
LW		 561 */
562struct d40_base {
563 spinlock_t interrupt_lock;
564 spinlock_t execmd_lock;
565 struct device *dev;
566 void __iomem *virtbase;
f4185592 567 u8 rev:4;
8d318a50
LW		 568 struct clk *clk;
569 phys_addr_t phy_start;
570 resource_size_t phy_size;
571 int irq;
a7dacb68 572 int num_memcpy_chans;
8d318a50
LW		 573 int num_phy_chans;
574 int num_log_chans;
b96710e5 575 struct device_dma_parameters dma_parms;
8d318a50
LW		 576 struct dma_device dma_both;
577 struct dma_device dma_slave;
578 struct dma_device dma_memcpy;
579 struct d40_chan *phy_chans;
580 struct d40_chan *log_chans;
581 struct d40_chan **lookup_log_chans;
582 struct d40_chan **lookup_phy_chans;
583 struct stedma40_platform_data *plat_data;
28c7a19d 584 struct regulator *lcpa_regulator;
8d318a50
LW		 585 /* Physical half channels */
586 struct d40_phy_res *phy_res;
587 struct d40_lcla_pool lcla_pool;
588 void *lcpa_base;
589 dma_addr_t phy_lcpa;
590 resource_size_t lcpa_size;
c675b1b4 591 struct kmem_cache *desc_slab;
7fb3e75e 592 u32 reg_val_backup[BACKUP_REGS_SZ];
84b3da14 593 u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
7fb3e75e
N		 594 u32 *reg_val_backup_chan;
595 u16 gcc_pwr_off_mask;
3cb645dc 596 struct d40_gen_dmac gen_dmac;
8d318a50
LW		 597};
598
262d2915
RV		 599static struct device *chan2dev(struct d40_chan *d40c)
600{
601 return &d40c->chan.dev->device;
602}
603
724a8577
RV		 604static bool chan_is_physical(struct d40_chan *chan)
605{
606 return chan->log_num == D40_PHY_CHAN;
607}
608
609static bool chan_is_logical(struct d40_chan *chan)
610{
611 return !chan_is_physical(chan);
612}
613
8ca84687
RV		 614static void __iomem *chan_base(struct d40_chan *chan)
615{
616 return chan->base->virtbase + D40_DREG_PCBASE +
617 chan->phy_chan->num * D40_DREG_PCDELTA;
618}
619
6db5a8ba
RV		 620#define d40_err(dev, format, arg...) \
621 dev_err(dev, "[%s] " format, __func__, ## arg)
622
623#define chan_err(d40c, format, arg...) \
624 d40_err(chan2dev(d40c), format, ## arg)
625
b00f938c 626static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 627 int lli_len)
8d318a50 628{
dbd88788 629 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 630 u32 align;
631 void *base;
632
633 if (is_log)
634 align = sizeof(struct d40_log_lli);
635 else
636 align = sizeof(struct d40_phy_lli);
637
638 if (lli_len == 1) {
639 base = d40d->lli_pool.pre_alloc_lli;
640 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
641 d40d->lli_pool.base = NULL;
642 } else {
594ece4d 643 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 644
645 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
646 d40d->lli_pool.base = base;
647
648 if (d40d->lli_pool.base == NULL)
649 return -ENOMEM;
650 }
651
652 if (is_log) {
d924abad 653 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 654 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 655
656 d40d->lli_pool.dma_addr = 0;
8d318a50 657 } else {
d924abad 658 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 659 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 660
661 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
662 d40d->lli_phy.src,
663 d40d->lli_pool.size,
664 DMA_TO_DEVICE);
665
666 if (dma_mapping_error(d40c->base->dev,
667 d40d->lli_pool.dma_addr)) {
668 kfree(d40d->lli_pool.base);
669 d40d->lli_pool.base = NULL;
670 d40d->lli_pool.dma_addr = 0;
671 return -ENOMEM;
672 }
8d318a50
LW		 673 }
674
675 return 0;
676}
677
b00f938c 678static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 679{
b00f938c
RV		 680 if (d40d->lli_pool.dma_addr)
681 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
682 d40d->lli_pool.size, DMA_TO_DEVICE);
683
8d318a50
LW		 684 kfree(d40d->lli_pool.base);
685 d40d->lli_pool.base = NULL;
686 d40d->lli_pool.size = 0;
687 d40d->lli_log.src = NULL;
688 d40d->lli_log.dst = NULL;
689 d40d->lli_phy.src = NULL;
690 d40d->lli_phy.dst = NULL;
8d318a50
LW		 691}
692
698e4732
JA		 693static int d40_lcla_alloc_one(struct d40_chan *d40c,
694 struct d40_desc *d40d)
695{
696 unsigned long flags;
697 int i;
698 int ret = -EINVAL;
698e4732
JA		 699
700 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
701
698e4732
JA		 702 /*
703 * Allocate both src and dst at the same time, therefore the half
704 * start on 1 since 0 can't be used since zero is used as end marker.
705 */
706 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 707 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
708
709 if (!d40c->base->lcla_pool.alloc_map[idx]) {
710 d40c->base->lcla_pool.alloc_map[idx] = d40d;
698e4732
JA		 711 d40d->lcla_alloc++;
712 ret = i;
713 break;
714 }
715 }
716
717 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
718
719 return ret;
720}
721
722static int d40_lcla_free_all(struct d40_chan *d40c,
723 struct d40_desc *d40d)
724{
725 unsigned long flags;
726 int i;
727 int ret = -EINVAL;
728
724a8577 729 if (chan_is_physical(d40c))
698e4732
JA		 730 return 0;
731
732 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
733
734 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 735 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
736
737 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
738 d40c->base->lcla_pool.alloc_map[idx] = NULL;
698e4732
JA		 739 d40d->lcla_alloc--;
740 if (d40d->lcla_alloc == 0) {
741 ret = 0;
742 break;
743 }
744 }
745 }
746
747 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
748
749 return ret;
750
751}
752
8d318a50
LW		 753static void d40_desc_remove(struct d40_desc *d40d)
754{
755 list_del(&d40d->node);
756}
757
758static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
759{
a2c15fa4 760 struct d40_desc *desc = NULL;
8d318a50
LW		 761
762 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 763 struct d40_desc *d;
764 struct d40_desc *_d;
765
7fb3e75e 766 list_for_each_entry_safe(d, _d, &d40c->client, node) {
8d318a50 767 if (async_tx_test_ack(&d->txd)) {
8d318a50 768 d40_desc_remove(d);
a2c15fa4
RV		 769 desc = d;
770 memset(desc, 0, sizeof(*desc));
c675b1b4 771 break;
8d318a50 772 }
7fb3e75e 773 }
8d318a50 774 }
a2c15fa4
RV		 775
776 if (!desc)
777 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
778
779 if (desc)
780 INIT_LIST_HEAD(&desc->node);
781
782 return desc;
8d318a50
LW		 783}
784
785static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
786{
698e4732 787
b00f938c 788 d40_pool_lli_free(d40c, d40d);
698e4732 789 d40_lcla_free_all(d40c, d40d);
c675b1b4 790 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 791}
792
793static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
794{
795 list_add_tail(&desc->node, &d40c->active);
796}
797
1c4b0927
RV		 798static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
799{
800 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
801 struct d40_phy_lli *lli_src = desc->lli_phy.src;
802 void __iomem *base = chan_base(chan);
803
804 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
805 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
806 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
807 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
808
809 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
810 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
811 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
812 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
813}
814
4226dd86
FB		 815static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
816{
817 list_add_tail(&desc->node, &d40c->done);
818}
819
e65889c7 820static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 821{
e65889c7
RV		 822 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
823 struct d40_log_lli_bidir *lli = &desc->lli_log;
824 int lli_current = desc->lli_current;
825 int lli_len = desc->lli_len;
0c842b55 826 bool cyclic = desc->cyclic;
e65889c7 827 int curr_lcla = -EINVAL;
0c842b55 828 int first_lcla = 0;
28c7a19d 829 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
0c842b55 830 bool linkback;
e65889c7 831
0c842b55
RV		 832 /*
833 * We may have partially running cyclic transfers, in case we did't get
834 * enough LCLA entries.
835 */
836 linkback = cyclic && lli_current == 0;
837
838 /*
839 * For linkback, we need one LCLA even with only one link, because we
840 * can't link back to the one in LCPA space
841 */
842 if (linkback || (lli_len - lli_current > 1)) {
7407048b
FB		 843 /*
844 * If the channel is expected to use only soft_lli don't
845 * allocate a lcla. This is to avoid a HW issue that exists
846 * in some controller during a peripheral to memory transfer
847 * that uses linked lists.
848 */
849 if (!(chan->phy_chan->use_soft_lli &&
2c2b62d5 850 chan->dma_cfg.dir == DMA_DEV_TO_MEM))
7407048b
FB		 851 curr_lcla = d40_lcla_alloc_one(chan, desc);
852
0c842b55
RV		 853 first_lcla = curr_lcla;
854 }
855
856 /*
857 * For linkback, we normally load the LCPA in the loop since we need to
858 * link it to the second LCLA and not the first. However, if we
859 * couldn't even get a first LCLA, then we have to run in LCPA and
860 * reload manually.
861 */
862 if (!linkback || curr_lcla == -EINVAL) {
863 unsigned int flags = 0;
e65889c7 864
0c842b55
RV		 865 if (curr_lcla == -EINVAL)
866 flags |= LLI_TERM_INT;
e65889c7 867
0c842b55
RV		 868 d40_log_lli_lcpa_write(chan->lcpa,
869 &lli->dst[lli_current],
870 &lli->src[lli_current],
871 curr_lcla,
872 flags);
873 lli_current++;
874 }
6045f0bb
RV		 875
876 if (curr_lcla < 0)
877 goto out;
878
e65889c7
RV		 879 for (; lli_current < lli_len; lli_current++) {
880 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
881 8 * curr_lcla * 2;
882 struct d40_log_lli *lcla = pool->base + lcla_offset;
0c842b55 883 unsigned int flags = 0;
e65889c7
RV		 884 int next_lcla;
885
886 if (lli_current + 1 < lli_len)
887 next_lcla = d40_lcla_alloc_one(chan, desc);
888 else
0c842b55
RV		 889 next_lcla = linkback ? first_lcla : -EINVAL;
890
891 if (cyclic || next_lcla == -EINVAL)
892 flags |= LLI_TERM_INT;
e65889c7 893
0c842b55
RV		 894 if (linkback && curr_lcla == first_lcla) {
895 /* First link goes in both LCPA and LCLA */
896 d40_log_lli_lcpa_write(chan->lcpa,
897 &lli->dst[lli_current],
898 &lli->src[lli_current],
899 next_lcla, flags);
900 }
901
902 /*
903 * One unused LCLA in the cyclic case if the very first
904 * next_lcla fails...
905 */
e65889c7
RV		 906 d40_log_lli_lcla_write(lcla,
907 &lli->dst[lli_current],
908 &lli->src[lli_current],
0c842b55 909 next_lcla, flags);
e65889c7 910
28c7a19d
N		 911 /*
912 * Cache maintenance is not needed if lcla is
913 * mapped in esram
914 */
915 if (!use_esram_lcla) {
916 dma_sync_single_range_for_device(chan->base->dev,
917 pool->dma_addr, lcla_offset,
918 2 * sizeof(struct d40_log_lli),
919 DMA_TO_DEVICE);
920 }
e65889c7
RV		 921 curr_lcla = next_lcla;
922
0c842b55 923 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
e65889c7
RV		 924 lli_current++;
925 break;
926 }
927 }
928
6045f0bb 929out:
e65889c7
RV		 930 desc->lli_current = lli_current;
931}
698e4732 932
e65889c7
RV		 933static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
934{
724a8577 935 if (chan_is_physical(d40c)) {
1c4b0927 936 d40_phy_lli_load(d40c, d40d);
698e4732 937 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 938 } else
939 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 940}
941
8d318a50
LW		 942static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
943{
944 struct d40_desc *d;
945
946 if (list_empty(&d40c->active))
947 return NULL;
948
949 d = list_first_entry(&d40c->active,
950 struct d40_desc,
951 node);
952 return d;
953}
954
7404368c 955/* remove desc from current queue and add it to the pending_queue */
8d318a50
LW		 956static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
957{
7404368c
PF		 958 d40_desc_remove(desc);
959 desc->is_in_client_list = false;
a8f3067b
PF		 960 list_add_tail(&desc->node, &d40c->pending_queue);
961}
962
963static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
964{
965 struct d40_desc *d;
966
967 if (list_empty(&d40c->pending_queue))
968 return NULL;
969
970 d = list_first_entry(&d40c->pending_queue,
971 struct d40_desc,
972 node);
973 return d;
8d318a50
LW		 974}
975
976static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
977{
978 struct d40_desc *d;
979
980 if (list_empty(&d40c->queue))
981 return NULL;
982
983 d = list_first_entry(&d40c->queue,
984 struct d40_desc,
985 node);
986 return d;
987}
988
4226dd86
FB		 989static struct d40_desc *d40_first_done(struct d40_chan *d40c)
990{
991 if (list_empty(&d40c->done))
992 return NULL;
993
994 return list_first_entry(&d40c->done, struct d40_desc, node);
995}
996
d49278e3
PF		 997static int d40_psize_2_burst_size(bool is_log, int psize)
998{
999 if (is_log) {
1000 if (psize == STEDMA40_PSIZE_LOG_1)
1001 return 1;
1002 } else {
1003 if (psize == STEDMA40_PSIZE_PHY_1)
1004 return 1;
1005 }
1006
1007 return 2 << psize;
1008}
1009
1010/*
1011 * The dma only supports transmitting packages up to
43f2e1a3
LJ		 1012 * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
1013 *
1014 * Calculate the total number of dma elements required to send the entire sg list.
d49278e3
PF		 1015 */
1016static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
1017{
1018 int dmalen;
1019 u32 max_w = max(data_width1, data_width2);
1020 u32 min_w = min(data_width1, data_width2);
43f2e1a3 1021 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
d49278e3
PF		 1022
1023 if (seg_max > STEDMA40_MAX_SEG_SIZE)
43f2e1a3 1024 seg_max -= max_w;
d49278e3 1025
43f2e1a3 1026 if (!IS_ALIGNED(size, max_w))
d49278e3
PF		 1027 return -EINVAL;
1028
1029 if (size <= seg_max)
1030 dmalen = 1;
1031 else {
1032 dmalen = size / seg_max;
1033 if (dmalen * seg_max < size)
1034 dmalen++;
1035 }
1036 return dmalen;
1037}
1038
1039static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1040 u32 data_width1, u32 data_width2)
1041{
1042 struct scatterlist *sg;
1043 int i;
1044 int len = 0;
1045 int ret;
1046
1047 for_each_sg(sgl, sg, sg_len, i) {
1048 ret = d40_size_2_dmalen(sg_dma_len(sg),
1049 data_width1, data_width2);
1050 if (ret < 0)
1051 return ret;
1052 len += ret;
1053 }
1054 return len;
1055}
8d318a50 1056
1bdae6f4
N		 1057static int __d40_execute_command_phy(struct d40_chan *d40c,
1058 enum d40_command command)
8d318a50 1059{
767a9675
JA		 1060 u32 status;
1061 int i;
8d318a50
LW		 1062 void __iomem *active_reg;
1063 int ret = 0;
1064 unsigned long flags;
1d392a7b 1065 u32 wmask;
8d318a50 1066
1bdae6f4
N		 1067 if (command == D40_DMA_STOP) {
1068 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1069 if (ret)
1070 return ret;
1071 }
1072
8d318a50
LW		 1073 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1074
1075 if (d40c->phy_chan->num % 2 == 0)
1076 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1077 else
1078 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1079
1080 if (command == D40_DMA_SUSPEND_REQ) {
1081 status = (readl(active_reg) &
1082 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1083 D40_CHAN_POS(d40c->phy_chan->num);
1084
1085 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1086 goto done;
1087 }
1088
1d392a7b
JA		 1089 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1090 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1091 active_reg);
8d318a50
LW		 1092
1093 if (command == D40_DMA_SUSPEND_REQ) {
1094
1095 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1096 status = (readl(active_reg) &
1097 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1098 D40_CHAN_POS(d40c->phy_chan->num);
1099
1100 cpu_relax();
1101 /*
1102 * Reduce the number of bus accesses while
1103 * waiting for the DMA to suspend.
1104 */
1105 udelay(3);
1106
1107 if (status == D40_DMA_STOP ||
1108 status == D40_DMA_SUSPENDED)
1109 break;
1110 }
1111
1112 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 1113 chan_err(d40c,
1114 "unable to suspend the chl %d (log: %d) status %x\n",
1115 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 1116 status);
1117 dump_stack();
1118 ret = -EBUSY;
1119 }
1120
1121 }
1122done:
1123 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1124 return ret;
1125}
1126
1127static void d40_term_all(struct d40_chan *d40c)
1128{
1129 struct d40_desc *d40d;
7404368c 1130 struct d40_desc *_d;
8d318a50 1131
4226dd86
FB		 1132 /* Release completed descriptors */
1133 while ((d40d = d40_first_done(d40c))) {
1134 d40_desc_remove(d40d);
1135 d40_desc_free(d40c, d40d);
1136 }
1137
8d318a50
LW		 1138 /* Release active descriptors */
1139 while ((d40d = d40_first_active_get(d40c))) {
1140 d40_desc_remove(d40d);
8d318a50
LW		 1141 d40_desc_free(d40c, d40d);
1142 }
1143
1144 /* Release queued descriptors waiting for transfer */
1145 while ((d40d = d40_first_queued(d40c))) {
1146 d40_desc_remove(d40d);
8d318a50
LW		 1147 d40_desc_free(d40c, d40d);
1148 }
1149
a8f3067b
PF		 1150 /* Release pending descriptors */
1151 while ((d40d = d40_first_pending(d40c))) {
1152 d40_desc_remove(d40d);
1153 d40_desc_free(d40c, d40d);
1154 }
8d318a50 1155
7404368c
PF		 1156 /* Release client owned descriptors */
1157 if (!list_empty(&d40c->client))
1158 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1159 d40_desc_remove(d40d);
1160 d40_desc_free(d40c, d40d);
1161 }
1162
82babbb3
PF		 1163 /* Release descriptors in prepare queue */
1164 if (!list_empty(&d40c->prepare_queue))
1165 list_for_each_entry_safe(d40d, _d,
1166 &d40c->prepare_queue, node) {
1167 d40_desc_remove(d40d);
1168 d40_desc_free(d40c, d40d);
1169 }
7404368c 1170
8d318a50 1171 d40c->pending_tx = 0;
8d318a50
LW		 1172}
1173
1bdae6f4
N		 1174static void __d40_config_set_event(struct d40_chan *d40c,
1175 enum d40_events event_type, u32 event,
1176 int reg)
262d2915 1177{
8ca84687 1178 void __iomem *addr = chan_base(d40c) + reg;
262d2915 1179 int tries;
1bdae6f4
N		 1180 u32 status;
1181
1182 switch (event_type) {
1183
1184 case D40_DEACTIVATE_EVENTLINE:
262d2915 1185
262d2915
RV		 1186 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1187 | ~D40_EVENTLINE_MASK(event), addr);
1bdae6f4
N		 1188 break;
1189
1190 case D40_SUSPEND_REQ_EVENTLINE:
1191 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1192 D40_EVENTLINE_POS(event);
1193
1194 if (status == D40_DEACTIVATE_EVENTLINE ||
1195 status == D40_SUSPEND_REQ_EVENTLINE)
1196 break;
262d2915 1197
1bdae6f4
N		 1198 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1199 | ~D40_EVENTLINE_MASK(event), addr);
1200
1201 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1202
1203 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1204 D40_EVENTLINE_POS(event);
1205
1206 cpu_relax();
1207 /*
1208 * Reduce the number of bus accesses while
1209 * waiting for the DMA to suspend.
1210 */
1211 udelay(3);
1212
1213 if (status == D40_DEACTIVATE_EVENTLINE)
1214 break;
1215 }
1216
1217 if (tries == D40_SUSPEND_MAX_IT) {
1218 chan_err(d40c,
1219 "unable to stop the event_line chl %d (log: %d)"
1220 "status %x\n", d40c->phy_chan->num,
1221 d40c->log_num, status);
1222 }
1223 break;
1224
1225 case D40_ACTIVATE_EVENTLINE:
262d2915
RV		 1226 /*
1227 * The hardware sometimes doesn't register the enable when src and dst
1228 * event lines are active on the same logical channel. Retry to ensure
1229 * it does. Usually only one retry is sufficient.
1230 */
1bdae6f4
N		 1231 tries = 100;
1232 while (--tries) {
1233 writel((D40_ACTIVATE_EVENTLINE <<
1234 D40_EVENTLINE_POS(event)) |
1235 ~D40_EVENTLINE_MASK(event), addr);
262d2915 1236
1bdae6f4
N		 1237 if (readl(addr) & D40_EVENTLINE_MASK(event))
1238 break;
1239 }
262d2915 1240
1bdae6f4
N		 1241 if (tries != 99)
1242 dev_dbg(chan2dev(d40c),
1243 "[%s] workaround enable S%cLNK (%d tries)\n",
1244 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1245 100 - tries);
262d2915 1246
1bdae6f4
N		 1247 WARN_ON(!tries);
1248 break;
262d2915 1249
1bdae6f4
N		 1250 case D40_ROUND_EVENTLINE:
1251 BUG();
1252 break;
8d318a50 1253
1bdae6f4
N		 1254 }
1255}
8d318a50 1256
1bdae6f4
N		 1257static void d40_config_set_event(struct d40_chan *d40c,
1258 enum d40_events event_type)
1259{
26955c07
LJ		 1260 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1261
8d318a50 1262 /* Enable event line connected to device (or memcpy) */
2c2b62d5
LJ		 1263 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1264 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1bdae6f4 1265 __d40_config_set_event(d40c, event_type, event,
262d2915 1266 D40_CHAN_REG_SSLNK);
8d318a50 1267
2c2b62d5 1268 if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
1bdae6f4 1269 __d40_config_set_event(d40c, event_type, event,
262d2915 1270 D40_CHAN_REG_SDLNK);
8d318a50
LW		 1271}
1272
a5ebca47 1273static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 1274{
8ca84687 1275 void __iomem *chanbase = chan_base(d40c);
be8cb7df 1276 u32 val;
8d318a50 1277
8ca84687
RV		 1278 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1279 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 1280
a5ebca47 1281 return val;
8d318a50
LW		 1282}
1283
1bdae6f4
N		 1284static int
1285__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1286{
1287 unsigned long flags;
1288 int ret = 0;
1289 u32 active_status;
1290 void __iomem *active_reg;
1291
1292 if (d40c->phy_chan->num % 2 == 0)
1293 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1294 else
1295 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1296
1297
1298 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1299
1300 switch (command) {
1301 case D40_DMA_STOP:
1302 case D40_DMA_SUSPEND_REQ:
1303
1304 active_status = (readl(active_reg) &
1305 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1306 D40_CHAN_POS(d40c->phy_chan->num);
1307
1308 if (active_status == D40_DMA_RUN)
1309 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1310 else
1311 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1312
1313 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1314 ret = __d40_execute_command_phy(d40c, command);
1315
1316 break;
1317
1318 case D40_DMA_RUN:
1319
1320 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1321 ret = __d40_execute_command_phy(d40c, command);
1322 break;
1323
1324 case D40_DMA_SUSPENDED:
1325 BUG();
1326 break;
1327 }
1328
1329 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1330 return ret;
1331}
1332
1333static int d40_channel_execute_command(struct d40_chan *d40c,
1334 enum d40_command command)
1335{
1336 if (chan_is_logical(d40c))
1337 return __d40_execute_command_log(d40c, command);
1338 else
1339 return __d40_execute_command_phy(d40c, command);
1340}
1341
20a5b6d0
RV		 1342static u32 d40_get_prmo(struct d40_chan *d40c)
1343{
1344 static const unsigned int phy_map[] = {
1345 [STEDMA40_PCHAN_BASIC_MODE]
1346 = D40_DREG_PRMO_PCHAN_BASIC,
1347 [STEDMA40_PCHAN_MODULO_MODE]
1348 = D40_DREG_PRMO_PCHAN_MODULO,
1349 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1350 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1351 };
1352 static const unsigned int log_map[] = {
1353 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1354 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1355 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1356 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1357 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1358 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1359 };
1360
724a8577 1361 if (chan_is_physical(d40c))
20a5b6d0
RV		 1362 return phy_map[d40c->dma_cfg.mode_opt];
1363 else
1364 return log_map[d40c->dma_cfg.mode_opt];
1365}
1366
b55912c6 1367static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 1368{
1369 u32 addr_base;
1370 u32 var;
8d318a50
LW		 1371
1372 /* Odd addresses are even addresses + 4 */
1373 addr_base = (d40c->phy_chan->num % 2) * 4;
1374 /* Setup channel mode to logical or physical */
724a8577 1375 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 1376 D40_CHAN_POS(d40c->phy_chan->num);
1377 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1378
1379 /* Setup operational mode option register */
20a5b6d0 1380 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 1381
1382 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1383
724a8577 1384 if (chan_is_logical(d40c)) {
8ca84687
RV		 1385 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1386 & D40_SREG_ELEM_LOG_LIDX_MASK;
1387 void __iomem *chanbase = chan_base(d40c);
1388
8d318a50 1389 /* Set default config for CFG reg */
8ca84687
RV		 1390 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1391 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 1392
b55912c6 1393 /* Set LIDX for lcla */
8ca84687
RV		 1394 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1395 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
e9f3a49c
RV		 1396
1397 /* Clear LNK which will be used by d40_chan_has_events() */
1398 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1399 writel(0, chanbase + D40_CHAN_REG_SDLNK);
8d318a50 1400 }
8d318a50
LW		 1401}
1402
aa182ae2
JA		 1403static u32 d40_residue(struct d40_chan *d40c)
1404{
1405 u32 num_elt;
1406
724a8577 1407 if (chan_is_logical(d40c))
aa182ae2
JA		 1408 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1409 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 1410 else {
1411 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1412 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1413 >> D40_SREG_ELEM_PHY_ECNT_POS;
1414 }
1415
43f2e1a3 1416 return num_elt * d40c->dma_cfg.dst_info.data_width;
aa182ae2
JA		 1417}
1418
1419static bool d40_tx_is_linked(struct d40_chan *d40c)
1420{
1421 bool is_link;
1422
724a8577 1423 if (chan_is_logical(d40c))
aa182ae2
JA		 1424 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1425 else
8ca84687
RV		 1426 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1427 & D40_SREG_LNK_PHYS_LNK_MASK;
1428
aa182ae2
JA		 1429 return is_link;
1430}
1431
6f5bad03 1432static int d40_pause(struct dma_chan *chan)
aa182ae2 1433{
6f5bad03 1434 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
aa182ae2
JA		 1435 int res = 0;
1436 unsigned long flags;
1437
6f5bad03
MR		 1438 if (d40c->phy_chan == NULL) {
1439 chan_err(d40c, "Channel is not allocated!\n");
1440 return -EINVAL;
1441 }
1442
3ac012af
JA		 1443 if (!d40c->busy)
1444 return 0;
1445
aa182ae2 1446 spin_lock_irqsave(&d40c->lock, flags);
80245216 1447 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1448
1449 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1bdae6f4 1450
7fb3e75e
N		 1451 pm_runtime_mark_last_busy(d40c->base->dev);
1452 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1453 spin_unlock_irqrestore(&d40c->lock, flags);
1454 return res;
1455}
1456
6f5bad03 1457static int d40_resume(struct dma_chan *chan)
aa182ae2 1458{
6f5bad03 1459 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
aa182ae2
JA		 1460 int res = 0;
1461 unsigned long flags;
1462
6f5bad03
MR		 1463 if (d40c->phy_chan == NULL) {
1464 chan_err(d40c, "Channel is not allocated!\n");
1465 return -EINVAL;
1466 }
1467
3ac012af
JA		 1468 if (!d40c->busy)
1469 return 0;
1470
aa182ae2 1471 spin_lock_irqsave(&d40c->lock, flags);
7fb3e75e 1472 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1473
1474 /* If bytes left to transfer or linked tx resume job */
1bdae6f4 1475 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
aa182ae2 1476 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
aa182ae2 1477
7fb3e75e
N		 1478 pm_runtime_mark_last_busy(d40c->base->dev);
1479 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1480 spin_unlock_irqrestore(&d40c->lock, flags);
1481 return res;
1482}
1483
8d318a50
LW		 1484static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1485{
1486 struct d40_chan *d40c = container_of(tx->chan,
1487 struct d40_chan,
1488 chan);
1489 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1490 unsigned long flags;
884485e1 1491 dma_cookie_t cookie;
8d318a50
LW		 1492
1493 spin_lock_irqsave(&d40c->lock, flags);
884485e1 1494 cookie = dma_cookie_assign(tx);
8d318a50 1495 d40_desc_queue(d40c, d40d);
8d318a50
LW		 1496 spin_unlock_irqrestore(&d40c->lock, flags);
1497
884485e1 1498 return cookie;
8d318a50
LW		 1499}
1500
1501static int d40_start(struct d40_chan *d40c)
1502{
0c32269d 1503 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1504}
1505
1506static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1507{
1508 struct d40_desc *d40d;
1509 int err;
1510
1511 /* Start queued jobs, if any */
1512 d40d = d40_first_queued(d40c);
1513
1514 if (d40d != NULL) {
1bdae6f4 1515 if (!d40c->busy) {
7fb3e75e 1516 d40c->busy = true;
1bdae6f4
N		 1517 pm_runtime_get_sync(d40c->base->dev);
1518 }
8d318a50
LW		 1519
1520 /* Remove from queue */
1521 d40_desc_remove(d40d);
1522
1523 /* Add to active queue */
1524 d40_desc_submit(d40c, d40d);
1525
7d83a854
RV		 1526 /* Initiate DMA job */
1527 d40_desc_load(d40c, d40d);
8d318a50 1528
7d83a854
RV		 1529 /* Start dma job */
1530 err = d40_start(d40c);
8d318a50 1531
7d83a854
RV		 1532 if (err)
1533 return NULL;
8d318a50
LW		 1534 }
1535
1536 return d40d;
1537}
1538
1539/* called from interrupt context */
1540static void dma_tc_handle(struct d40_chan *d40c)
1541{
1542 struct d40_desc *d40d;
1543
8d318a50
LW		 1544 /* Get first active entry from list */
1545 d40d = d40_first_active_get(d40c);
1546
1547 if (d40d == NULL)
1548 return;
1549
0c842b55
RV		 1550 if (d40d->cyclic) {
1551 /*
1552 * If this was a paritially loaded list, we need to reloaded
1553 * it, and only when the list is completed. We need to check
1554 * for done because the interrupt will hit for every link, and
1555 * not just the last one.
1556 */
1557 if (d40d->lli_current < d40d->lli_len
1558 && !d40_tx_is_linked(d40c)
1559 && !d40_residue(d40c)) {
1560 d40_lcla_free_all(d40c, d40d);
1561 d40_desc_load(d40c, d40d);
1562 (void) d40_start(d40c);
8d318a50 1563
0c842b55
RV		 1564 if (d40d->lli_current == d40d->lli_len)
1565 d40d->lli_current = 0;
1566 }
1567 } else {
1568 d40_lcla_free_all(d40c, d40d);
8d318a50 1569
0c842b55
RV		 1570 if (d40d->lli_current < d40d->lli_len) {
1571 d40_desc_load(d40c, d40d);
1572 /* Start dma job */
1573 (void) d40_start(d40c);
1574 return;
1575 }
1576
9ecb41bd 1577 if (d40_queue_start(d40c) == NULL) {
0c842b55 1578 d40c->busy = false;
9ecb41bd
RV		 1579
1580 pm_runtime_mark_last_busy(d40c->base->dev);
1581 pm_runtime_put_autosuspend(d40c->base->dev);
1582 }
8d318a50 1583
7dd14525
FB		 1584 d40_desc_remove(d40d);
1585 d40_desc_done(d40c, d40d);
1586 }
4226dd86 1587
8d318a50
LW		 1588 d40c->pending_tx++;
1589 tasklet_schedule(&d40c->tasklet);
1590
1591}
1592
1593static void dma_tasklet(unsigned long data)
1594{
1595 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1596 struct d40_desc *d40d;
8d318a50 1597 unsigned long flags;
e9baa9d9 1598 bool callback_active;
3a315d5d 1599 struct dmaengine_desc_callback cb;
8d318a50
LW		 1600
1601 spin_lock_irqsave(&d40c->lock, flags);
1602
4226dd86
FB		 1603 /* Get first entry from the done list */
1604 d40d = d40_first_done(d40c);
1605 if (d40d == NULL) {
1606 /* Check if we have reached here for cyclic job */
1607 d40d = d40_first_active_get(d40c);
1608 if (d40d == NULL || !d40d->cyclic)
1609 goto err;
1610 }
8d318a50 1611
0c842b55 1612 if (!d40d->cyclic)
f7fbce07 1613 dma_cookie_complete(&d40d->txd);
8d318a50
LW		 1614
1615 /*
1616 * If terminating a channel pending_tx is set to zero.
1617 * This prevents any finished active jobs to return to the client.
1618 */
1619 if (d40c->pending_tx == 0) {
1620 spin_unlock_irqrestore(&d40c->lock, flags);
1621 return;
1622 }
1623
1624 /* Callback to client */
e9baa9d9 1625 callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
3a315d5d 1626 dmaengine_desc_get_callback(&d40d->txd, &cb);
767a9675 1627
0c842b55
RV		 1628 if (!d40d->cyclic) {
1629 if (async_tx_test_ack(&d40d->txd)) {
767a9675 1630 d40_desc_remove(d40d);
0c842b55 1631 d40_desc_free(d40c, d40d);
f26e03ad
FB		 1632 } else if (!d40d->is_in_client_list) {
1633 d40_desc_remove(d40d);
1634 d40_lcla_free_all(d40c, d40d);
1635 list_add_tail(&d40d->node, &d40c->client);
1636 d40d->is_in_client_list = true;
8d318a50
LW		 1637 }
1638 }
1639
1640 d40c->pending_tx--;
1641
1642 if (d40c->pending_tx)
1643 tasklet_schedule(&d40c->tasklet);
1644
1645 spin_unlock_irqrestore(&d40c->lock, flags);
1646
3a315d5d
DJ		 1647 if (callback_active)
1648 dmaengine_desc_callback_invoke(&cb, NULL);
8d318a50
LW		 1649
1650 return;
1651
1bdae6f4
N		 1652err:
1653 /* Rescue manouver if receiving double interrupts */
8d318a50
LW		 1654 if (d40c->pending_tx > 0)
1655 d40c->pending_tx--;
1656 spin_unlock_irqrestore(&d40c->lock, flags);
1657}
1658
1659static irqreturn_t d40_handle_interrupt(int irq, void *data)
1660{
8d318a50 1661 int i;
8d318a50
LW		 1662 u32 idx;
1663 u32 row;
1664 long chan = -1;
1665 struct d40_chan *d40c;
1666 unsigned long flags;
1667 struct d40_base *base = data;
3cb645dc
TL		 1668 u32 regs[base->gen_dmac.il_size];
1669 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1670 u32 il_size = base->gen_dmac.il_size;
8d318a50
LW		 1671
1672 spin_lock_irqsave(&base->interrupt_lock, flags);
1673
1674 /* Read interrupt status of both logical and physical channels */
3cb645dc 1675 for (i = 0; i < il_size; i++)
8d318a50
LW		 1676 regs[i] = readl(base->virtbase + il[i].src);
1677
1678 for (;;) {
1679
1680 chan = find_next_bit((unsigned long *)regs,
3cb645dc 1681 BITS_PER_LONG * il_size, chan + 1);
8d318a50
LW		 1682
1683 /* No more set bits found? */
3cb645dc 1684 if (chan == BITS_PER_LONG * il_size)
8d318a50
LW		 1685 break;
1686
1687 row = chan / BITS_PER_LONG;
1688 idx = chan & (BITS_PER_LONG - 1);
1689
8d318a50
LW		 1690 if (il[row].offset == D40_PHY_CHAN)
1691 d40c = base->lookup_phy_chans[idx];
1692 else
1693 d40c = base->lookup_log_chans[il[row].offset + idx];
53d6d68f
FB		 1694
1695 if (!d40c) {
1696 /*
1697 * No error because this can happen if something else
1698 * in the system is using the channel.
1699 */
1700 continue;
1701 }
1702
1703 /* ACK interrupt */
8a3b6e14 1704 writel(BIT(idx), base->virtbase + il[row].clr);
53d6d68f 1705
8d318a50
LW		 1706 spin_lock(&d40c->lock);
1707
1708 if (!il[row].is_error)
1709 dma_tc_handle(d40c);
1710 else
6db5a8ba
RV		 1711 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1712 chan, il[row].offset, idx);
8d318a50
LW		 1713
1714 spin_unlock(&d40c->lock);
1715 }
1716
1717 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1718
1719 return IRQ_HANDLED;
1720}
1721
8d318a50
LW		 1722static int d40_validate_conf(struct d40_chan *d40c,
1723 struct stedma40_chan_cfg *conf)
1724{
1725 int res = 0;
38bdbf02 1726 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1727
0747c7ba 1728 if (!conf->dir) {
6db5a8ba 1729 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1730 res = -EINVAL;
1731 }
1732
26955c07
LJ		 1733 if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
1734 (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1735 (conf->dev_type < 0)) {
1736 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
0747c7ba
LW		 1737 res = -EINVAL;
1738 }
1739
2c2b62d5 1740 if (conf->dir == DMA_DEV_TO_DEV) {
8d318a50
LW		 1741 /*
1742 * DMAC HW supports it. Will be added to this driver,
1743 * in case any dma client requires it.
1744 */
6db5a8ba 1745 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1746 res = -EINVAL;
1747 }
1748
d49278e3 1749 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
43f2e1a3 1750 conf->src_info.data_width !=
d49278e3 1751 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
43f2e1a3 1752 conf->dst_info.data_width) {
d49278e3
PF		 1753 /*
1754 * The DMAC hardware only supports
1755 * src (burst x width) == dst (burst x width)
1756 */
1757
6db5a8ba 1758 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1759 res = -EINVAL;
1760 }
1761
8d318a50
LW		 1762 return res;
1763}
1764
5cd326fd
N		 1765static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1766 bool is_src, int log_event_line, bool is_log,
1767 bool *first_user)
8d318a50
LW		 1768{
1769 unsigned long flags;
1770 spin_lock_irqsave(&phy->lock, flags);
5cd326fd
N		 1771
1772 *first_user = ((phy->allocated_src | phy->allocated_dst)
1773 == D40_ALLOC_FREE);
1774
4aed79b2 1775 if (!is_log) {
8d318a50
LW		 1776 /* Physical interrupts are masked per physical full channel */
1777 if (phy->allocated_src == D40_ALLOC_FREE &&
1778 phy->allocated_dst == D40_ALLOC_FREE) {
1779 phy->allocated_dst = D40_ALLOC_PHY;
1780 phy->allocated_src = D40_ALLOC_PHY;
1781 goto found;
1782 } else
1783 goto not_found;
1784 }
1785
1786 /* Logical channel */
1787 if (is_src) {
1788 if (phy->allocated_src == D40_ALLOC_PHY)
1789 goto not_found;
1790
1791 if (phy->allocated_src == D40_ALLOC_FREE)
1792 phy->allocated_src = D40_ALLOC_LOG_FREE;
1793
8a3b6e14
LJ		 1794 if (!(phy->allocated_src & BIT(log_event_line))) {
1795 phy->allocated_src |= BIT(log_event_line);
8d318a50
LW		 1796 goto found;
1797 } else
1798 goto not_found;
1799 } else {
1800 if (phy->allocated_dst == D40_ALLOC_PHY)
1801 goto not_found;
1802
1803 if (phy->allocated_dst == D40_ALLOC_FREE)
1804 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1805
8a3b6e14
LJ		 1806 if (!(phy->allocated_dst & BIT(log_event_line))) {
1807 phy->allocated_dst |= BIT(log_event_line);
8d318a50
LW		 1808 goto found;
1809 } else
1810 goto not_found;
1811 }
1812
1813not_found:
1814 spin_unlock_irqrestore(&phy->lock, flags);
1815 return false;
1816found:
1817 spin_unlock_irqrestore(&phy->lock, flags);
1818 return true;
1819}
1820
1821static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1822 int log_event_line)
1823{
1824 unsigned long flags;
1825 bool is_free = false;
1826
1827 spin_lock_irqsave(&phy->lock, flags);
1828 if (!log_event_line) {
8d318a50
LW		 1829 phy->allocated_dst = D40_ALLOC_FREE;
1830 phy->allocated_src = D40_ALLOC_FREE;
1831 is_free = true;
1832 goto out;
1833 }
1834
1835 /* Logical channel */
1836 if (is_src) {
8a3b6e14 1837 phy->allocated_src &= ~BIT(log_event_line);
8d318a50
LW		 1838 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1839 phy->allocated_src = D40_ALLOC_FREE;
1840 } else {
8a3b6e14 1841 phy->allocated_dst &= ~BIT(log_event_line);
8d318a50
LW		 1842 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1843 phy->allocated_dst = D40_ALLOC_FREE;
1844 }
1845
1846 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1847 D40_ALLOC_FREE);
1848
1849out:
1850 spin_unlock_irqrestore(&phy->lock, flags);
1851
1852 return is_free;
1853}
1854
5cd326fd 1855static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
8d318a50 1856{
26955c07 1857 int dev_type = d40c->dma_cfg.dev_type;
8d318a50
LW		 1858 int event_group;
1859 int event_line;
1860 struct d40_phy_res *phys;
1861 int i;
1862 int j;
1863 int log_num;
f000df8c 1864 int num_phy_chans;
8d318a50 1865 bool is_src;
38bdbf02 1866 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1867
1868 phys = d40c->base->phy_res;
f000df8c 1869 num_phy_chans = d40c->base->num_phy_chans;
8d318a50 1870
2c2b62d5 1871 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
8d318a50
LW		 1872 log_num = 2 * dev_type;
1873 is_src = true;
2c2b62d5
LJ		 1874 } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1875 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8d318a50 1876 /* dst event lines are used for logical memcpy */
8d318a50
LW		 1877 log_num = 2 * dev_type + 1;
1878 is_src = false;
1879 } else
1880 return -EINVAL;
1881
1882 event_group = D40_TYPE_TO_GROUP(dev_type);
1883 event_line = D40_TYPE_TO_EVENT(dev_type);
1884
1885 if (!is_log) {
2c2b62d5 1886 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8d318a50 1887 /* Find physical half channel */
f000df8c
GB		 1888 if (d40c->dma_cfg.use_fixed_channel) {
1889 i = d40c->dma_cfg.phy_channel;
4aed79b2 1890 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1891 0, is_log,
1892 first_phy_user))
8d318a50 1893 goto found_phy;
f000df8c
GB		 1894 } else {
1895 for (i = 0; i < num_phy_chans; i++) {
1896 if (d40_alloc_mask_set(&phys[i], is_src,
1897 0, is_log,
1898 first_phy_user))
1899 goto found_phy;
1900 }
8d318a50
LW		 1901 }
1902 } else
1903 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1904 int phy_num = j + event_group * 2;
1905 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1906 if (d40_alloc_mask_set(&phys[i],
1907 is_src,
1908 0,
5cd326fd
N		 1909 is_log,
1910 first_phy_user))
8d318a50
LW		 1911 goto found_phy;
1912 }
1913 }
1914 return -EINVAL;
1915found_phy:
1916 d40c->phy_chan = &phys[i];
1917 d40c->log_num = D40_PHY_CHAN;
1918 goto out;
1919 }
1920 if (dev_type == -1)
1921 return -EINVAL;
1922
1923 /* Find logical channel */
1924 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1925 int phy_num = j + event_group * 2;
5cd326fd
N		 1926
1927 if (d40c->dma_cfg.use_fixed_channel) {
1928 i = d40c->dma_cfg.phy_channel;
1929
1930 if ((i != phy_num) && (i != phy_num + 1)) {
1931 dev_err(chan2dev(d40c),
1932 "invalid fixed phy channel %d\n", i);
1933 return -EINVAL;
1934 }
1935
1936 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1937 is_log, first_phy_user))
1938 goto found_log;
1939
1940 dev_err(chan2dev(d40c),
1941 "could not allocate fixed phy channel %d\n", i);
1942 return -EINVAL;
1943 }
1944
8d318a50
LW		 1945 /*
1946 * Spread logical channels across all available physical rather
1947 * than pack every logical channel at the first available phy
1948 * channels.
1949 */
1950 if (is_src) {
1951 for (i = phy_num; i < phy_num + 2; i++) {
1952 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1953 event_line, is_log,
1954 first_phy_user))
8d318a50
LW		 1955 goto found_log;
1956 }
1957 } else {
1958 for (i = phy_num + 1; i >= phy_num; i--) {
1959 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1960 event_line, is_log,
1961 first_phy_user))
8d318a50
LW		 1962 goto found_log;
1963 }
1964 }
1965 }
1966 return -EINVAL;
1967
1968found_log:
1969 d40c->phy_chan = &phys[i];
1970 d40c->log_num = log_num;
1971out:
1972
1973 if (is_log)
1974 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1975 else
1976 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1977
1978 return 0;
1979
1980}
1981
8d318a50
LW		 1982static int d40_config_memcpy(struct d40_chan *d40c)
1983{
1984 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1985
1986 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
29027a1e 1987 d40c->dma_cfg = dma40_memcpy_conf_log;
26955c07 1988 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
8d318a50 1989
9b233f9b
LJ		 1990 d40_log_cfg(&d40c->dma_cfg,
1991 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1992
8d318a50
LW		 1993 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1994 dma_has_cap(DMA_SLAVE, cap)) {
29027a1e 1995 d40c->dma_cfg = dma40_memcpy_conf_phy;
57e65ad7
LJ		 1996
1997 /* Generate interrrupt at end of transfer or relink. */
1998 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
1999
2000 /* Generate interrupt on error. */
2001 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2002 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2003
8d318a50 2004 } else {
6db5a8ba 2005 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 2006 return -EINVAL;
2007 }
2008
2009 return 0;
2010}
2011
8d318a50
LW		 2012static int d40_free_dma(struct d40_chan *d40c)
2013{
2014
2015 int res = 0;
26955c07 2016 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
8d318a50
LW		 2017 struct d40_phy_res *phy = d40c->phy_chan;
2018 bool is_src;
2019
2020 /* Terminate all queued and active transfers */
2021 d40_term_all(d40c);
2022
2023 if (phy == NULL) {
6db5a8ba 2024 chan_err(d40c, "phy == null\n");
8d318a50
LW		 2025 return -EINVAL;
2026 }
2027
2028 if (phy->allocated_src == D40_ALLOC_FREE &&
2029 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 2030 chan_err(d40c, "channel already free\n");
8d318a50
LW		 2031 return -EINVAL;
2032 }
2033
2c2b62d5
LJ		 2034 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2035 d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
8d318a50 2036 is_src = false;
2c2b62d5 2037 else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
8d318a50 2038 is_src = true;
26955c07 2039 else {
6db5a8ba 2040 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 2041 return -EINVAL;
2042 }
2043
7fb3e75e 2044 pm_runtime_get_sync(d40c->base->dev);
1bdae6f4 2045 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
d181b3a8 2046 if (res) {
1bdae6f4 2047 chan_err(d40c, "stop failed\n");
7fb3e75e 2048 goto out;
d181b3a8
JA		 2049 }
2050
1bdae6f4 2051 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
8d318a50 2052
1bdae6f4 2053 if (chan_is_logical(d40c))
8d318a50 2054 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1bdae6f4
N		 2055 else
2056 d40c->base->lookup_phy_chans[phy->num] = NULL;
7fb3e75e
N		 2057
2058 if (d40c->busy) {
2059 pm_runtime_mark_last_busy(d40c->base->dev);
2060 pm_runtime_put_autosuspend(d40c->base->dev);
2061 }
2062
2063 d40c->busy = false;
8d318a50 2064 d40c->phy_chan = NULL;
ce2ca125 2065 d40c->configured = false;
7fb3e75e 2066out:
8d318a50 2067
7fb3e75e
N		 2068 pm_runtime_mark_last_busy(d40c->base->dev);
2069 pm_runtime_put_autosuspend(d40c->base->dev);
2070 return res;
8d318a50
LW		 2071}
2072
a5ebca47
JA		 2073static bool d40_is_paused(struct d40_chan *d40c)
2074{
8ca84687 2075 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 2076 bool is_paused = false;
2077 unsigned long flags;
2078 void __iomem *active_reg;
2079 u32 status;
26955c07 2080 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
a5ebca47
JA		 2081
2082 spin_lock_irqsave(&d40c->lock, flags);
2083
724a8577 2084 if (chan_is_physical(d40c)) {
a5ebca47
JA		 2085 if (d40c->phy_chan->num % 2 == 0)
2086 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2087 else
2088 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2089
2090 status = (readl(active_reg) &
2091 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2092 D40_CHAN_POS(d40c->phy_chan->num);
2093 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2094 is_paused = true;
2095
2096 goto _exit;
2097 }
2098
2c2b62d5
LJ		 2099 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2100 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8ca84687 2101 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2c2b62d5 2102 } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
8ca84687 2103 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 2104 } else {
6db5a8ba 2105 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 2106 goto _exit;
2107 }
9dbfbd35 2108
a5ebca47
JA		 2109 status = (status & D40_EVENTLINE_MASK(event)) >>
2110 D40_EVENTLINE_POS(event);
2111
2112 if (status != D40_DMA_RUN)
2113 is_paused = true;
a5ebca47
JA		 2114_exit:
2115 spin_unlock_irqrestore(&d40c->lock, flags);
2116 return is_paused;
2117
2118}
2119
8d318a50
LW		 2120static u32 stedma40_residue(struct dma_chan *chan)
2121{
2122 struct d40_chan *d40c =
2123 container_of(chan, struct d40_chan, chan);
2124 u32 bytes_left;
2125 unsigned long flags;
2126
2127 spin_lock_irqsave(&d40c->lock, flags);
2128 bytes_left = d40_residue(d40c);
2129 spin_unlock_irqrestore(&d40c->lock, flags);
2130
2131 return bytes_left;
2132}
2133
3e3a0763
RV		 2134static int
2135d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2136 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2137 unsigned int sg_len, dma_addr_t src_dev_addr,
2138 dma_addr_t dst_dev_addr)
3e3a0763
RV		 2139{
2140 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2141 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2142 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 2143 int ret;
3e3a0763 2144
5ed04b85
RV		 2145 ret = d40_log_sg_to_lli(sg_src, sg_len,
2146 src_dev_addr,
2147 desc->lli_log.src,
2148 chan->log_def.lcsp1,
2149 src_info->data_width,
2150 dst_info->data_width);
2151
2152 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2153 dst_dev_addr,
2154 desc->lli_log.dst,
2155 chan->log_def.lcsp3,
2156 dst_info->data_width,
2157 src_info->data_width);
2158
2159 return ret < 0 ? ret : 0;
3e3a0763
RV		 2160}
2161
2162static int
2163d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2164 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2165 unsigned int sg_len, dma_addr_t src_dev_addr,
2166 dma_addr_t dst_dev_addr)
3e3a0763 2167{
3e3a0763
RV		 2168 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2169 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2170 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
0c842b55 2171 unsigned long flags = 0;
3e3a0763
RV		 2172 int ret;
2173
0c842b55
RV		 2174 if (desc->cyclic)
2175 flags |= LLI_CYCLIC | LLI_TERM_INT;
2176
3e3a0763
RV		 2177 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2178 desc->lli_phy.src,
2179 virt_to_phys(desc->lli_phy.src),
2180 chan->src_def_cfg,
0c842b55 2181 src_info, dst_info, flags);
3e3a0763
RV		 2182
2183 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2184 desc->lli_phy.dst,
2185 virt_to_phys(desc->lli_phy.dst),
2186 chan->dst_def_cfg,
0c842b55 2187 dst_info, src_info, flags);
3e3a0763
RV		 2188
2189 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2190 desc->lli_pool.size, DMA_TO_DEVICE);
2191
2192 return ret < 0 ? ret : 0;
2193}
2194
5f81158f
RV		 2195static struct d40_desc *
2196d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2197 unsigned int sg_len, unsigned long dma_flags)
2198{
2199 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2200 struct d40_desc *desc;
dbd88788 2201 int ret;
5f81158f
RV		 2202
2203 desc = d40_desc_get(chan);
2204 if (!desc)
2205 return NULL;
2206
2207 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2208 cfg->dst_info.data_width);
2209 if (desc->lli_len < 0) {
2210 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 2211 goto err;
2212 }
5f81158f 2213
dbd88788
RV		 2214 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2215 if (ret < 0) {
2216 chan_err(chan, "Could not allocate lli\n");
2217 goto err;
5f81158f
RV		 2218 }
2219
2220 desc->lli_current = 0;
2221 desc->txd.flags = dma_flags;
2222 desc->txd.tx_submit = d40_tx_submit;
2223
2224 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2225
2226 return desc;
dbd88788
RV		 2227
2228err:
2229 d40_desc_free(chan, desc);
2230 return NULL;
5f81158f
RV		 2231}
2232
cade1d30
RV		 2233static struct dma_async_tx_descriptor *
2234d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2235 struct scatterlist *sg_dst, unsigned int sg_len,
db8196df 2236 enum dma_transfer_direction direction, unsigned long dma_flags)
cade1d30
RV		 2237{
2238 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 2239 dma_addr_t src_dev_addr = 0;
2240 dma_addr_t dst_dev_addr = 0;
cade1d30 2241 struct d40_desc *desc;
2a614340 2242 unsigned long flags;
cade1d30 2243 int ret;
8d318a50 2244
cade1d30
RV		 2245 if (!chan->phy_chan) {
2246 chan_err(chan, "Cannot prepare unallocated channel\n");
2247 return NULL;
0d0f6b8b
JA		 2248 }
2249
cade1d30 2250 spin_lock_irqsave(&chan->lock, flags);
8d318a50 2251
cade1d30
RV		 2252 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2253 if (desc == NULL)
8d318a50
LW		 2254 goto err;
2255
0c842b55
RV		 2256 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2257 desc->cyclic = true;
2258
ef9c89b3
LJ		 2259 if (direction == DMA_DEV_TO_MEM)
2260 src_dev_addr = chan->runtime_addr;
2261 else if (direction == DMA_MEM_TO_DEV)
2262 dst_dev_addr = chan->runtime_addr;
cade1d30
RV		 2263
2264 if (chan_is_logical(chan))
2265 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 2266 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2267 else
2268 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 2269 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2270
2271 if (ret) {
2272 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2273 chan_is_logical(chan) ? "log" : "phy", ret);
2274 goto err;
8d318a50
LW		 2275 }
2276
82babbb3
PF		 2277 /*
2278 * add descriptor to the prepare queue in order to be able
2279 * to free them later in terminate_all
2280 */
2281 list_add_tail(&desc->node, &chan->prepare_queue);
2282
cade1d30
RV		 2283 spin_unlock_irqrestore(&chan->lock, flags);
2284
2285 return &desc->txd;
8d318a50 2286
8d318a50 2287err:
cade1d30
RV		 2288 if (desc)
2289 d40_desc_free(chan, desc);
2290 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 2291 return NULL;
2292}
8d318a50
LW		 2293
2294bool stedma40_filter(struct dma_chan *chan, void *data)
2295{
2296 struct stedma40_chan_cfg *info = data;
2297 struct d40_chan *d40c =
2298 container_of(chan, struct d40_chan, chan);
2299 int err;
2300
2301 if (data) {
2302 err = d40_validate_conf(d40c, info);
2303 if (!err)
2304 d40c->dma_cfg = *info;
2305 } else
2306 err = d40_config_memcpy(d40c);
2307
ce2ca125
RV		 2308 if (!err)
2309 d40c->configured = true;
2310
8d318a50
LW		 2311 return err == 0;
2312}
2313EXPORT_SYMBOL(stedma40_filter);
2314
ac2c0a38
RV		 2315static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2316{
2317 bool realtime = d40c->dma_cfg.realtime;
2318 bool highprio = d40c->dma_cfg.high_priority;
3cb645dc 2319 u32 rtreg;
ac2c0a38
RV		 2320 u32 event = D40_TYPE_TO_EVENT(dev_type);
2321 u32 group = D40_TYPE_TO_GROUP(dev_type);
8a3b6e14 2322 u32 bit = BIT(event);
ccc3d697 2323 u32 prioreg;
3cb645dc 2324 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
ccc3d697 2325
3cb645dc 2326 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
ccc3d697
RV		 2327 /*
2328 * Due to a hardware bug, in some cases a logical channel triggered by
2329 * a high priority destination event line can generate extra packet
2330 * transactions.
2331 *
2332 * The workaround is to not set the high priority level for the
2333 * destination event lines that trigger logical channels.
2334 */
2335 if (!src && chan_is_logical(d40c))
2336 highprio = false;
2337
3cb645dc 2338 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
ac2c0a38
RV		 2339
2340 /* Destination event lines are stored in the upper halfword */
2341 if (!src)
2342 bit <<= 16;
2343
2344 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2345 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2346}
2347
2348static void d40_set_prio_realtime(struct d40_chan *d40c)
2349{
2350 if (d40c->base->rev < 3)
2351 return;
2352
2c2b62d5
LJ		 2353 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
2354 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
26955c07 2355 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
ac2c0a38 2356
2c2b62d5
LJ		 2357 if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
2358 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
26955c07 2359 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
ac2c0a38
RV		 2360}
2361
fa332de5
LJ		 2362#define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
2363#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2364#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2365#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
bddd5a2b 2366#define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
fa332de5
LJ		 2367
2368static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2369 struct of_dma *ofdma)
2370{
2371 struct stedma40_chan_cfg cfg;
2372 dma_cap_mask_t cap;
2373 u32 flags;
2374
2375 memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2376
2377 dma_cap_zero(cap);
2378 dma_cap_set(DMA_SLAVE, cap);
2379
2380 cfg.dev_type = dma_spec->args[0];
2381 flags = dma_spec->args[2];
2382
2383 switch (D40_DT_FLAGS_MODE(flags)) {
2384 case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2385 case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2386 }
2387
2388 switch (D40_DT_FLAGS_DIR(flags)) {
2389 case 0:
2c2b62d5 2390 cfg.dir = DMA_MEM_TO_DEV;
fa332de5
LJ		 2391 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2392 break;
2393 case 1:
2c2b62d5 2394 cfg.dir = DMA_DEV_TO_MEM;
fa332de5
LJ		 2395 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2396 break;
2397 }
2398
2399 if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2400 cfg.phy_channel = dma_spec->args[1];
2401 cfg.use_fixed_channel = true;
2402 }
2403
bddd5a2b
LJ		 2404 if (D40_DT_FLAGS_HIGH_PRIO(flags))
2405 cfg.high_priority = true;
2406
fa332de5
LJ		 2407 return dma_request_channel(cap, stedma40_filter, &cfg);
2408}
2409
8d318a50
LW		 2410/* DMA ENGINE functions */
2411static int d40_alloc_chan_resources(struct dma_chan *chan)
2412{
2413 int err;
2414 unsigned long flags;
2415 struct d40_chan *d40c =
2416 container_of(chan, struct d40_chan, chan);
ef1872ec 2417 bool is_free_phy;
8d318a50
LW		 2418 spin_lock_irqsave(&d40c->lock, flags);
2419
d3ee98cd 2420 dma_cookie_init(chan);
8d318a50 2421
ce2ca125
RV		 2422 /* If no dma configuration is set use default configuration (memcpy) */
2423 if (!d40c->configured) {
8d318a50 2424 err = d40_config_memcpy(d40c);
ff0b12ba 2425 if (err) {
6db5a8ba 2426 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 2427 goto fail;
2428 }
8d318a50
LW		 2429 }
2430
5cd326fd 2431 err = d40_allocate_channel(d40c, &is_free_phy);
8d318a50 2432 if (err) {
6db5a8ba 2433 chan_err(d40c, "Failed to allocate channel\n");
7fb3e75e 2434 d40c->configured = false;
ff0b12ba 2435 goto fail;
8d318a50
LW		 2436 }
2437
7fb3e75e 2438 pm_runtime_get_sync(d40c->base->dev);
ef1872ec 2439
ac2c0a38
RV		 2440 d40_set_prio_realtime(d40c);
2441
724a8577 2442 if (chan_is_logical(d40c)) {
2c2b62d5 2443 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
ef1872ec 2444 d40c->lcpa = d40c->base->lcpa_base +
26955c07 2445 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
ef1872ec
LW		 2446 else
2447 d40c->lcpa = d40c->base->lcpa_base +
26955c07 2448 d40c->dma_cfg.dev_type *
f26e03ad 2449 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
9778256b
LJ		 2450
2451 /* Unmask the Global Interrupt Mask. */
2452 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2453 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
ef1872ec
LW		 2454 }
2455
5cd326fd
N		 2456 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2457 chan_is_logical(d40c) ? "logical" : "physical",
2458 d40c->phy_chan->num,
2459 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2460
2461
ef1872ec
LW		 2462 /*
2463 * Only write channel configuration to the DMA if the physical
2464 * resource is free. In case of multiple logical channels
2465 * on the same physical resource, only the first write is necessary.
2466 */
b55912c6
JA		 2467 if (is_free_phy)
2468 d40_config_write(d40c);
ff0b12ba 2469fail:
7fb3e75e
N		 2470 pm_runtime_mark_last_busy(d40c->base->dev);
2471 pm_runtime_put_autosuspend(d40c->base->dev);
8d318a50 2472 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 2473 return err;
8d318a50
LW		 2474}
2475
2476static void d40_free_chan_resources(struct dma_chan *chan)
2477{
2478 struct d40_chan *d40c =
2479 container_of(chan, struct d40_chan, chan);
2480 int err;
2481 unsigned long flags;
2482
0d0f6b8b 2483 if (d40c->phy_chan == NULL) {
6db5a8ba 2484 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 2485 return;
2486 }
2487
8d318a50
LW		 2488 spin_lock_irqsave(&d40c->lock, flags);
2489
2490 err = d40_free_dma(d40c);
2491
2492 if (err)
6db5a8ba 2493 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 2494 spin_unlock_irqrestore(&d40c->lock, flags);
2495}
2496
2497static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2498 dma_addr_t dst,
2499 dma_addr_t src,
2500 size_t size,
2a614340 2501 unsigned long dma_flags)
8d318a50 2502{
95944c6e
RV		 2503 struct scatterlist dst_sg;
2504 struct scatterlist src_sg;
8d318a50 2505
95944c6e
RV		 2506 sg_init_table(&dst_sg, 1);
2507 sg_init_table(&src_sg, 1);
8d318a50 2508
95944c6e
RV		 2509 sg_dma_address(&dst_sg) = dst;
2510 sg_dma_address(&src_sg) = src;
8d318a50 2511
95944c6e
RV		 2512 sg_dma_len(&dst_sg) = size;
2513 sg_dma_len(&src_sg) = size;
8d318a50 2514
de6b641e
SA		 2515 return d40_prep_sg(chan, &src_sg, &dst_sg, 1,
2516 DMA_MEM_TO_MEM, dma_flags);
8d318a50
LW		 2517}
2518
0d688662 2519static struct dma_async_tx_descriptor *
cade1d30
RV		 2520d40_prep_memcpy_sg(struct dma_chan *chan,
2521 struct scatterlist *dst_sg, unsigned int dst_nents,
2522 struct scatterlist *src_sg, unsigned int src_nents,
2523 unsigned long dma_flags)
0d688662
IS		 2524{
2525 if (dst_nents != src_nents)
2526 return NULL;
2527
de6b641e
SA		 2528 return d40_prep_sg(chan, src_sg, dst_sg, src_nents,
2529 DMA_MEM_TO_MEM, dma_flags);
00ac0341
RV		 2530}
2531
f26e03ad
FB		 2532static struct dma_async_tx_descriptor *
2533d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2534 unsigned int sg_len, enum dma_transfer_direction direction,
2535 unsigned long dma_flags, void *context)
8d318a50 2536{
a725dcc0 2537 if (!is_slave_direction(direction))
00ac0341
RV		 2538 return NULL;
2539
cade1d30 2540 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 2541}
2542
0c842b55
RV		 2543static struct dma_async_tx_descriptor *
2544dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2545 size_t buf_len, size_t period_len,
31c1e5a1 2546 enum dma_transfer_direction direction, unsigned long flags)
0c842b55
RV		 2547{
2548 unsigned int periods = buf_len / period_len;
2549 struct dma_async_tx_descriptor *txd;
2550 struct scatterlist *sg;
2551 int i;
2552
79ca7ec3 2553 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2ec7e2e7
SK		 2554 if (!sg)
2555 return NULL;
2556
0c842b55
RV		 2557 for (i = 0; i < periods; i++) {
2558 sg_dma_address(&sg[i]) = dma_addr;
2559 sg_dma_len(&sg[i]) = period_len;
2560 dma_addr += period_len;
2561 }
2562
2563 sg[periods].offset = 0;
fdaf9c4b 2564 sg_dma_len(&sg[periods]) = 0;
0c842b55
RV		 2565 sg[periods].page_link =
2566 ((unsigned long)sg | 0x01) & ~0x02;
2567
2568 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2569 DMA_PREP_INTERRUPT);
2570
2571 kfree(sg);
2572
2573 return txd;
2574}
2575
8d318a50
LW		 2576static enum dma_status d40_tx_status(struct dma_chan *chan,
2577 dma_cookie_t cookie,
2578 struct dma_tx_state *txstate)
2579{
2580 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
96a2af41 2581 enum dma_status ret;
8d318a50 2582
0d0f6b8b 2583 if (d40c->phy_chan == NULL) {
6db5a8ba 2584 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2585 return -EINVAL;
2586 }
2587
96a2af41 2588 ret = dma_cookie_status(chan, cookie, txstate);
a90e56e5 2589 if (ret != DMA_COMPLETE && txstate)
96a2af41 2590 dma_set_residue(txstate, stedma40_residue(chan));
8d318a50 2591
a5ebca47
JA		 2592 if (d40_is_paused(d40c))
2593 ret = DMA_PAUSED;
8d318a50
LW		 2594
2595 return ret;
2596}
2597
2598static void d40_issue_pending(struct dma_chan *chan)
2599{
2600 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2601 unsigned long flags;
2602
0d0f6b8b 2603 if (d40c->phy_chan == NULL) {
6db5a8ba 2604 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2605 return;
2606 }
2607
8d318a50
LW		 2608 spin_lock_irqsave(&d40c->lock, flags);
2609
a8f3067b
PF		 2610 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2611
2612 /* Busy means that queued jobs are already being processed */
8d318a50
LW		 2613 if (!d40c->busy)
2614 (void) d40_queue_start(d40c);
2615
2616 spin_unlock_irqrestore(&d40c->lock, flags);
2617}
2618
35e639d1 2619static int d40_terminate_all(struct dma_chan *chan)
1bdae6f4
N		 2620{
2621 unsigned long flags;
2622 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2623 int ret;
2624
6f5bad03
MR		 2625 if (d40c->phy_chan == NULL) {
2626 chan_err(d40c, "Channel is not allocated!\n");
2627 return -EINVAL;
2628 }
2629
1bdae6f4
N		 2630 spin_lock_irqsave(&d40c->lock, flags);
2631
2632 pm_runtime_get_sync(d40c->base->dev);
2633 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2634 if (ret)
2635 chan_err(d40c, "Failed to stop channel\n");
2636
2637 d40_term_all(d40c);
2638 pm_runtime_mark_last_busy(d40c->base->dev);
2639 pm_runtime_put_autosuspend(d40c->base->dev);
2640 if (d40c->busy) {
2641 pm_runtime_mark_last_busy(d40c->base->dev);
2642 pm_runtime_put_autosuspend(d40c->base->dev);
2643 }
2644 d40c->busy = false;
2645
2646 spin_unlock_irqrestore(&d40c->lock, flags);
35e639d1 2647 return 0;
1bdae6f4
N		 2648}
2649
98ca5289
RV		 2650static int
2651dma40_config_to_halfchannel(struct d40_chan *d40c,
2652 struct stedma40_half_channel_info *info,
98ca5289
RV		 2653 u32 maxburst)
2654{
98ca5289
RV		 2655 int psize;
2656
98ca5289
RV		 2657 if (chan_is_logical(d40c)) {
2658 if (maxburst >= 16)
2659 psize = STEDMA40_PSIZE_LOG_16;
2660 else if (maxburst >= 8)
2661 psize = STEDMA40_PSIZE_LOG_8;
2662 else if (maxburst >= 4)
2663 psize = STEDMA40_PSIZE_LOG_4;
2664 else
2665 psize = STEDMA40_PSIZE_LOG_1;
2666 } else {
2667 if (maxburst >= 16)
2668 psize = STEDMA40_PSIZE_PHY_16;
2669 else if (maxburst >= 8)
2670 psize = STEDMA40_PSIZE_PHY_8;
2671 else if (maxburst >= 4)
2672 psize = STEDMA40_PSIZE_PHY_4;
2673 else
2674 psize = STEDMA40_PSIZE_PHY_1;
2675 }
2676
98ca5289
RV		 2677 info->psize = psize;
2678 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2679
2680 return 0;
2681}
2682
95e1400f 2683/* Runtime reconfiguration extension */
98ca5289
RV		 2684static int d40_set_runtime_config(struct dma_chan *chan,
2685 struct dma_slave_config *config)
95e1400f
LW		 2686{
2687 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2688 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
98ca5289 2689 enum dma_slave_buswidth src_addr_width, dst_addr_width;
95e1400f 2690 dma_addr_t config_addr;
98ca5289
RV		 2691 u32 src_maxburst, dst_maxburst;
2692 int ret;
2693
6f5bad03
MR		 2694 if (d40c->phy_chan == NULL) {
2695 chan_err(d40c, "Channel is not allocated!\n");
2696 return -EINVAL;
2697 }
2698
98ca5289
RV		 2699 src_addr_width = config->src_addr_width;
2700 src_maxburst = config->src_maxburst;
2701 dst_addr_width = config->dst_addr_width;
2702 dst_maxburst = config->dst_maxburst;
95e1400f 2703
db8196df 2704 if (config->direction == DMA_DEV_TO_MEM) {
95e1400f 2705 config_addr = config->src_addr;
ef9c89b3 2706
2c2b62d5 2707 if (cfg->dir != DMA_DEV_TO_MEM)
95e1400f
LW		 2708 dev_dbg(d40c->base->dev,
2709 "channel was not configured for peripheral "
2710 "to memory transfer (%d) overriding\n",
2711 cfg->dir);
2c2b62d5 2712 cfg->dir = DMA_DEV_TO_MEM;
95e1400f 2713
98ca5289
RV		 2714 /* Configure the memory side */
2715 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2716 dst_addr_width = src_addr_width;
2717 if (dst_maxburst == 0)
2718 dst_maxburst = src_maxburst;
95e1400f 2719
db8196df 2720 } else if (config->direction == DMA_MEM_TO_DEV) {
95e1400f 2721 config_addr = config->dst_addr;
ef9c89b3 2722
2c2b62d5 2723 if (cfg->dir != DMA_MEM_TO_DEV)
95e1400f
LW		 2724 dev_dbg(d40c->base->dev,
2725 "channel was not configured for memory "
2726 "to peripheral transfer (%d) overriding\n",
2727 cfg->dir);
2c2b62d5 2728 cfg->dir = DMA_MEM_TO_DEV;
95e1400f 2729
98ca5289
RV		 2730 /* Configure the memory side */
2731 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2732 src_addr_width = dst_addr_width;
2733 if (src_maxburst == 0)
2734 src_maxburst = dst_maxburst;
95e1400f
LW		 2735 } else {
2736 dev_err(d40c->base->dev,
2737 "unrecognized channel direction %d\n",
2738 config->direction);
98ca5289 2739 return -EINVAL;
95e1400f
LW		 2740 }
2741
ef9c89b3
LJ		 2742 if (config_addr <= 0) {
2743 dev_err(d40c->base->dev, "no address supplied\n");
2744 return -EINVAL;
2745 }
2746
98ca5289 2747 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
95e1400f 2748 dev_err(d40c->base->dev,
98ca5289
RV		 2749 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2750 src_maxburst,
2751 src_addr_width,
2752 dst_maxburst,
2753 dst_addr_width);
2754 return -EINVAL;
95e1400f
LW		 2755 }
2756
92bb6cdb
PF		 2757 if (src_maxburst > 16) {
2758 src_maxburst = 16;
2759 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2760 } else if (dst_maxburst > 16) {
2761 dst_maxburst = 16;
2762 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2763 }
2764
43f2e1a3
LJ		 2765 /* Only valid widths are; 1, 2, 4 and 8. */
2766 if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2767 src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2768 dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2769 dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
c95905a6
GL		 2770 !is_power_of_2(src_addr_width) ||
2771 !is_power_of_2(dst_addr_width))
43f2e1a3
LJ		 2772 return -EINVAL;
2773
2774 cfg->src_info.data_width = src_addr_width;
2775 cfg->dst_info.data_width = dst_addr_width;
2776
98ca5289 2777 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
98ca5289
RV		 2778 src_maxburst);
2779 if (ret)
2780 return ret;
95e1400f 2781
98ca5289 2782 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
98ca5289
RV		 2783 dst_maxburst);
2784 if (ret)
2785 return ret;
95e1400f 2786
a59670a4 2787 /* Fill in register values */
724a8577 2788 if (chan_is_logical(d40c))
a59670a4
PF		 2789 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2790 else
57e65ad7 2791 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
a59670a4 2792
95e1400f
LW		 2793 /* These settings will take precedence later */
2794 d40c->runtime_addr = config_addr;
2795 d40c->runtime_direction = config->direction;
2796 dev_dbg(d40c->base->dev,
98ca5289
RV		 2797 "configured channel %s for %s, data width %d/%d, "
2798 "maxburst %d/%d elements, LE, no flow control\n",
95e1400f 2799 dma_chan_name(chan),
db8196df 2800 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
98ca5289
RV		 2801 src_addr_width, dst_addr_width,
2802 src_maxburst, dst_maxburst);
2803
2804 return 0;
95e1400f
LW		 2805}
2806
8d318a50
LW		 2807/* Initialization functions */
2808
2809static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2810 struct d40_chan *chans, int offset,
2811 int num_chans)
2812{
2813 int i = 0;
2814 struct d40_chan *d40c;
2815
2816 INIT_LIST_HEAD(&dma->channels);
2817
2818 for (i = offset; i < offset + num_chans; i++) {
2819 d40c = &chans[i];
2820 d40c->base = base;
2821 d40c->chan.device = dma;
2822
8d318a50
LW		 2823 spin_lock_init(&d40c->lock);
2824
2825 d40c->log_num = D40_PHY_CHAN;
2826
4226dd86 2827 INIT_LIST_HEAD(&d40c->done);
8d318a50
LW		 2828 INIT_LIST_HEAD(&d40c->active);
2829 INIT_LIST_HEAD(&d40c->queue);
a8f3067b 2830 INIT_LIST_HEAD(&d40c->pending_queue);
8d318a50 2831 INIT_LIST_HEAD(&d40c->client);
82babbb3 2832 INIT_LIST_HEAD(&d40c->prepare_queue);
8d318a50 2833
8d318a50
LW		 2834 tasklet_init(&d40c->tasklet, dma_tasklet,
2835 (unsigned long) d40c);
2836
2837 list_add_tail(&d40c->chan.device_node,
2838 &dma->channels);
2839 }
2840}
2841
7ad74a7c
RV		 2842static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2843{
2844 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2845 dev->device_prep_slave_sg = d40_prep_slave_sg;
2846
2847 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2848 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2849
2850 /*
2851 * This controller can only access address at even
2852 * 32bit boundaries, i.e. 2^2
2853 */
77a68e56 2854 dev->copy_align = DMAENGINE_ALIGN_4_BYTES;
7ad74a7c
RV		 2855 }
2856
2857 if (dma_has_cap(DMA_SG, dev->cap_mask))
2858 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2859
0c842b55
RV		 2860 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2861 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2862
7ad74a7c
RV		 2863 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2864 dev->device_free_chan_resources = d40_free_chan_resources;
2865 dev->device_issue_pending = d40_issue_pending;
2866 dev->device_tx_status = d40_tx_status;
6f5bad03
MR		 2867 dev->device_config = d40_set_runtime_config;
2868 dev->device_pause = d40_pause;
2869 dev->device_resume = d40_resume;
2870 dev->device_terminate_all = d40_terminate_all;
7ad74a7c
RV		 2871 dev->dev = base->dev;
2872}
2873
8d318a50
LW		 2874static int __init d40_dmaengine_init(struct d40_base *base,
2875 int num_reserved_chans)
2876{
2877 int err ;
2878
2879 d40_chan_init(base, &base->dma_slave, base->log_chans,
2880 0, base->num_log_chans);
2881
2882 dma_cap_zero(base->dma_slave.cap_mask);
2883 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
0c842b55 2884 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
8d318a50 2885
7ad74a7c 2886 d40_ops_init(base, &base->dma_slave);
8d318a50
LW		 2887
2888 err = dma_async_device_register(&base->dma_slave);
2889
2890 if (err) {
6db5a8ba 2891 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2892 goto failure1;
2893 }
2894
2895 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
a7dacb68 2896 base->num_log_chans, base->num_memcpy_chans);
8d318a50
LW		 2897
2898 dma_cap_zero(base->dma_memcpy.cap_mask);
2899 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
7ad74a7c
RV		 2900 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2901
2902 d40_ops_init(base, &base->dma_memcpy);
8d318a50
LW		 2903
2904 err = dma_async_device_register(&base->dma_memcpy);
2905
2906 if (err) {
6db5a8ba 2907 d40_err(base->dev,
52984aab 2908 "Failed to register memcpy only channels\n");
8d318a50
LW		 2909 goto failure2;
2910 }
2911
2912 d40_chan_init(base, &base->dma_both, base->phy_chans,
2913 0, num_reserved_chans);
2914
2915 dma_cap_zero(base->dma_both.cap_mask);
2916 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2917 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
7ad74a7c 2918 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
0c842b55 2919 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
7ad74a7c
RV		 2920
2921 d40_ops_init(base, &base->dma_both);
8d318a50
LW		 2922 err = dma_async_device_register(&base->dma_both);
2923
2924 if (err) {
6db5a8ba
RV		 2925 d40_err(base->dev,
2926 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2927 goto failure3;
2928 }
2929 return 0;
2930failure3:
2931 dma_async_device_unregister(&base->dma_memcpy);
2932failure2:
2933 dma_async_device_unregister(&base->dma_slave);
2934failure1:
2935 return err;
2936}
2937
7fb3e75e 2938/* Suspend resume functionality */
123e4ca1
UH		 2939#ifdef CONFIG_PM_SLEEP
2940static int dma40_suspend(struct device *dev)
7fb3e75e 2941{
28c7a19d
N		 2942 struct platform_device *pdev = to_platform_device(dev);
2943 struct d40_base *base = platform_get_drvdata(pdev);
c906a3ec
UH		 2944 int ret;
2945
2946 ret = pm_runtime_force_suspend(dev);
2947 if (ret)
2948 return ret;
7fb3e75e 2949
28c7a19d
N		 2950 if (base->lcpa_regulator)
2951 ret = regulator_disable(base->lcpa_regulator);
2952 return ret;
7fb3e75e
N		 2953}
2954
123e4ca1
UH		 2955static int dma40_resume(struct device *dev)
2956{
2957 struct platform_device *pdev = to_platform_device(dev);
2958 struct d40_base *base = platform_get_drvdata(pdev);
2959 int ret = 0;
2960
c906a3ec 2961 if (base->lcpa_regulator) {
123e4ca1 2962 ret = regulator_enable(base->lcpa_regulator);
c906a3ec
UH		 2963 if (ret)
2964 return ret;
2965 }
123e4ca1 2966
c906a3ec 2967 return pm_runtime_force_resume(dev);
123e4ca1
UH		 2968}
2969#endif
2970
2971#ifdef CONFIG_PM
2972static void dma40_backup(void __iomem *baseaddr, u32 *backup,
2973 u32 *regaddr, int num, bool save)
2974{
2975 int i;
2976
2977 for (i = 0; i < num; i++) {
2978 void __iomem *addr = baseaddr + regaddr[i];
2979
2980 if (save)
2981 backup[i] = readl_relaxed(addr);
2982 else
2983 writel_relaxed(backup[i], addr);
2984 }
2985}
2986
2987static void d40_save_restore_registers(struct d40_base *base, bool save)
2988{
2989 int i;
2990
2991 /* Save/Restore channel specific registers */
2992 for (i = 0; i < base->num_phy_chans; i++) {
2993 void __iomem *addr;
2994 int idx;
2995
2996 if (base->phy_res[i].reserved)
2997 continue;
2998
2999 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
3000 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
3001
3002 dma40_backup(addr, &base->reg_val_backup_chan[idx],
3003 d40_backup_regs_chan,
3004 ARRAY_SIZE(d40_backup_regs_chan),
3005 save);
3006 }
3007
3008 /* Save/Restore global registers */
3009 dma40_backup(base->virtbase, base->reg_val_backup,
3010 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
3011 save);
3012
3013 /* Save/Restore registers only existing on dma40 v3 and later */
3014 if (base->gen_dmac.backup)
3015 dma40_backup(base->virtbase, base->reg_val_backup_v4,
3016 base->gen_dmac.backup,
3017 base->gen_dmac.backup_size,
3018 save);
3019}
3020
7fb3e75e
N		 3021static int dma40_runtime_suspend(struct device *dev)
3022{
3023 struct platform_device *pdev = to_platform_device(dev);
3024 struct d40_base *base = platform_get_drvdata(pdev);
3025
3026 d40_save_restore_registers(base, true);
3027
3028 /* Don't disable/enable clocks for v1 due to HW bugs */
3029 if (base->rev != 1)
3030 writel_relaxed(base->gcc_pwr_off_mask,
3031 base->virtbase + D40_DREG_GCC);
3032
3033 return 0;
3034}
3035
3036static int dma40_runtime_resume(struct device *dev)
3037{
3038 struct platform_device *pdev = to_platform_device(dev);
3039 struct d40_base *base = platform_get_drvdata(pdev);
3040
2dafca17 3041 d40_save_restore_registers(base, false);
7fb3e75e
N		 3042
3043 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3044 base->virtbase + D40_DREG_GCC);
3045 return 0;
3046}
123e4ca1 3047#endif
7fb3e75e
N		 3048
3049static const struct dev_pm_ops dma40_pm_ops = {
673d3773 3050 SET_LATE_SYSTEM_SLEEP_PM_OPS(dma40_suspend, dma40_resume)
6ed23b80 3051 SET_RUNTIME_PM_OPS(dma40_runtime_suspend,
123e4ca1
UH		 3052 dma40_runtime_resume,
3053 NULL)
7fb3e75e 3054};
7fb3e75e 3055
8d318a50
LW		 3056/* Initialization functions. */
3057
3058static int __init d40_phy_res_init(struct d40_base *base)
3059{
3060 int i;
3061 int num_phy_chans_avail = 0;
3062 u32 val[2];
3063 int odd_even_bit = -2;
7fb3e75e 3064 int gcc = D40_DREG_GCC_ENA;
8d318a50
LW		 3065
3066 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3067 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3068
3069 for (i = 0; i < base->num_phy_chans; i++) {
3070 base->phy_res[i].num = i;
3071 odd_even_bit += 2 * ((i % 2) == 0);
3072 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3073 /* Mark security only channels as occupied */
3074 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3075 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3076 base->phy_res[i].reserved = true;
3077 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3078 D40_DREG_GCC_SRC);
3079 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3080 D40_DREG_GCC_DST);
3081
3082
8d318a50
LW		 3083 } else {
3084 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3085 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
7fb3e75e 3086 base->phy_res[i].reserved = false;
8d318a50
LW		 3087 num_phy_chans_avail++;
3088 }
3089 spin_lock_init(&base->phy_res[i].lock);
3090 }
6b7acd84
JA		 3091
3092 /* Mark disabled channels as occupied */
3093 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 3094 int chan = base->plat_data->disabled_channels[i];
3095
3096 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3097 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3098 base->phy_res[chan].reserved = true;
3099 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3100 D40_DREG_GCC_SRC);
3101 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3102 D40_DREG_GCC_DST);
f57b407c 3103 num_phy_chans_avail--;
6b7acd84
JA		 3104 }
3105
7407048b
FB		 3106 /* Mark soft_lli channels */
3107 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3108 int chan = base->plat_data->soft_lli_chans[i];
3109
3110 base->phy_res[chan].use_soft_lli = true;
3111 }
3112
8d318a50
LW		 3113 dev_info(base->dev, "%d of %d physical DMA channels available\n",
3114 num_phy_chans_avail, base->num_phy_chans);
3115
3116 /* Verify settings extended vs standard */
3117 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3118
3119 for (i = 0; i < base->num_phy_chans; i++) {
3120
3121 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3122 (val[0] & 0x3) != 1)
3123 dev_info(base->dev,
3124 "[%s] INFO: channel %d is misconfigured (%d)\n",
3125 __func__, i, val[0] & 0x3);
3126
3127 val[0] = val[0] >> 2;
3128 }
3129
7fb3e75e
N		 3130 /*
3131 * To keep things simple, Enable all clocks initially.
3132 * The clocks will get managed later post channel allocation.
3133 * The clocks for the event lines on which reserved channels exists
3134 * are not managed here.
3135 */
3136 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3137 base->gcc_pwr_off_mask = gcc;
3138
8d318a50
LW		 3139 return num_phy_chans_avail;
3140}
3141
3142static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3143{
d4adcc01 3144 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
8d318a50
LW		 3145 struct clk *clk = NULL;
3146 void __iomem *virtbase = NULL;
3147 struct resource *res = NULL;
3148 struct d40_base *base = NULL;
3149 int num_log_chans = 0;
3150 int num_phy_chans;
a7dacb68 3151 int num_memcpy_chans;
b707c658 3152 int clk_ret = -EINVAL;
8d318a50 3153 int i;
f4b89764
LW		 3154 u32 pid;
3155 u32 cid;
3156 u8 rev;
8d318a50
LW		 3157
3158 clk = clk_get(&pdev->dev, NULL);
8d318a50 3159 if (IS_ERR(clk)) {
6db5a8ba 3160 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 3161 goto failure;
3162 }
3163
b707c658
UH		 3164 clk_ret = clk_prepare_enable(clk);
3165 if (clk_ret) {
3166 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3167 goto failure;
3168 }
8d318a50
LW		 3169
3170 /* Get IO for DMAC base address */
3171 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3172 if (!res)
3173 goto failure;
3174
3175 if (request_mem_region(res->start, resource_size(res),
3176 D40_NAME " I/O base") == NULL)
3177 goto failure;
3178
3179 virtbase = ioremap(res->start, resource_size(res));
3180 if (!virtbase)
3181 goto failure;
3182
f4b89764
LW		 3183 /* This is just a regular AMBA PrimeCell ID actually */
3184 for (pid = 0, i = 0; i < 4; i++)
3185 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3186 & 255) << (i * 8);
3187 for (cid = 0, i = 0; i < 4; i++)
3188 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3189 & 255) << (i * 8);
8d318a50 3190
f4b89764
LW		 3191 if (cid != AMBA_CID) {
3192 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3193 goto failure;
3194 }
3195 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
6db5a8ba 3196 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
f4b89764
LW		 3197 AMBA_MANF_BITS(pid),
3198 AMBA_VENDOR_ST);
8d318a50
LW		 3199 goto failure;
3200 }
f4b89764
LW		 3201 /*
3202 * HW revision:
3203 * DB8500ed has revision 0
3204 * ? has revision 1
3205 * DB8500v1 has revision 2
3206 * DB8500v2 has revision 3
47db92f4
GB		 3207 * AP9540v1 has revision 4
3208 * DB8540v1 has revision 4
f4b89764
LW		 3209 */
3210 rev = AMBA_REV_BITS(pid);
8b2fe9b6
LJ		 3211 if (rev < 2) {
3212 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3213 goto failure;
3214 }
3ae0267f 3215
8d318a50 3216 /* The number of physical channels on this HW */
47db92f4
GB		 3217 if (plat_data->num_of_phy_chans)
3218 num_phy_chans = plat_data->num_of_phy_chans;
3219 else
3220 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
8d318a50 3221
a7dacb68
LJ		 3222 /* The number of channels used for memcpy */
3223 if (plat_data->num_of_memcpy_chans)
3224 num_memcpy_chans = plat_data->num_of_memcpy_chans;
3225 else
3226 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
3227
db72da92
LJ		 3228 num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3229
b2abb249 3230 dev_info(&pdev->dev,
3a919d5b
FE		 3231 "hardware rev: %d @ %pa with %d physical and %d logical channels\n",
3232 rev, &res->start, num_phy_chans, num_log_chans);
8d318a50 3233
8d318a50 3234 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
a7dacb68 3235 (num_phy_chans + num_log_chans + num_memcpy_chans) *
8d318a50
LW		 3236 sizeof(struct d40_chan), GFP_KERNEL);
3237
aef94fea 3238 if (base == NULL)
8d318a50 3239 goto failure;
8d318a50 3240
3ae0267f 3241 base->rev = rev;
8d318a50 3242 base->clk = clk;
a7dacb68 3243 base->num_memcpy_chans = num_memcpy_chans;
8d318a50
LW		 3244 base->num_phy_chans = num_phy_chans;
3245 base->num_log_chans = num_log_chans;
3246 base->phy_start = res->start;
3247 base->phy_size = resource_size(res);
3248 base->virtbase = virtbase;
3249 base->plat_data = plat_data;
3250 base->dev = &pdev->dev;
3251 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3252 base->log_chans = &base->phy_chans[num_phy_chans];
3253
3cb645dc
TL		 3254 if (base->plat_data->num_of_phy_chans == 14) {
3255 base->gen_dmac.backup = d40_backup_regs_v4b;
3256 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3257 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3258 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3259 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3260 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3261 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3262 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3263 base->gen_dmac.il = il_v4b;
3264 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3265 base->gen_dmac.init_reg = dma_init_reg_v4b;
3266 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3267 } else {
3268 if (base->rev >= 3) {
3269 base->gen_dmac.backup = d40_backup_regs_v4a;
3270 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3271 }
3272 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3273 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3274 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3275 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3276 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3277 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3278 base->gen_dmac.il = il_v4a;
3279 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3280 base->gen_dmac.init_reg = dma_init_reg_v4a;
3281 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3282 }
3283
8d318a50
LW		 3284 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3285 GFP_KERNEL);
3286 if (!base->phy_res)
3287 goto failure;
3288
3289 base->lookup_phy_chans = kzalloc(num_phy_chans *
3290 sizeof(struct d40_chan *),
3291 GFP_KERNEL);
3292 if (!base->lookup_phy_chans)
3293 goto failure;
3294
8a59fed3
LJ		 3295 base->lookup_log_chans = kzalloc(num_log_chans *
3296 sizeof(struct d40_chan *),
3297 GFP_KERNEL);
3298 if (!base->lookup_log_chans)
3299 goto failure;
698e4732 3300
7fb3e75e
N		 3301 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3302 sizeof(d40_backup_regs_chan),
8d318a50 3303 GFP_KERNEL);
7fb3e75e
N		 3304 if (!base->reg_val_backup_chan)
3305 goto failure;
3306
3307 base->lcla_pool.alloc_map =
3308 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3309 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
8d318a50
LW		 3310 if (!base->lcla_pool.alloc_map)
3311 goto failure;
3312
c675b1b4
JA		 3313 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3314 0, SLAB_HWCACHE_ALIGN,
3315 NULL);
3316 if (base->desc_slab == NULL)
3317 goto failure;
3318
8d318a50
LW		 3319 return base;
3320
3321failure:
b707c658
UH		 3322 if (!clk_ret)
3323 clk_disable_unprepare(clk);
3324 if (!IS_ERR(clk))
8d318a50 3325 clk_put(clk);
8d318a50
LW		 3326 if (virtbase)
3327 iounmap(virtbase);
3328 if (res)
3329 release_mem_region(res->start,
3330 resource_size(res));
3331 if (virtbase)
3332 iounmap(virtbase);
3333
3334 if (base) {
3335 kfree(base->lcla_pool.alloc_map);
1bdae6f4 3336 kfree(base->reg_val_backup_chan);
8d318a50
LW		 3337 kfree(base->lookup_log_chans);
3338 kfree(base->lookup_phy_chans);
3339 kfree(base->phy_res);
3340 kfree(base);
3341 }
3342
3343 return NULL;
3344}
3345
3346static void __init d40_hw_init(struct d40_base *base)
3347{
3348
8d318a50
LW		 3349 int i;
3350 u32 prmseo[2] = {0, 0};
3351 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3352 u32 pcmis = 0;
3353 u32 pcicr = 0;
3cb645dc
TL		 3354 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3355 u32 reg_size = base->gen_dmac.init_reg_size;
8d318a50 3356
3cb645dc 3357 for (i = 0; i < reg_size; i++)
8d318a50
LW		 3358 writel(dma_init_reg[i].val,
3359 base->virtbase + dma_init_reg[i].reg);
3360
3361 /* Configure all our dma channels to default settings */
3362 for (i = 0; i < base->num_phy_chans; i++) {
3363
3364 activeo[i % 2] = activeo[i % 2] << 2;
3365
3366 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3367 == D40_ALLOC_PHY) {
3368 activeo[i % 2] |= 3;
3369 continue;
3370 }
3371
3372 /* Enable interrupt # */
3373 pcmis = (pcmis << 1) | 1;
3374
3375 /* Clear interrupt # */
3376 pcicr = (pcicr << 1) | 1;
3377
3378 /* Set channel to physical mode */
3379 prmseo[i % 2] = prmseo[i % 2] << 2;
3380 prmseo[i % 2] |= 1;
3381
3382 }
3383
3384 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3385 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3386 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3387 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3388
3389 /* Write which interrupt to enable */
3cb645dc 3390 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
8d318a50
LW		 3391
3392 /* Write which interrupt to clear */
3cb645dc 3393 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
8d318a50 3394
3cb645dc
TL		 3395 /* These are __initdata and cannot be accessed after init */
3396 base->gen_dmac.init_reg = NULL;
3397 base->gen_dmac.init_reg_size = 0;
8d318a50
LW		 3398}
3399
508849ad
LW		 3400static int __init d40_lcla_allocate(struct d40_base *base)
3401{
026cbc42 3402 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 3403 unsigned long *page_list;
3404 int i, j;
3405 int ret = 0;
3406
3407 /*
3408 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3409 * To full fill this hardware requirement without wasting 256 kb
3410 * we allocate pages until we get an aligned one.
3411 */
3412 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3413 GFP_KERNEL);
3414
3415 if (!page_list) {
3416 ret = -ENOMEM;
3417 goto failure;
3418 }
3419
3420 /* Calculating how many pages that are required */
3421 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3422
3423 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3424 page_list[i] = __get_free_pages(GFP_KERNEL,
3425 base->lcla_pool.pages);
3426 if (!page_list[i]) {
3427
6db5a8ba
RV		 3428 d40_err(base->dev, "Failed to allocate %d pages.\n",
3429 base->lcla_pool.pages);
39375334 3430 ret = -ENOMEM;
508849ad
LW		 3431
3432 for (j = 0; j < i; j++)
3433 free_pages(page_list[j], base->lcla_pool.pages);
3434 goto failure;
3435 }
3436
3437 if ((virt_to_phys((void *)page_list[i]) &
3438 (LCLA_ALIGNMENT - 1)) == 0)
3439 break;
3440 }
3441
3442 for (j = 0; j < i; j++)
3443 free_pages(page_list[j], base->lcla_pool.pages);
3444
3445 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3446 base->lcla_pool.base = (void *)page_list[i];
3447 } else {
767a9675
JA		 3448 /*
3449 * After many attempts and no succees with finding the correct
3450 * alignment, try with allocating a big buffer.
3451 */
508849ad
LW		 3452 dev_warn(base->dev,
3453 "[%s] Failed to get %d pages @ 18 bit align.\n",
3454 __func__, base->lcla_pool.pages);
3455 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3456 base->num_phy_chans +
3457 LCLA_ALIGNMENT,
3458 GFP_KERNEL);
3459 if (!base->lcla_pool.base_unaligned) {
3460 ret = -ENOMEM;
3461 goto failure;
3462 }
3463
3464 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3465 LCLA_ALIGNMENT);
3466 }
3467
026cbc42
RV		 3468 pool->dma_addr = dma_map_single(base->dev, pool->base,
3469 SZ_1K * base->num_phy_chans,
3470 DMA_TO_DEVICE);
3471 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3472 pool->dma_addr = 0;
3473 ret = -ENOMEM;
3474 goto failure;
3475 }
3476
508849ad
LW		 3477 writel(virt_to_phys(base->lcla_pool.base),
3478 base->virtbase + D40_DREG_LCLA);
3479failure:
3480 kfree(page_list);
3481 return ret;
3482}
3483
1814a170
LJ		 3484static int __init d40_of_probe(struct platform_device *pdev,
3485 struct device_node *np)
3486{
3487 struct stedma40_platform_data *pdata;
499c2bc3 3488 int num_phy = 0, num_memcpy = 0, num_disabled = 0;
cbbe13ea 3489 const __be32 *list;
1814a170
LJ		 3490
3491 pdata = devm_kzalloc(&pdev->dev,
3492 sizeof(struct stedma40_platform_data),
3493 GFP_KERNEL);
3494 if (!pdata)
3495 return -ENOMEM;
3496
fd59f9e6
LJ		 3497 /* If absent this value will be obtained from h/w. */
3498 of_property_read_u32(np, "dma-channels", &num_phy);
3499 if (num_phy > 0)
3500 pdata->num_of_phy_chans = num_phy;
3501
a7dacb68
LJ		 3502 list = of_get_property(np, "memcpy-channels", &num_memcpy);
3503 num_memcpy /= sizeof(*list);
3504
3505 if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
3506 d40_err(&pdev->dev,
3507 "Invalid number of memcpy channels specified (%d)\n",
3508 num_memcpy);
3509 return -EINVAL;
3510 }
3511 pdata->num_of_memcpy_chans = num_memcpy;
3512
3513 of_property_read_u32_array(np, "memcpy-channels",
3514 dma40_memcpy_channels,
3515 num_memcpy);
3516
499c2bc3
LJ		 3517 list = of_get_property(np, "disabled-channels", &num_disabled);
3518 num_disabled /= sizeof(*list);
3519
5be2190a 3520 if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) {
499c2bc3
LJ		 3521 d40_err(&pdev->dev,
3522 "Invalid number of disabled channels specified (%d)\n",
3523 num_disabled);
3524 return -EINVAL;
3525 }
3526
3527 of_property_read_u32_array(np, "disabled-channels",
3528 pdata->disabled_channels,
3529 num_disabled);
3530 pdata->disabled_channels[num_disabled] = -1;
3531
1814a170
LJ		 3532 pdev->dev.platform_data = pdata;
3533
3534 return 0;
3535}
3536
8d318a50
LW		 3537static int __init d40_probe(struct platform_device *pdev)
3538{
d4adcc01 3539 struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
1814a170 3540 struct device_node *np = pdev->dev.of_node;
8d318a50 3541 int ret = -ENOENT;
a9bae06d 3542 struct d40_base *base;
aeb8974a 3543 struct resource *res;
8d318a50
LW		 3544 int num_reserved_chans;
3545 u32 val;
3546
1814a170
LJ		 3547 if (!plat_data) {
3548 if (np) {
fe146473 3549 if (d40_of_probe(pdev, np)) {
1814a170 3550 ret = -ENOMEM;
a9bae06d 3551 goto report_failure;
1814a170
LJ		 3552 }
3553 } else {
3554 d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
a9bae06d 3555 goto report_failure;
1814a170
LJ		 3556 }
3557 }
8d318a50 3558
1814a170 3559 base = d40_hw_detect_init(pdev);
8d318a50 3560 if (!base)
a9bae06d 3561 goto report_failure;
8d318a50
LW		 3562
3563 num_reserved_chans = d40_phy_res_init(base);
3564
3565 platform_set_drvdata(pdev, base);
3566
3567 spin_lock_init(&base->interrupt_lock);
3568 spin_lock_init(&base->execmd_lock);
3569
3570 /* Get IO for logical channel parameter address */
3571 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3572 if (!res) {
3573 ret = -ENOENT;
6db5a8ba 3574 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 3575 goto failure;
3576 }
3577 base->lcpa_size = resource_size(res);
3578 base->phy_lcpa = res->start;
3579
3580 if (request_mem_region(res->start, resource_size(res),
3581 D40_NAME " I/O lcpa") == NULL) {
3582 ret = -EBUSY;
3a919d5b 3583 d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res);
8d318a50
LW		 3584 goto failure;
3585 }
3586
3587 /* We make use of ESRAM memory for this. */
3588 val = readl(base->virtbase + D40_DREG_LCPA);
3589 if (res->start != val && val != 0) {
3590 dev_warn(&pdev->dev,
3a919d5b
FE		 3591 "[%s] Mismatch LCPA dma 0x%x, def %pa\n",
3592 __func__, val, &res->start);
8d318a50
LW		 3593 } else
3594 writel(res->start, base->virtbase + D40_DREG_LCPA);
3595
3596 base->lcpa_base = ioremap(res->start, resource_size(res));
3597 if (!base->lcpa_base) {
3598 ret = -ENOMEM;
6db5a8ba 3599 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 3600 goto failure;
3601 }
28c7a19d
N		 3602 /* If lcla has to be located in ESRAM we don't need to allocate */
3603 if (base->plat_data->use_esram_lcla) {
3604 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3605 "lcla_esram");
3606 if (!res) {
3607 ret = -ENOENT;
3608 d40_err(&pdev->dev,
3609 "No \"lcla_esram\" memory resource\n");
3610 goto failure;
3611 }
3612 base->lcla_pool.base = ioremap(res->start,
3613 resource_size(res));
3614 if (!base->lcla_pool.base) {
3615 ret = -ENOMEM;
3616 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3617 goto failure;
3618 }
3619 writel(res->start, base->virtbase + D40_DREG_LCLA);
8d318a50 3620
28c7a19d
N		 3621 } else {
3622 ret = d40_lcla_allocate(base);
3623 if (ret) {
3624 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3625 goto failure;
3626 }
8d318a50
LW		 3627 }
3628
3629 spin_lock_init(&base->lcla_pool.lock);
3630
8d318a50
LW		 3631 base->irq = platform_get_irq(pdev, 0);
3632
3633 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 3634 if (ret) {
6db5a8ba 3635 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 3636 goto failure;
3637 }
3638
28c7a19d
N		 3639 if (base->plat_data->use_esram_lcla) {
3640
3641 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3642 if (IS_ERR(base->lcpa_regulator)) {
3643 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
8581bbcd 3644 ret = PTR_ERR(base->lcpa_regulator);
28c7a19d
N		 3645 base->lcpa_regulator = NULL;
3646 goto failure;
3647 }
3648
3649 ret = regulator_enable(base->lcpa_regulator);
3650 if (ret) {
3651 d40_err(&pdev->dev,
3652 "Failed to enable lcpa_regulator\n");
3653 regulator_put(base->lcpa_regulator);
3654 base->lcpa_regulator = NULL;
3655 goto failure;
3656 }
3657 }
3658
2dafca17
UH		 3659 writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3660
3661 pm_runtime_irq_safe(base->dev);
3662 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3663 pm_runtime_use_autosuspend(base->dev);
3664 pm_runtime_mark_last_busy(base->dev);
3665 pm_runtime_set_active(base->dev);
3666 pm_runtime_enable(base->dev);
3667
8581bbcd
WY		 3668 ret = d40_dmaengine_init(base, num_reserved_chans);
3669 if (ret)
8d318a50
LW		 3670 goto failure;
3671
b96710e5 3672 base->dev->dma_parms = &base->dma_parms;
8581bbcd
WY		 3673 ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3674 if (ret) {
b96710e5
PF		 3675 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3676 goto failure;
3677 }
3678
8d318a50
LW		 3679 d40_hw_init(base);
3680
fa332de5 3681 if (np) {
8581bbcd
WY		 3682 ret = of_dma_controller_register(np, d40_xlate, NULL);
3683 if (ret)
fa332de5
LJ		 3684 dev_err(&pdev->dev,
3685 "could not register of_dma_controller\n");
3686 }
3687
8d318a50
LW		 3688 dev_info(base->dev, "initialized\n");
3689 return 0;
3690
3691failure:
a9bae06d
ME		 3692 kmem_cache_destroy(base->desc_slab);
3693 if (base->virtbase)
3694 iounmap(base->virtbase);
026cbc42 3695
a9bae06d
ME		 3696 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3697 iounmap(base->lcla_pool.base);
3698 base->lcla_pool.base = NULL;
3699 }
28c7a19d 3700
a9bae06d
ME		 3701 if (base->lcla_pool.dma_addr)
3702 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3703 SZ_1K * base->num_phy_chans,
3704 DMA_TO_DEVICE);
8d318a50 3705
a9bae06d
ME		 3706 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3707 free_pages((unsigned long)base->lcla_pool.base,
3708 base->lcla_pool.pages);
28c7a19d 3709
a9bae06d
ME		 3710 kfree(base->lcla_pool.base_unaligned);
3711
3712 if (base->phy_lcpa)
3713 release_mem_region(base->phy_lcpa,
3714 base->lcpa_size);
3715 if (base->phy_start)
3716 release_mem_region(base->phy_start,
3717 base->phy_size);
3718 if (base->clk) {
3719 clk_disable_unprepare(base->clk);
3720 clk_put(base->clk);
3721 }
3722
3723 if (base->lcpa_regulator) {
3724 regulator_disable(base->lcpa_regulator);
3725 regulator_put(base->lcpa_regulator);
8d318a50
LW		 3726 }
3727
a9bae06d
ME		 3728 kfree(base->lcla_pool.alloc_map);
3729 kfree(base->lookup_log_chans);
3730 kfree(base->lookup_phy_chans);
3731 kfree(base->phy_res);
3732 kfree(base);
3733report_failure:
6db5a8ba 3734 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 3735 return ret;
3736}
3737
1814a170
LJ		 3738static const struct of_device_id d40_match[] = {
3739 { .compatible = "stericsson,dma40", },
3740 {}
3741};
3742
8d318a50
LW		 3743static struct platform_driver d40_driver = {
3744 .driver = {
8d318a50 3745 .name = D40_NAME,
123e4ca1 3746 .pm = &dma40_pm_ops,
1814a170 3747 .of_match_table = d40_match,
8d318a50
LW		 3748 },
3749};
3750
cb9ab2d8 3751static int __init stedma40_init(void)
8d318a50
LW		 3752{
3753 return platform_driver_probe(&d40_driver, d40_probe);
3754}
a0eb221a 3755subsys_initcall(stedma40_init);
Linux kernel - Deliverables
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