[deliverable/linux.git] / drivers / gpio / gpio-dwapb.c

/*
 * Copyright (c) 2011 Jamie Iles
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * All enquiries to support@picochip.com
 */
#include <linux/gpio/driver.h>
/* FIXME: for gpio_get_value(), replace this with direct register read */
#include <linux/gpio.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/platform_data/gpio-dwapb.h>
#include <linux/slab.h>

#define GPIO_SWPORTA_DR		0x00
#define GPIO_SWPORTA_DDR	0x04
#define GPIO_SWPORTB_DR		0x0c
#define GPIO_SWPORTB_DDR	0x10
#define GPIO_SWPORTC_DR		0x18
#define GPIO_SWPORTC_DDR	0x1c
#define GPIO_SWPORTD_DR		0x24
#define GPIO_SWPORTD_DDR	0x28
#define GPIO_INTEN		0x30
#define GPIO_INTMASK		0x34
#define GPIO_INTTYPE_LEVEL	0x38
#define GPIO_INT_POLARITY	0x3c
#define GPIO_INTSTATUS		0x40
#define GPIO_PORTA_DEBOUNCE	0x48
#define GPIO_PORTA_EOI		0x4c
#define GPIO_EXT_PORTA		0x50
#define GPIO_EXT_PORTB		0x54
#define GPIO_EXT_PORTC		0x58
#define GPIO_EXT_PORTD		0x5c

#define DWAPB_MAX_PORTS		4
#define GPIO_EXT_PORT_SIZE	(GPIO_EXT_PORTB - GPIO_EXT_PORTA)
#define GPIO_SWPORT_DR_SIZE	(GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
#define GPIO_SWPORT_DDR_SIZE	(GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)

struct dwapb_gpio;

#ifdef CONFIG_PM_SLEEP
/* Store GPIO context across system-wide suspend/resume transitions */
struct dwapb_context {
	u32 data;
	u32 dir;
	u32 ext;
	u32 int_en;
	u32 int_mask;
	u32 int_type;
	u32 int_pol;
	u32 int_deb;
};
#endif

struct dwapb_gpio_port {
	struct gpio_chip	gc;
	bool			is_registered;
	struct dwapb_gpio	*gpio;
#ifdef CONFIG_PM_SLEEP
	struct dwapb_context	*ctx;
#endif
	unsigned int		idx;
};

struct dwapb_gpio {
	struct	device		*dev;
	void __iomem		*regs;
	struct dwapb_gpio_port	*ports;
	unsigned int		nr_ports;
	struct irq_domain	*domain;
};

static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
{
	struct gpio_chip *gc	= &gpio->ports[0].gc;
	void __iomem *reg_base	= gpio->regs;

	return gc->read_reg(reg_base + offset);
}

static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
			       u32 val)
{
	struct gpio_chip *gc	= &gpio->ports[0].gc;
	void __iomem *reg_base	= gpio->regs;

	gc->write_reg(reg_base + offset, val);
}

static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct dwapb_gpio_port *port = gpiochip_get_data(gc);
	struct dwapb_gpio *gpio = port->gpio;

	return irq_find_mapping(gpio->domain, offset);
}

static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
{
	u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);

	if (gpio_get_value(gpio->ports[0].gc.base + offs))
		v &= ~BIT(offs);
	else
		v |= BIT(offs);

	dwapb_write(gpio, GPIO_INT_POLARITY, v);
}

static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
{
	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
	u32 ret = irq_status;

	while (irq_status) {
		int hwirq = fls(irq_status) - 1;
		int gpio_irq = irq_find_mapping(gpio->domain, hwirq);

		generic_handle_irq(gpio_irq);
		irq_status &= ~BIT(hwirq);

		if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
			== IRQ_TYPE_EDGE_BOTH)
			dwapb_toggle_trigger(gpio, hwirq);
	}

	return ret;
}

static void dwapb_irq_handler(struct irq_desc *desc)
{
	struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	dwapb_do_irq(gpio);

	if (chip->irq_eoi)
		chip->irq_eoi(irq_desc_get_irq_data(desc));
}

static void dwapb_irq_enable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct gpio_chip *gc = &gpio->ports[0].gc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&gc->bgpio_lock, flags);
	val = dwapb_read(gpio, GPIO_INTEN);
	val |= BIT(d->hwirq);
	dwapb_write(gpio, GPIO_INTEN, val);
	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}

static void dwapb_irq_disable(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct gpio_chip *gc = &gpio->ports[0].gc;
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&gc->bgpio_lock, flags);
	val = dwapb_read(gpio, GPIO_INTEN);
	val &= ~BIT(d->hwirq);
	dwapb_write(gpio, GPIO_INTEN, val);
	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
}

static int dwapb_irq_reqres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct gpio_chip *gc = &gpio->ports[0].gc;

	if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
		dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
			irqd_to_hwirq(d));
		return -EINVAL;
	}
	return 0;
}

static void dwapb_irq_relres(struct irq_data *d)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct gpio_chip *gc = &gpio->ports[0].gc;

	gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
}

static int dwapb_irq_set_type(struct irq_data *d, u32 type)
{
	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	struct dwapb_gpio *gpio = igc->private;
	struct gpio_chip *gc = &gpio->ports[0].gc;
	int bit = d->hwirq;
	unsigned long level, polarity, flags;

	if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
		     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		return -EINVAL;

	spin_lock_irqsave(&gc->bgpio_lock, flags);
	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);

	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		level |= BIT(bit);
		dwapb_toggle_trigger(gpio, bit);
		break;
	case IRQ_TYPE_EDGE_RISING:
		level |= BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		level |= BIT(bit);
		polarity &= ~BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		level &= ~BIT(bit);
		polarity |= BIT(bit);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		level &= ~BIT(bit);
		polarity &= ~BIT(bit);
		break;
	}

	irq_setup_alt_chip(d, type);

	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
	dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	return 0;
}

static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
				   unsigned offset, unsigned debounce)
{
	struct dwapb_gpio_port *port = gpiochip_get_data(gc);
	struct dwapb_gpio *gpio = port->gpio;
	unsigned long flags, val_deb;
	unsigned long mask = gc->pin2mask(gc, offset);

	spin_lock_irqsave(&gc->bgpio_lock, flags);

	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
	if (debounce)
		dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
	else
		dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);

	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	return 0;
}

static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
{
	u32 worked;
	struct dwapb_gpio *gpio = dev_id;

	worked = dwapb_do_irq(gpio);

	return worked ? IRQ_HANDLED : IRQ_NONE;
}

static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
				 struct dwapb_gpio_port *port,
				 struct dwapb_port_property *pp)
{
	struct gpio_chip *gc = &port->gc;
	struct device_node *node = pp->node;
	struct irq_chip_generic	*irq_gc = NULL;
	unsigned int hwirq, ngpio = gc->ngpio;
	struct irq_chip_type *ct;
	int err, i;

	gpio->domain = irq_domain_add_linear(node, ngpio,
					     &irq_generic_chip_ops, gpio);
	if (!gpio->domain)
		return;

	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
					     "gpio-dwapb", handle_level_irq,
					     IRQ_NOREQUEST, 0,
					     IRQ_GC_INIT_NESTED_LOCK);
	if (err) {
		dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	if (!irq_gc) {
		irq_domain_remove(gpio->domain);
		gpio->domain = NULL;
		return;
	}

	irq_gc->reg_base = gpio->regs;
	irq_gc->private = gpio;

	for (i = 0; i < 2; i++) {
		ct = &irq_gc->chip_types[i];
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_set_bit;
		ct->chip.irq_unmask = irq_gc_mask_clr_bit;
		ct->chip.irq_set_type = dwapb_irq_set_type;
		ct->chip.irq_enable = dwapb_irq_enable;
		ct->chip.irq_disable = dwapb_irq_disable;
		ct->chip.irq_request_resources = dwapb_irq_reqres;
		ct->chip.irq_release_resources = dwapb_irq_relres;
		ct->regs.ack = GPIO_PORTA_EOI;
		ct->regs.mask = GPIO_INTMASK;
		ct->type = IRQ_TYPE_LEVEL_MASK;
	}

	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	irq_gc->chip_types[1].handler = handle_edge_irq;

	if (!pp->irq_shared) {
		irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
						 gpio);
	} else {
		/*
		 * Request a shared IRQ since where MFD would have devices
		 * using the same irq pin
		 */
		err = devm_request_irq(gpio->dev, pp->irq,
				       dwapb_irq_handler_mfd,
				       IRQF_SHARED, "gpio-dwapb-mfd", gpio);
		if (err) {
			dev_err(gpio->dev, "error requesting IRQ\n");
			irq_domain_remove(gpio->domain);
			gpio->domain = NULL;
			return;
		}
	}

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_create_mapping(gpio->domain, hwirq);

	port->gc.to_irq = dwapb_gpio_to_irq;
}

static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
{
	struct dwapb_gpio_port *port = &gpio->ports[0];
	struct gpio_chip *gc = &port->gc;
	unsigned int ngpio = gc->ngpio;
	irq_hw_number_t hwirq;

	if (!gpio->domain)
		return;

	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
		irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));

	irq_domain_remove(gpio->domain);
	gpio->domain = NULL;
}

static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
			       struct dwapb_port_property *pp,
			       unsigned int offs)
{
	struct dwapb_gpio_port *port;
	void __iomem *dat, *set, *dirout;
	int err;

	port = &gpio->ports[offs];
	port->gpio = gpio;
	port->idx = pp->idx;

#ifdef CONFIG_PM_SLEEP
	port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
	if (!port->ctx)
		return -ENOMEM;
#endif

	dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
	set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
	dirout = gpio->regs + GPIO_SWPORTA_DDR +
		(pp->idx * GPIO_SWPORT_DDR_SIZE);

	err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
			 NULL, false);
	if (err) {
		dev_err(gpio->dev, "failed to init gpio chip for %s\n",
			pp->name);
		return err;
	}

#ifdef CONFIG_OF_GPIO
	port->gc.of_node = pp->node;
#endif
	port->gc.ngpio = pp->ngpio;
	port->gc.base = pp->gpio_base;

	/* Only port A support debounce */
	if (pp->idx == 0)
		port->gc.set_debounce = dwapb_gpio_set_debounce;

	if (pp->irq)
		dwapb_configure_irqs(gpio, port, pp);

	err = gpiochip_add_data(&port->gc, port);
	if (err)
		dev_err(gpio->dev, "failed to register gpiochip for %s\n",
			pp->name);
	else
		port->is_registered = true;

	return err;
}

static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
{
	unsigned int m;

	for (m = 0; m < gpio->nr_ports; ++m)
		if (gpio->ports[m].is_registered)
			gpiochip_remove(&gpio->ports[m].gc);
}

static struct dwapb_platform_data *
dwapb_gpio_get_pdata_of(struct device *dev)
{
	struct device_node *node, *port_np;
	struct dwapb_platform_data *pdata;
	struct dwapb_port_property *pp;
	int nports;
	int i;

	node = dev->of_node;
	if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
		return ERR_PTR(-ENODEV);

	nports = of_get_child_count(node);
	if (nports == 0)
		return ERR_PTR(-ENODEV);

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return ERR_PTR(-ENOMEM);

	pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
	if (!pdata->properties)
		return ERR_PTR(-ENOMEM);

	pdata->nports = nports;

	i = 0;
	for_each_child_of_node(node, port_np) {
		pp = &pdata->properties[i++];
		pp->node = port_np;

		if (of_property_read_u32(port_np, "reg", &pp->idx) ||
		    pp->idx >= DWAPB_MAX_PORTS) {
			dev_err(dev, "missing/invalid port index for %s\n",
				port_np->full_name);
			return ERR_PTR(-EINVAL);
		}

		if (of_property_read_u32(port_np, "snps,nr-gpios",
					 &pp->ngpio)) {
			dev_info(dev, "failed to get number of gpios for %s\n",
				 port_np->full_name);
			pp->ngpio = 32;
		}

		/*
		 * Only port A can provide interrupts in all configurations of
		 * the IP.
		 */
		if (pp->idx == 0 &&
		    of_property_read_bool(port_np, "interrupt-controller")) {
			pp->irq = irq_of_parse_and_map(port_np, 0);
			if (!pp->irq) {
				dev_warn(dev, "no irq for bank %s\n",
					 port_np->full_name);
			}
		}

		pp->irq_shared	= false;
		pp->gpio_base	= -1;
		pp->name	= port_np->full_name;
	}

	return pdata;
}

static int dwapb_gpio_probe(struct platform_device *pdev)
{
	unsigned int i;
	struct resource *res;
	struct dwapb_gpio *gpio;
	int err;
	struct device *dev = &pdev->dev;
	struct dwapb_platform_data *pdata = dev_get_platdata(dev);

	if (!pdata) {
		pdata = dwapb_gpio_get_pdata_of(dev);
		if (IS_ERR(pdata))
			return PTR_ERR(pdata);
	}

	if (!pdata->nports)
		return -ENODEV;

	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
	if (!gpio)
		return -ENOMEM;

	gpio->dev = &pdev->dev;
	gpio->nr_ports = pdata->nports;

	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
				   sizeof(*gpio->ports), GFP_KERNEL);
	if (!gpio->ports)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(gpio->regs))
		return PTR_ERR(gpio->regs);

	for (i = 0; i < gpio->nr_ports; i++) {
		err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
		if (err)
			goto out_unregister;
	}
	platform_set_drvdata(pdev, gpio);

	return 0;

out_unregister:
	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

	return err;
}

static int dwapb_gpio_remove(struct platform_device *pdev)
{
	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);

	dwapb_gpio_unregister(gpio);
	dwapb_irq_teardown(gpio);

	return 0;
}

static const struct of_device_id dwapb_of_match[] = {
	{ .compatible = "snps,dw-apb-gpio" },
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwapb_of_match);

#ifdef CONFIG_PM_SLEEP
static int dwapb_gpio_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
	struct gpio_chip *gc	= &gpio->ports[0].gc;
	unsigned long flags;
	int i;

	spin_lock_irqsave(&gc->bgpio_lock, flags);
	for (i = 0; i < gpio->nr_ports; i++) {
		unsigned int offset;
		unsigned int idx = gpio->ports[i].idx;
		struct dwapb_context *ctx = gpio->ports[i].ctx;

		BUG_ON(!ctx);

		offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
		ctx->dir = dwapb_read(gpio, offset);

		offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
		ctx->data = dwapb_read(gpio, offset);

		offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
		ctx->ext = dwapb_read(gpio, offset);

		/* Only port A can provide interrupts */
		if (idx == 0) {
			ctx->int_mask	= dwapb_read(gpio, GPIO_INTMASK);
			ctx->int_en	= dwapb_read(gpio, GPIO_INTEN);
			ctx->int_pol	= dwapb_read(gpio, GPIO_INT_POLARITY);
			ctx->int_type	= dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
			ctx->int_deb	= dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);

			/* Mask out interrupts */
			dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
		}
	}
	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	return 0;
}

static int dwapb_gpio_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
	struct gpio_chip *gc	= &gpio->ports[0].gc;
	unsigned long flags;
	int i;

	spin_lock_irqsave(&gc->bgpio_lock, flags);
	for (i = 0; i < gpio->nr_ports; i++) {
		unsigned int offset;
		unsigned int idx = gpio->ports[i].idx;
		struct dwapb_context *ctx = gpio->ports[i].ctx;

		BUG_ON(!ctx);

		offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
		dwapb_write(gpio, offset, ctx->data);

		offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
		dwapb_write(gpio, offset, ctx->dir);

		offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
		dwapb_write(gpio, offset, ctx->ext);

		/* Only port A can provide interrupts */
		if (idx == 0) {
			dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
			dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
			dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
			dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
			dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);

			/* Clear out spurious interrupts */
			dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
		}
	}
	spin_unlock_irqrestore(&gc->bgpio_lock, flags);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
			 dwapb_gpio_resume);

static struct platform_driver dwapb_gpio_driver = {
	.driver		= {
		.name	= "gpio-dwapb",
		.pm	= &dwapb_gpio_pm_ops,
		.of_match_table = of_match_ptr(dwapb_of_match),
	},
	.probe		= dwapb_gpio_probe,
	.remove		= dwapb_gpio_remove,
};

module_platform_driver(dwapb_gpio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jamie Iles");
MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
Commit	Line	Data
7779b345 JI	1	/*
	2	* Copyright (c) 2011 Jamie Iles
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* All enquiries to support@picochip.com
	9	*/
0f4630f3 LW	10	#include <linux/gpio/driver.h>
	11	/* FIXME: for gpio_get_value(), replace this with direct register read */
	12	#include <linux/gpio.h>
7779b345 JI	13	#include <linux/err.h>
	14	#include <linux/init.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/io.h>
	17	#include <linux/ioport.h>
	18	#include <linux/irq.h>
	19	#include <linux/irqdomain.h>
	20	#include <linux/module.h>
	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/spinlock.h>
3d2613c4 WC	26	#include <linux/platform_data/gpio-dwapb.h>
3d2613c4 WC	27	#include <linux/slab.h>
7779b345 JI	28
	29	#define GPIO_SWPORTA_DR 0x00
	30	#define GPIO_SWPORTA_DDR 0x04
	31	#define GPIO_SWPORTB_DR 0x0c
	32	#define GPIO_SWPORTB_DDR 0x10
	33	#define GPIO_SWPORTC_DR 0x18
	34	#define GPIO_SWPORTC_DDR 0x1c
	35	#define GPIO_SWPORTD_DR 0x24
	36	#define GPIO_SWPORTD_DDR 0x28
	37	#define GPIO_INTEN 0x30
	38	#define GPIO_INTMASK 0x34
	39	#define GPIO_INTTYPE_LEVEL 0x38
	40	#define GPIO_INT_POLARITY 0x3c
	41	#define GPIO_INTSTATUS 0x40
5d60d9ef	42	#define GPIO_PORTA_DEBOUNCE 0x48
7779b345 JI	43	#define GPIO_PORTA_EOI 0x4c
	44	#define GPIO_EXT_PORTA 0x50
	45	#define GPIO_EXT_PORTB 0x54
	46	#define GPIO_EXT_PORTC 0x58
	47	#define GPIO_EXT_PORTD 0x5c
	48
	49	#define DWAPB_MAX_PORTS 4
	50	#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
	51	#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
	52	#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
	53
	54	struct dwapb_gpio;
	55
1e960dbb WC	56	#ifdef CONFIG_PM_SLEEP
	57	/* Store GPIO context across system-wide suspend/resume transitions */
	58	struct dwapb_context {
	59	u32 data;
	60	u32 dir;
	61	u32 ext;
	62	u32 int_en;
	63	u32 int_mask;
	64	u32 int_type;
	65	u32 int_pol;
	66	u32 int_deb;
	67	};
	68	#endif
	69
7779b345	70	struct dwapb_gpio_port {
0f4630f3	71	struct gpio_chip gc;
7779b345 JI	72	bool is_registered;
7779b345 JI	73	struct dwapb_gpio *gpio;
1e960dbb WC	74	#ifdef CONFIG_PM_SLEEP
	75	struct dwapb_context *ctx;
	76	#endif
	77	unsigned int idx;
7779b345 JI	78	};
	79
	80	struct dwapb_gpio {
	81	struct device *dev;
	82	void __iomem *regs;
	83	struct dwapb_gpio_port *ports;
	84	unsigned int nr_ports;
	85	struct irq_domain *domain;
	86	};
	87
67809b97 WC	88	static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
67809b97 WC	89	{
0f4630f3	90	struct gpio_chip *gc = &gpio->ports[0].gc;
67809b97 WC	91	void __iomem *reg_base = gpio->regs;
67809b97 WC	92
0f4630f3	93	return gc->read_reg(reg_base + offset);
67809b97 WC	94	}
	95
	96	static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
	97	u32 val)
	98	{
0f4630f3	99	struct gpio_chip *gc = &gpio->ports[0].gc;
67809b97 WC	100	void __iomem *reg_base = gpio->regs;
67809b97 WC	101
0f4630f3	102	gc->write_reg(reg_base + offset, val);
67809b97 WC	103	}
67809b97 WC	104
7779b345 JI	105	static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
7779b345 JI	106	{
0f4630f3	107	struct dwapb_gpio_port *port = gpiochip_get_data(gc);
7779b345 JI	108	struct dwapb_gpio *gpio = port->gpio;
	109
	110	return irq_find_mapping(gpio->domain, offset);
	111	}
	112
	113	static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
	114	{
67809b97	115	u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
7779b345	116
0f4630f3	117	if (gpio_get_value(gpio->ports[0].gc.base + offs))
7779b345 JI	118	v &= ~BIT(offs);
	119	else
	120	v \|= BIT(offs);
	121
67809b97	122	dwapb_write(gpio, GPIO_INT_POLARITY, v);
7779b345 JI	123	}
7779b345 JI	124
3d2613c4	125	static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
7779b345	126	{
7779b345	127	u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
3d2613c4	128	u32 ret = irq_status;
7779b345 JI	129
	130	while (irq_status) {
	131	int hwirq = fls(irq_status) - 1;
	132	int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
	133
	134	generic_handle_irq(gpio_irq);
	135	irq_status &= ~BIT(hwirq);
	136
	137	if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
	138	== IRQ_TYPE_EDGE_BOTH)
	139	dwapb_toggle_trigger(gpio, hwirq);
	140	}
	141
3d2613c4 WC	142	return ret;
	143	}
	144
bd0b9ac4	145	static void dwapb_irq_handler(struct irq_desc *desc)
3d2613c4	146	{
476f8b4c	147	struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
3d2613c4 WC	148	struct irq_chip *chip = irq_desc_get_chip(desc);
	149
	150	dwapb_do_irq(gpio);
	151
7779b345 JI	152	if (chip->irq_eoi)
	153	chip->irq_eoi(irq_desc_get_irq_data(desc));
	154	}
	155
	156	static void dwapb_irq_enable(struct irq_data *d)
	157	{
	158	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	159	struct dwapb_gpio *gpio = igc->private;
0f4630f3	160	struct gpio_chip *gc = &gpio->ports[0].gc;
7779b345 JI	161	unsigned long flags;
	162	u32 val;
	163
0f4630f3	164	spin_lock_irqsave(&gc->bgpio_lock, flags);
67809b97	165	val = dwapb_read(gpio, GPIO_INTEN);
7779b345	166	val \|= BIT(d->hwirq);
67809b97	167	dwapb_write(gpio, GPIO_INTEN, val);
0f4630f3	168	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
7779b345 JI	169	}
	170
	171	static void dwapb_irq_disable(struct irq_data *d)
	172	{
	173	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	174	struct dwapb_gpio *gpio = igc->private;
0f4630f3	175	struct gpio_chip *gc = &gpio->ports[0].gc;
7779b345 JI	176	unsigned long flags;
	177	u32 val;
	178
0f4630f3	179	spin_lock_irqsave(&gc->bgpio_lock, flags);
67809b97	180	val = dwapb_read(gpio, GPIO_INTEN);
7779b345	181	val &= ~BIT(d->hwirq);
67809b97	182	dwapb_write(gpio, GPIO_INTEN, val);
0f4630f3	183	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
7779b345 JI	184	}
7779b345 JI	185
57ef0428	186	static int dwapb_irq_reqres(struct irq_data *d)
7779b345 JI	187	{
	188	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	189	struct dwapb_gpio *gpio = igc->private;
0f4630f3	190	struct gpio_chip *gc = &gpio->ports[0].gc;
7779b345	191
0f4630f3	192	if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
7779b345 JI	193	dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
7779b345 JI	194	irqd_to_hwirq(d));
57ef0428 LW	195	return -EINVAL;
57ef0428 LW	196	}
7779b345 JI	197	return 0;
	198	}
	199
57ef0428	200	static void dwapb_irq_relres(struct irq_data *d)
7779b345 JI	201	{
	202	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	203	struct dwapb_gpio *gpio = igc->private;
0f4630f3	204	struct gpio_chip *gc = &gpio->ports[0].gc;
7779b345	205
0f4630f3	206	gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
7779b345 JI	207	}
	208
	209	static int dwapb_irq_set_type(struct irq_data *d, u32 type)
	210	{
	211	struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
	212	struct dwapb_gpio *gpio = igc->private;
0f4630f3	213	struct gpio_chip *gc = &gpio->ports[0].gc;
7779b345 JI	214	int bit = d->hwirq;
	215	unsigned long level, polarity, flags;
	216
	217	if (type & ~(IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING \|
	218	IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
	219	return -EINVAL;
	220
0f4630f3	221	spin_lock_irqsave(&gc->bgpio_lock, flags);
67809b97 WC	222	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
67809b97 WC	223	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
7779b345 JI	224
	225	switch (type) {
	226	case IRQ_TYPE_EDGE_BOTH:
	227	level \|= BIT(bit);
	228	dwapb_toggle_trigger(gpio, bit);
	229	break;
	230	case IRQ_TYPE_EDGE_RISING:
	231	level \|= BIT(bit);
	232	polarity \|= BIT(bit);
	233	break;
	234	case IRQ_TYPE_EDGE_FALLING:
	235	level \|= BIT(bit);
	236	polarity &= ~BIT(bit);
	237	break;
	238	case IRQ_TYPE_LEVEL_HIGH:
	239	level &= ~BIT(bit);
	240	polarity \|= BIT(bit);
	241	break;
	242	case IRQ_TYPE_LEVEL_LOW:
	243	level &= ~BIT(bit);
	244	polarity &= ~BIT(bit);
	245	break;
	246	}
	247
6a2f4b7d SAS	248	irq_setup_alt_chip(d, type);
6a2f4b7d SAS	249
67809b97 WC	250	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
67809b97 WC	251	dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
0f4630f3	252	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
7779b345 JI	253
	254	return 0;
	255	}
	256
5d60d9ef WC	257	static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
	258	unsigned offset, unsigned debounce)
	259	{
0f4630f3	260	struct dwapb_gpio_port *port = gpiochip_get_data(gc);
5d60d9ef WC	261	struct dwapb_gpio *gpio = port->gpio;
5d60d9ef WC	262	unsigned long flags, val_deb;
0f4630f3	263	unsigned long mask = gc->pin2mask(gc, offset);
5d60d9ef	264
0f4630f3	265	spin_lock_irqsave(&gc->bgpio_lock, flags);
5d60d9ef WC	266
	267	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
	268	if (debounce)
	269	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb \| mask);
	270	else
	271	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
	272
0f4630f3	273	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
5d60d9ef WC	274
	275	return 0;
	276	}
	277
3d2613c4 WC	278	static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
	279	{
	280	u32 worked;
	281	struct dwapb_gpio *gpio = dev_id;
	282
	283	worked = dwapb_do_irq(gpio);
	284
	285	return worked ? IRQ_HANDLED : IRQ_NONE;
	286	}
	287
7779b345	288	static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
3d2613c4 WC	289	struct dwapb_gpio_port *port,
3d2613c4 WC	290	struct dwapb_port_property *pp)
7779b345	291	{
0f4630f3	292	struct gpio_chip *gc = &port->gc;
3d2613c4 WC	293	struct device_node *node = pp->node;
3d2613c4 WC	294	struct irq_chip_generic *irq_gc = NULL;
7779b345 JI	295	unsigned int hwirq, ngpio = gc->ngpio;
7779b345 JI	296	struct irq_chip_type *ct;
3d2613c4	297	int err, i;
7779b345 JI	298
	299	gpio->domain = irq_domain_add_linear(node, ngpio,
	300	&irq_generic_chip_ops, gpio);
	301	if (!gpio->domain)
	302	return;
	303
6a2f4b7d	304	err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
7779b345 JI	305	"gpio-dwapb", handle_level_irq,
	306	IRQ_NOREQUEST, 0,
	307	IRQ_GC_INIT_NESTED_LOCK);
	308	if (err) {
	309	dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
	310	irq_domain_remove(gpio->domain);
	311	gpio->domain = NULL;
	312	return;
	313	}
	314
	315	irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
	316	if (!irq_gc) {
	317	irq_domain_remove(gpio->domain);
	318	gpio->domain = NULL;
	319	return;
	320	}
	321
	322	irq_gc->reg_base = gpio->regs;
	323	irq_gc->private = gpio;
	324
6a2f4b7d SAS	325	for (i = 0; i < 2; i++) {
	326	ct = &irq_gc->chip_types[i];
	327	ct->chip.irq_ack = irq_gc_ack_set_bit;
	328	ct->chip.irq_mask = irq_gc_mask_set_bit;
	329	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
	330	ct->chip.irq_set_type = dwapb_irq_set_type;
	331	ct->chip.irq_enable = dwapb_irq_enable;
	332	ct->chip.irq_disable = dwapb_irq_disable;
	333	ct->chip.irq_request_resources = dwapb_irq_reqres;
	334	ct->chip.irq_release_resources = dwapb_irq_relres;
	335	ct->regs.ack = GPIO_PORTA_EOI;
	336	ct->regs.mask = GPIO_INTMASK;
	337	ct->type = IRQ_TYPE_LEVEL_MASK;
	338	}
	339
	340	irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
	341	irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
	342	irq_gc->chip_types[1].handler = handle_edge_irq;
7779b345	343
3d2613c4	344	if (!pp->irq_shared) {
6218b88d TG	345	irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
6218b88d TG	346	gpio);
3d2613c4 WC	347	} else {
	348	/*
	349	* Request a shared IRQ since where MFD would have devices
	350	* using the same irq pin
	351	*/
	352	err = devm_request_irq(gpio->dev, pp->irq,
	353	dwapb_irq_handler_mfd,
	354	IRQF_SHARED, "gpio-dwapb-mfd", gpio);
	355	if (err) {
	356	dev_err(gpio->dev, "error requesting IRQ\n");
	357	irq_domain_remove(gpio->domain);
	358	gpio->domain = NULL;
	359	return;
	360	}
	361	}
7779b345 JI	362
	363	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	364	irq_create_mapping(gpio->domain, hwirq);
	365
0f4630f3	366	port->gc.to_irq = dwapb_gpio_to_irq;
7779b345 JI	367	}
	368
	369	static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
	370	{
	371	struct dwapb_gpio_port *port = &gpio->ports[0];
0f4630f3	372	struct gpio_chip *gc = &port->gc;
7779b345 JI	373	unsigned int ngpio = gc->ngpio;
	374	irq_hw_number_t hwirq;
	375
	376	if (!gpio->domain)
	377	return;
	378
	379	for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
	380	irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
	381
	382	irq_domain_remove(gpio->domain);
	383	gpio->domain = NULL;
	384	}
	385
	386	static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
3d2613c4	387	struct dwapb_port_property *pp,
7779b345 JI	388	unsigned int offs)
	389	{
	390	struct dwapb_gpio_port *port;
7779b345 JI	391	void __iomem dat, set, *dirout;
	392	int err;
	393
7779b345 JI	394	port = &gpio->ports[offs];
7779b345 JI	395	port->gpio = gpio;
1e960dbb WC	396	port->idx = pp->idx;
	397
	398	#ifdef CONFIG_PM_SLEEP
	399	port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
	400	if (!port->ctx)
	401	return -ENOMEM;
	402	#endif
7779b345	403
3d2613c4 WC	404	dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
3d2613c4 WC	405	set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
7779b345	406	dirout = gpio->regs + GPIO_SWPORTA_DDR +
3d2613c4	407	(pp->idx * GPIO_SWPORT_DDR_SIZE);
7779b345	408
0f4630f3	409	err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
7779b345 JI	410	NULL, false);
	411	if (err) {
	412	dev_err(gpio->dev, "failed to init gpio chip for %s\n",
3d2613c4	413	pp->name);
7779b345 JI	414	return err;
	415	}
	416
3d2613c4	417	#ifdef CONFIG_OF_GPIO
0f4630f3	418	port->gc.of_node = pp->node;
3d2613c4	419	#endif
0f4630f3 LW	420	port->gc.ngpio = pp->ngpio;
0f4630f3 LW	421	port->gc.base = pp->gpio_base;
7779b345	422
5d60d9ef WC	423	/* Only port A support debounce */
5d60d9ef WC	424	if (pp->idx == 0)
0f4630f3	425	port->gc.set_debounce = dwapb_gpio_set_debounce;
5d60d9ef	426
3d2613c4 WC	427	if (pp->irq)
3d2613c4 WC	428	dwapb_configure_irqs(gpio, port, pp);
7779b345	429
0f4630f3	430	err = gpiochip_add_data(&port->gc, port);
7779b345 JI	431	if (err)
7779b345 JI	432	dev_err(gpio->dev, "failed to register gpiochip for %s\n",
3d2613c4	433	pp->name);
7779b345 JI	434	else
	435	port->is_registered = true;
	436
	437	return err;
	438	}
	439
	440	static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
	441	{
	442	unsigned int m;
	443
	444	for (m = 0; m < gpio->nr_ports; ++m)
	445	if (gpio->ports[m].is_registered)
0f4630f3	446	gpiochip_remove(&gpio->ports[m].gc);
7779b345 JI	447	}
7779b345 JI	448
3d2613c4 WC	449	static struct dwapb_platform_data *
	450	dwapb_gpio_get_pdata_of(struct device *dev)
	451	{
	452	struct device_node node, port_np;
	453	struct dwapb_platform_data *pdata;
	454	struct dwapb_port_property *pp;
	455	int nports;
	456	int i;
	457
	458	node = dev->of_node;
	459	if (!IS_ENABLED(CONFIG_OF_GPIO) \|\| !node)
	460	return ERR_PTR(-ENODEV);
	461
	462	nports = of_get_child_count(node);
	463	if (nports == 0)
	464	return ERR_PTR(-ENODEV);
	465
da9df93e	466	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3d2613c4 WC	467	if (!pdata)
	468	return ERR_PTR(-ENOMEM);
	469
da9df93e AL	470	pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
da9df93e AL	471	if (!pdata->properties)
3d2613c4	472	return ERR_PTR(-ENOMEM);
3d2613c4 WC	473
	474	pdata->nports = nports;
	475
	476	i = 0;
	477	for_each_child_of_node(node, port_np) {
	478	pp = &pdata->properties[i++];
	479	pp->node = port_np;
	480
	481	if (of_property_read_u32(port_np, "reg", &pp->idx) \|\|
	482	pp->idx >= DWAPB_MAX_PORTS) {
	483	dev_err(dev, "missing/invalid port index for %s\n",
	484	port_np->full_name);
3d2613c4 WC	485	return ERR_PTR(-EINVAL);
	486	}
	487
	488	if (of_property_read_u32(port_np, "snps,nr-gpios",
	489	&pp->ngpio)) {
	490	dev_info(dev, "failed to get number of gpios for %s\n",
	491	port_np->full_name);
	492	pp->ngpio = 32;
	493	}
	494
	495	/*
	496	* Only port A can provide interrupts in all configurations of
	497	* the IP.
	498	*/
	499	if (pp->idx == 0 &&
	500	of_property_read_bool(port_np, "interrupt-controller")) {
	501	pp->irq = irq_of_parse_and_map(port_np, 0);
	502	if (!pp->irq) {
	503	dev_warn(dev, "no irq for bank %s\n",
	504	port_np->full_name);
	505	}
	506	}
	507
	508	pp->irq_shared = false;
	509	pp->gpio_base = -1;
	510	pp->name = port_np->full_name;
	511	}
	512
	513	return pdata;
	514	}
	515
7779b345 JI	516	static int dwapb_gpio_probe(struct platform_device *pdev)
7779b345 JI	517	{
3d2613c4	518	unsigned int i;
7779b345 JI	519	struct resource *res;
7779b345 JI	520	struct dwapb_gpio *gpio;
7779b345	521	int err;
3d2613c4 WC	522	struct device *dev = &pdev->dev;
3d2613c4 WC	523	struct dwapb_platform_data *pdata = dev_get_platdata(dev);
3d2613c4	524
da9df93e	525	if (!pdata) {
3d2613c4 WC	526	pdata = dwapb_gpio_get_pdata_of(dev);
	527	if (IS_ERR(pdata))
	528	return PTR_ERR(pdata);
	529	}
7779b345	530
da9df93e AL	531	if (!pdata->nports)
da9df93e AL	532	return -ENODEV;
7779b345	533
3d2613c4	534	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
da9df93e AL	535	if (!gpio)
	536	return -ENOMEM;
	537
3d2613c4 WC	538	gpio->dev = &pdev->dev;
	539	gpio->nr_ports = pdata->nports;
	540
	541	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
7779b345	542	sizeof(*gpio->ports), GFP_KERNEL);
da9df93e AL	543	if (!gpio->ports)
da9df93e AL	544	return -ENOMEM;
7779b345 JI	545
	546	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	547	gpio->regs = devm_ioremap_resource(&pdev->dev, res);
da9df93e AL	548	if (IS_ERR(gpio->regs))
da9df93e AL	549	return PTR_ERR(gpio->regs);
7779b345	550
3d2613c4 WC	551	for (i = 0; i < gpio->nr_ports; i++) {
3d2613c4 WC	552	err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
7779b345 JI	553	if (err)
	554	goto out_unregister;
	555	}
	556	platform_set_drvdata(pdev, gpio);
	557
da9df93e	558	return 0;
7779b345 JI	559
	560	out_unregister:
	561	dwapb_gpio_unregister(gpio);
	562	dwapb_irq_teardown(gpio);
	563
7779b345 JI	564	return err;
	565	}
	566
	567	static int dwapb_gpio_remove(struct platform_device *pdev)
	568	{
	569	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
	570
	571	dwapb_gpio_unregister(gpio);
	572	dwapb_irq_teardown(gpio);
	573
	574	return 0;
	575	}
	576
	577	static const struct of_device_id dwapb_of_match[] = {
	578	{ .compatible = "snps,dw-apb-gpio" },
	579	{ /* Sentinel */ }
	580	};
	581	MODULE_DEVICE_TABLE(of, dwapb_of_match);
	582
1e960dbb WC	583	#ifdef CONFIG_PM_SLEEP
	584	static int dwapb_gpio_suspend(struct device *dev)
	585	{
	586	struct platform_device *pdev = to_platform_device(dev);
	587	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
0f4630f3	588	struct gpio_chip *gc = &gpio->ports[0].gc;
1e960dbb WC	589	unsigned long flags;
	590	int i;
	591
0f4630f3	592	spin_lock_irqsave(&gc->bgpio_lock, flags);
1e960dbb WC	593	for (i = 0; i < gpio->nr_ports; i++) {
	594	unsigned int offset;
	595	unsigned int idx = gpio->ports[i].idx;
	596	struct dwapb_context *ctx = gpio->ports[i].ctx;
	597
58a3b92d	598	BUG_ON(!ctx);
1e960dbb WC	599
	600	offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
	601	ctx->dir = dwapb_read(gpio, offset);
	602
	603	offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
	604	ctx->data = dwapb_read(gpio, offset);
	605
	606	offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
	607	ctx->ext = dwapb_read(gpio, offset);
	608
	609	/* Only port A can provide interrupts */
	610	if (idx == 0) {
	611	ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
	612	ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
	613	ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
	614	ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
	615	ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
	616
	617	/* Mask out interrupts */
	618	dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
	619	}
	620	}
0f4630f3	621	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1e960dbb WC	622
	623	return 0;
	624	}
	625
	626	static int dwapb_gpio_resume(struct device *dev)
	627	{
	628	struct platform_device *pdev = to_platform_device(dev);
	629	struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
0f4630f3	630	struct gpio_chip *gc = &gpio->ports[0].gc;
1e960dbb WC	631	unsigned long flags;
	632	int i;
	633
0f4630f3	634	spin_lock_irqsave(&gc->bgpio_lock, flags);
1e960dbb WC	635	for (i = 0; i < gpio->nr_ports; i++) {
	636	unsigned int offset;
	637	unsigned int idx = gpio->ports[i].idx;
	638	struct dwapb_context *ctx = gpio->ports[i].ctx;
	639
58a3b92d	640	BUG_ON(!ctx);
1e960dbb WC	641
	642	offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
	643	dwapb_write(gpio, offset, ctx->data);
	644
	645	offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
	646	dwapb_write(gpio, offset, ctx->dir);
	647
	648	offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
	649	dwapb_write(gpio, offset, ctx->ext);
	650
	651	/* Only port A can provide interrupts */
	652	if (idx == 0) {
	653	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
	654	dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
	655	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
	656	dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
	657	dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
	658
	659	/* Clear out spurious interrupts */
	660	dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
	661	}
	662	}
0f4630f3	663	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
1e960dbb WC	664
	665	return 0;
	666	}
	667	#endif
	668
	669	static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
	670	dwapb_gpio_resume);
	671
7779b345 JI	672	static struct platform_driver dwapb_gpio_driver = {
	673	.driver = {
	674	.name = "gpio-dwapb",
1e960dbb	675	.pm = &dwapb_gpio_pm_ops,
7779b345 JI	676	.of_match_table = of_match_ptr(dwapb_of_match),
	677	},
	678	.probe = dwapb_gpio_probe,
	679	.remove = dwapb_gpio_remove,
	680	};
	681
	682	module_platform_driver(dwapb_gpio_driver);
	683
	684	MODULE_LICENSE("GPL");
	685	MODULE_AUTHOR("Jamie Iles");
	686	MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");