[deliverable/linux.git] / drivers / gpio / gpio-generic.c

/*
 * Generic driver for memory-mapped GPIO controllers.
 *
 * Copyright 2008 MontaVista Software, Inc.
 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
 * ...``                                                         ```````..
 * ..The simplest form of a GPIO controller that the driver supports is``
 *  `.just a single "data" register, where GPIO state can be read and/or `
 *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
 *        `````````
                                    ___
_/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
__________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
                                                 `....trivial..'~`.```.```
 *                                                    ```````
 *  .```````~~~~`..`.``.``.
 * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
 * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
 *  . register the device with -be`. .with a pair of set/clear-bit registers ,
 *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
 *     ``.`.``...```                  ```.. output pins are also supported.`
 *                        ^^             `````.`````````.,``~``~``~~``````
 *                                                   .                  ^^
 *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
 * .. The expectation is that in at least some cases .    ,-~~~-,
 *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
 *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
 *  ..````````......```````````                             \o_
 *                                                           |
 *                              ^^                          / \
 *
 *           ...`````~~`.....``.`..........``````.`.``.```........``.
 *            `  8, 16, 32 and 64 bits registers are supported, and``.
 *            . the number of GPIOs is determined by the width of   ~
 *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
 *               `.......````.```
 */

#include <linux/init.h>
#include <linux/err.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/log2.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/mod_devicetable.h>
#include <linux/basic_mmio_gpio.h>

static void bgpio_write8(void __iomem *reg, unsigned long data)
{
	writeb(data, reg);
}

static unsigned long bgpio_read8(void __iomem *reg)
{
	return readb(reg);
}

static void bgpio_write16(void __iomem *reg, unsigned long data)
{
	writew(data, reg);
}

static unsigned long bgpio_read16(void __iomem *reg)
{
	return readw(reg);
}

static void bgpio_write32(void __iomem *reg, unsigned long data)
{
	writel(data, reg);
}

static unsigned long bgpio_read32(void __iomem *reg)
{
	return readl(reg);
}

#if BITS_PER_LONG >= 64
static void bgpio_write64(void __iomem *reg, unsigned long data)
{
	writeq(data, reg);
}

static unsigned long bgpio_read64(void __iomem *reg)
{
	return readq(reg);
}
#endif /* BITS_PER_LONG >= 64 */

static void bgpio_write16be(void __iomem *reg, unsigned long data)
{
	iowrite16be(data, reg);
}

static unsigned long bgpio_read16be(void __iomem *reg)
{
	return ioread16be(reg);
}

static void bgpio_write32be(void __iomem *reg, unsigned long data)
{
	iowrite32be(data, reg);
}

static unsigned long bgpio_read32be(void __iomem *reg)
{
	return ioread32be(reg);
}

static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
{
	return 1 << pin;
}

static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
				       unsigned int pin)
{
	return 1 << (bgc->bits - 1 - pin);
}

static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long pinmask = bgc->pin2mask(bgc, gpio);

	if (bgc->dir & pinmask)
		return bgc->read_reg(bgc->reg_set) & pinmask;
	else
		return bgc->read_reg(bgc->reg_dat) & pinmask;
}

static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
}

static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
{
}

static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	if (val)
		bgc->data |= mask;
	else
		bgc->data &= ~mask;

	bgc->write_reg(bgc->reg_dat, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
				 int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);

	if (val)
		bgc->write_reg(bgc->reg_set, mask);
	else
		bgc->write_reg(bgc->reg_clr, mask);
}

static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long mask = bgc->pin2mask(bgc, gpio);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	if (val)
		bgc->data |= mask;
	else
		bgc->data &= ~mask;

	bgc->write_reg(bgc->reg_set, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
				     unsigned long *mask, unsigned long *bits,
				     unsigned long *set_mask,
				     unsigned long *clear_mask)
{
	int i;

	*set_mask = 0;
	*clear_mask = 0;

	for (i = 0; i < bgc->bits; i++) {
		if (*mask == 0)
			break;
		if (__test_and_clear_bit(i, mask)) {
			if (test_bit(i, bits))
				*set_mask |= bgc->pin2mask(bgc, i);
			else
				*clear_mask |= bgc->pin2mask(bgc, i);
		}
	}
}

static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
					  unsigned long *mask,
					  unsigned long *bits,
					  void __iomem *reg)
{
	unsigned long flags;
	unsigned long set_mask, clear_mask;

	spin_lock_irqsave(&bgc->lock, flags);

	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);

	bgc->data |= set_mask;
	bgc->data &= ~clear_mask;

	bgc->write_reg(reg, bgc->data);

	spin_unlock_irqrestore(&bgc->lock, flags);
}

static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
			       unsigned long *bits)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
}

static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
				   unsigned long *bits)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
}

static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
					  unsigned long *mask,
					  unsigned long *bits)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long set_mask, clear_mask;

	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);

	if (set_mask)
		bgc->write_reg(bgc->reg_set, set_mask);
	if (clear_mask)
		bgc->write_reg(bgc->reg_clr, clear_mask);
}

static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	return 0;
}

static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
				int val)
{
	return -EINVAL;
}

static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
				int val)
{
	gc->set(gc, gpio, val);

	return 0;
}

static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
	       GPIOF_DIR_OUT : GPIOF_DIR_IN;
}

static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	gc->set(gc, gpio, val);

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir |= bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir |= bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	unsigned long flags;

	gc->set(gc, gpio, val);

	spin_lock_irqsave(&bgc->lock, flags);

	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	bgc->write_reg(bgc->reg_dir, bgc->dir);

	spin_unlock_irqrestore(&bgc->lock, flags);

	return 0;
}

static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);

	return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
	       GPIOF_DIR_IN : GPIOF_DIR_OUT;
}

static int bgpio_setup_accessors(struct device *dev,
				 struct bgpio_chip *bgc,
				 bool bit_be,
				 bool byte_be)
{

	switch (bgc->bits) {
	case 8:
		bgc->read_reg	= bgpio_read8;
		bgc->write_reg	= bgpio_write8;
		break;
	case 16:
		if (byte_be) {
			bgc->read_reg	= bgpio_read16be;
			bgc->write_reg	= bgpio_write16be;
		} else {
			bgc->read_reg	= bgpio_read16;
			bgc->write_reg	= bgpio_write16;
		}
		break;
	case 32:
		if (byte_be) {
			bgc->read_reg	= bgpio_read32be;
			bgc->write_reg	= bgpio_write32be;
		} else {
			bgc->read_reg	= bgpio_read32;
			bgc->write_reg	= bgpio_write32;
		}
		break;
#if BITS_PER_LONG >= 64
	case 64:
		if (byte_be) {
			dev_err(dev,
				"64 bit big endian byte order unsupported\n");
			return -EINVAL;
		} else {
			bgc->read_reg	= bgpio_read64;
			bgc->write_reg	= bgpio_write64;
		}
		break;
#endif /* BITS_PER_LONG >= 64 */
	default:
		dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
		return -EINVAL;
	}

	bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;

	return 0;
}

/*
 * Create the device and allocate the resources.  For setting GPIO's there are
 * three supported configurations:
 *
 *	- single input/output register resource (named "dat").
 *	- set/clear pair (named "set" and "clr").
 *	- single output register resource and single input resource ("set" and
 *	dat").
 *
 * For the single output register, this drives a 1 by setting a bit and a zero
 * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
 * in the set register and clears it by setting a bit in the clear register.
 * The configuration is detected by which resources are present.
 *
 * For setting the GPIO direction, there are three supported configurations:
 *
 *	- simple bidirection GPIO that requires no configuration.
 *	- an output direction register (named "dirout") where a 1 bit
 *	indicates the GPIO is an output.
 *	- an input direction register (named "dirin") where a 1 bit indicates
 *	the GPIO is an input.
 */
static int bgpio_setup_io(struct bgpio_chip *bgc,
			  void __iomem *dat,
			  void __iomem *set,
			  void __iomem *clr,
			  unsigned long flags)
{

	bgc->reg_dat = dat;
	if (!bgc->reg_dat)
		return -EINVAL;

	if (set && clr) {
		bgc->reg_set = set;
		bgc->reg_clr = clr;
		bgc->gc.set = bgpio_set_with_clear;
		bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
	} else if (set && !clr) {
		bgc->reg_set = set;
		bgc->gc.set = bgpio_set_set;
		bgc->gc.set_multiple = bgpio_set_multiple_set;
	} else if (flags & BGPIOF_NO_OUTPUT) {
		bgc->gc.set = bgpio_set_none;
		bgc->gc.set_multiple = NULL;
	} else {
		bgc->gc.set = bgpio_set;
		bgc->gc.set_multiple = bgpio_set_multiple;
	}

	if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
	    (flags & BGPIOF_READ_OUTPUT_REG_SET))
		bgc->gc.get = bgpio_get_set;
	else
		bgc->gc.get = bgpio_get;

	return 0;
}

static int bgpio_setup_direction(struct bgpio_chip *bgc,
				 void __iomem *dirout,
				 void __iomem *dirin,
				 unsigned long flags)
{
	if (dirout && dirin) {
		return -EINVAL;
	} else if (dirout) {
		bgc->reg_dir = dirout;
		bgc->gc.direction_output = bgpio_dir_out;
		bgc->gc.direction_input = bgpio_dir_in;
		bgc->gc.get_direction = bgpio_get_dir;
	} else if (dirin) {
		bgc->reg_dir = dirin;
		bgc->gc.direction_output = bgpio_dir_out_inv;
		bgc->gc.direction_input = bgpio_dir_in_inv;
		bgc->gc.get_direction = bgpio_get_dir_inv;
	} else {
		if (flags & BGPIOF_NO_OUTPUT)
			bgc->gc.direction_output = bgpio_dir_out_err;
		else
			bgc->gc.direction_output = bgpio_simple_dir_out;
		bgc->gc.direction_input = bgpio_simple_dir_in;
	}

	return 0;
}

static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
{
	if (gpio_pin < chip->ngpio)
		return 0;

	return -EINVAL;
}

int bgpio_remove(struct bgpio_chip *bgc)
{
	gpiochip_remove(&bgc->gc);
	return 0;
}
EXPORT_SYMBOL_GPL(bgpio_remove);

int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags)
{
	int ret;

	if (!is_power_of_2(sz))
		return -EINVAL;

	bgc->bits = sz * 8;
	if (bgc->bits > BITS_PER_LONG)
		return -EINVAL;

	spin_lock_init(&bgc->lock);
	bgc->gc.dev = dev;
	bgc->gc.label = dev_name(dev);
	bgc->gc.base = -1;
	bgc->gc.ngpio = bgc->bits;
	bgc->gc.request = bgpio_request;

	ret = bgpio_setup_io(bgc, dat, set, clr, flags);
	if (ret)
		return ret;

	ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
				    flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
	if (ret)
		return ret;

	ret = bgpio_setup_direction(bgc, dirout, dirin, flags);
	if (ret)
		return ret;

	bgc->data = bgc->read_reg(bgc->reg_dat);
	if (bgc->gc.set == bgpio_set_set &&
			!(flags & BGPIOF_UNREADABLE_REG_SET))
		bgc->data = bgc->read_reg(bgc->reg_set);
	if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
		bgc->dir = bgc->read_reg(bgc->reg_dir);

	return ret;
}
EXPORT_SYMBOL_GPL(bgpio_init);

#ifdef CONFIG_GPIO_GENERIC_PLATFORM

static void __iomem *bgpio_map(struct platform_device *pdev,
			       const char *name,
			       resource_size_t sane_sz,
			       int *err)
{
	struct resource *r;
	resource_size_t sz;
	void __iomem *ret;

	*err = 0;

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
	if (!r) {
		*err = -EINVAL;
		return NULL;
	}

	sz = resource_size(r);
	if (sz != sane_sz) {
		*err = -EINVAL;
		return NULL;
	}

	ret = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(ret)) {
		*err = PTR_ERR(ret);
		return NULL;
	}

	return ret;
}

static int bgpio_pdev_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *r;
	void __iomem *dat;
	void __iomem *set;
	void __iomem *clr;
	void __iomem *dirout;
	void __iomem *dirin;
	unsigned long sz;
	unsigned long flags = pdev->id_entry->driver_data;
	int err;
	struct bgpio_chip *bgc;
	struct bgpio_pdata *pdata = dev_get_platdata(dev);

	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
	if (!r)
		return -EINVAL;

	sz = resource_size(r);

	dat = bgpio_map(pdev, "dat", sz, &err);
	if (err)
		return err;

	set = bgpio_map(pdev, "set", sz, &err);
	if (err)
		return err;

	clr = bgpio_map(pdev, "clr", sz, &err);
	if (err)
		return err;

	dirout = bgpio_map(pdev, "dirout", sz, &err);
	if (err)
		return err;

	dirin = bgpio_map(pdev, "dirin", sz, &err);
	if (err)
		return err;

	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
	if (!bgc)
		return -ENOMEM;

	err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
	if (err)
		return err;

	if (pdata) {
		if (pdata->label)
			bgc->gc.label = pdata->label;
		bgc->gc.base = pdata->base;
		if (pdata->ngpio > 0)
			bgc->gc.ngpio = pdata->ngpio;
	}

	platform_set_drvdata(pdev, bgc);

	return gpiochip_add(&bgc->gc);
}

static int bgpio_pdev_remove(struct platform_device *pdev)
{
	struct bgpio_chip *bgc = platform_get_drvdata(pdev);

	return bgpio_remove(bgc);
}

static const struct platform_device_id bgpio_id_table[] = {
	{
		.name		= "basic-mmio-gpio",
		.driver_data	= 0,
	}, {
		.name		= "basic-mmio-gpio-be",
		.driver_data	= BGPIOF_BIG_ENDIAN,
	},
	{ }
};
MODULE_DEVICE_TABLE(platform, bgpio_id_table);

static struct platform_driver bgpio_driver = {
	.driver = {
		.name = "basic-mmio-gpio",
	},
	.id_table = bgpio_id_table,
	.probe = bgpio_pdev_probe,
	.remove = bgpio_pdev_remove,
};

module_platform_driver(bgpio_driver);

#endif /* CONFIG_GPIO_GENERIC_PLATFORM */

MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
aeec56e3	1	/*
c103de24	2	* Generic driver for memory-mapped GPIO controllers.
aeec56e3 AV	3	*
	4	* Copyright 2008 MontaVista Software, Inc.
	5	* Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	* ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
	13	* ...`` ```````..
	14	* ..The simplest form of a GPIO controller that the driver supports is``
	15	* `.just a single "data" register, where GPIO state can be read and/or `
	16	* `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
	17	* `````````
	18	___
	19	_/~~\|___/~\| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
	20	__________\|~$@~~~ %~ /ooooo*o\ .. Implementing such a GPIO .
	21	o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
	22	`....trivial..'~`.```.```
	23	* ```````
	24	* .```````~~~~`..`.``.``.
	25	* . The driver supports `... ,..```.`~~~```````````````....````.``,,
	26	* . big-endian notation, just`. .. A bit more sophisticated controllers ,
	27	* . register the device with -be`. .with a pair of set/clear-bit registers ,
	28	* `.. suffix. ```~~`````....`.` . affecting the data register and the .`
	29	* ``.`.``...``` ```.. output pins are also supported.`
	30	* ^^ `````.`````````.,``~``~``~~``````
	31	* . ^^
	32	* ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
	33	* .. The expectation is that in at least some cases . ,-~~~-,
	34	* .this will be used with roll-your-own ASIC/FPGA .` \ /
	35	* .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
	36	* ..````````......``````````` \o_
	37	* \|
	38	* ^^ / \
	39	*
	40	* ...`````~~`.....``.`..........``````.`.``.```........``.
	41	* ` 8, 16, 32 and 64 bits registers are supported, and``.
	42	* . the number of GPIOs is determined by the width of ~
	43	* .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
	44	* `.......````.```
	45	*/
	46
	47	#include <linux/init.h>
280df6b3	48	#include <linux/err.h>
aeec56e3 AV	49	#include <linux/bug.h>
	50	#include <linux/kernel.h>
	51	#include <linux/module.h>
	52	#include <linux/spinlock.h>
	53	#include <linux/compiler.h>
	54	#include <linux/types.h>
	55	#include <linux/errno.h>
	56	#include <linux/log2.h>
	57	#include <linux/ioport.h>
	58	#include <linux/io.h>
	59	#include <linux/gpio.h>
	60	#include <linux/slab.h>
	61	#include <linux/platform_device.h>
	62	#include <linux/mod_devicetable.h>
	63	#include <linux/basic_mmio_gpio.h>
	64
8467afec	65	static void bgpio_write8(void __iomem *reg, unsigned long data)
aeec56e3	66	{
fd996235	67	writeb(data, reg);
aeec56e3 AV	68	}
aeec56e3 AV	69
8467afec	70	static unsigned long bgpio_read8(void __iomem *reg)
aeec56e3	71	{
fd996235	72	return readb(reg);
8467afec JI	73	}
	74
	75	static void bgpio_write16(void __iomem *reg, unsigned long data)
	76	{
fd996235	77	writew(data, reg);
8467afec JI	78	}
	79
	80	static unsigned long bgpio_read16(void __iomem *reg)
	81	{
fd996235	82	return readw(reg);
8467afec JI	83	}
	84
	85	static void bgpio_write32(void __iomem *reg, unsigned long data)
	86	{
fd996235	87	writel(data, reg);
8467afec JI	88	}
	89
	90	static unsigned long bgpio_read32(void __iomem *reg)
	91	{
fd996235	92	return readl(reg);
8467afec JI	93	}
8467afec JI	94
aeec56e3	95	#if BITS_PER_LONG >= 64
8467afec JI	96	static void bgpio_write64(void __iomem *reg, unsigned long data)
8467afec JI	97	{
fd996235	98	writeq(data, reg);
8467afec JI	99	}
	100
	101	static unsigned long bgpio_read64(void __iomem *reg)
	102	{
fd996235	103	return readq(reg);
aeec56e3	104	}
8467afec	105	#endif /* BITS_PER_LONG >= 64 */
aeec56e3	106
2b78f1e1 AL	107	static void bgpio_write16be(void __iomem *reg, unsigned long data)
	108	{
	109	iowrite16be(data, reg);
	110	}
	111
	112	static unsigned long bgpio_read16be(void __iomem *reg)
	113	{
	114	return ioread16be(reg);
	115	}
	116
	117	static void bgpio_write32be(void __iomem *reg, unsigned long data)
	118	{
	119	iowrite32be(data, reg);
	120	}
	121
	122	static unsigned long bgpio_read32be(void __iomem *reg)
	123	{
	124	return ioread32be(reg);
	125	}
	126
aeec56e3 AV	127	static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
aeec56e3 AV	128	{
8467afec JI	129	return 1 << pin;
	130	}
	131
	132	static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
	133	unsigned int pin)
	134	{
	135	return 1 << (bgc->bits - 1 - pin);
aeec56e3 AV	136	}
aeec56e3 AV	137
b19e7f51 VZ	138	static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
	139	{
	140	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	141	unsigned long pinmask = bgc->pin2mask(bgc, gpio);
	142
	143	if (bgc->dir & pinmask)
	144	return bgc->read_reg(bgc->reg_set) & pinmask;
	145	else
	146	return bgc->read_reg(bgc->reg_dat) & pinmask;
	147	}
	148
aeec56e3 AV	149	static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
	150	{
	151	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	152
25b35da7	153	return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
aeec56e3 AV	154	}
aeec56e3 AV	155
91492a44 RV	156	static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
	157	{
	158	}
	159
aeec56e3 AV	160	static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	161	{
	162	struct bgpio_chip *bgc = to_bgpio_chip(gc);
8467afec	163	unsigned long mask = bgc->pin2mask(bgc, gpio);
aeec56e3 AV	164	unsigned long flags;
aeec56e3 AV	165
aeec56e3 AV	166	spin_lock_irqsave(&bgc->lock, flags);
	167
	168	if (val)
	169	bgc->data \|= mask;
	170	else
	171	bgc->data &= ~mask;
	172
8467afec	173	bgc->write_reg(bgc->reg_dat, bgc->data);
aeec56e3 AV	174
	175	spin_unlock_irqrestore(&bgc->lock, flags);
	176	}
	177
e027d6f9 JI	178	static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
	179	int val)
	180	{
	181	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	182	unsigned long mask = bgc->pin2mask(bgc, gpio);
	183
	184	if (val)
	185	bgc->write_reg(bgc->reg_set, mask);
	186	else
	187	bgc->write_reg(bgc->reg_clr, mask);
	188	}
	189
dd86a0cc JI	190	static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
	191	{
	192	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	193	unsigned long mask = bgc->pin2mask(bgc, gpio);
	194	unsigned long flags;
	195
	196	spin_lock_irqsave(&bgc->lock, flags);
	197
	198	if (val)
	199	bgc->data \|= mask;
	200	else
	201	bgc->data &= ~mask;
	202
	203	bgc->write_reg(bgc->reg_set, bgc->data);
	204
	205	spin_unlock_irqrestore(&bgc->lock, flags);
	206	}
	207
73c4ceda RI	208	static void bgpio_multiple_get_masks(struct bgpio_chip *bgc,
	209	unsigned long mask, unsigned long bits,
	210	unsigned long *set_mask,
	211	unsigned long *clear_mask)
	212	{
	213	int i;
	214
	215	*set_mask = 0;
	216	*clear_mask = 0;
	217
	218	for (i = 0; i < bgc->bits; i++) {
	219	if (*mask == 0)
	220	break;
	221	if (__test_and_clear_bit(i, mask)) {
	222	if (test_bit(i, bits))
	223	*set_mask \|= bgc->pin2mask(bgc, i);
	224	else
	225	*clear_mask \|= bgc->pin2mask(bgc, i);
	226	}
	227	}
	228	}
	229
	230	static void bgpio_set_multiple_single_reg(struct bgpio_chip *bgc,
	231	unsigned long *mask,
	232	unsigned long *bits,
	233	void __iomem *reg)
	234	{
	235	unsigned long flags;
	236	unsigned long set_mask, clear_mask;
	237
	238	spin_lock_irqsave(&bgc->lock, flags);
	239
	240	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
	241
	242	bgc->data \|= set_mask;
	243	bgc->data &= ~clear_mask;
	244
	245	bgc->write_reg(reg, bgc->data);
	246
	247	spin_unlock_irqrestore(&bgc->lock, flags);
	248	}
	249
	250	static void bgpio_set_multiple(struct gpio_chip gc, unsigned long mask,
	251	unsigned long *bits)
	252	{
	253	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	254
	255	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_dat);
	256	}
	257
	258	static void bgpio_set_multiple_set(struct gpio_chip gc, unsigned long mask,
	259	unsigned long *bits)
	260	{
	261	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	262
	263	bgpio_set_multiple_single_reg(bgc, mask, bits, bgc->reg_set);
	264	}
	265
	266	static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
	267	unsigned long *mask,
	268	unsigned long *bits)
	269	{
	270	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	271	unsigned long set_mask, clear_mask;
272
273	bgpio_multiple_get_masks(bgc, mask, bits, &set_mask, &clear_mask);
274
275	if (set_mask)
276	bgc->write_reg(bgc->reg_set, set_mask);
277	if (clear_mask)
278	bgc->write_reg(bgc->reg_clr, clear_mask);
279	}
280
31029116 JI	281	static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
	282	{
	283	return 0;
	284	}
	285
91492a44 RV	286	static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
	287	int val)
	288	{
	289	return -EINVAL;
	290	}
	291
31029116 JI	292	static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
	293	int val)
	294	{
	295	gc->set(gc, gpio, val);
	296
	297	return 0;
	298	}
	299
aeec56e3 AV	300	static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
aeec56e3 AV	301	{
31029116 JI	302	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	303	unsigned long flags;
	304
	305	spin_lock_irqsave(&bgc->lock, flags);
	306
	307	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	308	bgc->write_reg(bgc->reg_dir, bgc->dir);
	309
	310	spin_unlock_irqrestore(&bgc->lock, flags);
	311
aeec56e3 AV	312	return 0;
	313	}
	314
db3b0fcc PZ	315	static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
	316	{
	317	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	318
	319	return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
	320	GPIOF_DIR_OUT : GPIOF_DIR_IN;
	321	}
	322
aeec56e3 AV	323	static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
aeec56e3 AV	324	{
31029116 JI	325	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	326	unsigned long flags;
	327
	328	gc->set(gc, gpio, val);
	329
	330	spin_lock_irqsave(&bgc->lock, flags);
	331
	332	bgc->dir \|= bgc->pin2mask(bgc, gpio);
	333	bgc->write_reg(bgc->reg_dir, bgc->dir);
	334
	335	spin_unlock_irqrestore(&bgc->lock, flags);
	336
	337	return 0;
	338	}
	339
	340	static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
	341	{
	342	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	343	unsigned long flags;
	344
	345	spin_lock_irqsave(&bgc->lock, flags);
	346
	347	bgc->dir \|= bgc->pin2mask(bgc, gpio);
	348	bgc->write_reg(bgc->reg_dir, bgc->dir);
	349
	350	spin_unlock_irqrestore(&bgc->lock, flags);
	351
	352	return 0;
	353	}
	354
	355	static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
	356	{
	357	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	358	unsigned long flags;
	359
e027d6f9 JI	360	gc->set(gc, gpio, val);
e027d6f9 JI	361
31029116 JI	362	spin_lock_irqsave(&bgc->lock, flags);
	363
	364	bgc->dir &= ~bgc->pin2mask(bgc, gpio);
	365	bgc->write_reg(bgc->reg_dir, bgc->dir);
	366
	367	spin_unlock_irqrestore(&bgc->lock, flags);
	368
aeec56e3 AV	369	return 0;
	370	}
	371
db3b0fcc PZ	372	static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
	373	{
	374	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	375
	376	return (bgc->read_reg(bgc->reg_dir) & bgc->pin2mask(bgc, gpio)) ?
	377	GPIOF_DIR_IN : GPIOF_DIR_OUT;
	378	}
	379
280df6b3 JI	380	static int bgpio_setup_accessors(struct device *dev,
280df6b3 JI	381	struct bgpio_chip *bgc,
2b78f1e1 AL	382	bool bit_be,
2b78f1e1 AL	383	bool byte_be)
aeec56e3	384	{
8467afec JI	385
	386	switch (bgc->bits) {
	387	case 8:
	388	bgc->read_reg = bgpio_read8;
	389	bgc->write_reg = bgpio_write8;
	390	break;
	391	case 16:
2b78f1e1 AL	392	if (byte_be) {
	393	bgc->read_reg = bgpio_read16be;
	394	bgc->write_reg = bgpio_write16be;
	395	} else {
	396	bgc->read_reg = bgpio_read16;
	397	bgc->write_reg = bgpio_write16;
	398	}
8467afec JI	399	break;
8467afec JI	400	case 32:
2b78f1e1 AL	401	if (byte_be) {
	402	bgc->read_reg = bgpio_read32be;
	403	bgc->write_reg = bgpio_write32be;
	404	} else {
	405	bgc->read_reg = bgpio_read32;
	406	bgc->write_reg = bgpio_write32;
	407	}
8467afec JI	408	break;
	409	#if BITS_PER_LONG >= 64
	410	case 64:
2b78f1e1 AL	411	if (byte_be) {
	412	dev_err(dev,
	413	"64 bit big endian byte order unsupported\n");
	414	return -EINVAL;
	415	} else {
	416	bgc->read_reg = bgpio_read64;
	417	bgc->write_reg = bgpio_write64;
	418	}
8467afec JI	419	break;
	420	#endif /* BITS_PER_LONG >= 64 */
	421	default:
280df6b3	422	dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
8467afec JI	423	return -EINVAL;
	424	}
	425
2b78f1e1	426	bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
8467afec JI	427
	428	return 0;
	429	}
	430
e027d6f9 JI	431	/*
e027d6f9 JI	432	* Create the device and allocate the resources. For setting GPIO's there are
dd86a0cc	433	* three supported configurations:
e027d6f9	434	*
dd86a0cc	435	* - single input/output register resource (named "dat").
e027d6f9	436	* - set/clear pair (named "set" and "clr").
dd86a0cc JI	437	* - single output register resource and single input resource ("set" and
dd86a0cc JI	438	* dat").
e027d6f9 JI	439	*
	440	* For the single output register, this drives a 1 by setting a bit and a zero
	441	* by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
	442	* in the set register and clears it by setting a bit in the clear register.
	443	* The configuration is detected by which resources are present.
31029116 JI	444	*
	445	* For setting the GPIO direction, there are three supported configurations:
	446	*
	447	* - simple bidirection GPIO that requires no configuration.
	448	* - an output direction register (named "dirout") where a 1 bit
	449	* indicates the GPIO is an output.
	450	* - an input direction register (named "dirin") where a 1 bit indicates
	451	* the GPIO is an input.
e027d6f9	452	*/
280df6b3 JI	453	static int bgpio_setup_io(struct bgpio_chip *bgc,
	454	void __iomem *dat,
	455	void __iomem *set,
b19e7f51 VZ	456	void __iomem *clr,
b19e7f51 VZ	457	unsigned long flags)
8467afec	458	{
aeec56e3	459
280df6b3	460	bgc->reg_dat = dat;
aeec56e3	461	if (!bgc->reg_dat)
280df6b3	462	return -EINVAL;
e027d6f9	463
280df6b3 JI	464	if (set && clr) {
	465	bgc->reg_set = set;
	466	bgc->reg_clr = clr;
e027d6f9	467	bgc->gc.set = bgpio_set_with_clear;
73c4ceda	468	bgc->gc.set_multiple = bgpio_set_multiple_with_clear;
280df6b3 JI	469	} else if (set && !clr) {
280df6b3 JI	470	bgc->reg_set = set;
dd86a0cc	471	bgc->gc.set = bgpio_set_set;
73c4ceda	472	bgc->gc.set_multiple = bgpio_set_multiple_set;
91492a44 RV	473	} else if (flags & BGPIOF_NO_OUTPUT) {
	474	bgc->gc.set = bgpio_set_none;
	475	bgc->gc.set_multiple = NULL;
e027d6f9 JI	476	} else {
e027d6f9 JI	477	bgc->gc.set = bgpio_set;
73c4ceda	478	bgc->gc.set_multiple = bgpio_set_multiple;
aeec56e3 AV	479	}
aeec56e3 AV	480
b19e7f51 VZ	481	if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
	482	(flags & BGPIOF_READ_OUTPUT_REG_SET))
	483	bgc->gc.get = bgpio_get_set;
	484	else
	485	bgc->gc.get = bgpio_get;
dd86a0cc	486
e027d6f9 JI	487	return 0;
	488	}
	489
280df6b3 JI	490	static int bgpio_setup_direction(struct bgpio_chip *bgc,
280df6b3 JI	491	void __iomem *dirout,
91492a44 RV	492	void __iomem *dirin,
91492a44 RV	493	unsigned long flags)
31029116	494	{
280df6b3	495	if (dirout && dirin) {
31029116	496	return -EINVAL;
280df6b3 JI	497	} else if (dirout) {
280df6b3 JI	498	bgc->reg_dir = dirout;
31029116 JI	499	bgc->gc.direction_output = bgpio_dir_out;
31029116 JI	500	bgc->gc.direction_input = bgpio_dir_in;
db3b0fcc	501	bgc->gc.get_direction = bgpio_get_dir;
280df6b3 JI	502	} else if (dirin) {
280df6b3 JI	503	bgc->reg_dir = dirin;
31029116 JI	504	bgc->gc.direction_output = bgpio_dir_out_inv;
31029116 JI	505	bgc->gc.direction_input = bgpio_dir_in_inv;
db3b0fcc	506	bgc->gc.get_direction = bgpio_get_dir_inv;
31029116	507	} else {
91492a44 RV	508	if (flags & BGPIOF_NO_OUTPUT)
	509	bgc->gc.direction_output = bgpio_dir_out_err;
	510	else
	511	bgc->gc.direction_output = bgpio_simple_dir_out;
31029116 JI	512	bgc->gc.direction_input = bgpio_simple_dir_in;
	513	}
	514
	515	return 0;
	516	}
	517
7b42e3db AF	518	static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
	519	{
	520	if (gpio_pin < chip->ngpio)
	521	return 0;
	522
	523	return -EINVAL;
	524	}
	525
4f5b0480	526	int bgpio_remove(struct bgpio_chip *bgc)
280df6b3	527	{
9f5132ae	528	gpiochip_remove(&bgc->gc);
9f5132ae	529	return 0;
280df6b3 JI	530	}
	531	EXPORT_SYMBOL_GPL(bgpio_remove);
	532
4f5b0480 RK	533	int bgpio_init(struct bgpio_chip bgc, struct device dev,
	534	unsigned long sz, void __iomem dat, void __iomem set,
	535	void __iomem clr, void __iomem dirout, void __iomem *dirin,
3e11f7b8	536	unsigned long flags)
e027d6f9	537	{
e027d6f9	538	int ret;
e027d6f9	539
280df6b3 JI	540	if (!is_power_of_2(sz))
280df6b3 JI	541	return -EINVAL;
e027d6f9	542
280df6b3 JI	543	bgc->bits = sz * 8;
	544	if (bgc->bits > BITS_PER_LONG)
	545	return -EINVAL;
	546
	547	spin_lock_init(&bgc->lock);
	548	bgc->gc.dev = dev;
	549	bgc->gc.label = dev_name(dev);
	550	bgc->gc.base = -1;
	551	bgc->gc.ngpio = bgc->bits;
7b42e3db	552	bgc->gc.request = bgpio_request;
280df6b3	553
b19e7f51	554	ret = bgpio_setup_io(bgc, dat, set, clr, flags);
e027d6f9 JI	555	if (ret)
e027d6f9 JI	556	return ret;
aeec56e3	557
2b78f1e1 AL	558	ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
2b78f1e1 AL	559	flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
8467afec JI	560	if (ret)
8467afec JI	561	return ret;
aeec56e3	562
91492a44	563	ret = bgpio_setup_direction(bgc, dirout, dirin, flags);
31029116 JI	564	if (ret)
	565	return ret;
	566
8467afec	567	bgc->data = bgc->read_reg(bgc->reg_dat);
3e11f7b8 SG	568	if (bgc->gc.set == bgpio_set_set &&
	569	!(flags & BGPIOF_UNREADABLE_REG_SET))
	570	bgc->data = bgc->read_reg(bgc->reg_set);
	571	if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
	572	bgc->dir = bgc->read_reg(bgc->reg_dir);
924e7a9f	573
280df6b3 JI	574	return ret;
	575	}
	576	EXPORT_SYMBOL_GPL(bgpio_init);
aeec56e3	577
c103de24	578	#ifdef CONFIG_GPIO_GENERIC_PLATFORM
aeec56e3	579
280df6b3 JI	580	static void __iomem bgpio_map(struct platform_device pdev,
	581	const char *name,
	582	resource_size_t sane_sz,
	583	int *err)
	584	{
280df6b3	585	struct resource *r;
280df6b3 JI	586	resource_size_t sz;
	587	void __iomem *ret;
	588
	589	*err = 0;
	590
	591	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
cf3f2a2c HK	592	if (!r) {
cf3f2a2c HK	593	*err = -EINVAL;
280df6b3	594	return NULL;
cf3f2a2c	595	}
280df6b3 JI	596
	597	sz = resource_size(r);
	598	if (sz != sane_sz) {
	599	*err = -EINVAL;
	600	return NULL;
	601	}
	602
43960b47 HK	603	ret = devm_ioremap_resource(&pdev->dev, r);
	604	if (IS_ERR(ret)) {
	605	*err = PTR_ERR(ret);
280df6b3 JI	606	return NULL;
280df6b3 JI	607	}
aeec56e3 AV	608
	609	return ret;
	610	}
	611
3836309d	612	static int bgpio_pdev_probe(struct platform_device *pdev)
280df6b3 JI	613	{
	614	struct device *dev = &pdev->dev;
	615	struct resource *r;
	616	void __iomem *dat;
	617	void __iomem *set;
	618	void __iomem *clr;
	619	void __iomem *dirout;
	620	void __iomem *dirin;
	621	unsigned long sz;
19338530	622	unsigned long flags = pdev->id_entry->driver_data;
280df6b3 JI	623	int err;
	624	struct bgpio_chip *bgc;
	625	struct bgpio_pdata *pdata = dev_get_platdata(dev);
	626
	627	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
	628	if (!r)
	629	return -EINVAL;
	630
	631	sz = resource_size(r);
	632
	633	dat = bgpio_map(pdev, "dat", sz, &err);
cf3f2a2c HK	634	if (err)
cf3f2a2c HK	635	return err;
280df6b3 JI	636
	637	set = bgpio_map(pdev, "set", sz, &err);
	638	if (err)
	639	return err;
	640
	641	clr = bgpio_map(pdev, "clr", sz, &err);
	642	if (err)
	643	return err;
	644
	645	dirout = bgpio_map(pdev, "dirout", sz, &err);
	646	if (err)
	647	return err;
	648
	649	dirin = bgpio_map(pdev, "dirin", sz, &err);
	650	if (err)
	651	return err;
	652
280df6b3 JI	653	bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
	654	if (!bgc)
	655	return -ENOMEM;
	656
3e11f7b8	657	err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
280df6b3 JI	658	if (err)
	659	return err;
	660
	661	if (pdata) {
781f6d71 PM	662	if (pdata->label)
781f6d71 PM	663	bgc->gc.label = pdata->label;
280df6b3 JI	664	bgc->gc.base = pdata->base;
	665	if (pdata->ngpio > 0)
	666	bgc->gc.ngpio = pdata->ngpio;
	667	}
	668
	669	platform_set_drvdata(pdev, bgc);
	670
	671	return gpiochip_add(&bgc->gc);
	672	}
	673
206210ce	674	static int bgpio_pdev_remove(struct platform_device *pdev)
aeec56e3	675	{
4ddb8ae2	676	struct bgpio_chip *bgc = platform_get_drvdata(pdev);
aeec56e3	677
280df6b3	678	return bgpio_remove(bgc);
aeec56e3 AV	679	}
	680
	681	static const struct platform_device_id bgpio_id_table[] = {
19338530 AS	682	{
	683	.name = "basic-mmio-gpio",
	684	.driver_data = 0,
	685	}, {
	686	.name = "basic-mmio-gpio-be",
	687	.driver_data = BGPIOF_BIG_ENDIAN,
	688	},
	689	{ }
aeec56e3 AV	690	};
	691	MODULE_DEVICE_TABLE(platform, bgpio_id_table);
	692
	693	static struct platform_driver bgpio_driver = {
	694	.driver = {
	695	.name = "basic-mmio-gpio",
	696	},
	697	.id_table = bgpio_id_table,
280df6b3	698	.probe = bgpio_pdev_probe,
8283c4ff	699	.remove = bgpio_pdev_remove,
aeec56e3 AV	700	};
aeec56e3 AV	701
6f61415e	702	module_platform_driver(bgpio_driver);
280df6b3	703
c103de24	704	#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
aeec56e3 AV	705
	706	MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
	707	MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
	708	MODULE_LICENSE("GPL");