gpio: pca953x: Add NXP PCA9698
[deliverable/linux.git] / drivers / gpio / gpio-pca953x.c
CommitLineData
9e60fdcf 1/*
1e191695 2 * PCA953x 4/8/16/24/40 bit I/O ports
9e60fdcf 3 *
4 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
5 * Copyright (C) 2007 Marvell International Ltd.
6 *
7 * Derived from drivers/i2c/chips/pca9539.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 */
13
14#include <linux/module.h>
15#include <linux/init.h>
d120c17f 16#include <linux/gpio.h>
89ea8bbe
MZ
17#include <linux/interrupt.h>
18#include <linux/irq.h>
55ecd263 19#include <linux/irqdomain.h>
9e60fdcf 20#include <linux/i2c.h>
5877457a 21#include <linux/platform_data/pca953x.h>
5a0e3ad6 22#include <linux/slab.h>
1965d303
NC
23#ifdef CONFIG_OF_GPIO
24#include <linux/of_platform.h>
1965d303 25#endif
9e60fdcf 26
33226ffd
HZ
27#define PCA953X_INPUT 0
28#define PCA953X_OUTPUT 1
29#define PCA953X_INVERT 2
30#define PCA953X_DIRECTION 3
31
ae79c190
AS
32#define REG_ADDR_AI 0x80
33
33226ffd
HZ
34#define PCA957X_IN 0
35#define PCA957X_INVRT 1
36#define PCA957X_BKEN 2
37#define PCA957X_PUPD 3
38#define PCA957X_CFG 4
39#define PCA957X_OUT 5
40#define PCA957X_MSK 6
41#define PCA957X_INTS 7
42
43#define PCA_GPIO_MASK 0x00FF
44#define PCA_INT 0x0100
45#define PCA953X_TYPE 0x1000
46#define PCA957X_TYPE 0x2000
89ea8bbe 47
3760f736 48static const struct i2c_device_id pca953x_id[] = {
89f5df01 49 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
33226ffd
HZ
50 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
51 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
52 { "pca9536", 4 | PCA953X_TYPE, },
53 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
54 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
55 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
56 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
57 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
58 { "pca9556", 8 | PCA953X_TYPE, },
59 { "pca9557", 8 | PCA953X_TYPE, },
60 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
61 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
eb32b5aa 62 { "pca9698", 40 | PCA953X_TYPE, },
33226ffd
HZ
63
64 { "max7310", 8 | PCA953X_TYPE, },
65 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
66 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
67 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
68 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
69 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
70 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
ae79c190 71 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
3760f736 72 { }
f5e8ff48 73};
3760f736 74MODULE_DEVICE_TABLE(i2c, pca953x_id);
9e60fdcf 75
f5f0b7aa
GC
76#define MAX_BANK 5
77#define BANK_SZ 8
78
79#define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
80
f3dc3630 81struct pca953x_chip {
9e60fdcf 82 unsigned gpio_start;
f5f0b7aa
GC
83 u8 reg_output[MAX_BANK];
84 u8 reg_direction[MAX_BANK];
6e20fb18 85 struct mutex i2c_lock;
9e60fdcf 86
89ea8bbe
MZ
87#ifdef CONFIG_GPIO_PCA953X_IRQ
88 struct mutex irq_lock;
f5f0b7aa
GC
89 u8 irq_mask[MAX_BANK];
90 u8 irq_stat[MAX_BANK];
91 u8 irq_trig_raise[MAX_BANK];
92 u8 irq_trig_fall[MAX_BANK];
55ecd263 93 struct irq_domain *domain;
89ea8bbe
MZ
94#endif
95
9e60fdcf 96 struct i2c_client *client;
97 struct gpio_chip gpio_chip;
62154991 98 const char *const *names;
33226ffd 99 int chip_type;
9e60fdcf 100};
101
f5f0b7aa
GC
102static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
103 int off)
104{
105 int ret;
106 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
107 int offset = off / BANK_SZ;
108
109 ret = i2c_smbus_read_byte_data(chip->client,
110 (reg << bank_shift) + offset);
111 *val = ret;
112
113 if (ret < 0) {
114 dev_err(&chip->client->dev, "failed reading register\n");
115 return ret;
116 }
117
118 return 0;
119}
120
121static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
122 int off)
123{
124 int ret = 0;
125 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
126 int offset = off / BANK_SZ;
127
128 ret = i2c_smbus_write_byte_data(chip->client,
129 (reg << bank_shift) + offset, val);
130
131 if (ret < 0) {
132 dev_err(&chip->client->dev, "failed writing register\n");
133 return ret;
134 }
135
136 return 0;
137}
138
139static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 140{
33226ffd 141 int ret = 0;
f5e8ff48
GL
142
143 if (chip->gpio_chip.ngpio <= 8)
f5f0b7aa
GC
144 ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
145 else if (chip->gpio_chip.ngpio >= 24) {
146 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
96b70641 147 ret = i2c_smbus_write_i2c_block_data(chip->client,
f5f0b7aa
GC
148 (reg << bank_shift) | REG_ADDR_AI,
149 NBANK(chip), val);
50e44430 150 } else {
33226ffd
HZ
151 switch (chip->chip_type) {
152 case PCA953X_TYPE:
153 ret = i2c_smbus_write_word_data(chip->client,
f5f0b7aa 154 reg << 1, (u16) *val);
33226ffd
HZ
155 break;
156 case PCA957X_TYPE:
157 ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
f5f0b7aa 158 val[0]);
33226ffd
HZ
159 if (ret < 0)
160 break;
161 ret = i2c_smbus_write_byte_data(chip->client,
162 (reg << 1) + 1,
f5f0b7aa 163 val[1]);
33226ffd
HZ
164 break;
165 }
166 }
f5e8ff48
GL
167
168 if (ret < 0) {
169 dev_err(&chip->client->dev, "failed writing register\n");
ab5dc372 170 return ret;
f5e8ff48
GL
171 }
172
173 return 0;
9e60fdcf 174}
175
f5f0b7aa 176static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
9e60fdcf 177{
178 int ret;
179
96b70641 180 if (chip->gpio_chip.ngpio <= 8) {
f5e8ff48 181 ret = i2c_smbus_read_byte_data(chip->client, reg);
96b70641 182 *val = ret;
f5f0b7aa
GC
183 } else if (chip->gpio_chip.ngpio >= 24) {
184 int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
185
96b70641 186 ret = i2c_smbus_read_i2c_block_data(chip->client,
f5f0b7aa
GC
187 (reg << bank_shift) | REG_ADDR_AI,
188 NBANK(chip), val);
96b70641 189 } else {
f5e8ff48 190 ret = i2c_smbus_read_word_data(chip->client, reg << 1);
f5f0b7aa
GC
191 val[0] = (u16)ret & 0xFF;
192 val[1] = (u16)ret >> 8;
96b70641 193 }
9e60fdcf 194 if (ret < 0) {
195 dev_err(&chip->client->dev, "failed reading register\n");
ab5dc372 196 return ret;
9e60fdcf 197 }
198
9e60fdcf 199 return 0;
200}
201
f3dc3630 202static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
9e60fdcf 203{
f3dc3630 204 struct pca953x_chip *chip;
f5f0b7aa 205 u8 reg_val;
33226ffd 206 int ret, offset = 0;
9e60fdcf 207
f3dc3630 208 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 209
6e20fb18 210 mutex_lock(&chip->i2c_lock);
f5f0b7aa 211 reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
33226ffd
HZ
212
213 switch (chip->chip_type) {
214 case PCA953X_TYPE:
215 offset = PCA953X_DIRECTION;
216 break;
217 case PCA957X_TYPE:
218 offset = PCA957X_CFG;
219 break;
220 }
f5f0b7aa 221 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 222 if (ret)
6e20fb18 223 goto exit;
9e60fdcf 224
f5f0b7aa 225 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
226 ret = 0;
227exit:
228 mutex_unlock(&chip->i2c_lock);
229 return ret;
9e60fdcf 230}
231
f3dc3630 232static int pca953x_gpio_direction_output(struct gpio_chip *gc,
9e60fdcf 233 unsigned off, int val)
234{
f3dc3630 235 struct pca953x_chip *chip;
f5f0b7aa 236 u8 reg_val;
33226ffd 237 int ret, offset = 0;
9e60fdcf 238
f3dc3630 239 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 240
6e20fb18 241 mutex_lock(&chip->i2c_lock);
9e60fdcf 242 /* set output level */
243 if (val)
f5f0b7aa
GC
244 reg_val = chip->reg_output[off / BANK_SZ]
245 | (1u << (off % BANK_SZ));
9e60fdcf 246 else
f5f0b7aa
GC
247 reg_val = chip->reg_output[off / BANK_SZ]
248 & ~(1u << (off % BANK_SZ));
9e60fdcf 249
33226ffd
HZ
250 switch (chip->chip_type) {
251 case PCA953X_TYPE:
252 offset = PCA953X_OUTPUT;
253 break;
254 case PCA957X_TYPE:
255 offset = PCA957X_OUT;
256 break;
257 }
f5f0b7aa 258 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 259 if (ret)
6e20fb18 260 goto exit;
9e60fdcf 261
f5f0b7aa 262 chip->reg_output[off / BANK_SZ] = reg_val;
9e60fdcf 263
264 /* then direction */
f5f0b7aa 265 reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
33226ffd
HZ
266 switch (chip->chip_type) {
267 case PCA953X_TYPE:
268 offset = PCA953X_DIRECTION;
269 break;
270 case PCA957X_TYPE:
271 offset = PCA957X_CFG;
272 break;
273 }
f5f0b7aa 274 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 275 if (ret)
6e20fb18 276 goto exit;
9e60fdcf 277
f5f0b7aa 278 chip->reg_direction[off / BANK_SZ] = reg_val;
6e20fb18
RS
279 ret = 0;
280exit:
281 mutex_unlock(&chip->i2c_lock);
282 return ret;
9e60fdcf 283}
284
f3dc3630 285static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
9e60fdcf 286{
f3dc3630 287 struct pca953x_chip *chip;
ae79c190 288 u32 reg_val;
33226ffd 289 int ret, offset = 0;
9e60fdcf 290
f3dc3630 291 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 292
6e20fb18 293 mutex_lock(&chip->i2c_lock);
33226ffd
HZ
294 switch (chip->chip_type) {
295 case PCA953X_TYPE:
296 offset = PCA953X_INPUT;
297 break;
298 case PCA957X_TYPE:
299 offset = PCA957X_IN;
300 break;
301 }
f5f0b7aa 302 ret = pca953x_read_single(chip, offset, &reg_val, off);
6e20fb18 303 mutex_unlock(&chip->i2c_lock);
9e60fdcf 304 if (ret < 0) {
305 /* NOTE: diagnostic already emitted; that's all we should
306 * do unless gpio_*_value_cansleep() calls become different
307 * from their nonsleeping siblings (and report faults).
308 */
309 return 0;
310 }
311
40a625da 312 return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
9e60fdcf 313}
314
f3dc3630 315static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
9e60fdcf 316{
f3dc3630 317 struct pca953x_chip *chip;
f5f0b7aa 318 u8 reg_val;
33226ffd 319 int ret, offset = 0;
9e60fdcf 320
f3dc3630 321 chip = container_of(gc, struct pca953x_chip, gpio_chip);
9e60fdcf 322
6e20fb18 323 mutex_lock(&chip->i2c_lock);
9e60fdcf 324 if (val)
f5f0b7aa
GC
325 reg_val = chip->reg_output[off / BANK_SZ]
326 | (1u << (off % BANK_SZ));
9e60fdcf 327 else
f5f0b7aa
GC
328 reg_val = chip->reg_output[off / BANK_SZ]
329 & ~(1u << (off % BANK_SZ));
9e60fdcf 330
33226ffd
HZ
331 switch (chip->chip_type) {
332 case PCA953X_TYPE:
333 offset = PCA953X_OUTPUT;
334 break;
335 case PCA957X_TYPE:
336 offset = PCA957X_OUT;
337 break;
338 }
f5f0b7aa 339 ret = pca953x_write_single(chip, offset, reg_val, off);
9e60fdcf 340 if (ret)
6e20fb18 341 goto exit;
9e60fdcf 342
f5f0b7aa 343 chip->reg_output[off / BANK_SZ] = reg_val;
6e20fb18
RS
344exit:
345 mutex_unlock(&chip->i2c_lock);
9e60fdcf 346}
347
f5e8ff48 348static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
9e60fdcf 349{
350 struct gpio_chip *gc;
351
352 gc = &chip->gpio_chip;
353
f3dc3630
GL
354 gc->direction_input = pca953x_gpio_direction_input;
355 gc->direction_output = pca953x_gpio_direction_output;
356 gc->get = pca953x_gpio_get_value;
357 gc->set = pca953x_gpio_set_value;
9fb1f39e 358 gc->can_sleep = true;
9e60fdcf 359
360 gc->base = chip->gpio_start;
f5e8ff48
GL
361 gc->ngpio = gpios;
362 gc->label = chip->client->name;
d8f388d8 363 gc->dev = &chip->client->dev;
d72cbed0 364 gc->owner = THIS_MODULE;
77906a54 365 gc->names = chip->names;
9e60fdcf 366}
367
89ea8bbe
MZ
368#ifdef CONFIG_GPIO_PCA953X_IRQ
369static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
370{
371 struct pca953x_chip *chip;
372
373 chip = container_of(gc, struct pca953x_chip, gpio_chip);
0e8f2fda 374 return irq_create_mapping(chip->domain, off);
89ea8bbe
MZ
375}
376
6f5cfc0e 377static void pca953x_irq_mask(struct irq_data *d)
89ea8bbe 378{
6f5cfc0e 379 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
89ea8bbe 380
f5f0b7aa 381 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
89ea8bbe
MZ
382}
383
6f5cfc0e 384static void pca953x_irq_unmask(struct irq_data *d)
89ea8bbe 385{
6f5cfc0e 386 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
89ea8bbe 387
f5f0b7aa 388 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
389}
390
6f5cfc0e 391static void pca953x_irq_bus_lock(struct irq_data *d)
89ea8bbe 392{
6f5cfc0e 393 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
89ea8bbe
MZ
394
395 mutex_lock(&chip->irq_lock);
396}
397
6f5cfc0e 398static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
89ea8bbe 399{
6f5cfc0e 400 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
f5f0b7aa
GC
401 u8 new_irqs;
402 int level, i;
a2cb9aeb
MZ
403
404 /* Look for any newly setup interrupt */
f5f0b7aa
GC
405 for (i = 0; i < NBANK(chip); i++) {
406 new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
407 new_irqs &= ~chip->reg_direction[i];
408
409 while (new_irqs) {
410 level = __ffs(new_irqs);
411 pca953x_gpio_direction_input(&chip->gpio_chip,
412 level + (BANK_SZ * i));
413 new_irqs &= ~(1 << level);
414 }
a2cb9aeb 415 }
89ea8bbe
MZ
416
417 mutex_unlock(&chip->irq_lock);
418}
419
6f5cfc0e 420static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
89ea8bbe 421{
6f5cfc0e 422 struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
f5f0b7aa
GC
423 int bank_nb = d->hwirq / BANK_SZ;
424 u8 mask = 1 << (d->hwirq % BANK_SZ);
89ea8bbe
MZ
425
426 if (!(type & IRQ_TYPE_EDGE_BOTH)) {
427 dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
6f5cfc0e 428 d->irq, type);
89ea8bbe
MZ
429 return -EINVAL;
430 }
431
432 if (type & IRQ_TYPE_EDGE_FALLING)
f5f0b7aa 433 chip->irq_trig_fall[bank_nb] |= mask;
89ea8bbe 434 else
f5f0b7aa 435 chip->irq_trig_fall[bank_nb] &= ~mask;
89ea8bbe
MZ
436
437 if (type & IRQ_TYPE_EDGE_RISING)
f5f0b7aa 438 chip->irq_trig_raise[bank_nb] |= mask;
89ea8bbe 439 else
f5f0b7aa 440 chip->irq_trig_raise[bank_nb] &= ~mask;
89ea8bbe 441
a2cb9aeb 442 return 0;
89ea8bbe
MZ
443}
444
445static struct irq_chip pca953x_irq_chip = {
446 .name = "pca953x",
6f5cfc0e
LB
447 .irq_mask = pca953x_irq_mask,
448 .irq_unmask = pca953x_irq_unmask,
449 .irq_bus_lock = pca953x_irq_bus_lock,
450 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
451 .irq_set_type = pca953x_irq_set_type,
89ea8bbe
MZ
452};
453
f5f0b7aa 454static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
89ea8bbe 455{
f5f0b7aa
GC
456 u8 cur_stat[MAX_BANK];
457 u8 old_stat[MAX_BANK];
458 u8 pendings = 0;
459 u8 trigger[MAX_BANK], triggers = 0;
460 int ret, i, offset = 0;
33226ffd
HZ
461
462 switch (chip->chip_type) {
463 case PCA953X_TYPE:
464 offset = PCA953X_INPUT;
465 break;
466 case PCA957X_TYPE:
467 offset = PCA957X_IN;
468 break;
469 }
f5f0b7aa 470 ret = pca953x_read_regs(chip, offset, cur_stat);
89ea8bbe
MZ
471 if (ret)
472 return 0;
473
474 /* Remove output pins from the equation */
f5f0b7aa
GC
475 for (i = 0; i < NBANK(chip); i++)
476 cur_stat[i] &= chip->reg_direction[i];
89ea8bbe 477
f5f0b7aa 478 memcpy(old_stat, chip->irq_stat, NBANK(chip));
89ea8bbe 479
f5f0b7aa
GC
480 for (i = 0; i < NBANK(chip); i++) {
481 trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
482 triggers += trigger[i];
483 }
484
485 if (!triggers)
89ea8bbe
MZ
486 return 0;
487
f5f0b7aa 488 memcpy(chip->irq_stat, cur_stat, NBANK(chip));
89ea8bbe 489
f5f0b7aa
GC
490 for (i = 0; i < NBANK(chip); i++) {
491 pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
492 (cur_stat[i] & chip->irq_trig_raise[i]);
493 pending[i] &= trigger[i];
494 pendings += pending[i];
495 }
89ea8bbe 496
f5f0b7aa 497 return pendings;
89ea8bbe
MZ
498}
499
500static irqreturn_t pca953x_irq_handler(int irq, void *devid)
501{
502 struct pca953x_chip *chip = devid;
f5f0b7aa
GC
503 u8 pending[MAX_BANK];
504 u8 level;
505 int i;
89ea8bbe 506
f5f0b7aa 507 if (!pca953x_irq_pending(chip, pending))
89ea8bbe
MZ
508 return IRQ_HANDLED;
509
f5f0b7aa
GC
510 for (i = 0; i < NBANK(chip); i++) {
511 while (pending[i]) {
512 level = __ffs(pending[i]);
513 handle_nested_irq(irq_find_mapping(chip->domain,
514 level + (BANK_SZ * i)));
515 pending[i] &= ~(1 << level);
516 }
517 }
89ea8bbe
MZ
518
519 return IRQ_HANDLED;
520}
521
0e8f2fda
GC
522static int pca953x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
523 irq_hw_number_t hwirq)
524{
525 irq_clear_status_flags(irq, IRQ_NOREQUEST);
526 irq_set_chip_data(irq, d->host_data);
527 irq_set_chip(irq, &pca953x_irq_chip);
528 irq_set_nested_thread(irq, true);
529#ifdef CONFIG_ARM
530 set_irq_flags(irq, IRQF_VALID);
531#else
532 irq_set_noprobe(irq);
533#endif
534
535 return 0;
536}
537
538static const struct irq_domain_ops pca953x_irq_simple_ops = {
539 .map = pca953x_gpio_irq_map,
540 .xlate = irq_domain_xlate_twocell,
541};
542
89ea8bbe 543static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
544 const struct i2c_device_id *id,
545 int irq_base)
89ea8bbe
MZ
546{
547 struct i2c_client *client = chip->client;
f5f0b7aa 548 int ret, i, offset = 0;
89ea8bbe 549
c6dcf592 550 if (irq_base != -1
33226ffd 551 && (id->driver_data & PCA_INT)) {
89ea8bbe 552
33226ffd
HZ
553 switch (chip->chip_type) {
554 case PCA953X_TYPE:
555 offset = PCA953X_INPUT;
556 break;
557 case PCA957X_TYPE:
558 offset = PCA957X_IN;
559 break;
560 }
f5f0b7aa 561 ret = pca953x_read_regs(chip, offset, chip->irq_stat);
89ea8bbe 562 if (ret)
b42748c9 563 return ret;
89ea8bbe
MZ
564
565 /*
566 * There is no way to know which GPIO line generated the
567 * interrupt. We have to rely on the previous read for
568 * this purpose.
569 */
f5f0b7aa
GC
570 for (i = 0; i < NBANK(chip); i++)
571 chip->irq_stat[i] &= chip->reg_direction[i];
89ea8bbe
MZ
572 mutex_init(&chip->irq_lock);
573
0e8f2fda 574 chip->domain = irq_domain_add_simple(client->dev.of_node,
55ecd263 575 chip->gpio_chip.ngpio,
0e8f2fda
GC
576 irq_base,
577 &pca953x_irq_simple_ops,
e7a7f972 578 chip);
0e8f2fda
GC
579 if (!chip->domain)
580 return -ENODEV;
89ea8bbe 581
b42748c9
LW
582 ret = devm_request_threaded_irq(&client->dev,
583 client->irq,
89ea8bbe
MZ
584 NULL,
585 pca953x_irq_handler,
17e8b42c 586 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
89ea8bbe
MZ
587 dev_name(&client->dev), chip);
588 if (ret) {
589 dev_err(&client->dev, "failed to request irq %d\n",
590 client->irq);
0e8f2fda 591 return ret;
89ea8bbe
MZ
592 }
593
594 chip->gpio_chip.to_irq = pca953x_gpio_to_irq;
595 }
596
597 return 0;
89ea8bbe
MZ
598}
599
89ea8bbe
MZ
600#else /* CONFIG_GPIO_PCA953X_IRQ */
601static int pca953x_irq_setup(struct pca953x_chip *chip,
c6dcf592
DJ
602 const struct i2c_device_id *id,
603 int irq_base)
89ea8bbe
MZ
604{
605 struct i2c_client *client = chip->client;
89ea8bbe 606
c6dcf592 607 if (irq_base != -1 && (id->driver_data & PCA_INT))
89ea8bbe
MZ
608 dev_warn(&client->dev, "interrupt support not compiled in\n");
609
610 return 0;
611}
89ea8bbe
MZ
612#endif
613
1965d303
NC
614/*
615 * Handlers for alternative sources of platform_data
616 */
617#ifdef CONFIG_OF_GPIO
618/*
619 * Translate OpenFirmware node properties into platform_data
a57339b4 620 * WARNING: This is DEPRECATED and will be removed eventually!
1965d303 621 */
404ba2b8 622static void
6a7b36aa 623pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
1965d303 624{
1965d303 625 struct device_node *node;
1648237d
DE
626 const __be32 *val;
627 int size;
1965d303 628
61c7a080 629 node = client->dev.of_node;
1965d303 630 if (node == NULL)
c6dcf592 631 return;
1965d303 632
c6dcf592 633 *gpio_base = -1;
1648237d 634 val = of_get_property(node, "linux,gpio-base", &size);
a57339b4 635 WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__);
1965d303 636 if (val) {
1648237d
DE
637 if (size != sizeof(*val))
638 dev_warn(&client->dev, "%s: wrong linux,gpio-base\n",
639 node->full_name);
1965d303 640 else
c6dcf592 641 *gpio_base = be32_to_cpup(val);
1965d303
NC
642 }
643
644 val = of_get_property(node, "polarity", NULL);
a57339b4 645 WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__);
1965d303 646 if (val)
c6dcf592 647 *invert = *val;
1965d303
NC
648}
649#else
404ba2b8 650static void
6a7b36aa 651pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
1965d303 652{
25fcf2b7 653 *gpio_base = -1;
1965d303
NC
654}
655#endif
656
3836309d 657static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
658{
659 int ret;
f5f0b7aa 660 u8 val[MAX_BANK];
33226ffd 661
f5f0b7aa 662 ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
33226ffd
HZ
663 if (ret)
664 goto out;
665
f5f0b7aa
GC
666 ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
667 chip->reg_direction);
33226ffd
HZ
668 if (ret)
669 goto out;
670
671 /* set platform specific polarity inversion */
f5f0b7aa
GC
672 if (invert)
673 memset(val, 0xFF, NBANK(chip));
674 else
675 memset(val, 0, NBANK(chip));
676
677 ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
33226ffd
HZ
678out:
679 return ret;
680}
681
3836309d 682static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
33226ffd
HZ
683{
684 int ret;
f5f0b7aa 685 u8 val[MAX_BANK];
33226ffd 686
f5f0b7aa 687 ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
33226ffd
HZ
688 if (ret)
689 goto out;
f5f0b7aa 690 ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
33226ffd
HZ
691 if (ret)
692 goto out;
693
694 /* set platform specific polarity inversion */
f5f0b7aa
GC
695 if (invert)
696 memset(val, 0xFF, NBANK(chip));
697 else
698 memset(val, 0, NBANK(chip));
699 pca953x_write_regs(chip, PCA957X_INVRT, val);
33226ffd
HZ
700
701 /* To enable register 6, 7 to controll pull up and pull down */
f5f0b7aa
GC
702 memset(val, 0x02, NBANK(chip));
703 pca953x_write_regs(chip, PCA957X_BKEN, val);
33226ffd
HZ
704
705 return 0;
706out:
707 return ret;
708}
709
3836309d 710static int pca953x_probe(struct i2c_client *client,
3760f736 711 const struct i2c_device_id *id)
9e60fdcf 712{
f3dc3630
GL
713 struct pca953x_platform_data *pdata;
714 struct pca953x_chip *chip;
6a7b36aa 715 int irq_base = 0;
7ea2aa20 716 int ret;
6a7b36aa 717 u32 invert = 0;
9e60fdcf 718
b42748c9
LW
719 chip = devm_kzalloc(&client->dev,
720 sizeof(struct pca953x_chip), GFP_KERNEL);
1965d303
NC
721 if (chip == NULL)
722 return -ENOMEM;
723
e56aee18 724 pdata = dev_get_platdata(&client->dev);
c6dcf592
DJ
725 if (pdata) {
726 irq_base = pdata->irq_base;
727 chip->gpio_start = pdata->gpio_base;
728 invert = pdata->invert;
729 chip->names = pdata->names;
730 } else {
731 pca953x_get_alt_pdata(client, &chip->gpio_start, &invert);
a57339b4
DJ
732#ifdef CONFIG_OF_GPIO
733 /* If I2C node has no interrupts property, disable GPIO interrupts */
734 if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL)
735 irq_base = -1;
736#endif
1965d303 737 }
9e60fdcf 738
739 chip->client = client;
740
33226ffd 741 chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
77906a54 742
6e20fb18
RS
743 mutex_init(&chip->i2c_lock);
744
9e60fdcf 745 /* initialize cached registers from their original values.
746 * we can't share this chip with another i2c master.
747 */
33226ffd 748 pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
f5e8ff48 749
33226ffd 750 if (chip->chip_type == PCA953X_TYPE)
7ea2aa20 751 ret = device_pca953x_init(chip, invert);
33226ffd 752 else
7ea2aa20
WS
753 ret = device_pca957x_init(chip, invert);
754 if (ret)
b42748c9 755 return ret;
9e60fdcf 756
c6dcf592 757 ret = pca953x_irq_setup(chip, id, irq_base);
89ea8bbe 758 if (ret)
b42748c9 759 return ret;
f5e8ff48
GL
760
761 ret = gpiochip_add(&chip->gpio_chip);
9e60fdcf 762 if (ret)
b42748c9 763 return ret;
9e60fdcf 764
c6dcf592 765 if (pdata && pdata->setup) {
9e60fdcf 766 ret = pdata->setup(client, chip->gpio_chip.base,
767 chip->gpio_chip.ngpio, pdata->context);
768 if (ret < 0)
769 dev_warn(&client->dev, "setup failed, %d\n", ret);
770 }
771
772 i2c_set_clientdata(client, chip);
773 return 0;
9e60fdcf 774}
775
f3dc3630 776static int pca953x_remove(struct i2c_client *client)
9e60fdcf 777{
e56aee18 778 struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
f3dc3630 779 struct pca953x_chip *chip = i2c_get_clientdata(client);
9e60fdcf 780 int ret = 0;
781
c6dcf592 782 if (pdata && pdata->teardown) {
9e60fdcf 783 ret = pdata->teardown(client, chip->gpio_chip.base,
784 chip->gpio_chip.ngpio, pdata->context);
785 if (ret < 0) {
786 dev_err(&client->dev, "%s failed, %d\n",
787 "teardown", ret);
788 return ret;
789 }
790 }
791
792 ret = gpiochip_remove(&chip->gpio_chip);
793 if (ret) {
794 dev_err(&client->dev, "%s failed, %d\n",
795 "gpiochip_remove()", ret);
796 return ret;
797 }
798
9e60fdcf 799 return 0;
800}
801
ed32620e 802static const struct of_device_id pca953x_dt_ids[] = {
89f5df01 803 { .compatible = "nxp,pca9505", },
ed32620e
MR
804 { .compatible = "nxp,pca9534", },
805 { .compatible = "nxp,pca9535", },
806 { .compatible = "nxp,pca9536", },
807 { .compatible = "nxp,pca9537", },
808 { .compatible = "nxp,pca9538", },
809 { .compatible = "nxp,pca9539", },
810 { .compatible = "nxp,pca9554", },
811 { .compatible = "nxp,pca9555", },
812 { .compatible = "nxp,pca9556", },
813 { .compatible = "nxp,pca9557", },
814 { .compatible = "nxp,pca9574", },
815 { .compatible = "nxp,pca9575", },
eb32b5aa 816 { .compatible = "nxp,pca9698", },
ed32620e
MR
817
818 { .compatible = "maxim,max7310", },
819 { .compatible = "maxim,max7312", },
820 { .compatible = "maxim,max7313", },
821 { .compatible = "maxim,max7315", },
822
823 { .compatible = "ti,pca6107", },
824 { .compatible = "ti,tca6408", },
825 { .compatible = "ti,tca6416", },
826 { .compatible = "ti,tca6424", },
827 { }
828};
829
830MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
831
f3dc3630 832static struct i2c_driver pca953x_driver = {
9e60fdcf 833 .driver = {
f3dc3630 834 .name = "pca953x",
ed32620e 835 .of_match_table = pca953x_dt_ids,
9e60fdcf 836 },
f3dc3630
GL
837 .probe = pca953x_probe,
838 .remove = pca953x_remove,
3760f736 839 .id_table = pca953x_id,
9e60fdcf 840};
841
f3dc3630 842static int __init pca953x_init(void)
9e60fdcf 843{
f3dc3630 844 return i2c_add_driver(&pca953x_driver);
9e60fdcf 845}
2f8d1197
DB
846/* register after i2c postcore initcall and before
847 * subsys initcalls that may rely on these GPIOs
848 */
849subsys_initcall(pca953x_init);
9e60fdcf 850
f3dc3630 851static void __exit pca953x_exit(void)
9e60fdcf 852{
f3dc3630 853 i2c_del_driver(&pca953x_driver);
9e60fdcf 854}
f3dc3630 855module_exit(pca953x_exit);
9e60fdcf 856
857MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
f3dc3630 858MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
9e60fdcf 859MODULE_LICENSE("GPL");
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