[deliverable/linux.git] / drivers / gpio / gpio-pxa.c

/*
 *  linux/arch/arm/plat-pxa/gpio.c
 *
 *  Generic PXA GPIO handling
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/slab.h>

/*
 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
 * one set of registers. The register offsets are organized below:
 *
 *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
 * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
 * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
 * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
 *
 * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
 * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
 * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
 *
 * NOTE:
 *   BANK 3 is only available on PXA27x and later processors.
 *   BANK 4 and 5 are only available on PXA935
 */

#define GPLR_OFFSET	0x00
#define GPDR_OFFSET	0x0C
#define GPSR_OFFSET	0x18
#define GPCR_OFFSET	0x24
#define GRER_OFFSET	0x30
#define GFER_OFFSET	0x3C
#define GEDR_OFFSET	0x48
#define GAFR_OFFSET	0x54
#define ED_MASK_OFFSET	0x9C	/* GPIO edge detection for AP side */

#define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))

int pxa_last_gpio;

struct pxa_gpio_chip {
	struct gpio_chip chip;
	void __iomem	*regbase;
	char label[10];

	unsigned long	irq_mask;
	unsigned long	irq_edge_rise;
	unsigned long	irq_edge_fall;

#ifdef CONFIG_PM
	unsigned long	saved_gplr;
	unsigned long	saved_gpdr;
	unsigned long	saved_grer;
	unsigned long	saved_gfer;
#endif
};

enum {
	PXA25X_GPIO = 0,
	PXA26X_GPIO,
	PXA27X_GPIO,
	PXA3XX_GPIO,
	PXA93X_GPIO,
	MMP_GPIO = 0x10,
	MMP2_GPIO,
};

static DEFINE_SPINLOCK(gpio_lock);
static struct pxa_gpio_chip *pxa_gpio_chips;
static int gpio_type;
static void __iomem *gpio_reg_base;

#define for_each_gpio_chip(i, c)			\
	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)

static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
{
	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
}

static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
{
	return &pxa_gpio_chips[gpio_to_bank(gpio)];
}

static inline int gpio_is_pxa_type(int type)
{
	return (type & MMP_GPIO) == 0;
}

static inline int gpio_is_mmp_type(int type)
{
	return (type & MMP_GPIO) != 0;
}

/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
 */
static inline int __gpio_is_inverted(int gpio)
{
	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
		return 1;
	return 0;
}

/*
 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 * function of a GPIO, and GPDRx cannot be altered once configured. It
 * is attributed as "occupied" here (I know this terminology isn't
 * accurate, you are welcome to propose a better one :-)
 */
static inline int __gpio_is_occupied(unsigned gpio)
{
	struct pxa_gpio_chip *pxachip;
	void __iomem *base;
	unsigned long gafr = 0, gpdr = 0;
	int ret, af = 0, dir = 0;

	pxachip = gpio_to_pxachip(gpio);
	base = gpio_chip_base(&pxachip->chip);
	gpdr = readl_relaxed(base + GPDR_OFFSET);

	switch (gpio_type) {
	case PXA25X_GPIO:
	case PXA26X_GPIO:
	case PXA27X_GPIO:
		gafr = readl_relaxed(base + GAFR_OFFSET);
		af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
		dir = gpdr & GPIO_bit(gpio);

		if (__gpio_is_inverted(gpio))
			ret = (af != 1) || (dir == 0);
		else
			ret = (af != 0) || (dir != 0);
		break;
	default:
		ret = gpdr & GPIO_bit(gpio);
		break;
	}
	return ret;
}

#ifdef CONFIG_ARCH_PXA
static inline int __pxa_gpio_to_irq(int gpio)
{
	if (gpio_is_pxa_type(gpio_type))
		return PXA_GPIO_TO_IRQ(gpio);
	return -1;
}

static inline int __pxa_irq_to_gpio(int irq)
{
	if (gpio_is_pxa_type(gpio_type))
		return irq - PXA_GPIO_TO_IRQ(0);
	return -1;
}
#else
static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
static inline int __pxa_irq_to_gpio(int irq) { return -1; }
#endif

#ifdef CONFIG_ARCH_MMP
static inline int __mmp_gpio_to_irq(int gpio)
{
	if (gpio_is_mmp_type(gpio_type))
		return MMP_GPIO_TO_IRQ(gpio);
	return -1;
}

static inline int __mmp_irq_to_gpio(int irq)
{
	if (gpio_is_mmp_type(gpio_type))
		return irq - MMP_GPIO_TO_IRQ(0);
	return -1;
}
#else
static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
static inline int __mmp_irq_to_gpio(int irq) { return -1; }
#endif

static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	int gpio, ret;

	gpio = chip->base + offset;
	ret = __pxa_gpio_to_irq(gpio);
	if (ret >= 0)
		return ret;
	return __mmp_gpio_to_irq(gpio);
}

int pxa_irq_to_gpio(int irq)
{
	int ret;

	ret = __pxa_irq_to_gpio(irq);
	if (ret >= 0)
		return ret;
	return __mmp_irq_to_gpio(irq);
}

static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t value, mask = 1 << offset;
	unsigned long flags;

	spin_lock_irqsave(&gpio_lock, flags);

	value = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		value |= mask;
	else
		value &= ~mask;
	writel_relaxed(value, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_direction_output(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t tmp, mask = 1 << offset;
	unsigned long flags;

	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));

	spin_lock_irqsave(&gpio_lock, flags);

	tmp = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		tmp &= ~mask;
	else
		tmp |= mask;
	writel_relaxed(tmp, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
}

static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	writel_relaxed(1 << offset, gpio_chip_base(chip) +
				(value ? GPSR_OFFSET : GPCR_OFFSET));
}

static int __devinit pxa_init_gpio_chip(int gpio_end)
{
	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
	struct pxa_gpio_chip *chips;

	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
	if (chips == NULL) {
		pr_err("%s: failed to allocate GPIO chips\n", __func__);
		return -ENOMEM;
	}

	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
		struct gpio_chip *c = &chips[i].chip;

		sprintf(chips[i].label, "gpio-%d", i);
		chips[i].regbase = gpio_reg_base + BANK_OFF(i);

		c->base  = gpio;
		c->label = chips[i].label;

		c->direction_input  = pxa_gpio_direction_input;
		c->direction_output = pxa_gpio_direction_output;
		c->get = pxa_gpio_get;
		c->set = pxa_gpio_set;
		c->to_irq = pxa_gpio_to_irq;

		/* number of GPIOs on last bank may be less than 32 */
		c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
		gpiochip_add(c);
	}
	pxa_gpio_chips = chips;
	return 0;
}

/* Update only those GRERx and GFERx edge detection register bits if those
 * bits are set in c->irq_mask
 */
static inline void update_edge_detect(struct pxa_gpio_chip *c)
{
	uint32_t grer, gfer;

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
	grer |= c->irq_edge_rise & c->irq_mask;
	gfer |= c->irq_edge_fall & c->irq_mask;
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct pxa_gpio_chip *c;
	int gpio = pxa_irq_to_gpio(d->irq);
	unsigned long gpdr, mask = GPIO_bit(gpio);

	c = gpio_to_pxachip(gpio);

	if (type == IRQ_TYPE_PROBE) {
		/* Don't mess with enabled GPIOs using preconfigured edges or
		 * GPIOs set to alternate function or to output during probe
		 */
		if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
			return 0;

		if (__gpio_is_occupied(gpio))
			return 0;

		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);

	if (__gpio_is_inverted(gpio))
		writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
	else
		writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);

	if (type & IRQ_TYPE_EDGE_RISING)
		c->irq_edge_rise |= mask;
	else
		c->irq_edge_rise &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		c->irq_edge_fall |= mask;
	else
		c->irq_edge_fall &= ~mask;

	update_edge_detect(c);

	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
		((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
		((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	return 0;
}

static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
	struct pxa_gpio_chip *c;
	int loop, gpio, gpio_base, n;
	unsigned long gedr;

	do {
		loop = 0;
		for_each_gpio_chip(gpio, c) {
			gpio_base = c->chip.base;

			gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
			gedr = gedr & c->irq_mask;
			writel_relaxed(gedr, c->regbase + GEDR_OFFSET);

			n = find_first_bit(&gedr, BITS_PER_LONG);
			while (n < BITS_PER_LONG) {
				loop = 1;

				generic_handle_irq(gpio_to_irq(gpio_base + n));
				n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
			}
		}
	} while (loop);
}

static void pxa_ack_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
}

static void pxa_mask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
	uint32_t grer, gfer;

	c->irq_mask &= ~GPIO_bit(gpio);

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static void pxa_unmask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	c->irq_mask |= GPIO_bit(gpio);
	update_edge_detect(c);
}

static struct irq_chip pxa_muxed_gpio_chip = {
	.name		= "GPIO",
	.irq_ack	= pxa_ack_muxed_gpio,
	.irq_mask	= pxa_mask_muxed_gpio,
	.irq_unmask	= pxa_unmask_muxed_gpio,
	.irq_set_type	= pxa_gpio_irq_type,
};

static int pxa_gpio_nums(void)
{
	int count = 0;

#ifdef CONFIG_ARCH_PXA
	if (cpu_is_pxa25x()) {
#ifdef CONFIG_CPU_PXA26x
		count = 89;
		gpio_type = PXA26X_GPIO;
#elif defined(CONFIG_PXA25x)
		count = 84;
		gpio_type = PXA26X_GPIO;
#endif /* CONFIG_CPU_PXA26x */
	} else if (cpu_is_pxa27x()) {
		count = 120;
		gpio_type = PXA27X_GPIO;
	} else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
		count = 191;
		gpio_type = PXA93X_GPIO;
	} else if (cpu_is_pxa3xx()) {
		count = 127;
		gpio_type = PXA3XX_GPIO;
	}
#endif /* CONFIG_ARCH_PXA */

#ifdef CONFIG_ARCH_MMP
	if (cpu_is_pxa168() || cpu_is_pxa910()) {
		count = 127;
		gpio_type = MMP_GPIO;
	} else if (cpu_is_mmp2()) {
		count = 191;
		gpio_type = MMP2_GPIO;
	}
#endif /* CONFIG_ARCH_MMP */
	return count;
}

static int __devinit pxa_gpio_probe(struct platform_device *pdev)
{
	struct pxa_gpio_chip *c;
	struct resource *res;
	int gpio, irq;
	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;

	pxa_last_gpio = pxa_gpio_nums();
	if (!pxa_last_gpio)
		return -EINVAL;

	irq0 = platform_get_irq_byname(pdev, "gpio0");
	irq1 = platform_get_irq_byname(pdev, "gpio1");
	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
		|| (irq_mux <= 0))
		return -EINVAL;
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EINVAL;
	gpio_reg_base = ioremap(res->start, resource_size(res));
	if (!gpio_reg_base)
		return -EINVAL;

	if (irq0 > 0)
		gpio_offset = 2;

	/* Initialize GPIO chips */
	pxa_init_gpio_chip(pxa_last_gpio);

	/* clear all GPIO edge detects */
	for_each_gpio_chip(gpio, c) {
		writel_relaxed(0, c->regbase + GFER_OFFSET);
		writel_relaxed(0, c->regbase + GRER_OFFSET);
		writel_relaxed(~0,c->regbase + GEDR_OFFSET);
		/* unmask GPIO edge detect for AP side */
		if (gpio_is_mmp_type(gpio_type))
			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
	}

#ifdef CONFIG_ARCH_PXA
	irq = gpio_to_irq(0);
	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
				 handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);

	irq = gpio_to_irq(1);
	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
				 handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
#endif

	for (irq  = gpio_to_irq(gpio_offset);
		irq <= gpio_to_irq(pxa_last_gpio); irq++) {
		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	return 0;
}

static struct platform_driver pxa_gpio_driver = {
	.probe		= pxa_gpio_probe,
	.driver		= {
		.name	= "pxa-gpio",
	},
};

static int __init pxa_gpio_init(void)
{
	return platform_driver_register(&pxa_gpio_driver);
}
postcore_initcall(pxa_gpio_init);

#ifdef CONFIG_PM
static int pxa_gpio_suspend(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
		c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
		c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
		c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);

		/* Clear GPIO transition detect bits */
		writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
	}
	return 0;
}

static void pxa_gpio_resume(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		/* restore level with set/clear */
		writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
		writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);

		writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
		writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
		writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
	}
}
#else
#define pxa_gpio_suspend	NULL
#define pxa_gpio_resume		NULL
#endif

struct syscore_ops pxa_gpio_syscore_ops = {
	.suspend	= pxa_gpio_suspend,
	.resume		= pxa_gpio_resume,
};

static int __init pxa_gpio_sysinit(void)
{
	register_syscore_ops(&pxa_gpio_syscore_ops);
	return 0;
}
postcore_initcall(pxa_gpio_sysinit);
Commit	Line	Data
1c44f5f1	1	/*
38f539a6	2	* linux/arch/arm/plat-pxa/gpio.c
1c44f5f1 PZ	3	*
	4	* Generic PXA GPIO handling
	5	*
	6	* Author: Nicolas Pitre
	7	* Created: Jun 15, 2001
	8	* Copyright: MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
2f8163ba	14	#include <linux/gpio.h>
157d2644	15	#include <linux/gpio-pxa.h>
1c44f5f1	16	#include <linux/init.h>
e3630db1	17	#include <linux/irq.h>
fced80c7	18	#include <linux/io.h>
157d2644	19	#include <linux/platform_device.h>
2eaa03b5	20	#include <linux/syscore_ops.h>
4aa78264	21	#include <linux/slab.h>
1c44f5f1	22
157d2644 HZ	23	/*
	24	* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
	25	* one set of registers. The register offsets are organized below:
	26	*
	27	* GPLR GPDR GPSR GPCR GRER GFER GEDR
	28	* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
	29	* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
	30	* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
	31	*
	32	* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
	33	* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
	34	* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
	35	*
	36	* NOTE:
	37	* BANK 3 is only available on PXA27x and later processors.
	38	* BANK 4 and 5 are only available on PXA935
	39	*/
	40
	41	#define GPLR_OFFSET 0x00
	42	#define GPDR_OFFSET 0x0C
	43	#define GPSR_OFFSET 0x18
	44	#define GPCR_OFFSET 0x24
	45	#define GRER_OFFSET 0x30
	46	#define GFER_OFFSET 0x3C
	47	#define GEDR_OFFSET 0x48
	48	#define GAFR_OFFSET 0x54
be24168f	49	#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
157d2644 HZ	50
157d2644 HZ	51	#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
1c44f5f1	52
3b8e285c EM	53	int pxa_last_gpio;
3b8e285c EM	54
1c44f5f1 PZ	55	struct pxa_gpio_chip {
1c44f5f1 PZ	56	struct gpio_chip chip;
0807da59 EM	57	void __iomem *regbase;
	58	char label[10];
	59
	60	unsigned long irq_mask;
	61	unsigned long irq_edge_rise;
	62	unsigned long irq_edge_fall;
	63
	64	#ifdef CONFIG_PM
	65	unsigned long saved_gplr;
	66	unsigned long saved_gpdr;
	67	unsigned long saved_grer;
	68	unsigned long saved_gfer;
	69	#endif
1c44f5f1 PZ	70	};
1c44f5f1 PZ	71
4929f5a8 HZ	72	enum {
	73	PXA25X_GPIO = 0,
	74	PXA26X_GPIO,
	75	PXA27X_GPIO,
	76	PXA3XX_GPIO,
	77	PXA93X_GPIO,
	78	MMP_GPIO = 0x10,
	79	MMP2_GPIO,
	80	};
	81
0807da59 EM	82	static DEFINE_SPINLOCK(gpio_lock);
0807da59 EM	83	static struct pxa_gpio_chip *pxa_gpio_chips;
4929f5a8	84	static int gpio_type;
157d2644	85	static void __iomem *gpio_reg_base;
0807da59 EM	86
	87	#define for_each_gpio_chip(i, c) \
	88	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
	89
	90	static inline void __iomem gpio_chip_base(struct gpio_chip c)
	91	{
	92	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
	93	}
	94
a065685d	95	static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
0807da59 EM	96	{
	97	return &pxa_gpio_chips[gpio_to_bank(gpio)];
	98	}
	99
4929f5a8 HZ	100	static inline int gpio_is_pxa_type(int type)
	101	{
	102	return (type & MMP_GPIO) == 0;
	103	}
	104
	105	static inline int gpio_is_mmp_type(int type)
	106	{
	107	return (type & MMP_GPIO) != 0;
	108	}
	109
157d2644 HZ	110	/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
	111	* as well as their Alternate Function value being '1' for GPIO in GAFRx.
	112	*/
	113	static inline int __gpio_is_inverted(int gpio)
	114	{
	115	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
	116	return 1;
	117	return 0;
	118	}
	119
	120	/*
	121	* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
	122	* function of a GPIO, and GPDRx cannot be altered once configured. It
	123	* is attributed as "occupied" here (I know this terminology isn't
	124	* accurate, you are welcome to propose a better one :-)
	125	*/
	126	static inline int __gpio_is_occupied(unsigned gpio)
	127	{
	128	struct pxa_gpio_chip *pxachip;
	129	void __iomem *base;
	130	unsigned long gafr = 0, gpdr = 0;
	131	int ret, af = 0, dir = 0;
	132
	133	pxachip = gpio_to_pxachip(gpio);
	134	base = gpio_chip_base(&pxachip->chip);
	135	gpdr = readl_relaxed(base + GPDR_OFFSET);
	136
	137	switch (gpio_type) {
	138	case PXA25X_GPIO:
	139	case PXA26X_GPIO:
	140	case PXA27X_GPIO:
	141	gafr = readl_relaxed(base + GAFR_OFFSET);
	142	af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
	143	dir = gpdr & GPIO_bit(gpio);
	144
	145	if (__gpio_is_inverted(gpio))
	146	ret = (af != 1) \|\| (dir == 0);
	147	else
	148	ret = (af != 0) \|\| (dir != 0);
	149	break;
	150	default:
	151	ret = gpdr & GPIO_bit(gpio);
	152	break;
	153	}
	154	return ret;
	155	}
	156
4929f5a8 HZ	157	#ifdef CONFIG_ARCH_PXA
	158	static inline int __pxa_gpio_to_irq(int gpio)
	159	{
	160	if (gpio_is_pxa_type(gpio_type))
	161	return PXA_GPIO_TO_IRQ(gpio);
	162	return -1;
	163	}
	164
	165	static inline int __pxa_irq_to_gpio(int irq)
	166	{
	167	if (gpio_is_pxa_type(gpio_type))
	168	return irq - PXA_GPIO_TO_IRQ(0);
	169	return -1;
	170	}
	171	#else
	172	static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
	173	static inline int __pxa_irq_to_gpio(int irq) { return -1; }
	174	#endif
	175
	176	#ifdef CONFIG_ARCH_MMP
	177	static inline int __mmp_gpio_to_irq(int gpio)
	178	{
	179	if (gpio_is_mmp_type(gpio_type))
	180	return MMP_GPIO_TO_IRQ(gpio);
	181	return -1;
	182	}
	183
	184	static inline int __mmp_irq_to_gpio(int irq)
	185	{
	186	if (gpio_is_mmp_type(gpio_type))
	187	return irq - MMP_GPIO_TO_IRQ(0);
	188	return -1;
	189	}
	190	#else
	191	static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
	192	static inline int __mmp_irq_to_gpio(int irq) { return -1; }
	193	#endif
	194
	195	static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	196	{
	197	int gpio, ret;
	198
	199	gpio = chip->base + offset;
	200	ret = __pxa_gpio_to_irq(gpio);
	201	if (ret >= 0)
	202	return ret;
	203	return __mmp_gpio_to_irq(gpio);
	204	}
	205
	206	int pxa_irq_to_gpio(int irq)
	207	{
	208	int ret;
	209
	210	ret = __pxa_irq_to_gpio(irq);
	211	if (ret >= 0)
	212	return ret;
	213	return __mmp_irq_to_gpio(irq);
	214	}
	215
1c44f5f1 PZ	216	static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	217	{
0807da59 EM	218	void __iomem *base = gpio_chip_base(chip);
	219	uint32_t value, mask = 1 << offset;
	220	unsigned long flags;
	221
	222	spin_lock_irqsave(&gpio_lock, flags);
	223
df664d20	224	value = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	225	if (__gpio_is_inverted(chip->base + offset))
	226	value \|= mask;
	227	else
	228	value &= ~mask;
df664d20	229	writel_relaxed(value, base + GPDR_OFFSET);
1c44f5f1	230
0807da59	231	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	232	return 0;
	233	}
	234
	235	static int pxa_gpio_direction_output(struct gpio_chip *chip,
0807da59	236	unsigned offset, int value)
1c44f5f1	237	{
0807da59 EM	238	void __iomem *base = gpio_chip_base(chip);
	239	uint32_t tmp, mask = 1 << offset;
	240	unsigned long flags;
	241
df664d20	242	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
0807da59 EM	243
	244	spin_lock_irqsave(&gpio_lock, flags);
	245
df664d20	246	tmp = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	247	if (__gpio_is_inverted(chip->base + offset))
	248	tmp &= ~mask;
	249	else
	250	tmp \|= mask;
df664d20	251	writel_relaxed(tmp, base + GPDR_OFFSET);
1c44f5f1	252
0807da59	253	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	254	return 0;
	255	}
	256
1c44f5f1 PZ	257	static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	258	{
df664d20	259	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
1c44f5f1 PZ	260	}
1c44f5f1 PZ	261
1c44f5f1 PZ	262	static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1c44f5f1 PZ	263	{
df664d20	264	writel_relaxed(1 << offset, gpio_chip_base(chip) +
0807da59	265	(value ? GPSR_OFFSET : GPCR_OFFSET));
1c44f5f1 PZ	266	}
1c44f5f1 PZ	267
157d2644	268	static int __devinit pxa_init_gpio_chip(int gpio_end)
a58fbcd8	269	{
0807da59 EM	270	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
0807da59 EM	271	struct pxa_gpio_chip *chips;
a58fbcd8	272
4aa78264	273	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
0807da59 EM	274	if (chips == NULL) {
	275	pr_err("%s: failed to allocate GPIO chips\n", __func__);
	276	return -ENOMEM;
a58fbcd8	277	}
a58fbcd8	278
0807da59 EM	279	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
0807da59 EM	280	struct gpio_chip *c = &chips[i].chip;
e3630db1	281
0807da59	282	sprintf(chips[i].label, "gpio-%d", i);
157d2644	283	chips[i].regbase = gpio_reg_base + BANK_OFF(i);
0807da59 EM	284
	285	c->base = gpio;
	286	c->label = chips[i].label;
	287
	288	c->direction_input = pxa_gpio_direction_input;
	289	c->direction_output = pxa_gpio_direction_output;
	290	c->get = pxa_gpio_get;
	291	c->set = pxa_gpio_set;
4929f5a8	292	c->to_irq = pxa_gpio_to_irq;
0807da59 EM	293
	294	/* number of GPIOs on last bank may be less than 32 */
	295	c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
	296	gpiochip_add(c);
	297	}
	298	pxa_gpio_chips = chips;
	299	return 0;
	300	}
e3630db1	301
a8f6faeb EM	302	/* Update only those GRERx and GFERx edge detection register bits if those
	303	* bits are set in c->irq_mask
	304	*/
	305	static inline void update_edge_detect(struct pxa_gpio_chip *c)
	306	{
	307	uint32_t grer, gfer;
	308
df664d20 HZ	309	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
df664d20 HZ	310	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
a8f6faeb EM	311	grer \|= c->irq_edge_rise & c->irq_mask;
a8f6faeb EM	312	gfer \|= c->irq_edge_fall & c->irq_mask;
df664d20 HZ	313	writel_relaxed(grer, c->regbase + GRER_OFFSET);
df664d20 HZ	314	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
a8f6faeb EM	315	}
a8f6faeb EM	316
a3f4c927	317	static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
e3630db1	318	{
0807da59	319	struct pxa_gpio_chip *c;
4929f5a8	320	int gpio = pxa_irq_to_gpio(d->irq);
0807da59	321	unsigned long gpdr, mask = GPIO_bit(gpio);
e3630db1	322
a065685d	323	c = gpio_to_pxachip(gpio);
e3630db1	324
	325	if (type == IRQ_TYPE_PROBE) {
	326	/* Don't mess with enabled GPIOs using preconfigured edges or
	327	* GPIOs set to alternate function or to output during probe
	328	*/
0807da59	329	if ((c->irq_edge_rise \| c->irq_edge_fall) & GPIO_bit(gpio))
e3630db1	330	return 0;
689c04a3	331
689c04a3	332	if (__gpio_is_occupied(gpio))
e3630db1	333	return 0;
689c04a3	334
e3630db1	335	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
	336	}
	337
df664d20	338	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
0807da59	339
067455aa	340	if (__gpio_is_inverted(gpio))
df664d20	341	writel_relaxed(gpdr \| mask, c->regbase + GPDR_OFFSET);
067455aa	342	else
df664d20	343	writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
e3630db1	344
e3630db1	345	if (type & IRQ_TYPE_EDGE_RISING)
0807da59	346	c->irq_edge_rise \|= mask;
e3630db1	347	else
0807da59	348	c->irq_edge_rise &= ~mask;
e3630db1	349
e3630db1	350	if (type & IRQ_TYPE_EDGE_FALLING)
0807da59	351	c->irq_edge_fall \|= mask;
e3630db1	352	else
0807da59	353	c->irq_edge_fall &= ~mask;
e3630db1	354
a8f6faeb	355	update_edge_detect(c);
e3630db1	356
a3f4c927	357	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
e3630db1	358	((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
	359	((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	360	return 0;
	361	}
	362
e3630db1	363	static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
e3630db1	364	{
0807da59 EM	365	struct pxa_gpio_chip *c;
	366	int loop, gpio, gpio_base, n;
	367	unsigned long gedr;
e3630db1	368
e3630db1	369	do {
e3630db1	370	loop = 0;
0807da59 EM	371	for_each_gpio_chip(gpio, c) {
	372	gpio_base = c->chip.base;
	373
df664d20	374	gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
0807da59	375	gedr = gedr & c->irq_mask;
df664d20	376	writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
e3630db1	377
0807da59 EM	378	n = find_first_bit(&gedr, BITS_PER_LONG);
	379	while (n < BITS_PER_LONG) {
	380	loop = 1;
e3630db1	381
0807da59 EM	382	generic_handle_irq(gpio_to_irq(gpio_base + n));
	383	n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
	384	}
e3630db1	385	}
	386	} while (loop);
	387	}
	388
a3f4c927	389	static void pxa_ack_muxed_gpio(struct irq_data *d)
e3630db1	390	{
4929f5a8	391	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	392	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59	393
df664d20	394	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
e3630db1	395	}
e3630db1	396
a3f4c927	397	static void pxa_mask_muxed_gpio(struct irq_data *d)
e3630db1	398	{
4929f5a8	399	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	400	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	401	uint32_t grer, gfer;
	402
	403	c->irq_mask &= ~GPIO_bit(gpio);
	404
df664d20 HZ	405	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	406	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	407	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	408	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
e3630db1	409	}
e3630db1	410
a3f4c927	411	static void pxa_unmask_muxed_gpio(struct irq_data *d)
e3630db1	412	{
4929f5a8	413	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	414	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	415
0807da59 EM	416	c->irq_mask \|= GPIO_bit(gpio);
a8f6faeb	417	update_edge_detect(c);
e3630db1	418	}
	419
	420	static struct irq_chip pxa_muxed_gpio_chip = {
	421	.name = "GPIO",
a3f4c927 LB	422	.irq_ack = pxa_ack_muxed_gpio,
	423	.irq_mask = pxa_mask_muxed_gpio,
	424	.irq_unmask = pxa_unmask_muxed_gpio,
	425	.irq_set_type = pxa_gpio_irq_type,
e3630db1	426	};
e3630db1	427
478e223c HZ	428	static int pxa_gpio_nums(void)
	429	{
	430	int count = 0;
	431
	432	#ifdef CONFIG_ARCH_PXA
	433	if (cpu_is_pxa25x()) {
	434	#ifdef CONFIG_CPU_PXA26x
	435	count = 89;
	436	gpio_type = PXA26X_GPIO;
	437	#elif defined(CONFIG_PXA25x)
	438	count = 84;
	439	gpio_type = PXA26X_GPIO;
	440	#endif /* CONFIG_CPU_PXA26x */
	441	} else if (cpu_is_pxa27x()) {
	442	count = 120;
	443	gpio_type = PXA27X_GPIO;
	444	} else if (cpu_is_pxa93x() \|\| cpu_is_pxa95x()) {
	445	count = 191;
	446	gpio_type = PXA93X_GPIO;
	447	} else if (cpu_is_pxa3xx()) {
	448	count = 127;
	449	gpio_type = PXA3XX_GPIO;
	450	}
	451	#endif /* CONFIG_ARCH_PXA */
	452
	453	#ifdef CONFIG_ARCH_MMP
	454	if (cpu_is_pxa168() \|\| cpu_is_pxa910()) {
	455	count = 127;
	456	gpio_type = MMP_GPIO;
	457	} else if (cpu_is_mmp2()) {
	458	count = 191;
	459	gpio_type = MMP2_GPIO;
	460	}
	461	#endif /* CONFIG_ARCH_MMP */
	462	return count;
	463	}
	464
157d2644	465	static int __devinit pxa_gpio_probe(struct platform_device *pdev)
e3630db1	466	{
0807da59	467	struct pxa_gpio_chip *c;
157d2644	468	struct resource *res;
0807da59	469	int gpio, irq;
157d2644	470	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
e3630db1	471
478e223c HZ	472	pxa_last_gpio = pxa_gpio_nums();
478e223c HZ	473	if (!pxa_last_gpio)
157d2644 HZ	474	return -EINVAL;
	475
	476	irq0 = platform_get_irq_byname(pdev, "gpio0");
	477	irq1 = platform_get_irq_byname(pdev, "gpio1");
	478	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	479	if ((irq0 > 0 && irq1 <= 0) \|\| (irq0 <= 0 && irq1 > 0)
	480	\|\| (irq_mux <= 0))
	481	return -EINVAL;
	482	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	483	if (!res)
	484	return -EINVAL;
	485	gpio_reg_base = ioremap(res->start, resource_size(res));
	486	if (!gpio_reg_base)
	487	return -EINVAL;
	488
	489	if (irq0 > 0)
	490	gpio_offset = 2;
e3630db1	491
0807da59	492	/* Initialize GPIO chips */
157d2644	493	pxa_init_gpio_chip(pxa_last_gpio);
0807da59	494
e3630db1	495	/* clear all GPIO edge detects */
0807da59	496	for_each_gpio_chip(gpio, c) {
df664d20 HZ	497	writel_relaxed(0, c->regbase + GFER_OFFSET);
	498	writel_relaxed(0, c->regbase + GRER_OFFSET);
	499	writel_relaxed(~0,c->regbase + GEDR_OFFSET);
be24168f HZ	500	/* unmask GPIO edge detect for AP side */
	501	if (gpio_is_mmp_type(gpio_type))
	502	writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
e3630db1	503	}
e3630db1	504
87c49e20 HZ	505	#ifdef CONFIG_ARCH_PXA
	506	irq = gpio_to_irq(0);
	507	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	508	handle_edge_irq);
	509	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	510	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
	511
	512	irq = gpio_to_irq(1);
	513	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	514	handle_edge_irq);
	515	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	516	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
	517	#endif
	518
157d2644 HZ	519	for (irq = gpio_to_irq(gpio_offset);
157d2644 HZ	520	irq <= gpio_to_irq(pxa_last_gpio); irq++) {
f38c02f3 TG	521	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
f38c02f3 TG	522	handle_edge_irq);
e3630db1	523	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	524	}
	525
157d2644 HZ	526	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	527	return 0;
	528	}
	529
	530	static struct platform_driver pxa_gpio_driver = {
	531	.probe = pxa_gpio_probe,
	532	.driver = {
	533	.name = "pxa-gpio",
	534	},
	535	};
	536
	537	static int __init pxa_gpio_init(void)
	538	{
	539	return platform_driver_register(&pxa_gpio_driver);
e3630db1	540	}
157d2644	541	postcore_initcall(pxa_gpio_init);
663707c1	542
663707c1	543	#ifdef CONFIG_PM
2eaa03b5	544	static int pxa_gpio_suspend(void)
663707c1	545	{
0807da59 EM	546	struct pxa_gpio_chip *c;
0807da59 EM	547	int gpio;
663707c1	548
0807da59	549	for_each_gpio_chip(gpio, c) {
df664d20 HZ	550	c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
	551	c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
	552	c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
	553	c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
663707c1	554
663707c1	555	/* Clear GPIO transition detect bits */
df664d20	556	writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
663707c1	557	}
	558	return 0;
	559	}
	560
2eaa03b5	561	static void pxa_gpio_resume(void)
663707c1	562	{
0807da59 EM	563	struct pxa_gpio_chip *c;
0807da59 EM	564	int gpio;
663707c1	565
0807da59	566	for_each_gpio_chip(gpio, c) {
663707c1	567	/* restore level with set/clear */
df664d20 HZ	568	writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
df664d20 HZ	569	writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
663707c1	570
df664d20 HZ	571	writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
	572	writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
	573	writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
663707c1	574	}
663707c1	575	}
	576	#else
	577	#define pxa_gpio_suspend NULL
	578	#define pxa_gpio_resume NULL
	579	#endif
	580
2eaa03b5	581	struct syscore_ops pxa_gpio_syscore_ops = {
663707c1	582	.suspend = pxa_gpio_suspend,
	583	.resume = pxa_gpio_resume,
	584	};
157d2644 HZ	585
	586	static int __init pxa_gpio_sysinit(void)
	587	{
	588	register_syscore_ops(&pxa_gpio_syscore_ops);
	589	return 0;
	590	}
	591	postcore_initcall(pxa_gpio_sysinit);