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gpio: davinci: preparation for switch to common clock framework
[deliverable/linux.git] / drivers / gpio / gpio-pxa.c
CommitLineData
1c44f5f1 1/*
38f539a6 2 * linux/arch/arm/plat-pxa/gpio.c
1c44f5f1
PZ		 3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
7a4d5079 14#include <linux/module.h>
389eda15
HZ		 15#include <linux/clk.h>
16#include <linux/err.h>
2f8163ba 17#include <linux/gpio.h>
157d2644 18#include <linux/gpio-pxa.h>
1c44f5f1 19#include <linux/init.h>
e3630db1 20#include <linux/irq.h>
7a4d5079 21#include <linux/irqdomain.h>
fced80c7 22#include <linux/io.h>
7a4d5079
HZ		 23#include <linux/of.h>
24#include <linux/of_device.h>
157d2644 25#include <linux/platform_device.h>
2eaa03b5 26#include <linux/syscore_ops.h>
4aa78264 27#include <linux/slab.h>
1c44f5f1 28
feefe73f
RH		 29#include <mach/irqs.h>
30
157d2644
HZ		 31/*
32 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
33 * one set of registers. The register offsets are organized below:
34 *
35 * GPLR GPDR GPSR GPCR GRER GFER GEDR
36 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
37 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
38 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
39 *
40 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
41 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
42 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
43 *
44 * NOTE:
45 * BANK 3 is only available on PXA27x and later processors.
46 * BANK 4 and 5 are only available on PXA935
47 */
48
49#define GPLR_OFFSET 0x00
50#define GPDR_OFFSET 0x0C
51#define GPSR_OFFSET 0x18
52#define GPCR_OFFSET 0x24
53#define GRER_OFFSET 0x30
54#define GFER_OFFSET 0x3C
55#define GEDR_OFFSET 0x48
56#define GAFR_OFFSET 0x54
be24168f 57#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
157d2644
HZ		 58
59#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
1c44f5f1 60
3b8e285c
EM		 61int pxa_last_gpio;
62
7a4d5079
HZ		 63#ifdef CONFIG_OF
64static struct irq_domain *domain;
72121572 65static struct device_node *pxa_gpio_of_node;
7a4d5079
HZ		 66#endif
67
1c44f5f1
PZ		 68struct pxa_gpio_chip {
69 struct gpio_chip chip;
0807da59
EM		 70 void __iomem *regbase;
71 char label[10];
72
73 unsigned long irq_mask;
74 unsigned long irq_edge_rise;
75 unsigned long irq_edge_fall;
b95ace54 76 int (*set_wake)(unsigned int gpio, unsigned int on);
0807da59
EM		 77
78#ifdef CONFIG_PM
79 unsigned long saved_gplr;
80 unsigned long saved_gpdr;
81 unsigned long saved_grer;
82 unsigned long saved_gfer;
83#endif
1c44f5f1
PZ		 84};
85
4929f5a8
HZ		 86enum {
87 PXA25X_GPIO = 0,
88 PXA26X_GPIO,
89 PXA27X_GPIO,
90 PXA3XX_GPIO,
91 PXA93X_GPIO,
92 MMP_GPIO = 0x10,
4929f5a8
HZ		 93};
94
0807da59
EM		 95static DEFINE_SPINLOCK(gpio_lock);
96static struct pxa_gpio_chip *pxa_gpio_chips;
4929f5a8 97static int gpio_type;
157d2644 98static void __iomem *gpio_reg_base;
0807da59
EM		 99
100#define for_each_gpio_chip(i, c) \
101 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
102
103static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
104{
105 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
106}
107
a065685d 108static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
0807da59
EM		 109{
110 return &pxa_gpio_chips[gpio_to_bank(gpio)];
111}
112
4929f5a8
HZ		 113static inline int gpio_is_pxa_type(int type)
114{
115 return (type & MMP_GPIO) == 0;
116}
117
118static inline int gpio_is_mmp_type(int type)
119{
120 return (type & MMP_GPIO) != 0;
121}
122
157d2644
HZ		 123/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
124 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
125 */
126static inline int __gpio_is_inverted(int gpio)
127{
128 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
129 return 1;
130 return 0;
131}
132
133/*
134 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
135 * function of a GPIO, and GPDRx cannot be altered once configured. It
136 * is attributed as "occupied" here (I know this terminology isn't
137 * accurate, you are welcome to propose a better one :-)
138 */
139static inline int __gpio_is_occupied(unsigned gpio)
140{
141 struct pxa_gpio_chip *pxachip;
142 void __iomem *base;
143 unsigned long gafr = 0, gpdr = 0;
144 int ret, af = 0, dir = 0;
145
146 pxachip = gpio_to_pxachip(gpio);
147 base = gpio_chip_base(&pxachip->chip);
148 gpdr = readl_relaxed(base + GPDR_OFFSET);
149
150 switch (gpio_type) {
151 case PXA25X_GPIO:
152 case PXA26X_GPIO:
153 case PXA27X_GPIO:
154 gafr = readl_relaxed(base + GAFR_OFFSET);
155 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
156 dir = gpdr & GPIO_bit(gpio);
157
158 if (__gpio_is_inverted(gpio))
159 ret = (af != 1) || (dir == 0);
160 else
161 ret = (af != 0) || (dir != 0);
162 break;
163 default:
164 ret = gpdr & GPIO_bit(gpio);
165 break;
166 }
167 return ret;
168}
169
4929f5a8
HZ		 170#ifdef CONFIG_ARCH_PXA
171static inline int __pxa_gpio_to_irq(int gpio)
172{
173 if (gpio_is_pxa_type(gpio_type))
174 return PXA_GPIO_TO_IRQ(gpio);
175 return -1;
176}
177
178static inline int __pxa_irq_to_gpio(int irq)
179{
180 if (gpio_is_pxa_type(gpio_type))
181 return irq - PXA_GPIO_TO_IRQ(0);
182 return -1;
183}
184#else
185static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
186static inline int __pxa_irq_to_gpio(int irq) { return -1; }
187#endif
188
189#ifdef CONFIG_ARCH_MMP
190static inline int __mmp_gpio_to_irq(int gpio)
191{
192 if (gpio_is_mmp_type(gpio_type))
193 return MMP_GPIO_TO_IRQ(gpio);
194 return -1;
195}
196
197static inline int __mmp_irq_to_gpio(int irq)
198{
199 if (gpio_is_mmp_type(gpio_type))
200 return irq - MMP_GPIO_TO_IRQ(0);
201 return -1;
202}
203#else
204static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
205static inline int __mmp_irq_to_gpio(int irq) { return -1; }
206#endif
207
208static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
209{
210 int gpio, ret;
211
212 gpio = chip->base + offset;
213 ret = __pxa_gpio_to_irq(gpio);
214 if (ret >= 0)
215 return ret;
216 return __mmp_gpio_to_irq(gpio);
217}
218
219int pxa_irq_to_gpio(int irq)
220{
221 int ret;
222
223 ret = __pxa_irq_to_gpio(irq);
224 if (ret >= 0)
225 return ret;
226 return __mmp_irq_to_gpio(irq);
227}
228
1c44f5f1
PZ		 229static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
230{
0807da59
EM		 231 void __iomem *base = gpio_chip_base(chip);
232 uint32_t value, mask = 1 << offset;
233 unsigned long flags;
234
235 spin_lock_irqsave(&gpio_lock, flags);
236
df664d20 237 value = readl_relaxed(base + GPDR_OFFSET);
067455aa
EM		 238 if (__gpio_is_inverted(chip->base + offset))
239 value |= mask;
240 else
241 value &= ~mask;
df664d20 242 writel_relaxed(value, base + GPDR_OFFSET);
1c44f5f1 243
0807da59 244 spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1
PZ		 245 return 0;
246}
247
248static int pxa_gpio_direction_output(struct gpio_chip *chip,
0807da59 249 unsigned offset, int value)
1c44f5f1 250{
0807da59
EM		 251 void __iomem *base = gpio_chip_base(chip);
252 uint32_t tmp, mask = 1 << offset;
253 unsigned long flags;
254
df664d20 255 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
0807da59
EM		 256
257 spin_lock_irqsave(&gpio_lock, flags);
258
df664d20 259 tmp = readl_relaxed(base + GPDR_OFFSET);
067455aa
EM		 260 if (__gpio_is_inverted(chip->base + offset))
261 tmp &= ~mask;
262 else
263 tmp |= mask;
df664d20 264 writel_relaxed(tmp, base + GPDR_OFFSET);
1c44f5f1 265
0807da59 266 spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1
PZ		 267 return 0;
268}
269
1c44f5f1
PZ		 270static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
271{
df664d20 272 return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
1c44f5f1
PZ		 273}
274
1c44f5f1
PZ		 275static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
276{
df664d20 277 writel_relaxed(1 << offset, gpio_chip_base(chip) +
0807da59 278 (value ? GPSR_OFFSET : GPCR_OFFSET));
1c44f5f1
PZ		 279}
280
72121572
DM		 281#ifdef CONFIG_OF_GPIO
282static int pxa_gpio_of_xlate(struct gpio_chip *gc,
283 const struct of_phandle_args *gpiospec,
284 u32 *flags)
285{
286 if (gpiospec->args[0] > pxa_last_gpio)
287 return -EINVAL;
288
289 if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip)
290 return -EINVAL;
291
292 if (flags)
293 *flags = gpiospec->args[1];
294
295 return gpiospec->args[0] % 32;
296}
297#endif
298
b95ace54
RJ		 299static int __devinit pxa_init_gpio_chip(int gpio_end,
300 int (*set_wake)(unsigned int, unsigned int))
a58fbcd8 301{
0807da59
EM		 302 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
303 struct pxa_gpio_chip *chips;
a58fbcd8 304
4aa78264 305 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
0807da59
EM		 306 if (chips == NULL) {
307 pr_err("%s: failed to allocate GPIO chips\n", __func__);
308 return -ENOMEM;
a58fbcd8 309 }
a58fbcd8 310
0807da59
EM		 311 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
312 struct gpio_chip *c = &chips[i].chip;
e3630db1 313
0807da59 314 sprintf(chips[i].label, "gpio-%d", i);
157d2644 315 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
b95ace54 316 chips[i].set_wake = set_wake;
0807da59
EM		 317
318 c->base = gpio;
319 c->label = chips[i].label;
320
321 c->direction_input = pxa_gpio_direction_input;
322 c->direction_output = pxa_gpio_direction_output;
323 c->get = pxa_gpio_get;
324 c->set = pxa_gpio_set;
4929f5a8 325 c->to_irq = pxa_gpio_to_irq;
72121572
DM		 326#ifdef CONFIG_OF_GPIO
327 c->of_node = pxa_gpio_of_node;
328 c->of_xlate = pxa_gpio_of_xlate;
329 c->of_gpio_n_cells = 2;
330#endif
0807da59
EM		 331
332 /* number of GPIOs on last bank may be less than 32 */
333 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
334 gpiochip_add(c);
335 }
336 pxa_gpio_chips = chips;
337 return 0;
338}
e3630db1 339
a8f6faeb
EM		 340/* Update only those GRERx and GFERx edge detection register bits if those
341 * bits are set in c->irq_mask
342 */
343static inline void update_edge_detect(struct pxa_gpio_chip *c)
344{
345 uint32_t grer, gfer;
346
df664d20
HZ		 347 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
348 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
a8f6faeb
EM		 349 grer |= c->irq_edge_rise & c->irq_mask;
350 gfer |= c->irq_edge_fall & c->irq_mask;
df664d20
HZ		 351 writel_relaxed(grer, c->regbase + GRER_OFFSET);
352 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
a8f6faeb
EM		 353}
354
a3f4c927 355static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
e3630db1 356{
0807da59 357 struct pxa_gpio_chip *c;
4929f5a8 358 int gpio = pxa_irq_to_gpio(d->irq);
0807da59 359 unsigned long gpdr, mask = GPIO_bit(gpio);
e3630db1 360
a065685d 361 c = gpio_to_pxachip(gpio);
e3630db1 362
363 if (type == IRQ_TYPE_PROBE) {
364 /* Don't mess with enabled GPIOs using preconfigured edges or
365 * GPIOs set to alternate function or to output during probe
366 */
0807da59 367 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
e3630db1 368 return 0;
689c04a3 369
370 if (__gpio_is_occupied(gpio))
e3630db1 371 return 0;
689c04a3 372
e3630db1 373 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
374 }
375
df664d20 376 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
0807da59 377
067455aa 378 if (__gpio_is_inverted(gpio))
df664d20 379 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
067455aa 380 else
df664d20 381 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
e3630db1 382
383 if (type & IRQ_TYPE_EDGE_RISING)
0807da59 384 c->irq_edge_rise |= mask;
e3630db1 385 else
0807da59 386 c->irq_edge_rise &= ~mask;
e3630db1 387
388 if (type & IRQ_TYPE_EDGE_FALLING)
0807da59 389 c->irq_edge_fall |= mask;
e3630db1 390 else
0807da59 391 c->irq_edge_fall &= ~mask;
e3630db1 392
a8f6faeb 393 update_edge_detect(c);
e3630db1 394
a3f4c927 395 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
e3630db1 396 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
397 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
398 return 0;
399}
400
e3630db1 401static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
402{
0807da59
EM		 403 struct pxa_gpio_chip *c;
404 int loop, gpio, gpio_base, n;
405 unsigned long gedr;
e3630db1 406
407 do {
e3630db1 408 loop = 0;
0807da59
EM		 409 for_each_gpio_chip(gpio, c) {
410 gpio_base = c->chip.base;
411
df664d20 412 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
0807da59 413 gedr = gedr & c->irq_mask;
df664d20 414 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
e3630db1 415
0807da59
EM		 416 n = find_first_bit(&gedr, BITS_PER_LONG);
417 while (n < BITS_PER_LONG) {
418 loop = 1;
e3630db1 419
0807da59
EM		 420 generic_handle_irq(gpio_to_irq(gpio_base + n));
421 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
422 }
e3630db1 423 }
424 } while (loop);
425}
426
a3f4c927 427static void pxa_ack_muxed_gpio(struct irq_data *d)
e3630db1 428{
4929f5a8 429 int gpio = pxa_irq_to_gpio(d->irq);
a065685d 430 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 431
df664d20 432 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
e3630db1 433}
434
a3f4c927 435static void pxa_mask_muxed_gpio(struct irq_data *d)
e3630db1 436{
4929f5a8 437 int gpio = pxa_irq_to_gpio(d->irq);
a065685d 438 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59
EM		 439 uint32_t grer, gfer;
440
441 c->irq_mask &= ~GPIO_bit(gpio);
442
df664d20
HZ		 443 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
444 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
445 writel_relaxed(grer, c->regbase + GRER_OFFSET);
446 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
e3630db1 447}
448
b95ace54
RJ		 449static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
450{
451 int gpio = pxa_irq_to_gpio(d->irq);
452 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
453
454 if (c->set_wake)
455 return c->set_wake(gpio, on);
456 else
457 return 0;
458}
459
a3f4c927 460static void pxa_unmask_muxed_gpio(struct irq_data *d)
e3630db1 461{
4929f5a8 462 int gpio = pxa_irq_to_gpio(d->irq);
a065685d 463 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59
EM		 464
465 c->irq_mask |= GPIO_bit(gpio);
a8f6faeb 466 update_edge_detect(c);
e3630db1 467}
468
469static struct irq_chip pxa_muxed_gpio_chip = {
470 .name = "GPIO",
a3f4c927
LB		 471 .irq_ack = pxa_ack_muxed_gpio,
472 .irq_mask = pxa_mask_muxed_gpio,
473 .irq_unmask = pxa_unmask_muxed_gpio,
474 .irq_set_type = pxa_gpio_irq_type,
b95ace54 475 .irq_set_wake = pxa_gpio_set_wake,
e3630db1 476};
477
478e223c
HZ		 478static int pxa_gpio_nums(void)
479{
480 int count = 0;
481
482#ifdef CONFIG_ARCH_PXA
483 if (cpu_is_pxa25x()) {
484#ifdef CONFIG_CPU_PXA26x
485 count = 89;
486 gpio_type = PXA26X_GPIO;
487#elif defined(CONFIG_PXA25x)
488 count = 84;
489 gpio_type = PXA26X_GPIO;
490#endif /* CONFIG_CPU_PXA26x */
491 } else if (cpu_is_pxa27x()) {
492 count = 120;
493 gpio_type = PXA27X_GPIO;
494 } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
495 count = 191;
496 gpio_type = PXA93X_GPIO;
497 } else if (cpu_is_pxa3xx()) {
498 count = 127;
499 gpio_type = PXA3XX_GPIO;
500 }
501#endif /* CONFIG_ARCH_PXA */
502
503#ifdef CONFIG_ARCH_MMP
504 if (cpu_is_pxa168() || cpu_is_pxa910()) {
505 count = 127;
506 gpio_type = MMP_GPIO;
507 } else if (cpu_is_mmp2()) {
508 count = 191;
7a4d5079 509 gpio_type = MMP_GPIO;
478e223c
HZ		 510 }
511#endif /* CONFIG_ARCH_MMP */
512 return count;
513}
514
f43e04ec 515#ifdef CONFIG_OF
7a4d5079
HZ		 516static struct of_device_id pxa_gpio_dt_ids[] = {
517 { .compatible = "mrvl,pxa-gpio" },
518 { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO },
519 {}
520};
521
522static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
523 irq_hw_number_t hw)
524{
525 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
526 handle_edge_irq);
527 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
528 return 0;
529}
530
531const struct irq_domain_ops pxa_irq_domain_ops = {
532 .map = pxa_irq_domain_map,
72121572 533 .xlate = irq_domain_xlate_twocell,
7a4d5079
HZ		 534};
535
7a4d5079
HZ		 536static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
537{
538 int ret, nr_banks, nr_gpios, irq_base;
539 struct device_node *prev, *next, *np = pdev->dev.of_node;
540 const struct of_device_id *of_id =
541 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
542
543 if (!of_id) {
544 dev_err(&pdev->dev, "Failed to find gpio controller\n");
545 return -EFAULT;
546 }
547 gpio_type = (int)of_id->data;
548
549 next = of_get_next_child(np, NULL);
550 prev = next;
551 if (!next) {
552 dev_err(&pdev->dev, "Failed to find child gpio node\n");
553 ret = -EINVAL;
554 goto err;
555 }
556 for (nr_banks = 1; ; nr_banks++) {
557 next = of_get_next_child(np, prev);
558 if (!next)
559 break;
560 prev = next;
561 }
562 of_node_put(prev);
563 nr_gpios = nr_banks << 5;
564 pxa_last_gpio = nr_gpios - 1;
565
566 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
567 if (irq_base < 0) {
568 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
569 goto err;
570 }
571 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
572 &pxa_irq_domain_ops, NULL);
72121572 573 pxa_gpio_of_node = np;
7a4d5079
HZ		 574 return 0;
575err:
576 iounmap(gpio_reg_base);
577 return ret;
578}
579#else
580#define pxa_gpio_probe_dt(pdev) (-1)
581#endif
582
157d2644 583static int __devinit pxa_gpio_probe(struct platform_device *pdev)
e3630db1 584{
0807da59 585 struct pxa_gpio_chip *c;
157d2644 586 struct resource *res;
389eda15 587 struct clk *clk;
b95ace54 588 struct pxa_gpio_platform_data *info;
7a4d5079 589 int gpio, irq, ret, use_of = 0;
157d2644 590 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
e3630db1 591
7a4d5079
HZ		 592 ret = pxa_gpio_probe_dt(pdev);
593 if (ret < 0)
594 pxa_last_gpio = pxa_gpio_nums();
595 else
596 use_of = 1;
478e223c 597 if (!pxa_last_gpio)
157d2644
HZ		 598 return -EINVAL;
599
600 irq0 = platform_get_irq_byname(pdev, "gpio0");
601 irq1 = platform_get_irq_byname(pdev, "gpio1");
602 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
603 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
604 || (irq_mux <= 0))
605 return -EINVAL;
606 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
607 if (!res)
608 return -EINVAL;
609 gpio_reg_base = ioremap(res->start, resource_size(res));
610 if (!gpio_reg_base)
611 return -EINVAL;
612
613 if (irq0 > 0)
614 gpio_offset = 2;
e3630db1 615
389eda15
HZ		 616 clk = clk_get(&pdev->dev, NULL);
617 if (IS_ERR(clk)) {
618 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
619 PTR_ERR(clk));
620 iounmap(gpio_reg_base);
621 return PTR_ERR(clk);
622 }
623 ret = clk_prepare(clk);
624 if (ret) {
625 clk_put(clk);
626 iounmap(gpio_reg_base);
627 return ret;
628 }
629 ret = clk_enable(clk);
630 if (ret) {
631 clk_unprepare(clk);
632 clk_put(clk);
633 iounmap(gpio_reg_base);
634 return ret;
635 }
636
0807da59 637 /* Initialize GPIO chips */
b95ace54
RJ		 638 info = dev_get_platdata(&pdev->dev);
639 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
0807da59 640
e3630db1 641 /* clear all GPIO edge detects */
0807da59 642 for_each_gpio_chip(gpio, c) {
df664d20
HZ		 643 writel_relaxed(0, c->regbase + GFER_OFFSET);
644 writel_relaxed(0, c->regbase + GRER_OFFSET);
645 writel_relaxed(~0,c->regbase + GEDR_OFFSET);
be24168f
HZ		 646 /* unmask GPIO edge detect for AP side */
647 if (gpio_is_mmp_type(gpio_type))
648 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
e3630db1 649 }
650
7a4d5079 651 if (!use_of) {
87c49e20 652#ifdef CONFIG_ARCH_PXA
7a4d5079
HZ		 653 irq = gpio_to_irq(0);
654 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
655 handle_edge_irq);
656 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
657 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
87c49e20 658
7a4d5079 659 irq = gpio_to_irq(1);
f38c02f3
TG		 660 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
661 handle_edge_irq);
e3630db1 662 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
7a4d5079
HZ		 663 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
664#endif
665
666 for (irq = gpio_to_irq(gpio_offset);
667 irq <= gpio_to_irq(pxa_last_gpio); irq++) {
668 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
669 handle_edge_irq);
670 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
671 }
e3630db1 672 }
673
157d2644
HZ		 674 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
675 return 0;
676}
677
678static struct platform_driver pxa_gpio_driver = {
679 .probe = pxa_gpio_probe,
680 .driver = {
681 .name = "pxa-gpio",
f43e04ec 682 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
157d2644
HZ		 683 },
684};
685
686static int __init pxa_gpio_init(void)
687{
688 return platform_driver_register(&pxa_gpio_driver);
e3630db1 689}
157d2644 690postcore_initcall(pxa_gpio_init);
663707c1 691
692#ifdef CONFIG_PM
2eaa03b5 693static int pxa_gpio_suspend(void)
663707c1 694{
0807da59
EM		 695 struct pxa_gpio_chip *c;
696 int gpio;
663707c1 697
0807da59 698 for_each_gpio_chip(gpio, c) {
df664d20
HZ		 699 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
700 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
701 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
702 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
663707c1 703
704 /* Clear GPIO transition detect bits */
df664d20 705 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
663707c1 706 }
707 return 0;
708}
709
2eaa03b5 710static void pxa_gpio_resume(void)
663707c1 711{
0807da59
EM		 712 struct pxa_gpio_chip *c;
713 int gpio;
663707c1 714
0807da59 715 for_each_gpio_chip(gpio, c) {
663707c1 716 /* restore level with set/clear */
df664d20
HZ		 717 writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
718 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
663707c1 719
df664d20
HZ		 720 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
721 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
722 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
663707c1 723 }
663707c1 724}
725#else
726#define pxa_gpio_suspend NULL
727#define pxa_gpio_resume NULL
728#endif
729
2eaa03b5 730struct syscore_ops pxa_gpio_syscore_ops = {
663707c1 731 .suspend = pxa_gpio_suspend,
732 .resume = pxa_gpio_resume,
733};
157d2644
HZ		 734
735static int __init pxa_gpio_sysinit(void)
736{
737 register_syscore_ops(&pxa_gpio_syscore_ops);
738 return 0;
739}
740postcore_initcall(pxa_gpio_sysinit);
Linux kernel - Deliverables
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