Commit | Line | Data |
---|---|---|
1c44f5f1 | 1 | /* |
38f539a6 | 2 | * linux/arch/arm/plat-pxa/gpio.c |
1c44f5f1 PZ |
3 | * |
4 | * Generic PXA GPIO handling | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Jun 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
7a4d5079 | 14 | #include <linux/module.h> |
389eda15 HZ |
15 | #include <linux/clk.h> |
16 | #include <linux/err.h> | |
2f8163ba | 17 | #include <linux/gpio.h> |
157d2644 | 18 | #include <linux/gpio-pxa.h> |
1c44f5f1 | 19 | #include <linux/init.h> |
ae4f4cfd | 20 | #include <linux/interrupt.h> |
e3630db1 | 21 | #include <linux/irq.h> |
7a4d5079 | 22 | #include <linux/irqdomain.h> |
de88cbb7 | 23 | #include <linux/irqchip/chained_irq.h> |
fced80c7 | 24 | #include <linux/io.h> |
7a4d5079 HZ |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
157d2644 | 27 | #include <linux/platform_device.h> |
2eaa03b5 | 28 | #include <linux/syscore_ops.h> |
4aa78264 | 29 | #include <linux/slab.h> |
1c44f5f1 | 30 | |
157d2644 HZ |
31 | /* |
32 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | |
33 | * one set of registers. The register offsets are organized below: | |
34 | * | |
35 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | |
36 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | |
37 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | |
38 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | |
39 | * | |
40 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | |
41 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | |
42 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | |
43 | * | |
684bba2f RH |
44 | * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 |
45 | * | |
157d2644 HZ |
46 | * NOTE: |
47 | * BANK 3 is only available on PXA27x and later processors. | |
684bba2f RH |
48 | * BANK 4 and 5 are only available on PXA935, PXA1928 |
49 | * BANK 6 is only available on PXA1928 | |
157d2644 HZ |
50 | */ |
51 | ||
52 | #define GPLR_OFFSET 0x00 | |
53 | #define GPDR_OFFSET 0x0C | |
54 | #define GPSR_OFFSET 0x18 | |
55 | #define GPCR_OFFSET 0x24 | |
56 | #define GRER_OFFSET 0x30 | |
57 | #define GFER_OFFSET 0x3C | |
58 | #define GEDR_OFFSET 0x48 | |
59 | #define GAFR_OFFSET 0x54 | |
be24168f | 60 | #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ |
157d2644 | 61 | |
1e970b7d | 62 | #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2) |
1c44f5f1 | 63 | |
3b8e285c | 64 | int pxa_last_gpio; |
9450be76 | 65 | static int irq_base; |
3b8e285c | 66 | |
7a4d5079 HZ |
67 | #ifdef CONFIG_OF |
68 | static struct irq_domain *domain; | |
72121572 | 69 | static struct device_node *pxa_gpio_of_node; |
7a4d5079 HZ |
70 | #endif |
71 | ||
fc0589ca | 72 | struct pxa_gpio_bank { |
0807da59 | 73 | void __iomem *regbase; |
0807da59 EM |
74 | unsigned long irq_mask; |
75 | unsigned long irq_edge_rise; | |
76 | unsigned long irq_edge_fall; | |
77 | ||
78 | #ifdef CONFIG_PM | |
79 | unsigned long saved_gplr; | |
80 | unsigned long saved_gpdr; | |
81 | unsigned long saved_grer; | |
82 | unsigned long saved_gfer; | |
83 | #endif | |
1c44f5f1 PZ |
84 | }; |
85 | ||
fc0589ca RJ |
86 | struct pxa_gpio_chip { |
87 | struct device *dev; | |
88 | struct gpio_chip chip; | |
89 | struct pxa_gpio_bank *banks; | |
90 | ||
91 | int irq0; | |
92 | int irq1; | |
93 | int (*set_wake)(unsigned int gpio, unsigned int on); | |
94 | }; | |
95 | ||
2cab0292 | 96 | enum pxa_gpio_type { |
4929f5a8 HZ |
97 | PXA25X_GPIO = 0, |
98 | PXA26X_GPIO, | |
99 | PXA27X_GPIO, | |
100 | PXA3XX_GPIO, | |
101 | PXA93X_GPIO, | |
102 | MMP_GPIO = 0x10, | |
2cab0292 | 103 | MMP2_GPIO, |
684bba2f | 104 | PXA1928_GPIO, |
2cab0292 HZ |
105 | }; |
106 | ||
107 | struct pxa_gpio_id { | |
108 | enum pxa_gpio_type type; | |
109 | int gpio_nums; | |
4929f5a8 HZ |
110 | }; |
111 | ||
0807da59 | 112 | static DEFINE_SPINLOCK(gpio_lock); |
fc0589ca | 113 | static struct pxa_gpio_chip *pxa_gpio_chip; |
2cab0292 | 114 | static enum pxa_gpio_type gpio_type; |
0807da59 | 115 | |
2cab0292 HZ |
116 | static struct pxa_gpio_id pxa25x_id = { |
117 | .type = PXA25X_GPIO, | |
118 | .gpio_nums = 85, | |
119 | }; | |
120 | ||
121 | static struct pxa_gpio_id pxa26x_id = { | |
122 | .type = PXA26X_GPIO, | |
123 | .gpio_nums = 90, | |
124 | }; | |
125 | ||
126 | static struct pxa_gpio_id pxa27x_id = { | |
127 | .type = PXA27X_GPIO, | |
128 | .gpio_nums = 121, | |
129 | }; | |
130 | ||
131 | static struct pxa_gpio_id pxa3xx_id = { | |
132 | .type = PXA3XX_GPIO, | |
133 | .gpio_nums = 128, | |
134 | }; | |
135 | ||
136 | static struct pxa_gpio_id pxa93x_id = { | |
137 | .type = PXA93X_GPIO, | |
138 | .gpio_nums = 192, | |
139 | }; | |
140 | ||
141 | static struct pxa_gpio_id mmp_id = { | |
142 | .type = MMP_GPIO, | |
143 | .gpio_nums = 128, | |
144 | }; | |
145 | ||
146 | static struct pxa_gpio_id mmp2_id = { | |
147 | .type = MMP2_GPIO, | |
148 | .gpio_nums = 192, | |
149 | }; | |
150 | ||
684bba2f RH |
151 | static struct pxa_gpio_id pxa1928_id = { |
152 | .type = PXA1928_GPIO, | |
153 | .gpio_nums = 224, | |
154 | }; | |
155 | ||
fc0589ca RJ |
156 | #define for_each_gpio_bank(i, b, pc) \ |
157 | for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++) | |
0807da59 | 158 | |
fc0589ca | 159 | static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) |
0807da59 | 160 | { |
fc0589ca RJ |
161 | struct pxa_gpio_chip *pxa_chip = |
162 | container_of(c, struct pxa_gpio_chip, chip); | |
163 | ||
164 | return pxa_chip; | |
0807da59 | 165 | } |
fc0589ca RJ |
166 | static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) |
167 | { | |
168 | struct pxa_gpio_bank *bank = chip_to_pxachip(c)->banks + (gpio / 32); | |
0807da59 | 169 | |
fc0589ca RJ |
170 | return bank->regbase; |
171 | } | |
172 | ||
173 | static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, | |
174 | unsigned gpio) | |
0807da59 | 175 | { |
fc0589ca | 176 | return chip_to_pxachip(c)->banks + gpio / 32; |
0807da59 EM |
177 | } |
178 | ||
4929f5a8 HZ |
179 | static inline int gpio_is_pxa_type(int type) |
180 | { | |
181 | return (type & MMP_GPIO) == 0; | |
182 | } | |
183 | ||
184 | static inline int gpio_is_mmp_type(int type) | |
185 | { | |
186 | return (type & MMP_GPIO) != 0; | |
187 | } | |
188 | ||
157d2644 HZ |
189 | /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, |
190 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | |
191 | */ | |
192 | static inline int __gpio_is_inverted(int gpio) | |
193 | { | |
194 | if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) | |
195 | return 1; | |
196 | return 0; | |
197 | } | |
198 | ||
199 | /* | |
200 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | |
201 | * function of a GPIO, and GPDRx cannot be altered once configured. It | |
202 | * is attributed as "occupied" here (I know this terminology isn't | |
203 | * accurate, you are welcome to propose a better one :-) | |
204 | */ | |
fc0589ca | 205 | static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) |
157d2644 | 206 | { |
157d2644 HZ |
207 | void __iomem *base; |
208 | unsigned long gafr = 0, gpdr = 0; | |
209 | int ret, af = 0, dir = 0; | |
210 | ||
fc0589ca | 211 | base = gpio_bank_base(&pchip->chip, gpio); |
157d2644 HZ |
212 | gpdr = readl_relaxed(base + GPDR_OFFSET); |
213 | ||
214 | switch (gpio_type) { | |
215 | case PXA25X_GPIO: | |
216 | case PXA26X_GPIO: | |
217 | case PXA27X_GPIO: | |
218 | gafr = readl_relaxed(base + GAFR_OFFSET); | |
219 | af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; | |
220 | dir = gpdr & GPIO_bit(gpio); | |
221 | ||
222 | if (__gpio_is_inverted(gpio)) | |
223 | ret = (af != 1) || (dir == 0); | |
224 | else | |
225 | ret = (af != 0) || (dir != 0); | |
226 | break; | |
227 | default: | |
228 | ret = gpdr & GPIO_bit(gpio); | |
229 | break; | |
230 | } | |
231 | return ret; | |
232 | } | |
233 | ||
4929f5a8 HZ |
234 | static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
235 | { | |
fc0589ca | 236 | return offset + irq_base; |
4929f5a8 HZ |
237 | } |
238 | ||
239 | int pxa_irq_to_gpio(int irq) | |
240 | { | |
9450be76 | 241 | return irq - irq_base; |
4929f5a8 HZ |
242 | } |
243 | ||
1c44f5f1 PZ |
244 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
245 | { | |
fc0589ca RJ |
246 | void __iomem *base = gpio_bank_base(chip, offset); |
247 | uint32_t value, mask = GPIO_bit(offset); | |
0807da59 EM |
248 | unsigned long flags; |
249 | ||
250 | spin_lock_irqsave(&gpio_lock, flags); | |
251 | ||
df664d20 | 252 | value = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
253 | if (__gpio_is_inverted(chip->base + offset)) |
254 | value |= mask; | |
255 | else | |
256 | value &= ~mask; | |
df664d20 | 257 | writel_relaxed(value, base + GPDR_OFFSET); |
1c44f5f1 | 258 | |
0807da59 | 259 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
260 | return 0; |
261 | } | |
262 | ||
263 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | |
0807da59 | 264 | unsigned offset, int value) |
1c44f5f1 | 265 | { |
fc0589ca RJ |
266 | void __iomem *base = gpio_bank_base(chip, offset); |
267 | uint32_t tmp, mask = GPIO_bit(offset); | |
0807da59 EM |
268 | unsigned long flags; |
269 | ||
df664d20 | 270 | writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); |
0807da59 EM |
271 | |
272 | spin_lock_irqsave(&gpio_lock, flags); | |
273 | ||
df664d20 | 274 | tmp = readl_relaxed(base + GPDR_OFFSET); |
067455aa EM |
275 | if (__gpio_is_inverted(chip->base + offset)) |
276 | tmp &= ~mask; | |
277 | else | |
278 | tmp |= mask; | |
df664d20 | 279 | writel_relaxed(tmp, base + GPDR_OFFSET); |
1c44f5f1 | 280 | |
0807da59 | 281 | spin_unlock_irqrestore(&gpio_lock, flags); |
1c44f5f1 PZ |
282 | return 0; |
283 | } | |
284 | ||
1c44f5f1 PZ |
285 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) |
286 | { | |
fc0589ca RJ |
287 | void __iomem *base = gpio_bank_base(chip, offset); |
288 | u32 gplr = readl_relaxed(base + GPLR_OFFSET); | |
289 | ||
290 | return !!(gplr & GPIO_bit(offset)); | |
1c44f5f1 PZ |
291 | } |
292 | ||
1c44f5f1 PZ |
293 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
294 | { | |
fc0589ca RJ |
295 | void __iomem *base = gpio_bank_base(chip, offset); |
296 | ||
297 | writel_relaxed(GPIO_bit(offset), | |
298 | base + (value ? GPSR_OFFSET : GPCR_OFFSET)); | |
1c44f5f1 PZ |
299 | } |
300 | ||
72121572 DM |
301 | #ifdef CONFIG_OF_GPIO |
302 | static int pxa_gpio_of_xlate(struct gpio_chip *gc, | |
303 | const struct of_phandle_args *gpiospec, | |
304 | u32 *flags) | |
305 | { | |
306 | if (gpiospec->args[0] > pxa_last_gpio) | |
307 | return -EINVAL; | |
308 | ||
72121572 DM |
309 | if (flags) |
310 | *flags = gpiospec->args[1]; | |
311 | ||
fc0589ca | 312 | return gpiospec->args[0]; |
72121572 DM |
313 | } |
314 | #endif | |
315 | ||
fc0589ca RJ |
316 | static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, |
317 | void __iomem *regbase) | |
a58fbcd8 | 318 | { |
fc0589ca RJ |
319 | int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32); |
320 | struct pxa_gpio_bank *bank; | |
a58fbcd8 | 321 | |
fc0589ca RJ |
322 | pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), |
323 | GFP_KERNEL); | |
324 | if (!pchip->banks) | |
0807da59 | 325 | return -ENOMEM; |
a58fbcd8 | 326 | |
fc0589ca RJ |
327 | pchip->chip.label = "gpio-pxa"; |
328 | pchip->chip.direction_input = pxa_gpio_direction_input; | |
329 | pchip->chip.direction_output = pxa_gpio_direction_output; | |
330 | pchip->chip.get = pxa_gpio_get; | |
331 | pchip->chip.set = pxa_gpio_set; | |
332 | pchip->chip.to_irq = pxa_gpio_to_irq; | |
333 | pchip->chip.ngpio = ngpio; | |
72121572 | 334 | #ifdef CONFIG_OF_GPIO |
fc0589ca RJ |
335 | pchip->chip.of_node = pxa_gpio_of_node; |
336 | pchip->chip.of_xlate = pxa_gpio_of_xlate; | |
337 | pchip->chip.of_gpio_n_cells = 2; | |
72121572 | 338 | #endif |
0807da59 | 339 | |
fc0589ca RJ |
340 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { |
341 | bank = pchip->banks + i; | |
342 | bank->regbase = regbase + BANK_OFF(i); | |
0807da59 | 343 | } |
fc0589ca RJ |
344 | |
345 | return gpiochip_add(&pchip->chip); | |
0807da59 | 346 | } |
e3630db1 | 347 | |
a8f6faeb EM |
348 | /* Update only those GRERx and GFERx edge detection register bits if those |
349 | * bits are set in c->irq_mask | |
350 | */ | |
fc0589ca | 351 | static inline void update_edge_detect(struct pxa_gpio_bank *c) |
a8f6faeb EM |
352 | { |
353 | uint32_t grer, gfer; | |
354 | ||
df664d20 HZ |
355 | grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; |
356 | gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; | |
a8f6faeb EM |
357 | grer |= c->irq_edge_rise & c->irq_mask; |
358 | gfer |= c->irq_edge_fall & c->irq_mask; | |
df664d20 HZ |
359 | writel_relaxed(grer, c->regbase + GRER_OFFSET); |
360 | writel_relaxed(gfer, c->regbase + GFER_OFFSET); | |
a8f6faeb EM |
361 | } |
362 | ||
a3f4c927 | 363 | static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) |
e3630db1 | 364 | { |
fc0589ca | 365 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
4929f5a8 | 366 | int gpio = pxa_irq_to_gpio(d->irq); |
fc0589ca | 367 | struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); |
0807da59 | 368 | unsigned long gpdr, mask = GPIO_bit(gpio); |
e3630db1 | 369 | |
e3630db1 | 370 | if (type == IRQ_TYPE_PROBE) { |
371 | /* Don't mess with enabled GPIOs using preconfigured edges or | |
372 | * GPIOs set to alternate function or to output during probe | |
373 | */ | |
0807da59 | 374 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) |
e3630db1 | 375 | return 0; |
689c04a3 | 376 | |
fc0589ca | 377 | if (__gpio_is_occupied(pchip, gpio)) |
e3630db1 | 378 | return 0; |
689c04a3 | 379 | |
e3630db1 | 380 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
381 | } | |
382 | ||
df664d20 | 383 | gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); |
0807da59 | 384 | |
067455aa | 385 | if (__gpio_is_inverted(gpio)) |
df664d20 | 386 | writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); |
067455aa | 387 | else |
df664d20 | 388 | writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); |
e3630db1 | 389 | |
390 | if (type & IRQ_TYPE_EDGE_RISING) | |
0807da59 | 391 | c->irq_edge_rise |= mask; |
e3630db1 | 392 | else |
0807da59 | 393 | c->irq_edge_rise &= ~mask; |
e3630db1 | 394 | |
395 | if (type & IRQ_TYPE_EDGE_FALLING) | |
0807da59 | 396 | c->irq_edge_fall |= mask; |
e3630db1 | 397 | else |
0807da59 | 398 | c->irq_edge_fall &= ~mask; |
e3630db1 | 399 | |
a8f6faeb | 400 | update_edge_detect(c); |
e3630db1 | 401 | |
a3f4c927 | 402 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, |
e3630db1 | 403 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), |
404 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | |
405 | return 0; | |
406 | } | |
407 | ||
bd0b9ac4 | 408 | static void pxa_gpio_demux_handler(struct irq_desc *desc) |
e3630db1 | 409 | { |
fc0589ca | 410 | int loop, gpio, n, handled = 0; |
0807da59 | 411 | unsigned long gedr; |
0d2ee5d7 | 412 | struct irq_chip *chip = irq_desc_get_chip(desc); |
fc0589ca RJ |
413 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
414 | struct pxa_gpio_bank *c; | |
0d2ee5d7 CX |
415 | |
416 | chained_irq_enter(chip, desc); | |
e3630db1 | 417 | |
418 | do { | |
e3630db1 | 419 | loop = 0; |
fc0589ca | 420 | for_each_gpio_bank(gpio, c, pchip) { |
df664d20 | 421 | gedr = readl_relaxed(c->regbase + GEDR_OFFSET); |
0807da59 | 422 | gedr = gedr & c->irq_mask; |
df664d20 | 423 | writel_relaxed(gedr, c->regbase + GEDR_OFFSET); |
e3630db1 | 424 | |
d724f1c9 | 425 | for_each_set_bit(n, &gedr, BITS_PER_LONG) { |
0807da59 | 426 | loop = 1; |
e3630db1 | 427 | |
fc0589ca | 428 | generic_handle_irq(gpio_to_irq(gpio + n)); |
0807da59 | 429 | } |
e3630db1 | 430 | } |
431 | } while (loop); | |
0d2ee5d7 CX |
432 | |
433 | chained_irq_exit(chip, desc); | |
e3630db1 | 434 | } |
435 | ||
a3f4c927 | 436 | static void pxa_ack_muxed_gpio(struct irq_data *d) |
e3630db1 | 437 | { |
fc0589ca | 438 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
4929f5a8 | 439 | int gpio = pxa_irq_to_gpio(d->irq); |
fc0589ca | 440 | void __iomem *base = gpio_bank_base(&pchip->chip, gpio); |
0807da59 | 441 | |
fc0589ca | 442 | writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); |
e3630db1 | 443 | } |
444 | ||
a3f4c927 | 445 | static void pxa_mask_muxed_gpio(struct irq_data *d) |
e3630db1 | 446 | { |
fc0589ca | 447 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
4929f5a8 | 448 | int gpio = pxa_irq_to_gpio(d->irq); |
fc0589ca RJ |
449 | struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); |
450 | void __iomem *base = gpio_bank_base(&pchip->chip, gpio); | |
0807da59 EM |
451 | uint32_t grer, gfer; |
452 | ||
fc0589ca | 453 | b->irq_mask &= ~GPIO_bit(gpio); |
0807da59 | 454 | |
fc0589ca RJ |
455 | grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); |
456 | gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); | |
457 | writel_relaxed(grer, base + GRER_OFFSET); | |
458 | writel_relaxed(gfer, base + GFER_OFFSET); | |
e3630db1 | 459 | } |
460 | ||
b95ace54 RJ |
461 | static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) |
462 | { | |
463 | int gpio = pxa_irq_to_gpio(d->irq); | |
fc0589ca | 464 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
b95ace54 | 465 | |
fc0589ca RJ |
466 | if (pchip->set_wake) |
467 | return pchip->set_wake(gpio, on); | |
b95ace54 RJ |
468 | else |
469 | return 0; | |
470 | } | |
471 | ||
a3f4c927 | 472 | static void pxa_unmask_muxed_gpio(struct irq_data *d) |
e3630db1 | 473 | { |
fc0589ca | 474 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
4929f5a8 | 475 | int gpio = pxa_irq_to_gpio(d->irq); |
fc0589ca | 476 | struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); |
0807da59 EM |
477 | |
478 | c->irq_mask |= GPIO_bit(gpio); | |
a8f6faeb | 479 | update_edge_detect(c); |
e3630db1 | 480 | } |
481 | ||
482 | static struct irq_chip pxa_muxed_gpio_chip = { | |
483 | .name = "GPIO", | |
a3f4c927 LB |
484 | .irq_ack = pxa_ack_muxed_gpio, |
485 | .irq_mask = pxa_mask_muxed_gpio, | |
486 | .irq_unmask = pxa_unmask_muxed_gpio, | |
487 | .irq_set_type = pxa_gpio_irq_type, | |
b95ace54 | 488 | .irq_set_wake = pxa_gpio_set_wake, |
e3630db1 | 489 | }; |
490 | ||
2cab0292 | 491 | static int pxa_gpio_nums(struct platform_device *pdev) |
478e223c | 492 | { |
2cab0292 HZ |
493 | const struct platform_device_id *id = platform_get_device_id(pdev); |
494 | struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; | |
478e223c HZ |
495 | int count = 0; |
496 | ||
2cab0292 HZ |
497 | switch (pxa_id->type) { |
498 | case PXA25X_GPIO: | |
499 | case PXA26X_GPIO: | |
500 | case PXA27X_GPIO: | |
501 | case PXA3XX_GPIO: | |
502 | case PXA93X_GPIO: | |
503 | case MMP_GPIO: | |
504 | case MMP2_GPIO: | |
684bba2f | 505 | case PXA1928_GPIO: |
2cab0292 HZ |
506 | gpio_type = pxa_id->type; |
507 | count = pxa_id->gpio_nums - 1; | |
508 | break; | |
509 | default: | |
510 | count = -EINVAL; | |
511 | break; | |
478e223c | 512 | } |
478e223c HZ |
513 | return count; |
514 | } | |
515 | ||
f43e04ec | 516 | #ifdef CONFIG_OF |
0fb39412 | 517 | static const struct of_device_id pxa_gpio_dt_ids[] = { |
f8731174 HZ |
518 | { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, |
519 | { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, | |
520 | { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, | |
521 | { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, | |
522 | { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, | |
523 | { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, | |
524 | { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, | |
684bba2f | 525 | { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, |
7a4d5079 HZ |
526 | {} |
527 | }; | |
528 | ||
529 | static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, | |
530 | irq_hw_number_t hw) | |
531 | { | |
532 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
533 | handle_edge_irq); | |
23393d49 | 534 | irq_set_noprobe(irq); |
7a4d5079 HZ |
535 | return 0; |
536 | } | |
537 | ||
538 | const struct irq_domain_ops pxa_irq_domain_ops = { | |
539 | .map = pxa_irq_domain_map, | |
72121572 | 540 | .xlate = irq_domain_xlate_twocell, |
7a4d5079 HZ |
541 | }; |
542 | ||
fc0589ca RJ |
543 | static int pxa_gpio_probe_dt(struct platform_device *pdev, |
544 | struct pxa_gpio_chip *pchip) | |
7a4d5079 | 545 | { |
fc0589ca | 546 | int nr_gpios; |
5dbb7c63 | 547 | struct device_node *np = pdev->dev.of_node; |
7a4d5079 HZ |
548 | const struct of_device_id *of_id = |
549 | of_match_device(pxa_gpio_dt_ids, &pdev->dev); | |
f8731174 | 550 | const struct pxa_gpio_id *gpio_id; |
7a4d5079 | 551 | |
f8731174 | 552 | if (!of_id || !of_id->data) { |
7a4d5079 HZ |
553 | dev_err(&pdev->dev, "Failed to find gpio controller\n"); |
554 | return -EFAULT; | |
555 | } | |
f8731174 HZ |
556 | gpio_id = of_id->data; |
557 | gpio_type = gpio_id->type; | |
7a4d5079 | 558 | |
f8731174 | 559 | nr_gpios = gpio_id->gpio_nums; |
7a4d5079 HZ |
560 | pxa_last_gpio = nr_gpios - 1; |
561 | ||
562 | irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); | |
563 | if (irq_base < 0) { | |
564 | dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); | |
fc0589ca | 565 | return irq_base; |
7a4d5079 HZ |
566 | } |
567 | domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, | |
fc0589ca | 568 | &pxa_irq_domain_ops, pchip); |
72121572 | 569 | pxa_gpio_of_node = np; |
7a4d5079 | 570 | return 0; |
7a4d5079 HZ |
571 | } |
572 | #else | |
fc0589ca | 573 | #define pxa_gpio_probe_dt(pdev, pchip) (-1) |
7a4d5079 HZ |
574 | #endif |
575 | ||
3836309d | 576 | static int pxa_gpio_probe(struct platform_device *pdev) |
e3630db1 | 577 | { |
fc0589ca RJ |
578 | struct pxa_gpio_chip *pchip; |
579 | struct pxa_gpio_bank *c; | |
157d2644 | 580 | struct resource *res; |
389eda15 | 581 | struct clk *clk; |
b95ace54 | 582 | struct pxa_gpio_platform_data *info; |
fc0589ca | 583 | void __iomem *gpio_reg_base; |
7a4d5079 | 584 | int gpio, irq, ret, use_of = 0; |
157d2644 | 585 | int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; |
e3630db1 | 586 | |
fc0589ca RJ |
587 | pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); |
588 | if (!pchip) | |
589 | return -ENOMEM; | |
590 | pchip->dev = &pdev->dev; | |
591 | ||
b8f649f1 HZ |
592 | info = dev_get_platdata(&pdev->dev); |
593 | if (info) { | |
594 | irq_base = info->irq_base; | |
595 | if (irq_base <= 0) | |
596 | return -EINVAL; | |
2cab0292 | 597 | pxa_last_gpio = pxa_gpio_nums(pdev); |
fc0589ca | 598 | pchip->set_wake = info->gpio_set_wake; |
9450be76 | 599 | } else { |
b8f649f1 | 600 | irq_base = 0; |
7a4d5079 | 601 | use_of = 1; |
fc0589ca | 602 | ret = pxa_gpio_probe_dt(pdev, pchip); |
b8f649f1 HZ |
603 | if (ret < 0) |
604 | return -EINVAL; | |
9450be76 DM |
605 | } |
606 | ||
478e223c | 607 | if (!pxa_last_gpio) |
157d2644 HZ |
608 | return -EINVAL; |
609 | ||
610 | irq0 = platform_get_irq_byname(pdev, "gpio0"); | |
611 | irq1 = platform_get_irq_byname(pdev, "gpio1"); | |
612 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); | |
613 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) | |
614 | || (irq_mux <= 0)) | |
615 | return -EINVAL; | |
616 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
617 | if (!res) | |
618 | return -EINVAL; | |
619 | gpio_reg_base = ioremap(res->start, resource_size(res)); | |
620 | if (!gpio_reg_base) | |
621 | return -EINVAL; | |
622 | ||
623 | if (irq0 > 0) | |
624 | gpio_offset = 2; | |
e3630db1 | 625 | |
389eda15 HZ |
626 | clk = clk_get(&pdev->dev, NULL); |
627 | if (IS_ERR(clk)) { | |
628 | dev_err(&pdev->dev, "Error %ld to get gpio clock\n", | |
629 | PTR_ERR(clk)); | |
630 | iounmap(gpio_reg_base); | |
631 | return PTR_ERR(clk); | |
632 | } | |
6ab49f42 | 633 | ret = clk_prepare_enable(clk); |
389eda15 HZ |
634 | if (ret) { |
635 | clk_put(clk); | |
636 | iounmap(gpio_reg_base); | |
637 | return ret; | |
638 | } | |
389eda15 | 639 | |
0807da59 | 640 | /* Initialize GPIO chips */ |
fc0589ca RJ |
641 | ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base); |
642 | if (ret) { | |
643 | clk_put(clk); | |
644 | return ret; | |
645 | } | |
0807da59 | 646 | |
e3630db1 | 647 | /* clear all GPIO edge detects */ |
fc0589ca | 648 | for_each_gpio_bank(gpio, c, pchip) { |
df664d20 HZ |
649 | writel_relaxed(0, c->regbase + GFER_OFFSET); |
650 | writel_relaxed(0, c->regbase + GRER_OFFSET); | |
e37f4af7 | 651 | writel_relaxed(~0, c->regbase + GEDR_OFFSET); |
be24168f HZ |
652 | /* unmask GPIO edge detect for AP side */ |
653 | if (gpio_is_mmp_type(gpio_type)) | |
654 | writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); | |
e3630db1 | 655 | } |
656 | ||
7a4d5079 | 657 | if (!use_of) { |
ae4f4cfd RH |
658 | if (irq0 > 0) { |
659 | irq = gpio_to_irq(0); | |
660 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
661 | handle_edge_irq); | |
23393d49 | 662 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
ae4f4cfd RH |
663 | } |
664 | if (irq1 > 0) { | |
665 | irq = gpio_to_irq(1); | |
666 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
667 | handle_edge_irq); | |
23393d49 | 668 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
ae4f4cfd | 669 | } |
7a4d5079 HZ |
670 | |
671 | for (irq = gpio_to_irq(gpio_offset); | |
672 | irq <= gpio_to_irq(pxa_last_gpio); irq++) { | |
673 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, | |
674 | handle_edge_irq); | |
23393d49 | 675 | irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
7a4d5079 | 676 | } |
e3630db1 | 677 | } |
678 | ||
ae4f4cfd RH |
679 | if (irq0 > 0) |
680 | irq_set_chained_handler(irq0, pxa_gpio_demux_handler); | |
681 | if (irq1 > 0) | |
682 | irq_set_chained_handler(irq1, pxa_gpio_demux_handler); | |
fc0589ca | 683 | pxa_gpio_chip = pchip; |
ae4f4cfd | 684 | |
157d2644 HZ |
685 | irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); |
686 | return 0; | |
687 | } | |
688 | ||
2cab0292 HZ |
689 | static const struct platform_device_id gpio_id_table[] = { |
690 | { "pxa25x-gpio", (unsigned long)&pxa25x_id }, | |
691 | { "pxa26x-gpio", (unsigned long)&pxa26x_id }, | |
692 | { "pxa27x-gpio", (unsigned long)&pxa27x_id }, | |
693 | { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, | |
694 | { "pxa93x-gpio", (unsigned long)&pxa93x_id }, | |
695 | { "mmp-gpio", (unsigned long)&mmp_id }, | |
696 | { "mmp2-gpio", (unsigned long)&mmp2_id }, | |
684bba2f | 697 | { "pxa1928-gpio", (unsigned long)&pxa1928_id }, |
2cab0292 HZ |
698 | { }, |
699 | }; | |
700 | ||
157d2644 HZ |
701 | static struct platform_driver pxa_gpio_driver = { |
702 | .probe = pxa_gpio_probe, | |
703 | .driver = { | |
704 | .name = "pxa-gpio", | |
f43e04ec | 705 | .of_match_table = of_match_ptr(pxa_gpio_dt_ids), |
157d2644 | 706 | }, |
2cab0292 | 707 | .id_table = gpio_id_table, |
157d2644 | 708 | }; |
cf3fa17c | 709 | |
eae122b8 | 710 | static int __init pxa_gpio_legacy_init(void) |
cf3fa17c | 711 | { |
eae122b8 RJ |
712 | if (of_have_populated_dt()) |
713 | return 0; | |
714 | ||
cf3fa17c LW |
715 | return platform_driver_register(&pxa_gpio_driver); |
716 | } | |
eae122b8 RJ |
717 | postcore_initcall(pxa_gpio_legacy_init); |
718 | ||
719 | static int __init pxa_gpio_dt_init(void) | |
720 | { | |
721 | if (of_have_populated_dt()) | |
722 | return platform_driver_register(&pxa_gpio_driver); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | device_initcall(pxa_gpio_dt_init); | |
663707c1 | 727 | |
728 | #ifdef CONFIG_PM | |
2eaa03b5 | 729 | static int pxa_gpio_suspend(void) |
663707c1 | 730 | { |
fc0589ca RJ |
731 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
732 | struct pxa_gpio_bank *c; | |
0807da59 | 733 | int gpio; |
663707c1 | 734 | |
fc0589ca | 735 | for_each_gpio_bank(gpio, c, pchip) { |
df664d20 HZ |
736 | c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); |
737 | c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); | |
738 | c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); | |
739 | c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); | |
663707c1 | 740 | |
741 | /* Clear GPIO transition detect bits */ | |
df664d20 | 742 | writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); |
663707c1 | 743 | } |
744 | return 0; | |
745 | } | |
746 | ||
2eaa03b5 | 747 | static void pxa_gpio_resume(void) |
663707c1 | 748 | { |
fc0589ca RJ |
749 | struct pxa_gpio_chip *pchip = pxa_gpio_chip; |
750 | struct pxa_gpio_bank *c; | |
0807da59 | 751 | int gpio; |
663707c1 | 752 | |
fc0589ca | 753 | for_each_gpio_bank(gpio, c, pchip) { |
663707c1 | 754 | /* restore level with set/clear */ |
e37f4af7 | 755 | writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); |
df664d20 | 756 | writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); |
663707c1 | 757 | |
df664d20 HZ |
758 | writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); |
759 | writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); | |
760 | writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); | |
663707c1 | 761 | } |
663707c1 | 762 | } |
763 | #else | |
764 | #define pxa_gpio_suspend NULL | |
765 | #define pxa_gpio_resume NULL | |
766 | #endif | |
767 | ||
2eaa03b5 | 768 | struct syscore_ops pxa_gpio_syscore_ops = { |
663707c1 | 769 | .suspend = pxa_gpio_suspend, |
770 | .resume = pxa_gpio_resume, | |
771 | }; | |
157d2644 HZ |
772 | |
773 | static int __init pxa_gpio_sysinit(void) | |
774 | { | |
775 | register_syscore_ops(&pxa_gpio_syscore_ops); | |
776 | return 0; | |
777 | } | |
778 | postcore_initcall(pxa_gpio_sysinit); |