[deliverable/linux.git] / drivers / gpio / gpio-stmpe.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>
#include <linux/seq_file.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

enum { LSB, CSB, MSB };

#define CACHE_NR_REGS	3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS	(24 / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;
	u32 norequest_mask;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which + (offset / 8)];
	u8 mask = 1 << (offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_get_direction(struct gpio_chip *chip,
				    unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !(ret & mask);
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = 1 << (offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = 1 << (offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & (1 << offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
}

static struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.get_direction		= stmpe_gpio_get_direction,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.request		= stmpe_gpio_request,
	.can_sleep		= true,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801 ||
	    stmpe_gpio->stmpe->partnum == STMPE1600)
		return 0;

	if (type & IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
		[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
		[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
		[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
		[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
		[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
		[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
		[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
		[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
		[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 and STMPE1600 don't have RE and FE registers */
		if ((stmpe->partnum == STMPE801 ||
		     stmpe->partnum == STMPE1600) &&
		     (i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] |= mask;

	/*
	 * STMPE1600 workaround: to be able to get IRQ from pins,
	 * a read must be done on GPMR register, or a write in
	 * GPSR or GPCR registers
	 */
	if (stmpe->partnum == STMPE1600)
		stmpe_reg_read(stmpe,
			       stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
}

static void stmpe_dbg_show_one(struct seq_file *s,
			       struct gpio_chip *gc,
			       unsigned offset, unsigned gpio)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	const char *label = gpiochip_is_requested(gc, offset);
	bool val = !!stmpe_gpio_get(gc, offset);
	u8 bank = offset / 8;
	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
	u8 mask = 1 << (offset % 8);
	int ret;
	u8 dir;

	ret = stmpe_reg_read(stmpe, dir_reg);
	if (ret < 0)
		return;
	dir = !!(ret & mask);

	if (dir) {
		seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo");
	} else {
		u8 edge_det_reg;
		u8 rise_reg;
		u8 fall_reg;
		u8 irqen_reg;

		char *edge_det_values[] = {"edge-inactive",
					   "edge-asserted",
					   "not-supported"};
		char *rise_values[] = {"no-rising-edge-detection",
				       "rising-edge-detection",
				       "not-supported"};
		char *fall_values[] = {"no-falling-edge-detection",
				       "falling-edge-detection",
				       "not-supported"};
		#define NOT_SUPPORTED_IDX 2
		u8 edge_det = NOT_SUPPORTED_IDX;
		u8 rise = NOT_SUPPORTED_IDX;
		u8 fall = NOT_SUPPORTED_IDX;
		bool irqen;

		switch (stmpe->partnum) {
		case STMPE610:
		case STMPE811:
		case STMPE1601:
		case STMPE2401:
		case STMPE2403:
			edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
			ret = stmpe_reg_read(stmpe, edge_det_reg);
			if (ret < 0)
				return;
			edge_det = !!(ret & mask);

		case STMPE1801:
			rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
			fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];

			ret = stmpe_reg_read(stmpe, rise_reg);
			if (ret < 0)
				return;
			rise = !!(ret & mask);
			ret = stmpe_reg_read(stmpe, fall_reg);
			if (ret < 0)
				return;
			fall = !!(ret & mask);

		case STMPE801:
		case STMPE1600:
			irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
			break;

		default:
			return;
		}

		ret = stmpe_reg_read(stmpe, irqen_reg);
		if (ret < 0)
			return;
		irqen = !!(ret & mask);

		seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo",
			   edge_det_values[edge_det],
			   irqen ? "IRQ-enabled" : "IRQ-disabled",
			   rise_values[rise],
			   fall_values[fall]);
	}
}

static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
	unsigned i;
	unsigned gpio = gc->base;

	for (i = 0; i < gc->ngpio; i++, gpio++) {
		stmpe_dbg_show_one(s, gc, i, gpio);
		seq_printf(s, "\n");
	}
}

static struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
};

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[num_banks];
	int ret;
	int i;

	/*
	 * the stmpe_block_read() call below, imposes to set statmsbreg
	 * with the register located at the lowest address. As STMPE1600
	 * variant is the only one which respect registers address's order
	 * (LSB regs located at lowest address than MSB ones) whereas all
	 * the others have a registers layout with MSB located before the
	 * LSB regs.
	 */
	if (stmpe->partnum == STMPE1600)
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	else
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
			   num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
							 line);

			handle_nested_irq(child_irq);
			stat &= ~(1 << bit);
		}

		/*
		 * interrupt status register write has no effect on
		 * 801/1801/1600, bits are cleared when read.
		 * Edge detect register is not present on 801/1600/1801
		 */
		if (stmpe->partnum != STMPE801 || stmpe->partnum != STMPE1600 ||
		    stmpe->partnum != STMPE1801) {
			stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
			stmpe_reg_write(stmpe,
					stmpe->regs[STMPE_IDX_GPEDR_LSB + i],
					status[i]);
		}
	}

	return IRQ_HANDLED;
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct stmpe_gpio *stmpe_gpio;
	int ret;
	int irq = 0;

	irq = platform_get_irq(pdev, 0);

	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.parent = &pdev->dev;
	stmpe_gpio->chip.of_node = np;
	stmpe_gpio->chip.base = -1;

	if (IS_ENABLED(CONFIG_DEBUG_FS))
                stmpe_gpio->chip.dbg_show = stmpe_dbg_show;

	of_property_read_u32(np, "st,norequest-mask",
			&stmpe_gpio->norequest_mask);

	if (irq < 0)
		dev_info(&pdev->dev,
			"device configured in no-irq mode: "
			"irqs are not available\n");

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		goto out_free;

	ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_disable;
	}

	if (irq > 0) {
		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
				stmpe_gpio_irq, IRQF_ONESHOT,
				"stmpe-gpio", stmpe_gpio);
		if (ret) {
			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
			goto out_disable;
		}
		ret =  gpiochip_irqchip_add(&stmpe_gpio->chip,
					    &stmpe_gpio_irq_chip,
					    0,
					    handle_simple_irq,
					    IRQ_TYPE_NONE);
		if (ret) {
			dev_err(&pdev->dev,
				"could not connect irqchip to gpiochip\n");
			goto out_disable;
		}

		gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
					     &stmpe_gpio_irq_chip,
					     irq,
					     NULL);
	}

	platform_set_drvdata(pdev, stmpe_gpio);

	return 0;

out_disable:
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	gpiochip_remove(&stmpe_gpio->chip);
out_free:
	kfree(stmpe_gpio);
	return ret;
}

static struct platform_driver stmpe_gpio_driver = {
	.driver = {
		.suppress_bind_attrs	= true,
		.name			= "stmpe-gpio",
	},
	.probe		= stmpe_gpio_probe,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);
Commit	Line	Data
03f822f5 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
03f822f5 RV	8	#include <linux/init.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/slab.h>
	11	#include <linux/gpio.h>
03f822f5	12	#include <linux/interrupt.h>
86605cfe	13	#include <linux/of.h>
03f822f5	14	#include <linux/mfd/stmpe.h>
27ec8a9c	15	#include <linux/seq_file.h>
03f822f5 RV	16
	17	/*
	18	* These registers are modified under the irq bus lock and cached to avoid
	19	* unnecessary writes in bus_sync_unlock.
	20	*/
	21	enum { REG_RE, REG_FE, REG_IE };
	22
43db289d PC	23	enum { LSB, CSB, MSB };
43db289d PC	24
03f822f5	25	#define CACHE_NR_REGS 3
9e9dc7d9 LW	26	/* No variant has more than 24 GPIOs */
9e9dc7d9 LW	27	#define CACHE_NR_BANKS (24 / 8)
03f822f5 RV	28
	29	struct stmpe_gpio {
	30	struct gpio_chip chip;
	31	struct stmpe *stmpe;
	32	struct device *dev;
	33	struct mutex irq_lock;
1dfb4a0d	34	u32 norequest_mask;
03f822f5 RV	35	/* Caches of interrupt control registers for bus_lock */
	36	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	37	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	38	};
	39
03f822f5 RV	40	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	41	{
b03c04a0	42	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	43	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	44	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
03f822f5 RV	45	u8 mask = 1 << (offset % 8);
	46	int ret;
	47
	48	ret = stmpe_reg_read(stmpe, reg);
	49	if (ret < 0)
	50	return ret;
	51
7535b8be	52	return !!(ret & mask);
03f822f5 RV	53	}
	54
	55	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	56	{
b03c04a0	57	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	58	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	59	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
43db289d	60	u8 reg = stmpe->regs[which + (offset / 8)];
03f822f5 RV	61	u8 mask = 1 << (offset % 8);
03f822f5 RV	62
cccdceb9 VK	63	/*
	64	* Some variants have single register for gpio set/clear functionality.
	65	* For them we need to write 0 to clear and 1 to set.
	66	*/
	67	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	68	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	69	else
	70	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	71	}
03f822f5 RV	72
8e293fb0 LW	73	static int stmpe_gpio_get_direction(struct gpio_chip *chip,
	74	unsigned offset)
	75	{
	76	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	77	struct stmpe *stmpe = stmpe_gpio->stmpe;
	78	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	79	u8 mask = 1 << (offset % 8);
	80	int ret;
	81
	82	ret = stmpe_reg_read(stmpe, reg);
	83	if (ret < 0)
	84	return ret;
	85
	86	return !(ret & mask);
	87	}
	88
03f822f5 RV	89	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	90	unsigned offset, int val)
	91	{
b03c04a0	92	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	93	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	94	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
03f822f5 RV	95	u8 mask = 1 << (offset % 8);
	96
	97	stmpe_gpio_set(chip, offset, val);
	98
	99	return stmpe_set_bits(stmpe, reg, mask, mask);
	100	}
	101
	102	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	103	unsigned offset)
	104	{
b03c04a0	105	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	106	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	107	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
03f822f5 RV	108	u8 mask = 1 << (offset % 8);
	109
	110	return stmpe_set_bits(stmpe, reg, mask, 0);
	111	}
	112
03f822f5 RV	113	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	114	{
b03c04a0	115	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	116	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	117
b8e9cf0b WS	118	if (stmpe_gpio->norequest_mask & (1 << offset))
	119	return -EINVAL;
	120
03f822f5 RV	121	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
	122	}
	123
	124	static struct gpio_chip template_chip = {
	125	.label = "stmpe",
	126	.owner = THIS_MODULE,
8e293fb0	127	.get_direction = stmpe_gpio_get_direction,
03f822f5 RV	128	.direction_input = stmpe_gpio_direction_input,
	129	.get = stmpe_gpio_get,
	130	.direction_output = stmpe_gpio_direction_output,
	131	.set = stmpe_gpio_set,
03f822f5	132	.request = stmpe_gpio_request,
9fb1f39e	133	.can_sleep = true,
03f822f5 RV	134	};
03f822f5 RV	135
2a866f39	136	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	137	{
fe44e70d	138	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	139	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	140	int offset = d->hwirq;
03f822f5 RV	141	int regoffset = offset / 8;
	142	int mask = 1 << (offset % 8);
	143
1fe3bd9e	144	if (type & IRQ_TYPE_LEVEL_LOW \|\| type & IRQ_TYPE_LEVEL_HIGH)
03f822f5 RV	145	return -EINVAL;
03f822f5 RV	146
c6a05a05 PC	147	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	148	if (stmpe_gpio->stmpe->partnum == STMPE801 \|\|
	149	stmpe_gpio->stmpe->partnum == STMPE1600)
cccdceb9 VK	150	return 0;
cccdceb9 VK	151
1fe3bd9e	152	if (type & IRQ_TYPE_EDGE_RISING)
03f822f5 RV	153	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	154	else
	155	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	156
1fe3bd9e	157	if (type & IRQ_TYPE_EDGE_FALLING)
03f822f5 RV	158	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	159	else
	160	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	161
	162	return 0;
	163	}
	164
2a866f39	165	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	166	{
fe44e70d	167	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	168	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	169
	170	mutex_lock(&stmpe_gpio->irq_lock);
	171	}
	172
2a866f39	173	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	174	{
fe44e70d	175	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	176	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	177	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	178	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
43db289d PC	179	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
	180	[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
	181	[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
	182	[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
	183	[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
	184	[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
	185	[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
	186	[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
	187	[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
	188	[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
03f822f5 RV	189	};
	190	int i, j;
	191
	192	for (i = 0; i < CACHE_NR_REGS; i++) {
c6a05a05 PC	193	/* STMPE801 and STMPE1600 don't have RE and FE registers */
	194	if ((stmpe->partnum == STMPE801 \|\|
	195	stmpe->partnum == STMPE1600) &&
	196	(i != REG_IE))
cccdceb9 VK	197	continue;
cccdceb9 VK	198
03f822f5 RV	199	for (j = 0; j < num_banks; j++) {
	200	u8 old = stmpe_gpio->oldregs[i][j];
	201	u8 new = stmpe_gpio->regs[i][j];
	202
	203	if (new == old)
	204	continue;
	205
	206	stmpe_gpio->oldregs[i][j] = new;
43db289d	207	stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
03f822f5 RV	208	}
	209	}
	210
	211	mutex_unlock(&stmpe_gpio->irq_lock);
	212	}
	213
2a866f39	214	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	215	{
fe44e70d	216	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	217	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	218	int offset = d->hwirq;
03f822f5 RV	219	int regoffset = offset / 8;
	220	int mask = 1 << (offset % 8);
	221
	222	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	223	}
	224
2a866f39	225	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	226	{
fe44e70d	227	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	228	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
c6a05a05	229	struct stmpe *stmpe = stmpe_gpio->stmpe;
fc13d5a5	230	int offset = d->hwirq;
03f822f5 RV	231	int regoffset = offset / 8;
	232	int mask = 1 << (offset % 8);
	233
	234	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
c6a05a05 PC	235
	236	/*
	237	* STMPE1600 workaround: to be able to get IRQ from pins,
	238	* a read must be done on GPMR register, or a write in
	239	* GPSR or GPCR registers
	240	*/
	241	if (stmpe->partnum == STMPE1600)
	242	stmpe_reg_read(stmpe,
	243	stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
03f822f5 RV	244	}
03f822f5 RV	245
27ec8a9c LW	246	static void stmpe_dbg_show_one(struct seq_file *s,
	247	struct gpio_chip *gc,
	248	unsigned offset, unsigned gpio)
	249	{
b03c04a0	250	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
27ec8a9c LW	251	struct stmpe *stmpe = stmpe_gpio->stmpe;
27ec8a9c LW	252	const char *label = gpiochip_is_requested(gc, offset);
27ec8a9c	253	bool val = !!stmpe_gpio_get(gc, offset);
43db289d PC	254	u8 bank = offset / 8;
43db289d PC	255	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
27ec8a9c LW	256	u8 mask = 1 << (offset % 8);
	257	int ret;
	258	u8 dir;
	259
	260	ret = stmpe_reg_read(stmpe, dir_reg);
	261	if (ret < 0)
	262	return;
	263	dir = !!(ret & mask);
	264
	265	if (dir) {
	266	seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
	267	gpio, label ?: "(none)",
	268	val ? "hi" : "lo");
	269	} else {
287849cb PC	270	u8 edge_det_reg;
	271	u8 rise_reg;
	272	u8 fall_reg;
	273	u8 irqen_reg;
	274
	275	char *edge_det_values[] = {"edge-inactive",
	276	"edge-asserted",
	277	"not-supported"};
	278	char *rise_values[] = {"no-rising-edge-detection",
	279	"rising-edge-detection",
	280	"not-supported"};
	281	char *fall_values[] = {"no-falling-edge-detection",
	282	"falling-edge-detection",
	283	"not-supported"};
	284	#define NOT_SUPPORTED_IDX 2
	285	u8 edge_det = NOT_SUPPORTED_IDX;
	286	u8 rise = NOT_SUPPORTED_IDX;
	287	u8 fall = NOT_SUPPORTED_IDX;
27ec8a9c LW	288	bool irqen;
27ec8a9c LW	289
287849cb PC	290	switch (stmpe->partnum) {
	291	case STMPE610:
	292	case STMPE811:
	293	case STMPE1601:
	294	case STMPE2401:
	295	case STMPE2403:
43db289d	296	edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
287849cb PC	297	ret = stmpe_reg_read(stmpe, edge_det_reg);
	298	if (ret < 0)
	299	return;
	300	edge_det = !!(ret & mask);
	301
	302	case STMPE1801:
43db289d PC	303	rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
	304	fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
	305
287849cb PC	306	ret = stmpe_reg_read(stmpe, rise_reg);
	307	if (ret < 0)
	308	return;
	309	rise = !!(ret & mask);
	310	ret = stmpe_reg_read(stmpe, fall_reg);
	311	if (ret < 0)
	312	return;
	313	fall = !!(ret & mask);
	314
	315	case STMPE801:
c6a05a05	316	case STMPE1600:
43db289d	317	irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
287849cb PC	318	break;
	319
	320	default:
27ec8a9c	321	return;
287849cb PC	322	}
287849cb PC	323
27ec8a9c LW	324	ret = stmpe_reg_read(stmpe, irqen_reg);
	325	if (ret < 0)
	326	return;
	327	irqen = !!(ret & mask);
	328
287849cb	329	seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
27ec8a9c LW	330	gpio, label ?: "(none)",
27ec8a9c LW	331	val ? "hi" : "lo",
287849cb PC	332	edge_det_values[edge_det],
	333	irqen ? "IRQ-enabled" : "IRQ-disabled",
	334	rise_values[rise],
	335	fall_values[fall]);
27ec8a9c LW	336	}
	337	}
	338
	339	static void stmpe_dbg_show(struct seq_file s, struct gpio_chip gc)
	340	{
	341	unsigned i;
	342	unsigned gpio = gc->base;
	343
	344	for (i = 0; i < gc->ngpio; i++, gpio++) {
	345	stmpe_dbg_show_one(s, gc, i, gpio);
	346	seq_printf(s, "\n");
	347	}
	348	}
	349
03f822f5 RV	350	static struct irq_chip stmpe_gpio_irq_chip = {
03f822f5 RV	351	.name = "stmpe-gpio",
2a866f39 LB	352	.irq_bus_lock = stmpe_gpio_irq_lock,
	353	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	354	.irq_mask = stmpe_gpio_irq_mask,
	355	.irq_unmask = stmpe_gpio_irq_unmask,
	356	.irq_set_type = stmpe_gpio_irq_set_type,
03f822f5 RV	357	};
	358
	359	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	360	{
	361	struct stmpe_gpio *stmpe_gpio = dev;
	362	struct stmpe *stmpe = stmpe_gpio->stmpe;
c6a05a05	363	u8 statmsbreg;
03f822f5 RV	364	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	365	u8 status[num_banks];
	366	int ret;
	367	int i;
	368
c6a05a05 PC	369	/*
	370	* the stmpe_block_read() call below, imposes to set statmsbreg
	371	* with the register located at the lowest address. As STMPE1600
	372	* variant is the only one which respect registers address's order
	373	* (LSB regs located at lowest address than MSB ones) whereas all
	374	* the others have a registers layout with MSB located before the
	375	* LSB regs.
	376	*/
	377	if (stmpe->partnum == STMPE1600)
	378	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	379	else
	380	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	381
03f822f5 RV	382	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	383	if (ret < 0)
	384	return IRQ_NONE;
	385
	386	for (i = 0; i < num_banks; i++) {
c6a05a05 PC	387	int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
c6a05a05 PC	388	num_banks - i - 1;
03f822f5 RV	389	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	390	unsigned int stat = status[i];
	391
	392	stat &= enabled;
	393	if (!stat)
	394	continue;
	395
	396	while (stat) {
	397	int bit = __ffs(stat);
	398	int line = bank * 8 + bit;
fe44e70d	399	int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
ed05e204	400	line);
03f822f5	401
ed05e204	402	handle_nested_irq(child_irq);
03f822f5 RV	403	stat &= ~(1 << bit);
	404	}
	405
6936e1f8 PC	406	/*
6936e1f8 PC	407	* interrupt status register write has no effect on
c6a05a05 PC	408	* 801/1801/1600, bits are cleared when read.
c6a05a05 PC	409	* Edge detect register is not present on 801/1600/1801
6936e1f8	410	*/
c6a05a05 PC	411	if (stmpe->partnum != STMPE801 \|\| stmpe->partnum != STMPE1600 \|\|
c6a05a05 PC	412	stmpe->partnum != STMPE1801) {
6936e1f8	413	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
43db289d PC	414	stmpe_reg_write(stmpe,
	415	stmpe->regs[STMPE_IDX_GPEDR_LSB + i],
	416	status[i]);
6936e1f8	417	}
03f822f5 RV	418	}
	419
	420	return IRQ_HANDLED;
	421	}
	422
3836309d	423	static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5 RV	424	{
03f822f5 RV	425	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
86605cfe	426	struct device_node *np = pdev->dev.of_node;
03f822f5 RV	427	struct stmpe_gpio *stmpe_gpio;
03f822f5 RV	428	int ret;
38040c85	429	int irq = 0;
03f822f5	430
03f822f5	431	irq = platform_get_irq(pdev, 0);
03f822f5 RV	432
	433	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	434	if (!stmpe_gpio)
	435	return -ENOMEM;
	436
	437	mutex_init(&stmpe_gpio->irq_lock);
	438
	439	stmpe_gpio->dev = &pdev->dev;
	440	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	441	stmpe_gpio->chip = template_chip;
03f822f5 RV	442	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
58383c78	443	stmpe_gpio->chip.parent = &pdev->dev;
9afd9b70	444	stmpe_gpio->chip.of_node = np;
9e9dc7d9	445	stmpe_gpio->chip.base = -1;
03f822f5	446
27ec8a9c LW	447	if (IS_ENABLED(CONFIG_DEBUG_FS))
	448	stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
	449
1dfb4a0d LW	450	of_property_read_u32(np, "st,norequest-mask",
1dfb4a0d LW	451	&stmpe_gpio->norequest_mask);
86605cfe	452
9e9dc7d9	453	if (irq < 0)
38040c85	454	dev_info(&pdev->dev,
fe44e70d	455	"device configured in no-irq mode: "
38040c85	456	"irqs are not available\n");
03f822f5 RV	457
	458	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	459	if (ret)
02bf0749	460	goto out_free;
03f822f5	461
b03c04a0	462	ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
3f97d5fc LW	463	if (ret) {
	464	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	465	goto out_disable;
	466	}
	467
fe44e70d LW	468	if (irq > 0) {
	469	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	470	stmpe_gpio_irq, IRQF_ONESHOT,
	471	"stmpe-gpio", stmpe_gpio);
38040c85 CB	472	if (ret) {
38040c85 CB	473	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
fc13d5a5	474	goto out_disable;
38040c85	475	}
fe44e70d LW	476	ret = gpiochip_irqchip_add(&stmpe_gpio->chip,
	477	&stmpe_gpio_irq_chip,
	478	0,
	479	handle_simple_irq,
	480	IRQ_TYPE_NONE);
	481	if (ret) {
	482	dev_err(&pdev->dev,
	483	"could not connect irqchip to gpiochip\n");
3f97d5fc	484	goto out_disable;
fe44e70d	485	}
03f822f5	486
3f97d5fc LW	487	gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
	488	&stmpe_gpio_irq_chip,
	489	irq,
	490	NULL);
03f822f5 RV	491	}
03f822f5 RV	492
03f822f5 RV	493	platform_set_drvdata(pdev, stmpe_gpio);
	494
	495	return 0;
	496
02bf0749 VK	497	out_disable:
02bf0749 VK	498	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
3f97d5fc	499	gpiochip_remove(&stmpe_gpio->chip);
03f822f5 RV	500	out_free:
	501	kfree(stmpe_gpio);
	502	return ret;
	503	}
	504
03f822f5	505	static struct platform_driver stmpe_gpio_driver = {
3b52bb96 PG	506	.driver = {
	507	.suppress_bind_attrs = true,
	508	.name = "stmpe-gpio",
3b52bb96	509	},
03f822f5	510	.probe = stmpe_gpio_probe,
03f822f5 RV	511	};
	512
	513	static int __init stmpe_gpio_init(void)
	514	{
	515	return platform_driver_register(&stmpe_gpio_driver);
	516	}
	517	subsys_initcall(stmpe_gpio_init);