[deliverable/linux.git] / drivers / gpio / gpio-tb10x.c

/* Abilis Systems MODULE DESCRIPTION
 *
 * Copyright (C) Abilis Systems 2013
 *
 * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
 *          Christian Ruppert <christian.ruppert@abilis.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <linux/pinctrl/consumer.h>

#define TB10X_GPIO_DIR_IN	(0x00000000)
#define TB10X_GPIO_DIR_OUT	(0x00000001)
#define OFFSET_TO_REG_DDR	(0x00)
#define OFFSET_TO_REG_DATA	(0x04)
#define OFFSET_TO_REG_INT_EN	(0x08)
#define OFFSET_TO_REG_CHANGE	(0x0C)
#define OFFSET_TO_REG_WRMASK	(0x10)
#define OFFSET_TO_REG_INT_TYPE	(0x14)


/**
 * @spinlock: used for atomic read/modify/write of registers
 * @base: register base address
 * @domain: IRQ domain of GPIO generated interrupts managed by this controller
 * @irq: Interrupt line of parent interrupt controller
 * @gc: gpio_chip structure associated to this GPIO controller
 */
struct tb10x_gpio {
	spinlock_t spinlock;
	void __iomem *base;
	struct irq_domain *domain;
	int irq;
	struct gpio_chip gc;
};

static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
{
	return ioread32(gpio->base + offs);
}

static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
				u32 val)
{
	iowrite32(val, gpio->base + offs);
}

static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
				u32 mask, u32 val)
{
	u32 r;
	unsigned long flags;

	spin_lock_irqsave(&gpio->spinlock, flags);

	r = tb10x_reg_read(gpio, offs);
	r = (r & ~mask) | (val & mask);

	tb10x_reg_write(gpio, offs, r);

	spin_unlock_irqrestore(&gpio->spinlock, flags);
}

static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int mask = BIT(offset);
	int val = TB10X_GPIO_DIR_IN << offset;

	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);

	return 0;
}

static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int val;

	val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);

	if (val & BIT(offset))
		return 1;
	else
		return 0;
}

static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int mask = BIT(offset);
	int val = value << offset;

	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
}

static int tb10x_gpio_direction_out(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int mask = BIT(offset);
	int val = TB10X_GPIO_DIR_OUT << offset;

	tb10x_gpio_set(chip, offset, value);
	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);

	return 0;
}

static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);

	return irq_create_mapping(tb10x_gpio->domain, offset);
}

static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
	if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
		pr_err("Only (both) edge triggered interrupts supported.\n");
		return -EINVAL;
	}

	irqd_set_trigger_type(data, type);

	return IRQ_SET_MASK_OK;
}

static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
{
	struct tb10x_gpio *tb10x_gpio = data;
	u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
	u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
	const unsigned long bits = r & m;
	int i;

	for_each_set_bit(i, &bits, 32)
		generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));

	return IRQ_HANDLED;
}

static int tb10x_gpio_probe(struct platform_device *pdev)
{
	struct tb10x_gpio *tb10x_gpio;
	struct resource *mem;
	struct device_node *dn = pdev->dev.of_node;
	int ret = -EBUSY;
	u32 ngpio;

	if (!dn)
		return -EINVAL;

	if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
		return -EINVAL;

	tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
	if (tb10x_gpio == NULL)
		return -ENOMEM;

	spin_lock_init(&tb10x_gpio->spinlock);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(tb10x_gpio->base))
		return PTR_ERR(tb10x_gpio->base);

	tb10x_gpio->gc.label		= of_node_full_name(dn);
	tb10x_gpio->gc.parent		= &pdev->dev;
	tb10x_gpio->gc.owner		= THIS_MODULE;
	tb10x_gpio->gc.direction_input	= tb10x_gpio_direction_in;
	tb10x_gpio->gc.get		= tb10x_gpio_get;
	tb10x_gpio->gc.direction_output	= tb10x_gpio_direction_out;
	tb10x_gpio->gc.set		= tb10x_gpio_set;
	tb10x_gpio->gc.request		= gpiochip_generic_request;
	tb10x_gpio->gc.free		= gpiochip_generic_free;
	tb10x_gpio->gc.base		= -1;
	tb10x_gpio->gc.ngpio		= ngpio;
	tb10x_gpio->gc.can_sleep	= false;


	ret = devm_gpiochip_add_data(&pdev->dev, &tb10x_gpio->gc, tb10x_gpio);
	if (ret < 0) {
		dev_err(&pdev->dev, "Could not add gpiochip.\n");
		return ret;
	}

	platform_set_drvdata(pdev, tb10x_gpio);

	if (of_find_property(dn, "interrupt-controller", NULL)) {
		struct irq_chip_generic *gc;

		ret = platform_get_irq(pdev, 0);
		if (ret < 0) {
			dev_err(&pdev->dev, "No interrupt specified.\n");
			return ret;
		}

		tb10x_gpio->gc.to_irq	= tb10x_gpio_to_irq;
		tb10x_gpio->irq		= ret;

		ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
				IRQF_TRIGGER_NONE | IRQF_SHARED,
				dev_name(&pdev->dev), tb10x_gpio);
		if (ret != 0)
			return ret;

		tb10x_gpio->domain = irq_domain_add_linear(dn,
						tb10x_gpio->gc.ngpio,
						&irq_generic_chip_ops, NULL);
		if (!tb10x_gpio->domain) {
			return -ENOMEM;
		}

		ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
				tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
				handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
				IRQ_GC_INIT_MASK_CACHE);
		if (ret)
			return ret;

		gc = tb10x_gpio->domain->gc->gc[0];
		gc->reg_base                         = tb10x_gpio->base;
		gc->chip_types[0].type               = IRQ_TYPE_EDGE_BOTH;
		gc->chip_types[0].chip.irq_ack       = irq_gc_ack_set_bit;
		gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
		gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
		gc->chip_types[0].chip.irq_set_type  = tb10x_gpio_irq_set_type;
		gc->chip_types[0].regs.ack           = OFFSET_TO_REG_CHANGE;
		gc->chip_types[0].regs.mask          = OFFSET_TO_REG_INT_EN;
	}

	return 0;
}

static int tb10x_gpio_remove(struct platform_device *pdev)
{
	struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);

	if (tb10x_gpio->gc.to_irq) {
		irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
					BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
		kfree(tb10x_gpio->domain->gc);
		irq_domain_remove(tb10x_gpio->domain);
	}

	return 0;
}

static const struct of_device_id tb10x_gpio_dt_ids[] = {
	{ .compatible = "abilis,tb10x-gpio" },
	{ }
};
MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);

static struct platform_driver tb10x_gpio_driver = {
	.probe		= tb10x_gpio_probe,
	.remove		= tb10x_gpio_remove,
	.driver = {
		.name	= "tb10x-gpio",
		.of_match_table = tb10x_gpio_dt_ids,
	}
};

module_platform_driver(tb10x_gpio_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("tb10x gpio.");
MODULE_VERSION("0.0.1");
Commit	Line	Data
c6ce2b6b CR	1	/* Abilis Systems MODULE DESCRIPTION
	2	*
	3	* Copyright (C) Abilis Systems 2013
	4	*
	5	* Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
	6	* Christian Ruppert <christian.ruppert@abilis.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/gpio.h>
	26	#include <linux/slab.h>
	27	#include <linux/irq.h>
	28	#include <linux/irqdomain.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/io.h>
	31	#include <linux/of.h>
	32	#include <linux/of_platform.h>
	33	#include <linux/of_gpio.h>
	34	#include <linux/spinlock.h>
	35	#include <linux/bitops.h>
	36	#include <linux/pinctrl/consumer.h>
	37
	38	#define TB10X_GPIO_DIR_IN (0x00000000)
	39	#define TB10X_GPIO_DIR_OUT (0x00000001)
	40	#define OFFSET_TO_REG_DDR (0x00)
	41	#define OFFSET_TO_REG_DATA (0x04)
	42	#define OFFSET_TO_REG_INT_EN (0x08)
	43	#define OFFSET_TO_REG_CHANGE (0x0C)
	44	#define OFFSET_TO_REG_WRMASK (0x10)
	45	#define OFFSET_TO_REG_INT_TYPE (0x14)
	46
	47
	48	/**
	49	* @spinlock: used for atomic read/modify/write of registers
	50	* @base: register base address
	51	* @domain: IRQ domain of GPIO generated interrupts managed by this controller
	52	* @irq: Interrupt line of parent interrupt controller
	53	* @gc: gpio_chip structure associated to this GPIO controller
	54	*/
	55	struct tb10x_gpio {
	56	spinlock_t spinlock;
	57	void __iomem *base;
	58	struct irq_domain *domain;
	59	int irq;
	60	struct gpio_chip gc;
	61	};
	62
	63	static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
	64	{
65	return ioread32(gpio->base + offs);
66	}
67
68	static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
69	u32 val)
70	{
71	iowrite32(val, gpio->base + offs);
72	}
73
74	static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
75	u32 mask, u32 val)
76	{
77	u32 r;
78	unsigned long flags;
79
80	spin_lock_irqsave(&gpio->spinlock, flags);
81
82	r = tb10x_reg_read(gpio, offs);
83	r = (r & ~mask) \| (val & mask);
84
85	tb10x_reg_write(gpio, offs, r);
86
87	spin_unlock_irqrestore(&gpio->spinlock, flags);
88	}
89
c6ce2b6b CR	90	static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
c6ce2b6b CR	91	{
0ca8c5c4	92	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	93	int mask = BIT(offset);
	94	int val = TB10X_GPIO_DIR_IN << offset;
	95
	96	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
	97
	98	return 0;
	99	}
	100
	101	static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
	102	{
0ca8c5c4	103	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	104	int val;
	105
	106	val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);
	107
	108	if (val & BIT(offset))
	109	return 1;
	110	else
	111	return 0;
	112	}
	113
	114	static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	115	{
0ca8c5c4	116	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	117	int mask = BIT(offset);
	118	int val = value << offset;
	119
	120	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
	121	}
	122
	123	static int tb10x_gpio_direction_out(struct gpio_chip *chip,
	124	unsigned offset, int value)
	125	{
0ca8c5c4	126	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	127	int mask = BIT(offset);
	128	int val = TB10X_GPIO_DIR_OUT << offset;
	129
2e86230f	130	tb10x_gpio_set(chip, offset, value);
c6ce2b6b CR	131	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
	132
	133	return 0;
	134	}
	135
c6ce2b6b CR	136	static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
c6ce2b6b CR	137	{
0ca8c5c4	138	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	139
	140	return irq_create_mapping(tb10x_gpio->domain, offset);
	141	}
	142
	143	static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
	144	{
	145	if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
	146	pr_err("Only (both) edge triggered interrupts supported.\n");
	147	return -EINVAL;
	148	}
	149
	150	irqd_set_trigger_type(data, type);
	151
	152	return IRQ_SET_MASK_OK;
	153	}
	154
	155	static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
	156	{
	157	struct tb10x_gpio *tb10x_gpio = data;
	158	u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
	159	u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
	160	const unsigned long bits = r & m;
	161	int i;
	162
	163	for_each_set_bit(i, &bits, 32)
	164	generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
	165
	166	return IRQ_HANDLED;
	167	}
	168
	169	static int tb10x_gpio_probe(struct platform_device *pdev)
	170	{
	171	struct tb10x_gpio *tb10x_gpio;
	172	struct resource *mem;
	173	struct device_node *dn = pdev->dev.of_node;
	174	int ret = -EBUSY;
	175	u32 ngpio;
	176
	177	if (!dn)
	178	return -EINVAL;
	179
	180	if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
	181	return -EINVAL;
	182
c6ce2b6b CR	183	tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
	184	if (tb10x_gpio == NULL)
	185	return -ENOMEM;
	186
	187	spin_lock_init(&tb10x_gpio->spinlock);
	188
ee2a9f7f	189	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c6ce2b6b	190	tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
9a4864c8 WY	191	if (IS_ERR(tb10x_gpio->base))
9a4864c8 WY	192	return PTR_ERR(tb10x_gpio->base);
c6ce2b6b CR	193
c6ce2b6b CR	194	tb10x_gpio->gc.label = of_node_full_name(dn);
58383c78	195	tb10x_gpio->gc.parent = &pdev->dev;
c6ce2b6b CR	196	tb10x_gpio->gc.owner = THIS_MODULE;
	197	tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
	198	tb10x_gpio->gc.get = tb10x_gpio_get;
	199	tb10x_gpio->gc.direction_output = tb10x_gpio_direction_out;
	200	tb10x_gpio->gc.set = tb10x_gpio_set;
203f0daa JG	201	tb10x_gpio->gc.request = gpiochip_generic_request;
203f0daa JG	202	tb10x_gpio->gc.free = gpiochip_generic_free;
c6ce2b6b CR	203	tb10x_gpio->gc.base = -1;
c6ce2b6b CR	204	tb10x_gpio->gc.ngpio = ngpio;
9fb1f39e	205	tb10x_gpio->gc.can_sleep = false;
c6ce2b6b CR	206
c6ce2b6b CR	207
ad7b550a	208	ret = devm_gpiochip_add_data(&pdev->dev, &tb10x_gpio->gc, tb10x_gpio);
c6ce2b6b CR	209	if (ret < 0) {
c6ce2b6b CR	210	dev_err(&pdev->dev, "Could not add gpiochip.\n");
ad7b550a	211	return ret;
c6ce2b6b CR	212	}
	213
	214	platform_set_drvdata(pdev, tb10x_gpio);
	215
	216	if (of_find_property(dn, "interrupt-controller", NULL)) {
	217	struct irq_chip_generic *gc;
	218
	219	ret = platform_get_irq(pdev, 0);
	220	if (ret < 0) {
	221	dev_err(&pdev->dev, "No interrupt specified.\n");
ad7b550a	222	return ret;
c6ce2b6b CR	223	}
	224
	225	tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
	226	tb10x_gpio->irq = ret;
	227
	228	ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
	229	IRQF_TRIGGER_NONE \| IRQF_SHARED,
	230	dev_name(&pdev->dev), tb10x_gpio);
	231	if (ret != 0)
ad7b550a	232	return ret;
c6ce2b6b CR	233
	234	tb10x_gpio->domain = irq_domain_add_linear(dn,
	235	tb10x_gpio->gc.ngpio,
	236	&irq_generic_chip_ops, NULL);
	237	if (!tb10x_gpio->domain) {
ad7b550a	238	return -ENOMEM;
c6ce2b6b CR	239	}
	240
	241	ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
	242	tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
	243	handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
	244	IRQ_GC_INIT_MASK_CACHE);
	245	if (ret)
ad7b550a	246	return ret;
c6ce2b6b CR	247
	248	gc = tb10x_gpio->domain->gc->gc[0];
	249	gc->reg_base = tb10x_gpio->base;
	250	gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
	251	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
	252	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
	253	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
	254	gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
	255	gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
	256	gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
	257	}
	258
	259	return 0;
c6ce2b6b CR	260	}
c6ce2b6b CR	261
b8a51a2e	262	static int tb10x_gpio_remove(struct platform_device *pdev)
c6ce2b6b CR	263	{
c6ce2b6b CR	264	struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
c6ce2b6b CR	265
	266	if (tb10x_gpio->gc.to_irq) {
	267	irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
	268	BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
	269	kfree(tb10x_gpio->domain->gc);
	270	irq_domain_remove(tb10x_gpio->domain);
c6ce2b6b	271	}
c6ce2b6b CR	272
	273	return 0;
	274	}
	275
	276	static const struct of_device_id tb10x_gpio_dt_ids[] = {
	277	{ .compatible = "abilis,tb10x-gpio" },
	278	{ }
	279	};
	280	MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
	281
	282	static struct platform_driver tb10x_gpio_driver = {
	283	.probe = tb10x_gpio_probe,
	284	.remove = tb10x_gpio_remove,
	285	.driver = {
	286	.name = "tb10x-gpio",
b10b45c0	287	.of_match_table = tb10x_gpio_dt_ids,
c6ce2b6b CR	288	}
	289	};
	290
85aa3915	291	module_platform_driver(tb10x_gpio_driver);
c6ce2b6b CR	292	MODULE_LICENSE("GPL");
	293	MODULE_DESCRIPTION("tb10x gpio.");
	294	MODULE_VERSION("0.0.1");