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drm/amdgpu: group VM mapping tree with its lock (v2)
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
97b2e202 56
b80d8475
AD		 57#include "gpu_scheduler.h"
58
97b2e202
AD		 59/*
60 * Modules parameters.
61 */
62extern int amdgpu_modeset;
63extern int amdgpu_vram_limit;
64extern int amdgpu_gart_size;
65extern int amdgpu_benchmarking;
66extern int amdgpu_testing;
67extern int amdgpu_audio;
68extern int amdgpu_disp_priority;
69extern int amdgpu_hw_i2c;
70extern int amdgpu_pcie_gen2;
71extern int amdgpu_msi;
72extern int amdgpu_lockup_timeout;
73extern int amdgpu_dpm;
74extern int amdgpu_smc_load_fw;
75extern int amdgpu_aspm;
76extern int amdgpu_runtime_pm;
77extern int amdgpu_hard_reset;
78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
b80d8475 85extern int amdgpu_enable_scheduler;
1333f723 86extern int amdgpu_sched_jobs;
4afcb303 87extern int amdgpu_sched_hw_submission;
3daea9e3 88extern int amdgpu_enable_semaphores;
1f7371b2 89extern int amdgpu_powerplay;
97b2e202 90
4b559c90 91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95#define AMDGPU_IB_POOL_SIZE 16
96#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97#define AMDGPUFB_CONN_LIMIT 4
98#define AMDGPU_BIOS_NUM_SCRATCH 8
99
97b2e202
AD		 100/* max number of rings */
101#define AMDGPU_MAX_RINGS 16
102#define AMDGPU_MAX_GFX_RINGS 1
103#define AMDGPU_MAX_COMPUTE_RINGS 8
104#define AMDGPU_MAX_VCE_RINGS 2
105
36f523a7
JZ		 106/* max number of IP instances */
107#define AMDGPU_MAX_SDMA_INSTANCES 2
108
97b2e202
AD		 109/* number of hw syncs before falling back on blocking */
110#define AMDGPU_NUM_SYNCS 4
111
112/* hardcode that limit for now */
113#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
114
115/* hard reset data */
116#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
117
118/* reset flags */
119#define AMDGPU_RESET_GFX (1 << 0)
120#define AMDGPU_RESET_COMPUTE (1 << 1)
121#define AMDGPU_RESET_DMA (1 << 2)
122#define AMDGPU_RESET_CP (1 << 3)
123#define AMDGPU_RESET_GRBM (1 << 4)
124#define AMDGPU_RESET_DMA1 (1 << 5)
125#define AMDGPU_RESET_RLC (1 << 6)
126#define AMDGPU_RESET_SEM (1 << 7)
127#define AMDGPU_RESET_IH (1 << 8)
128#define AMDGPU_RESET_VMC (1 << 9)
129#define AMDGPU_RESET_MC (1 << 10)
130#define AMDGPU_RESET_DISPLAY (1 << 11)
131#define AMDGPU_RESET_UVD (1 << 12)
132#define AMDGPU_RESET_VCE (1 << 13)
133#define AMDGPU_RESET_VCE1 (1 << 14)
134
135/* CG block flags */
136#define AMDGPU_CG_BLOCK_GFX (1 << 0)
137#define AMDGPU_CG_BLOCK_MC (1 << 1)
138#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
139#define AMDGPU_CG_BLOCK_UVD (1 << 3)
140#define AMDGPU_CG_BLOCK_VCE (1 << 4)
141#define AMDGPU_CG_BLOCK_HDP (1 << 5)
142#define AMDGPU_CG_BLOCK_BIF (1 << 6)
143
144/* CG flags */
145#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
146#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
147#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
148#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
149#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
150#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
151#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
152#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
153#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
154#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
155#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
156#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
157#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
158#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
159#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
160#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
161#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
162
163/* PG flags */
164#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
165#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
166#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
167#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
168#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
169#define AMDGPU_PG_SUPPORT_CP (1 << 5)
170#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
171#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
172#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
173#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
174#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
175
176/* GFX current status */
177#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
178#define AMDGPU_GFX_SAFE_MODE 0x00000001L
179#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
180#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
181#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
182
183/* max cursor sizes (in pixels) */
184#define CIK_CURSOR_WIDTH 128
185#define CIK_CURSOR_HEIGHT 128
186
187struct amdgpu_device;
188struct amdgpu_fence;
189struct amdgpu_ib;
190struct amdgpu_vm;
191struct amdgpu_ring;
192struct amdgpu_semaphore;
193struct amdgpu_cs_parser;
bb977d37 194struct amdgpu_job;
97b2e202 195struct amdgpu_irq_src;
0b492a4c 196struct amdgpu_fpriv;
97b2e202
AD		 197
198enum amdgpu_cp_irq {
199 AMDGPU_CP_IRQ_GFX_EOP = 0,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
207 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
208
209 AMDGPU_CP_IRQ_LAST
210};
211
212enum amdgpu_sdma_irq {
213 AMDGPU_SDMA_IRQ_TRAP0 = 0,
214 AMDGPU_SDMA_IRQ_TRAP1,
215
216 AMDGPU_SDMA_IRQ_LAST
217};
218
219enum amdgpu_thermal_irq {
220 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
221 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
222
223 AMDGPU_THERMAL_IRQ_LAST
224};
225
97b2e202 226int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 227 enum amd_ip_block_type block_type,
228 enum amd_clockgating_state state);
97b2e202 229int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 230 enum amd_ip_block_type block_type,
231 enum amd_powergating_state state);
97b2e202
AD		 232
233struct amdgpu_ip_block_version {
5fc3aeeb 234 enum amd_ip_block_type type;
97b2e202
AD		 235 u32 major;
236 u32 minor;
237 u32 rev;
5fc3aeeb 238 const struct amd_ip_funcs *funcs;
97b2e202
AD		 239};
240
241int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 242 enum amd_ip_block_type type,
97b2e202
AD		 243 u32 major, u32 minor);
244
245const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
246 struct amdgpu_device *adev,
5fc3aeeb 247 enum amd_ip_block_type type);
97b2e202
AD		 248
249/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
250struct amdgpu_buffer_funcs {
251 /* maximum bytes in a single operation */
252 uint32_t copy_max_bytes;
253
254 /* number of dw to reserve per operation */
255 unsigned copy_num_dw;
256
257 /* used for buffer migration */
c7ae72c0 258 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 259 /* src addr in bytes */
260 uint64_t src_offset,
261 /* dst addr in bytes */
262 uint64_t dst_offset,
263 /* number of byte to transfer */
264 uint32_t byte_count);
265
266 /* maximum bytes in a single operation */
267 uint32_t fill_max_bytes;
268
269 /* number of dw to reserve per operation */
270 unsigned fill_num_dw;
271
272 /* used for buffer clearing */
6e7a3840 273 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 274 /* value to write to memory */
275 uint32_t src_data,
276 /* dst addr in bytes */
277 uint64_t dst_offset,
278 /* number of byte to fill */
279 uint32_t byte_count);
280};
281
282/* provided by hw blocks that can write ptes, e.g., sdma */
283struct amdgpu_vm_pte_funcs {
284 /* copy pte entries from GART */
285 void (*copy_pte)(struct amdgpu_ib *ib,
286 uint64_t pe, uint64_t src,
287 unsigned count);
288 /* write pte one entry at a time with addr mapping */
289 void (*write_pte)(struct amdgpu_ib *ib,
290 uint64_t pe,
291 uint64_t addr, unsigned count,
292 uint32_t incr, uint32_t flags);
293 /* for linear pte/pde updates without addr mapping */
294 void (*set_pte_pde)(struct amdgpu_ib *ib,
295 uint64_t pe,
296 uint64_t addr, unsigned count,
297 uint32_t incr, uint32_t flags);
298 /* pad the indirect buffer to the necessary number of dw */
299 void (*pad_ib)(struct amdgpu_ib *ib);
300};
301
302/* provided by the gmc block */
303struct amdgpu_gart_funcs {
304 /* flush the vm tlb via mmio */
305 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
306 uint32_t vmid);
307 /* write pte/pde updates using the cpu */
308 int (*set_pte_pde)(struct amdgpu_device *adev,
309 void *cpu_pt_addr, /* cpu addr of page table */
310 uint32_t gpu_page_idx, /* pte/pde to update */
311 uint64_t addr, /* addr to write into pte/pde */
312 uint32_t flags); /* access flags */
313};
314
315/* provided by the ih block */
316struct amdgpu_ih_funcs {
317 /* ring read/write ptr handling, called from interrupt context */
318 u32 (*get_wptr)(struct amdgpu_device *adev);
319 void (*decode_iv)(struct amdgpu_device *adev,
320 struct amdgpu_iv_entry *entry);
321 void (*set_rptr)(struct amdgpu_device *adev);
322};
323
324/* provided by hw blocks that expose a ring buffer for commands */
325struct amdgpu_ring_funcs {
326 /* ring read/write ptr handling */
327 u32 (*get_rptr)(struct amdgpu_ring *ring);
328 u32 (*get_wptr)(struct amdgpu_ring *ring);
329 void (*set_wptr)(struct amdgpu_ring *ring);
330 /* validating and patching of IBs */
331 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
332 /* command emit functions */
333 void (*emit_ib)(struct amdgpu_ring *ring,
334 struct amdgpu_ib *ib);
335 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 336 uint64_t seq, unsigned flags);
97b2e202
AD		 337 bool (*emit_semaphore)(struct amdgpu_ring *ring,
338 struct amdgpu_semaphore *semaphore,
339 bool emit_wait);
340 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
341 uint64_t pd_addr);
d2edb07b 342 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 343 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
344 uint32_t gds_base, uint32_t gds_size,
345 uint32_t gws_base, uint32_t gws_size,
346 uint32_t oa_base, uint32_t oa_size);
347 /* testing functions */
348 int (*test_ring)(struct amdgpu_ring *ring);
349 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 350 /* insert NOP packets */
351 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 352};
353
354/*
355 * BIOS.
356 */
357bool amdgpu_get_bios(struct amdgpu_device *adev);
358bool amdgpu_read_bios(struct amdgpu_device *adev);
359
360/*
361 * Dummy page
362 */
363struct amdgpu_dummy_page {
364 struct page *page;
365 dma_addr_t addr;
366};
367int amdgpu_dummy_page_init(struct amdgpu_device *adev);
368void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
369
370
371/*
372 * Clocks
373 */
374
375#define AMDGPU_MAX_PPLL 3
376
377struct amdgpu_clock {
378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
379 struct amdgpu_pll spll;
380 struct amdgpu_pll mpll;
381 /* 10 Khz units */
382 uint32_t default_mclk;
383 uint32_t default_sclk;
384 uint32_t default_dispclk;
385 uint32_t current_dispclk;
386 uint32_t dp_extclk;
387 uint32_t max_pixel_clock;
388};
389
390/*
391 * Fences.
392 */
393struct amdgpu_fence_driver {
97b2e202
AD		 394 uint64_t gpu_addr;
395 volatile uint32_t *cpu_addr;
396 /* sync_seq is protected by ring emission lock */
397 uint64_t sync_seq[AMDGPU_MAX_RINGS];
398 atomic64_t last_seq;
399 bool initialized;
97b2e202
AD		 400 struct amdgpu_irq_src *irq_src;
401 unsigned irq_type;
c2776afe 402 struct timer_list fallback_timer;
7f06c236 403 wait_queue_head_t fence_queue;
97b2e202
AD		 404};
405
406/* some special values for the owner field */
407#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
408#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 409
890ee23f
CZ		 410#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
411#define AMDGPU_FENCE_FLAG_INT (1 << 1)
412
97b2e202
AD		 413struct amdgpu_fence {
414 struct fence base;
4cef9267 415
97b2e202
AD		 416 /* RB, DMA, etc. */
417 struct amdgpu_ring *ring;
418 uint64_t seq;
419
420 /* filp or special value for fence creator */
421 void *owner;
422
423 wait_queue_t fence_wake;
424};
425
426struct amdgpu_user_fence {
427 /* write-back bo */
428 struct amdgpu_bo *bo;
429 /* write-back address offset to bo start */
430 uint32_t offset;
431};
432
433int amdgpu_fence_driver_init(struct amdgpu_device *adev);
434void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
435void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
436
4f839a24 437int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 438int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
439 struct amdgpu_irq_src *irq_src,
440 unsigned irq_type);
5ceb54c6
AD		 441void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
442void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 443int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
444 struct amdgpu_fence **fence);
445void amdgpu_fence_process(struct amdgpu_ring *ring);
446int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
447int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
448unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
449
97b2e202
AD		 450bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
453 struct amdgpu_ring *ring);
454
97b2e202
AD		 455/*
456 * TTM.
457 */
458struct amdgpu_mman {
459 struct ttm_bo_global_ref bo_global_ref;
460 struct drm_global_reference mem_global_ref;
461 struct ttm_bo_device bdev;
462 bool mem_global_referenced;
463 bool initialized;
464
465#if defined(CONFIG_DEBUG_FS)
466 struct dentry *vram;
467 struct dentry *gtt;
468#endif
469
470 /* buffer handling */
471 const struct amdgpu_buffer_funcs *buffer_funcs;
472 struct amdgpu_ring *buffer_funcs_ring;
473};
474
475int amdgpu_copy_buffer(struct amdgpu_ring *ring,
476 uint64_t src_offset,
477 uint64_t dst_offset,
478 uint32_t byte_count,
479 struct reservation_object *resv,
c7ae72c0 480 struct fence **fence);
97b2e202
AD		 481int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
482
483struct amdgpu_bo_list_entry {
484 struct amdgpu_bo *robj;
485 struct ttm_validate_buffer tv;
486 struct amdgpu_bo_va *bo_va;
487 unsigned prefered_domains;
488 unsigned allowed_domains;
489 uint32_t priority;
490};
491
492struct amdgpu_bo_va_mapping {
493 struct list_head list;
494 struct interval_tree_node it;
495 uint64_t offset;
496 uint32_t flags;
497};
498
499/* bo virtual addresses in a specific vm */
500struct amdgpu_bo_va {
69b576a1 501 struct mutex mutex;
97b2e202
AD		 502 /* protected by bo being reserved */
503 struct list_head bo_list;
bb1e38a4 504 struct fence *last_pt_update;
97b2e202
AD		 505 unsigned ref_count;
506
7fc11959 507 /* protected by vm mutex and spinlock */
97b2e202
AD		 508 struct list_head vm_status;
509
7fc11959
CK		 510 /* mappings for this bo_va */
511 struct list_head invalids;
512 struct list_head valids;
513
97b2e202
AD		 514 /* constant after initialization */
515 struct amdgpu_vm *vm;
516 struct amdgpu_bo *bo;
517};
518
7e5a547f
CZ		 519#define AMDGPU_GEM_DOMAIN_MAX 0x3
520
97b2e202
AD		 521struct amdgpu_bo {
522 /* Protected by gem.mutex */
523 struct list_head list;
524 /* Protected by tbo.reserved */
525 u32 initial_domain;
7e5a547f 526 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 527 struct ttm_placement placement;
528 struct ttm_buffer_object tbo;
529 struct ttm_bo_kmap_obj kmap;
530 u64 flags;
531 unsigned pin_count;
532 void *kptr;
533 u64 tiling_flags;
534 u64 metadata_flags;
535 void *metadata;
536 u32 metadata_size;
537 /* list of all virtual address to which this bo
538 * is associated to
539 */
540 struct list_head va;
541 /* Constant after initialization */
542 struct amdgpu_device *adev;
543 struct drm_gem_object gem_base;
82b9c55b 544 struct amdgpu_bo *parent;
97b2e202
AD		 545
546 struct ttm_bo_kmap_obj dma_buf_vmap;
547 pid_t pid;
548 struct amdgpu_mn *mn;
549 struct list_head mn_list;
550};
551#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
552
553void amdgpu_gem_object_free(struct drm_gem_object *obj);
554int amdgpu_gem_object_open(struct drm_gem_object *obj,
555 struct drm_file *file_priv);
556void amdgpu_gem_object_close(struct drm_gem_object *obj,
557 struct drm_file *file_priv);
558unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
559struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
560struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
561 struct dma_buf_attachment *attach,
562 struct sg_table *sg);
563struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
564 struct drm_gem_object *gobj,
565 int flags);
566int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
567void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
568struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
569void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
570void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
571int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
572
573/* sub-allocation manager, it has to be protected by another lock.
574 * By conception this is an helper for other part of the driver
575 * like the indirect buffer or semaphore, which both have their
576 * locking.
577 *
578 * Principe is simple, we keep a list of sub allocation in offset
579 * order (first entry has offset == 0, last entry has the highest
580 * offset).
581 *
582 * When allocating new object we first check if there is room at
583 * the end total_size - (last_object_offset + last_object_size) >=
584 * alloc_size. If so we allocate new object there.
585 *
586 * When there is not enough room at the end, we start waiting for
587 * each sub object until we reach object_offset+object_size >=
588 * alloc_size, this object then become the sub object we return.
589 *
590 * Alignment can't be bigger than page size.
591 *
592 * Hole are not considered for allocation to keep things simple.
593 * Assumption is that there won't be hole (all object on same
594 * alignment).
595 */
596struct amdgpu_sa_manager {
597 wait_queue_head_t wq;
598 struct amdgpu_bo *bo;
599 struct list_head *hole;
600 struct list_head flist[AMDGPU_MAX_RINGS];
601 struct list_head olist;
602 unsigned size;
603 uint64_t gpu_addr;
604 void *cpu_ptr;
605 uint32_t domain;
606 uint32_t align;
607};
608
609struct amdgpu_sa_bo;
610
611/* sub-allocation buffer */
612struct amdgpu_sa_bo {
613 struct list_head olist;
614 struct list_head flist;
615 struct amdgpu_sa_manager *manager;
616 unsigned soffset;
617 unsigned eoffset;
4ce9891e 618 struct fence *fence;
97b2e202
AD		 619};
620
621/*
622 * GEM objects.
623 */
624struct amdgpu_gem {
625 struct mutex mutex;
626 struct list_head objects;
627};
628
629int amdgpu_gem_init(struct amdgpu_device *adev);
630void amdgpu_gem_fini(struct amdgpu_device *adev);
631int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
632 int alignment, u32 initial_domain,
633 u64 flags, bool kernel,
634 struct drm_gem_object **obj);
635
636int amdgpu_mode_dumb_create(struct drm_file *file_priv,
637 struct drm_device *dev,
638 struct drm_mode_create_dumb *args);
639int amdgpu_mode_dumb_mmap(struct drm_file *filp,
640 struct drm_device *dev,
641 uint32_t handle, uint64_t *offset_p);
642
643/*
644 * Semaphores.
645 */
646struct amdgpu_semaphore {
647 struct amdgpu_sa_bo *sa_bo;
648 signed waiters;
649 uint64_t gpu_addr;
650};
651
652int amdgpu_semaphore_create(struct amdgpu_device *adev,
653 struct amdgpu_semaphore **semaphore);
654bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
655 struct amdgpu_semaphore *semaphore);
656bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
657 struct amdgpu_semaphore *semaphore);
658void amdgpu_semaphore_free(struct amdgpu_device *adev,
659 struct amdgpu_semaphore **semaphore,
4ce9891e 660 struct fence *fence);
97b2e202
AD		 661
662/*
663 * Synchronization
664 */
665struct amdgpu_sync {
666 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
16545c32 667 struct fence *sync_to[AMDGPU_MAX_RINGS];
f91b3a69 668 DECLARE_HASHTABLE(fences, 4);
3c62338c 669 struct fence *last_vm_update;
97b2e202
AD		 670};
671
672void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 673int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
674 struct fence *f);
97b2e202
AD		 675int amdgpu_sync_resv(struct amdgpu_device *adev,
676 struct amdgpu_sync *sync,
677 struct reservation_object *resv,
678 void *owner);
679int amdgpu_sync_rings(struct amdgpu_sync *sync,
680 struct amdgpu_ring *ring);
e61235db 681struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 682int amdgpu_sync_wait(struct amdgpu_sync *sync);
97b2e202 683void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
4ce9891e 684 struct fence *fence);
97b2e202
AD		 685
686/*
687 * GART structures, functions & helpers
688 */
689struct amdgpu_mc;
690
691#define AMDGPU_GPU_PAGE_SIZE 4096
692#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
693#define AMDGPU_GPU_PAGE_SHIFT 12
694#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
695
696struct amdgpu_gart {
697 dma_addr_t table_addr;
698 struct amdgpu_bo *robj;
699 void *ptr;
700 unsigned num_gpu_pages;
701 unsigned num_cpu_pages;
702 unsigned table_size;
703 struct page **pages;
704 dma_addr_t *pages_addr;
705 bool ready;
706 const struct amdgpu_gart_funcs *gart_funcs;
707};
708
709int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
710void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
711int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
712void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
713int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
714void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
715int amdgpu_gart_init(struct amdgpu_device *adev);
716void amdgpu_gart_fini(struct amdgpu_device *adev);
717void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
718 int pages);
719int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
720 int pages, struct page **pagelist,
721 dma_addr_t *dma_addr, uint32_t flags);
722
723/*
724 * GPU MC structures, functions & helpers
725 */
726struct amdgpu_mc {
727 resource_size_t aper_size;
728 resource_size_t aper_base;
729 resource_size_t agp_base;
730 /* for some chips with <= 32MB we need to lie
731 * about vram size near mc fb location */
732 u64 mc_vram_size;
733 u64 visible_vram_size;
734 u64 gtt_size;
735 u64 gtt_start;
736 u64 gtt_end;
737 u64 vram_start;
738 u64 vram_end;
739 unsigned vram_width;
740 u64 real_vram_size;
741 int vram_mtrr;
742 u64 gtt_base_align;
743 u64 mc_mask;
744 const struct firmware *fw; /* MC firmware */
745 uint32_t fw_version;
746 struct amdgpu_irq_src vm_fault;
81c59f54 747 uint32_t vram_type;
97b2e202
AD		 748};
749
750/*
751 * GPU doorbell structures, functions & helpers
752 */
753typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
754{
755 AMDGPU_DOORBELL_KIQ = 0x000,
756 AMDGPU_DOORBELL_HIQ = 0x001,
757 AMDGPU_DOORBELL_DIQ = 0x002,
758 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
759 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
760 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
761 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
762 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
763 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
764 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
765 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
766 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
767 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
768 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
769 AMDGPU_DOORBELL_IH = 0x1E8,
770 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
771 AMDGPU_DOORBELL_INVALID = 0xFFFF
772} AMDGPU_DOORBELL_ASSIGNMENT;
773
774struct amdgpu_doorbell {
775 /* doorbell mmio */
776 resource_size_t base;
777 resource_size_t size;
778 u32 __iomem *ptr;
779 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
780};
781
782void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
783 phys_addr_t *aperture_base,
784 size_t *aperture_size,
785 size_t *start_offset);
786
787/*
788 * IRQS.
789 */
790
791struct amdgpu_flip_work {
792 struct work_struct flip_work;
793 struct work_struct unpin_work;
794 struct amdgpu_device *adev;
795 int crtc_id;
796 uint64_t base;
797 struct drm_pending_vblank_event *event;
798 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 799 struct fence *excl;
800 unsigned shared_count;
801 struct fence **shared;
97b2e202
AD		 802};
803
804
805/*
806 * CP & rings.
807 */
808
809struct amdgpu_ib {
810 struct amdgpu_sa_bo *sa_bo;
811 uint32_t length_dw;
812 uint64_t gpu_addr;
813 uint32_t *ptr;
814 struct amdgpu_ring *ring;
815 struct amdgpu_fence *fence;
816 struct amdgpu_user_fence *user;
817 struct amdgpu_vm *vm;
3cb485f3 818 struct amdgpu_ctx *ctx;
97b2e202 819 struct amdgpu_sync sync;
97b2e202
AD		 820 uint32_t gds_base, gds_size;
821 uint32_t gws_base, gws_size;
822 uint32_t oa_base, oa_size;
de807f81 823 uint32_t flags;
5430a3ff
CK		 824 /* resulting sequence number */
825 uint64_t sequence;
97b2e202
AD		 826};
827
828enum amdgpu_ring_type {
829 AMDGPU_RING_TYPE_GFX,
830 AMDGPU_RING_TYPE_COMPUTE,
831 AMDGPU_RING_TYPE_SDMA,
832 AMDGPU_RING_TYPE_UVD,
833 AMDGPU_RING_TYPE_VCE
834};
835
c1b69ed0
CZ		 836extern struct amd_sched_backend_ops amdgpu_sched_ops;
837
3c704e93
CZ		 838int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
839 struct amdgpu_ring *ring,
840 struct amdgpu_ib *ibs,
841 unsigned num_ibs,
bb977d37 842 int (*free_job)(struct amdgpu_job *),
1763552e
CZ		 843 void *owner,
844 struct fence **fence);
3c704e93 845
97b2e202
AD		 846struct amdgpu_ring {
847 struct amdgpu_device *adev;
848 const struct amdgpu_ring_funcs *funcs;
849 struct amdgpu_fence_driver fence_drv;
4f839a24 850 struct amd_gpu_scheduler sched;
97b2e202 851
176e1ab1 852 spinlock_t fence_lock;
97b2e202
AD		 853 struct mutex *ring_lock;
854 struct amdgpu_bo *ring_obj;
855 volatile uint32_t *ring;
856 unsigned rptr_offs;
857 u64 next_rptr_gpu_addr;
858 volatile u32 *next_rptr_cpu_addr;
859 unsigned wptr;
860 unsigned wptr_old;
861 unsigned ring_size;
862 unsigned ring_free_dw;
863 int count_dw;
97b2e202
AD		 864 uint64_t gpu_addr;
865 uint32_t align_mask;
866 uint32_t ptr_mask;
867 bool ready;
868 u32 nop;
869 u32 idx;
870 u64 last_semaphore_signal_addr;
871 u64 last_semaphore_wait_addr;
872 u32 me;
873 u32 pipe;
874 u32 queue;
875 struct amdgpu_bo *mqd_obj;
876 u32 doorbell_index;
877 bool use_doorbell;
878 unsigned wptr_offs;
879 unsigned next_rptr_offs;
880 unsigned fence_offs;
3cb485f3 881 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 882 enum amdgpu_ring_type type;
883 char name[16];
4274f5d4 884 bool is_pte_ring;
97b2e202
AD		 885};
886
887/*
888 * VM
889 */
890
891/* maximum number of VMIDs */
892#define AMDGPU_NUM_VM 16
893
894/* number of entries in page table */
895#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
896
897/* PTBs (Page Table Blocks) need to be aligned to 32K */
898#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
899#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
900#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
901
902#define AMDGPU_PTE_VALID (1 << 0)
903#define AMDGPU_PTE_SYSTEM (1 << 1)
904#define AMDGPU_PTE_SNOOPED (1 << 2)
905
906/* VI only */
907#define AMDGPU_PTE_EXECUTABLE (1 << 4)
908
909#define AMDGPU_PTE_READABLE (1 << 5)
910#define AMDGPU_PTE_WRITEABLE (1 << 6)
911
912/* PTE (Page Table Entry) fragment field for different page sizes */
913#define AMDGPU_PTE_FRAG_4KB (0 << 7)
914#define AMDGPU_PTE_FRAG_64KB (4 << 7)
915#define AMDGPU_LOG2_PAGES_PER_FRAG 4
916
d9c13156
CK		 917/* How to programm VM fault handling */
918#define AMDGPU_VM_FAULT_STOP_NEVER 0
919#define AMDGPU_VM_FAULT_STOP_FIRST 1
920#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
921
97b2e202 922struct amdgpu_vm_pt {
ee1782c3
CK		 923 struct amdgpu_bo_list_entry entry;
924 uint64_t addr;
97b2e202
AD		 925};
926
927struct amdgpu_vm_id {
928 unsigned id;
929 uint64_t pd_gpu_addr;
930 /* last flushed PD/PT update */
3c62338c 931 struct fence *flushed_updates;
97b2e202
AD		 932};
933
934struct amdgpu_vm {
25cfc3c2
CK		 935 /* tree of virtual addresses mapped */
936 spinlock_t it_lock;
97b2e202
AD		 937 struct rb_root va;
938
7fc11959 939 /* protecting invalidated */
97b2e202
AD		 940 spinlock_t status_lock;
941
942 /* BOs moved, but not yet updated in the PT */
943 struct list_head invalidated;
944
7fc11959
CK		 945 /* BOs cleared in the PT because of a move */
946 struct list_head cleared;
947
948 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 949 struct list_head freed;
950
951 /* contains the page directory */
952 struct amdgpu_bo *page_directory;
953 unsigned max_pde_used;
05906dec 954 struct fence *page_directory_fence;
97b2e202
AD		 955
956 /* array of page tables, one for each page directory entry */
957 struct amdgpu_vm_pt *page_tables;
958
959 /* for id and flush management per ring */
960 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 961
81d75a30 962 /* protecting freed */
963 spinlock_t freed_lock;
97b2e202
AD		 964};
965
966struct amdgpu_vm_manager {
1c16c0a7
CK		 967 struct {
968 struct fence *active;
969 atomic_long_t owner;
970 } ids[AMDGPU_NUM_VM];
971
8b4fb00b 972 uint32_t max_pfn;
97b2e202 973 /* number of VMIDs */
8b4fb00b 974 unsigned nvm;
97b2e202 975 /* vram base address for page table entry */
8b4fb00b 976 u64 vram_base_offset;
97b2e202 977 /* is vm enabled? */
8b4fb00b 978 bool enabled;
97b2e202
AD		 979 /* vm pte handling */
980 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
981 struct amdgpu_ring *vm_pte_funcs_ring;
982};
983
ea89f8c9 984void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 985int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
986void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 987void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
988 struct list_head *validated,
989 struct amdgpu_bo_list_entry *entry);
ee1782c3 990void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 991void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
992 struct amdgpu_vm *vm);
8b4fb00b
CK		 993int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
994 struct amdgpu_sync *sync);
995void amdgpu_vm_flush(struct amdgpu_ring *ring,
996 struct amdgpu_vm *vm,
997 struct fence *updates);
998void amdgpu_vm_fence(struct amdgpu_device *adev,
999 struct amdgpu_vm *vm,
1000 struct fence *fence);
1001uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
1002int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
1003 struct amdgpu_vm *vm);
1004int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1005 struct amdgpu_vm *vm);
1006int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1007 struct amdgpu_sync *sync);
1008int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1009 struct amdgpu_bo_va *bo_va,
1010 struct ttm_mem_reg *mem);
1011void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1012 struct amdgpu_bo *bo);
1013struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1014 struct amdgpu_bo *bo);
1015struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1016 struct amdgpu_vm *vm,
1017 struct amdgpu_bo *bo);
1018int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1019 struct amdgpu_bo_va *bo_va,
1020 uint64_t addr, uint64_t offset,
1021 uint64_t size, uint32_t flags);
1022int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1023 struct amdgpu_bo_va *bo_va,
1024 uint64_t addr);
1025void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1026 struct amdgpu_bo_va *bo_va);
1027int amdgpu_vm_free_job(struct amdgpu_job *job);
1028
97b2e202
AD		 1029/*
1030 * context related structures
1031 */
1032
21c16bf6 1033struct amdgpu_ctx_ring {
91404fb2 1034 uint64_t sequence;
37cd0ca2 1035 struct fence **fences;
91404fb2 1036 struct amd_sched_entity entity;
21c16bf6
CK		 1037};
1038
97b2e202 1039struct amdgpu_ctx {
0b492a4c 1040 struct kref refcount;
9cb7e5a9 1041 struct amdgpu_device *adev;
0b492a4c 1042 unsigned reset_counter;
21c16bf6 1043 spinlock_t ring_lock;
37cd0ca2 1044 struct fence **fences;
21c16bf6 1045 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1046};
1047
1048struct amdgpu_ctx_mgr {
0b492a4c
AD		 1049 struct amdgpu_device *adev;
1050 struct mutex lock;
1051 /* protected by lock */
1052 struct idr ctx_handles;
97b2e202
AD		 1053};
1054
d033a6de 1055int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
47f38501
CK		 1056 struct amdgpu_ctx *ctx);
1057void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
0b492a4c 1058
0b492a4c
AD		 1059struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1060int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1061
21c16bf6 1062uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1063 struct fence *fence);
21c16bf6
CK		 1064struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1065 struct amdgpu_ring *ring, uint64_t seq);
1066
0b492a4c
AD		 1067int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *filp);
1069
efd4ccb5
CK		 1070void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1071void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1072
97b2e202
AD		 1073/*
1074 * file private structure
1075 */
1076
1077struct amdgpu_fpriv {
1078 struct amdgpu_vm vm;
1079 struct mutex bo_list_lock;
1080 struct idr bo_list_handles;
0b492a4c 1081 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1082};
1083
1084/*
1085 * residency list
1086 */
1087
1088struct amdgpu_bo_list {
1089 struct mutex lock;
1090 struct amdgpu_bo *gds_obj;
1091 struct amdgpu_bo *gws_obj;
1092 struct amdgpu_bo *oa_obj;
1093 bool has_userptr;
1094 unsigned num_entries;
1095 struct amdgpu_bo_list_entry *array;
1096};
1097
1098struct amdgpu_bo_list *
1099amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1100void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1101void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1102
1103/*
1104 * GFX stuff
1105 */
1106#include "clearstate_defs.h"
1107
1108struct amdgpu_rlc {
1109 /* for power gating */
1110 struct amdgpu_bo *save_restore_obj;
1111 uint64_t save_restore_gpu_addr;
1112 volatile uint32_t *sr_ptr;
1113 const u32 *reg_list;
1114 u32 reg_list_size;
1115 /* for clear state */
1116 struct amdgpu_bo *clear_state_obj;
1117 uint64_t clear_state_gpu_addr;
1118 volatile uint32_t *cs_ptr;
1119 const struct cs_section_def *cs_data;
1120 u32 clear_state_size;
1121 /* for cp tables */
1122 struct amdgpu_bo *cp_table_obj;
1123 uint64_t cp_table_gpu_addr;
1124 volatile uint32_t *cp_table_ptr;
1125 u32 cp_table_size;
1126};
1127
1128struct amdgpu_mec {
1129 struct amdgpu_bo *hpd_eop_obj;
1130 u64 hpd_eop_gpu_addr;
1131 u32 num_pipe;
1132 u32 num_mec;
1133 u32 num_queue;
1134};
1135
1136/*
1137 * GPU scratch registers structures, functions & helpers
1138 */
1139struct amdgpu_scratch {
1140 unsigned num_reg;
1141 uint32_t reg_base;
1142 bool free[32];
1143 uint32_t reg[32];
1144};
1145
1146/*
1147 * GFX configurations
1148 */
1149struct amdgpu_gca_config {
1150 unsigned max_shader_engines;
1151 unsigned max_tile_pipes;
1152 unsigned max_cu_per_sh;
1153 unsigned max_sh_per_se;
1154 unsigned max_backends_per_se;
1155 unsigned max_texture_channel_caches;
1156 unsigned max_gprs;
1157 unsigned max_gs_threads;
1158 unsigned max_hw_contexts;
1159 unsigned sc_prim_fifo_size_frontend;
1160 unsigned sc_prim_fifo_size_backend;
1161 unsigned sc_hiz_tile_fifo_size;
1162 unsigned sc_earlyz_tile_fifo_size;
1163
1164 unsigned num_tile_pipes;
1165 unsigned backend_enable_mask;
1166 unsigned mem_max_burst_length_bytes;
1167 unsigned mem_row_size_in_kb;
1168 unsigned shader_engine_tile_size;
1169 unsigned num_gpus;
1170 unsigned multi_gpu_tile_size;
1171 unsigned mc_arb_ramcfg;
1172 unsigned gb_addr_config;
1173
1174 uint32_t tile_mode_array[32];
1175 uint32_t macrotile_mode_array[16];
1176};
1177
1178struct amdgpu_gfx {
1179 struct mutex gpu_clock_mutex;
1180 struct amdgpu_gca_config config;
1181 struct amdgpu_rlc rlc;
1182 struct amdgpu_mec mec;
1183 struct amdgpu_scratch scratch;
1184 const struct firmware *me_fw; /* ME firmware */
1185 uint32_t me_fw_version;
1186 const struct firmware *pfp_fw; /* PFP firmware */
1187 uint32_t pfp_fw_version;
1188 const struct firmware *ce_fw; /* CE firmware */
1189 uint32_t ce_fw_version;
1190 const struct firmware *rlc_fw; /* RLC firmware */
1191 uint32_t rlc_fw_version;
1192 const struct firmware *mec_fw; /* MEC firmware */
1193 uint32_t mec_fw_version;
1194 const struct firmware *mec2_fw; /* MEC2 firmware */
1195 uint32_t mec2_fw_version;
02558a00
KW		 1196 uint32_t me_feature_version;
1197 uint32_t ce_feature_version;
1198 uint32_t pfp_feature_version;
351643d7
JZ		 1199 uint32_t rlc_feature_version;
1200 uint32_t mec_feature_version;
1201 uint32_t mec2_feature_version;
97b2e202
AD		 1202 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1203 unsigned num_gfx_rings;
1204 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1205 unsigned num_compute_rings;
1206 struct amdgpu_irq_src eop_irq;
1207 struct amdgpu_irq_src priv_reg_irq;
1208 struct amdgpu_irq_src priv_inst_irq;
1209 /* gfx status */
1210 uint32_t gfx_current_status;
a101a899
KW		 1211 /* ce ram size*/
1212 unsigned ce_ram_size;
97b2e202
AD		 1213};
1214
1215int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1216 unsigned size, struct amdgpu_ib *ib);
1217void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1218int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1219 struct amdgpu_ib *ib, void *owner);
1220int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1221void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1222int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1223/* Ring access between begin & end cannot sleep */
1224void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1225int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1226int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1227void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 1228void amdgpu_ring_commit(struct amdgpu_ring *ring);
1229void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1230void amdgpu_ring_undo(struct amdgpu_ring *ring);
1231void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1232unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1233 uint32_t **data);
1234int amdgpu_ring_restore(struct amdgpu_ring *ring,
1235 unsigned size, uint32_t *data);
1236int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1237 unsigned ring_size, u32 nop, u32 align_mask,
1238 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1239 enum amdgpu_ring_type ring_type);
1240void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1241struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1242
1243/*
1244 * CS.
1245 */
1246struct amdgpu_cs_chunk {
1247 uint32_t chunk_id;
1248 uint32_t length_dw;
1249 uint32_t *kdata;
1250 void __user *user_ptr;
1251};
1252
1253struct amdgpu_cs_parser {
1254 struct amdgpu_device *adev;
1255 struct drm_file *filp;
3cb485f3 1256 struct amdgpu_ctx *ctx;
97b2e202
AD		 1257 struct amdgpu_bo_list *bo_list;
1258 /* chunks */
1259 unsigned nchunks;
1260 struct amdgpu_cs_chunk *chunks;
1261 /* relocations */
56467ebf 1262 struct amdgpu_bo_list_entry vm_pd;
97b2e202 1263 struct list_head validated;
984810fc 1264 struct fence *fence;
f69f90a1
CK		 1265 uint64_t bytes_moved_threshold;
1266 uint64_t bytes_moved;
97b2e202
AD		 1267
1268 struct amdgpu_ib *ibs;
1269 uint32_t num_ibs;
1270
1271 struct ww_acquire_ctx ticket;
1272
1273 /* user fence */
91acbeb6
CK		 1274 struct amdgpu_user_fence uf;
1275 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1276};
1277
bb977d37
CZ		 1278struct amdgpu_job {
1279 struct amd_sched_job base;
1280 struct amdgpu_device *adev;
bb977d37
CZ		 1281 struct amdgpu_ib *ibs;
1282 uint32_t num_ibs;
e2840221 1283 void *owner;
bb977d37 1284 struct amdgpu_user_fence uf;
4c7eb91c 1285 int (*free_job)(struct amdgpu_job *job);
bb977d37 1286};
a6db8a33
JZ		 1287#define to_amdgpu_job(sched_job) \
1288 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1289
97b2e202
AD		 1290static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1291{
1292 return p->ibs[ib_idx].ptr[idx];
1293}
1294
1295/*
1296 * Writeback
1297 */
1298#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1299
1300struct amdgpu_wb {
1301 struct amdgpu_bo *wb_obj;
1302 volatile uint32_t *wb;
1303 uint64_t gpu_addr;
1304 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1305 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1306};
1307
1308int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1309void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1310
97b2e202 1311
97b2e202
AD		 1312
1313enum amdgpu_int_thermal_type {
1314 THERMAL_TYPE_NONE,
1315 THERMAL_TYPE_EXTERNAL,
1316 THERMAL_TYPE_EXTERNAL_GPIO,
1317 THERMAL_TYPE_RV6XX,
1318 THERMAL_TYPE_RV770,
1319 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1320 THERMAL_TYPE_EVERGREEN,
1321 THERMAL_TYPE_SUMO,
1322 THERMAL_TYPE_NI,
1323 THERMAL_TYPE_SI,
1324 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1325 THERMAL_TYPE_CI,
1326 THERMAL_TYPE_KV,
1327};
1328
1329enum amdgpu_dpm_auto_throttle_src {
1330 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1331 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1332};
1333
1334enum amdgpu_dpm_event_src {
1335 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1336 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1337 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1338 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1339 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1340};
1341
1342#define AMDGPU_MAX_VCE_LEVELS 6
1343
1344enum amdgpu_vce_level {
1345 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1346 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1347 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1348 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1349 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1350 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1351};
1352
1353struct amdgpu_ps {
1354 u32 caps; /* vbios flags */
1355 u32 class; /* vbios flags */
1356 u32 class2; /* vbios flags */
1357 /* UVD clocks */
1358 u32 vclk;
1359 u32 dclk;
1360 /* VCE clocks */
1361 u32 evclk;
1362 u32 ecclk;
1363 bool vce_active;
1364 enum amdgpu_vce_level vce_level;
1365 /* asic priv */
1366 void *ps_priv;
1367};
1368
1369struct amdgpu_dpm_thermal {
1370 /* thermal interrupt work */
1371 struct work_struct work;
1372 /* low temperature threshold */
1373 int min_temp;
1374 /* high temperature threshold */
1375 int max_temp;
1376 /* was last interrupt low to high or high to low */
1377 bool high_to_low;
1378 /* interrupt source */
1379 struct amdgpu_irq_src irq;
1380};
1381
1382enum amdgpu_clk_action
1383{
1384 AMDGPU_SCLK_UP = 1,
1385 AMDGPU_SCLK_DOWN
1386};
1387
1388struct amdgpu_blacklist_clocks
1389{
1390 u32 sclk;
1391 u32 mclk;
1392 enum amdgpu_clk_action action;
1393};
1394
1395struct amdgpu_clock_and_voltage_limits {
1396 u32 sclk;
1397 u32 mclk;
1398 u16 vddc;
1399 u16 vddci;
1400};
1401
1402struct amdgpu_clock_array {
1403 u32 count;
1404 u32 *values;
1405};
1406
1407struct amdgpu_clock_voltage_dependency_entry {
1408 u32 clk;
1409 u16 v;
1410};
1411
1412struct amdgpu_clock_voltage_dependency_table {
1413 u32 count;
1414 struct amdgpu_clock_voltage_dependency_entry *entries;
1415};
1416
1417union amdgpu_cac_leakage_entry {
1418 struct {
1419 u16 vddc;
1420 u32 leakage;
1421 };
1422 struct {
1423 u16 vddc1;
1424 u16 vddc2;
1425 u16 vddc3;
1426 };
1427};
1428
1429struct amdgpu_cac_leakage_table {
1430 u32 count;
1431 union amdgpu_cac_leakage_entry *entries;
1432};
1433
1434struct amdgpu_phase_shedding_limits_entry {
1435 u16 voltage;
1436 u32 sclk;
1437 u32 mclk;
1438};
1439
1440struct amdgpu_phase_shedding_limits_table {
1441 u32 count;
1442 struct amdgpu_phase_shedding_limits_entry *entries;
1443};
1444
1445struct amdgpu_uvd_clock_voltage_dependency_entry {
1446 u32 vclk;
1447 u32 dclk;
1448 u16 v;
1449};
1450
1451struct amdgpu_uvd_clock_voltage_dependency_table {
1452 u8 count;
1453 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1454};
1455
1456struct amdgpu_vce_clock_voltage_dependency_entry {
1457 u32 ecclk;
1458 u32 evclk;
1459 u16 v;
1460};
1461
1462struct amdgpu_vce_clock_voltage_dependency_table {
1463 u8 count;
1464 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1465};
1466
1467struct amdgpu_ppm_table {
1468 u8 ppm_design;
1469 u16 cpu_core_number;
1470 u32 platform_tdp;
1471 u32 small_ac_platform_tdp;
1472 u32 platform_tdc;
1473 u32 small_ac_platform_tdc;
1474 u32 apu_tdp;
1475 u32 dgpu_tdp;
1476 u32 dgpu_ulv_power;
1477 u32 tj_max;
1478};
1479
1480struct amdgpu_cac_tdp_table {
1481 u16 tdp;
1482 u16 configurable_tdp;
1483 u16 tdc;
1484 u16 battery_power_limit;
1485 u16 small_power_limit;
1486 u16 low_cac_leakage;
1487 u16 high_cac_leakage;
1488 u16 maximum_power_delivery_limit;
1489};
1490
1491struct amdgpu_dpm_dynamic_state {
1492 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1493 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1494 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1495 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1496 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1497 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1498 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1499 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1500 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1501 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1502 struct amdgpu_clock_array valid_sclk_values;
1503 struct amdgpu_clock_array valid_mclk_values;
1504 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1505 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1506 u32 mclk_sclk_ratio;
1507 u32 sclk_mclk_delta;
1508 u16 vddc_vddci_delta;
1509 u16 min_vddc_for_pcie_gen2;
1510 struct amdgpu_cac_leakage_table cac_leakage_table;
1511 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1512 struct amdgpu_ppm_table *ppm_table;
1513 struct amdgpu_cac_tdp_table *cac_tdp_table;
1514};
1515
1516struct amdgpu_dpm_fan {
1517 u16 t_min;
1518 u16 t_med;
1519 u16 t_high;
1520 u16 pwm_min;
1521 u16 pwm_med;
1522 u16 pwm_high;
1523 u8 t_hyst;
1524 u32 cycle_delay;
1525 u16 t_max;
1526 u8 control_mode;
1527 u16 default_max_fan_pwm;
1528 u16 default_fan_output_sensitivity;
1529 u16 fan_output_sensitivity;
1530 bool ucode_fan_control;
1531};
1532
1533enum amdgpu_pcie_gen {
1534 AMDGPU_PCIE_GEN1 = 0,
1535 AMDGPU_PCIE_GEN2 = 1,
1536 AMDGPU_PCIE_GEN3 = 2,
1537 AMDGPU_PCIE_GEN_INVALID = 0xffff
1538};
1539
1540enum amdgpu_dpm_forced_level {
1541 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1542 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1543 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1544};
1545
1546struct amdgpu_vce_state {
1547 /* vce clocks */
1548 u32 evclk;
1549 u32 ecclk;
1550 /* gpu clocks */
1551 u32 sclk;
1552 u32 mclk;
1553 u8 clk_idx;
1554 u8 pstate;
1555};
1556
1557struct amdgpu_dpm_funcs {
1558 int (*get_temperature)(struct amdgpu_device *adev);
1559 int (*pre_set_power_state)(struct amdgpu_device *adev);
1560 int (*set_power_state)(struct amdgpu_device *adev);
1561 void (*post_set_power_state)(struct amdgpu_device *adev);
1562 void (*display_configuration_changed)(struct amdgpu_device *adev);
1563 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1564 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1565 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1566 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1567 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1568 bool (*vblank_too_short)(struct amdgpu_device *adev);
1569 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1570 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1571 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1572 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1573 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1574 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1575 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1576};
1577
1578struct amdgpu_dpm {
1579 struct amdgpu_ps *ps;
1580 /* number of valid power states */
1581 int num_ps;
1582 /* current power state that is active */
1583 struct amdgpu_ps *current_ps;
1584 /* requested power state */
1585 struct amdgpu_ps *requested_ps;
1586 /* boot up power state */
1587 struct amdgpu_ps *boot_ps;
1588 /* default uvd power state */
1589 struct amdgpu_ps *uvd_ps;
1590 /* vce requirements */
1591 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1592 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1593 enum amd_pm_state_type state;
1594 enum amd_pm_state_type user_state;
97b2e202
AD		 1595 u32 platform_caps;
1596 u32 voltage_response_time;
1597 u32 backbias_response_time;
1598 void *priv;
1599 u32 new_active_crtcs;
1600 int new_active_crtc_count;
1601 u32 current_active_crtcs;
1602 int current_active_crtc_count;
1603 struct amdgpu_dpm_dynamic_state dyn_state;
1604 struct amdgpu_dpm_fan fan;
1605 u32 tdp_limit;
1606 u32 near_tdp_limit;
1607 u32 near_tdp_limit_adjusted;
1608 u32 sq_ramping_threshold;
1609 u32 cac_leakage;
1610 u16 tdp_od_limit;
1611 u32 tdp_adjustment;
1612 u16 load_line_slope;
1613 bool power_control;
1614 bool ac_power;
1615 /* special states active */
1616 bool thermal_active;
1617 bool uvd_active;
1618 bool vce_active;
1619 /* thermal handling */
1620 struct amdgpu_dpm_thermal thermal;
1621 /* forced levels */
1622 enum amdgpu_dpm_forced_level forced_level;
1623};
1624
1625struct amdgpu_pm {
1626 struct mutex mutex;
97b2e202
AD		 1627 u32 current_sclk;
1628 u32 current_mclk;
1629 u32 default_sclk;
1630 u32 default_mclk;
1631 struct amdgpu_i2c_chan *i2c_bus;
1632 /* internal thermal controller on rv6xx+ */
1633 enum amdgpu_int_thermal_type int_thermal_type;
1634 struct device *int_hwmon_dev;
1635 /* fan control parameters */
1636 bool no_fan;
1637 u8 fan_pulses_per_revolution;
1638 u8 fan_min_rpm;
1639 u8 fan_max_rpm;
1640 /* dpm */
1641 bool dpm_enabled;
c86f5ebf 1642 bool sysfs_initialized;
97b2e202
AD		 1643 struct amdgpu_dpm dpm;
1644 const struct firmware *fw; /* SMC firmware */
1645 uint32_t fw_version;
1646 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1647 uint32_t pcie_gen_mask;
1648 uint32_t pcie_mlw_mask;
7fb72a1f 1649 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1650};
1651
d0dd7f0c
AD		 1652void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1653
97b2e202
AD		 1654/*
1655 * UVD
1656 */
1657#define AMDGPU_MAX_UVD_HANDLES 10
1658#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1659#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1660#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1661
1662struct amdgpu_uvd {
1663 struct amdgpu_bo *vcpu_bo;
1664 void *cpu_addr;
1665 uint64_t gpu_addr;
97b2e202
AD		 1666 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1667 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1668 struct delayed_work idle_work;
1669 const struct firmware *fw; /* UVD firmware */
1670 struct amdgpu_ring ring;
1671 struct amdgpu_irq_src irq;
1672 bool address_64_bit;
1673};
1674
1675/*
1676 * VCE
1677 */
1678#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1679#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1680
6a585777
AD		 1681#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1682#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1683
97b2e202
AD		 1684struct amdgpu_vce {
1685 struct amdgpu_bo *vcpu_bo;
1686 uint64_t gpu_addr;
1687 unsigned fw_version;
1688 unsigned fb_version;
1689 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1690 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1691 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1692 struct delayed_work idle_work;
1693 const struct firmware *fw; /* VCE firmware */
1694 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1695 struct amdgpu_irq_src irq;
6a585777 1696 unsigned harvest_config;
97b2e202
AD		 1697};
1698
1699/*
1700 * SDMA
1701 */
c113ea1c 1702struct amdgpu_sdma_instance {
97b2e202
AD		 1703 /* SDMA firmware */
1704 const struct firmware *fw;
1705 uint32_t fw_version;
cfa2104f 1706 uint32_t feature_version;
97b2e202
AD		 1707
1708 struct amdgpu_ring ring;
18111de0 1709 bool burst_nop;
97b2e202
AD		 1710};
1711
c113ea1c
AD		 1712struct amdgpu_sdma {
1713 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1714 struct amdgpu_irq_src trap_irq;
1715 struct amdgpu_irq_src illegal_inst_irq;
1716 int num_instances;
1717};
1718
97b2e202
AD		 1719/*
1720 * Firmware
1721 */
1722struct amdgpu_firmware {
1723 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1724 bool smu_load;
1725 struct amdgpu_bo *fw_buf;
1726 unsigned int fw_size;
1727};
1728
1729/*
1730 * Benchmarking
1731 */
1732void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1733
1734
1735/*
1736 * Testing
1737 */
1738void amdgpu_test_moves(struct amdgpu_device *adev);
1739void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1740 struct amdgpu_ring *cpA,
1741 struct amdgpu_ring *cpB);
1742void amdgpu_test_syncing(struct amdgpu_device *adev);
1743
1744/*
1745 * MMU Notifier
1746 */
1747#if defined(CONFIG_MMU_NOTIFIER)
1748int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1749void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1750#else
1d1106b0 1751static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1752{
1753 return -ENODEV;
1754}
1d1106b0 1755static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1756#endif
1757
1758/*
1759 * Debugfs
1760 */
1761struct amdgpu_debugfs {
1762 struct drm_info_list *files;
1763 unsigned num_files;
1764};
1765
1766int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1767 struct drm_info_list *files,
1768 unsigned nfiles);
1769int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1770
1771#if defined(CONFIG_DEBUG_FS)
1772int amdgpu_debugfs_init(struct drm_minor *minor);
1773void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1774#endif
1775
1776/*
1777 * amdgpu smumgr functions
1778 */
1779struct amdgpu_smumgr_funcs {
1780 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1781 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1782 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1783};
1784
1785/*
1786 * amdgpu smumgr
1787 */
1788struct amdgpu_smumgr {
1789 struct amdgpu_bo *toc_buf;
1790 struct amdgpu_bo *smu_buf;
1791 /* asic priv smu data */
1792 void *priv;
1793 spinlock_t smu_lock;
1794 /* smumgr functions */
1795 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1796 /* ucode loading complete flag */
1797 uint32_t fw_flags;
1798};
1799
1800/*
1801 * ASIC specific register table accessible by UMD
1802 */
1803struct amdgpu_allowed_register_entry {
1804 uint32_t reg_offset;
1805 bool untouched;
1806 bool grbm_indexed;
1807};
1808
1809struct amdgpu_cu_info {
1810 uint32_t number; /* total active CU number */
1811 uint32_t ao_cu_mask;
1812 uint32_t bitmap[4][4];
1813};
1814
1815
1816/*
1817 * ASIC specific functions.
1818 */
1819struct amdgpu_asic_funcs {
1820 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1821 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1822 u8 *bios, u32 length_bytes);
97b2e202
AD		 1823 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1824 u32 sh_num, u32 reg_offset, u32 *value);
1825 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1826 int (*reset)(struct amdgpu_device *adev);
1827 /* wait for mc_idle */
1828 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1829 /* get the reference clock */
1830 u32 (*get_xclk)(struct amdgpu_device *adev);
1831 /* get the gpu clock counter */
1832 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1833 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1834 /* MM block clocks */
1835 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1836 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1837};
1838
1839/*
1840 * IOCTL.
1841 */
1842int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *filp);
1844int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1845 struct drm_file *filp);
1846
1847int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1848 struct drm_file *filp);
1849int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1851int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1852 struct drm_file *filp);
1853int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1854 struct drm_file *filp);
1855int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1856 struct drm_file *filp);
1857int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1858 struct drm_file *filp);
1859int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1860int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1861
1862int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864
1865/* VRAM scratch page for HDP bug, default vram page */
1866struct amdgpu_vram_scratch {
1867 struct amdgpu_bo *robj;
1868 volatile uint32_t *ptr;
1869 u64 gpu_addr;
1870};
1871
1872/*
1873 * ACPI
1874 */
1875struct amdgpu_atif_notification_cfg {
1876 bool enabled;
1877 int command_code;
1878};
1879
1880struct amdgpu_atif_notifications {
1881 bool display_switch;
1882 bool expansion_mode_change;
1883 bool thermal_state;
1884 bool forced_power_state;
1885 bool system_power_state;
1886 bool display_conf_change;
1887 bool px_gfx_switch;
1888 bool brightness_change;
1889 bool dgpu_display_event;
1890};
1891
1892struct amdgpu_atif_functions {
1893 bool system_params;
1894 bool sbios_requests;
1895 bool select_active_disp;
1896 bool lid_state;
1897 bool get_tv_standard;
1898 bool set_tv_standard;
1899 bool get_panel_expansion_mode;
1900 bool set_panel_expansion_mode;
1901 bool temperature_change;
1902 bool graphics_device_types;
1903};
1904
1905struct amdgpu_atif {
1906 struct amdgpu_atif_notifications notifications;
1907 struct amdgpu_atif_functions functions;
1908 struct amdgpu_atif_notification_cfg notification_cfg;
1909 struct amdgpu_encoder *encoder_for_bl;
1910};
1911
1912struct amdgpu_atcs_functions {
1913 bool get_ext_state;
1914 bool pcie_perf_req;
1915 bool pcie_dev_rdy;
1916 bool pcie_bus_width;
1917};
1918
1919struct amdgpu_atcs {
1920 struct amdgpu_atcs_functions functions;
1921};
1922
d03846af
CZ		 1923/*
1924 * CGS
1925 */
1926void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1927void amdgpu_cgs_destroy_device(void *cgs_device);
1928
1929
97b2e202
AD		 1930/*
1931 * Core structure, functions and helpers.
1932 */
1933typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1934typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1935
1936typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1937typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1938
8faf0e08
AD		 1939struct amdgpu_ip_block_status {
1940 bool valid;
1941 bool sw;
1942 bool hw;
1943};
1944
97b2e202
AD		 1945struct amdgpu_device {
1946 struct device *dev;
1947 struct drm_device *ddev;
1948 struct pci_dev *pdev;
97b2e202
AD		 1949
1950 /* ASIC */
2f7d10b3 1951 enum amd_asic_type asic_type;
97b2e202
AD		 1952 uint32_t family;
1953 uint32_t rev_id;
1954 uint32_t external_rev_id;
1955 unsigned long flags;
1956 int usec_timeout;
1957 const struct amdgpu_asic_funcs *asic_funcs;
1958 bool shutdown;
1959 bool suspend;
1960 bool need_dma32;
1961 bool accel_working;
97b2e202
AD		 1962 struct work_struct reset_work;
1963 struct notifier_block acpi_nb;
1964 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1965 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1966 unsigned debugfs_count;
1967#if defined(CONFIG_DEBUG_FS)
1968 struct dentry *debugfs_regs;
1969#endif
1970 struct amdgpu_atif atif;
1971 struct amdgpu_atcs atcs;
1972 struct mutex srbm_mutex;
1973 /* GRBM index mutex. Protects concurrent access to GRBM index */
1974 struct mutex grbm_idx_mutex;
1975 struct dev_pm_domain vga_pm_domain;
1976 bool have_disp_power_ref;
1977
1978 /* BIOS */
1979 uint8_t *bios;
1980 bool is_atom_bios;
1981 uint16_t bios_header_start;
1982 struct amdgpu_bo *stollen_vga_memory;
1983 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1984
1985 /* Register/doorbell mmio */
1986 resource_size_t rmmio_base;
1987 resource_size_t rmmio_size;
1988 void __iomem *rmmio;
1989 /* protects concurrent MM_INDEX/DATA based register access */
1990 spinlock_t mmio_idx_lock;
1991 /* protects concurrent SMC based register access */
1992 spinlock_t smc_idx_lock;
1993 amdgpu_rreg_t smc_rreg;
1994 amdgpu_wreg_t smc_wreg;
1995 /* protects concurrent PCIE register access */
1996 spinlock_t pcie_idx_lock;
1997 amdgpu_rreg_t pcie_rreg;
1998 amdgpu_wreg_t pcie_wreg;
1999 /* protects concurrent UVD register access */
2000 spinlock_t uvd_ctx_idx_lock;
2001 amdgpu_rreg_t uvd_ctx_rreg;
2002 amdgpu_wreg_t uvd_ctx_wreg;
2003 /* protects concurrent DIDT register access */
2004 spinlock_t didt_idx_lock;
2005 amdgpu_rreg_t didt_rreg;
2006 amdgpu_wreg_t didt_wreg;
2007 /* protects concurrent ENDPOINT (audio) register access */
2008 spinlock_t audio_endpt_idx_lock;
2009 amdgpu_block_rreg_t audio_endpt_rreg;
2010 amdgpu_block_wreg_t audio_endpt_wreg;
2011 void __iomem *rio_mem;
2012 resource_size_t rio_mem_size;
2013 struct amdgpu_doorbell doorbell;
2014
2015 /* clock/pll info */
2016 struct amdgpu_clock clock;
2017
2018 /* MC */
2019 struct amdgpu_mc mc;
2020 struct amdgpu_gart gart;
2021 struct amdgpu_dummy_page dummy_page;
2022 struct amdgpu_vm_manager vm_manager;
2023
2024 /* memory management */
2025 struct amdgpu_mman mman;
2026 struct amdgpu_gem gem;
2027 struct amdgpu_vram_scratch vram_scratch;
2028 struct amdgpu_wb wb;
2029 atomic64_t vram_usage;
2030 atomic64_t vram_vis_usage;
2031 atomic64_t gtt_usage;
2032 atomic64_t num_bytes_moved;
d94aed5a 2033 atomic_t gpu_reset_counter;
97b2e202
AD		 2034
2035 /* display */
2036 struct amdgpu_mode_info mode_info;
2037 struct work_struct hotplug_work;
2038 struct amdgpu_irq_src crtc_irq;
2039 struct amdgpu_irq_src pageflip_irq;
2040 struct amdgpu_irq_src hpd_irq;
2041
2042 /* rings */
97b2e202
AD		 2043 unsigned fence_context;
2044 struct mutex ring_lock;
2045 unsigned num_rings;
2046 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2047 bool ib_pool_ready;
2048 struct amdgpu_sa_manager ring_tmp_bo;
2049
2050 /* interrupts */
2051 struct amdgpu_irq irq;
2052
1f7371b2
AD		 2053 /* powerplay */
2054 struct amd_powerplay powerplay;
e61710c5 2055 bool pp_enabled;
1f7371b2 2056
97b2e202
AD		 2057 /* dpm */
2058 struct amdgpu_pm pm;
2059 u32 cg_flags;
2060 u32 pg_flags;
2061
2062 /* amdgpu smumgr */
2063 struct amdgpu_smumgr smu;
2064
2065 /* gfx */
2066 struct amdgpu_gfx gfx;
2067
2068 /* sdma */
c113ea1c 2069 struct amdgpu_sdma sdma;
97b2e202
AD		 2070
2071 /* uvd */
2072 bool has_uvd;
2073 struct amdgpu_uvd uvd;
2074
2075 /* vce */
2076 struct amdgpu_vce vce;
2077
2078 /* firmwares */
2079 struct amdgpu_firmware firmware;
2080
2081 /* GDS */
2082 struct amdgpu_gds gds;
2083
2084 const struct amdgpu_ip_block_version *ip_blocks;
2085 int num_ip_blocks;
8faf0e08 2086 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2087 struct mutex mn_lock;
2088 DECLARE_HASHTABLE(mn_hash, 7);
2089
2090 /* tracking pinned memory */
2091 u64 vram_pin_size;
2092 u64 gart_pin_size;
130e0371
OG		 2093
2094 /* amdkfd interface */
2095 struct kfd_dev *kfd;
23ca0e4e
CZ		 2096
2097 /* kernel conext for IB submission */
47f38501 2098 struct amdgpu_ctx kernel_ctx;
97b2e202
AD		 2099};
2100
2101bool amdgpu_device_is_px(struct drm_device *dev);
2102int amdgpu_device_init(struct amdgpu_device *adev,
2103 struct drm_device *ddev,
2104 struct pci_dev *pdev,
2105 uint32_t flags);
2106void amdgpu_device_fini(struct amdgpu_device *adev);
2107int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2108
2109uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2110 bool always_indirect);
2111void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2112 bool always_indirect);
2113u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2114void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2115
2116u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2117void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2118
2119/*
2120 * Cast helper
2121 */
2122extern const struct fence_ops amdgpu_fence_ops;
2123static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2124{
2125 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2126
2127 if (__f->base.ops == &amdgpu_fence_ops)
2128 return __f;
2129
2130 return NULL;
2131}
2132
2133/*
2134 * Registers read & write functions.
2135 */
2136#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2137#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2138#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2139#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2140#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2141#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2142#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2143#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2144#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2145#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2146#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2147#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2148#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2149#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2150#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2151#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2152#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2153#define WREG32_P(reg, val, mask) \
2154 do { \
2155 uint32_t tmp_ = RREG32(reg); \
2156 tmp_ &= (mask); \
2157 tmp_ |= ((val) & ~(mask)); \
2158 WREG32(reg, tmp_); \
2159 } while (0)
2160#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2161#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2162#define WREG32_PLL_P(reg, val, mask) \
2163 do { \
2164 uint32_t tmp_ = RREG32_PLL(reg); \
2165 tmp_ &= (mask); \
2166 tmp_ |= ((val) & ~(mask)); \
2167 WREG32_PLL(reg, tmp_); \
2168 } while (0)
2169#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2170#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2171#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2172
2173#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2174#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2175
2176#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2177#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2178
2179#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2180 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2181 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2182
2183#define REG_GET_FIELD(value, reg, field) \
2184 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2185
2186/*
2187 * BIOS helpers.
2188 */
2189#define RBIOS8(i) (adev->bios[i])
2190#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2191#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2192
2193/*
2194 * RING helpers.
2195 */
2196static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2197{
2198 if (ring->count_dw <= 0)
86c2b790 2199 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2200 ring->ring[ring->wptr++] = v;
2201 ring->wptr &= ring->ptr_mask;
2202 ring->count_dw--;
2203 ring->ring_free_dw--;
2204}
2205
c113ea1c
AD		 2206static inline struct amdgpu_sdma_instance *
2207amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2208{
2209 struct amdgpu_device *adev = ring->adev;
2210 int i;
2211
c113ea1c
AD		 2212 for (i = 0; i < adev->sdma.num_instances; i++)
2213 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2214 break;
2215
2216 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2217 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2218 else
2219 return NULL;
2220}
2221
97b2e202
AD		 2222/*
2223 * ASICs macro.
2224 */
2225#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2226#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2227#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2228#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2229#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2230#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2231#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2232#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2233#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2234#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2235#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2236#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2237#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2238#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2239#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2240#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2241#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2242#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2243#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2244#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2245#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2246#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2247#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2248#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2249#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2250#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2251#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2252#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2253#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2254#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2255#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2256#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2257#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2258#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2259#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2260#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2261#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2262#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2263#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2264#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2265#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2266#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2267#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2268#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2269#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2270#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2271#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2272#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2273#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2274#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2275#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2276#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2277#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2278#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2279#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2280#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2281#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2282
2283#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2284 ((adev)->pp_enabled ? \
e61710c5 2285 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2286 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2287
2288#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2289 ((adev)->pp_enabled ? \
e61710c5 2290 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2291 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2292
2293#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2294 ((adev)->pp_enabled ? \
e61710c5 2295 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2296 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2297
2298#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2299 ((adev)->pp_enabled ? \
e61710c5 2300 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2301 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2302
2303#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2304 ((adev)->pp_enabled ? \
e61710c5 2305 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2306 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2307
1b5708ff 2308#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2309 ((adev)->pp_enabled ? \
e61710c5 2310 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2311 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2312
2313#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2314 ((adev)->pp_enabled ? \
e61710c5 2315 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2316 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2317
2318
2319#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2320 ((adev)->pp_enabled ? \
e61710c5 2321 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2322 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2323
2324#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2325 ((adev)->pp_enabled ? \
e61710c5 2326 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2327 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2328
2329#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2330 ((adev)->pp_enabled ? \
e61710c5 2331 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2332 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2333
2334#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2335 ((adev)->pp_enabled ? \
e61710c5 2336 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2337 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2338
2339#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2340 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2341
2342#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2343 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2344
e61710c5 2345#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2346 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2347
2348#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2349
2350/* Common functions */
2351int amdgpu_gpu_reset(struct amdgpu_device *adev);
2352void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2353bool amdgpu_card_posted(struct amdgpu_device *adev);
2354void amdgpu_update_display_priority(struct amdgpu_device *adev);
2355bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82 2356
97b2e202
AD		 2357int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2358int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2359 u32 ip_instance, u32 ring,
2360 struct amdgpu_ring **out_ring);
2361void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2362bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2363int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2364 uint32_t flags);
2365bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
d7006964
CK		 2366bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2367 unsigned long end);
97b2e202
AD		 2368bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2369uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2370 struct ttm_mem_reg *mem);
2371void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2372void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2373void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2374void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2375 const u32 *registers,
2376 const u32 array_size);
2377
2378bool amdgpu_device_is_px(struct drm_device *dev);
2379/* atpx handler */
2380#if defined(CONFIG_VGA_SWITCHEROO)
2381void amdgpu_register_atpx_handler(void);
2382void amdgpu_unregister_atpx_handler(void);
2383#else
2384static inline void amdgpu_register_atpx_handler(void) {}
2385static inline void amdgpu_unregister_atpx_handler(void) {}
2386#endif
2387
2388/*
2389 * KMS
2390 */
2391extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2392extern int amdgpu_max_kms_ioctl;
2393
2394int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2395int amdgpu_driver_unload_kms(struct drm_device *dev);
2396void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2397int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2398void amdgpu_driver_postclose_kms(struct drm_device *dev,
2399 struct drm_file *file_priv);
2400void amdgpu_driver_preclose_kms(struct drm_device *dev,
2401 struct drm_file *file_priv);
2402int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2403int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2404u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2405int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2406void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2407int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2408 int *max_error,
2409 struct timeval *vblank_time,
2410 unsigned flags);
2411long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2412 unsigned long arg);
2413
97b2e202
AD		 2414/*
2415 * functions used by amdgpu_encoder.c
2416 */
2417struct amdgpu_afmt_acr {
2418 u32 clock;
2419
2420 int n_32khz;
2421 int cts_32khz;
2422
2423 int n_44_1khz;
2424 int cts_44_1khz;
2425
2426 int n_48khz;
2427 int cts_48khz;
2428
2429};
2430
2431struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2432
2433/* amdgpu_acpi.c */
2434#if defined(CONFIG_ACPI)
2435int amdgpu_acpi_init(struct amdgpu_device *adev);
2436void amdgpu_acpi_fini(struct amdgpu_device *adev);
2437bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2438int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2439 u8 perf_req, bool advertise);
2440int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2441#else
2442static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2443static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2444#endif
2445
2446struct amdgpu_bo_va_mapping *
2447amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2448 uint64_t addr, struct amdgpu_bo **bo);
2449
2450#include "amdgpu_object.h"
2451
2452#endif
Linux kernel - Deliverables
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