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drm/amdgpu: bump the DRM version for new allowed mem-mapped registers
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
55
b80d8475
AD		 56#include "gpu_scheduler.h"
57
97b2e202
AD		 58/*
59 * Modules parameters.
60 */
61extern int amdgpu_modeset;
62extern int amdgpu_vram_limit;
63extern int amdgpu_gart_size;
64extern int amdgpu_benchmarking;
65extern int amdgpu_testing;
66extern int amdgpu_audio;
67extern int amdgpu_disp_priority;
68extern int amdgpu_hw_i2c;
69extern int amdgpu_pcie_gen2;
70extern int amdgpu_msi;
71extern int amdgpu_lockup_timeout;
72extern int amdgpu_dpm;
73extern int amdgpu_smc_load_fw;
74extern int amdgpu_aspm;
75extern int amdgpu_runtime_pm;
76extern int amdgpu_hard_reset;
77extern unsigned amdgpu_ip_block_mask;
78extern int amdgpu_bapm;
79extern int amdgpu_deep_color;
80extern int amdgpu_vm_size;
81extern int amdgpu_vm_block_size;
b80d8475 82extern int amdgpu_enable_scheduler;
1333f723 83extern int amdgpu_sched_jobs;
4afcb303 84extern int amdgpu_sched_hw_submission;
97b2e202 85
4b559c90 86#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 87#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
88#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
89/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
90#define AMDGPU_IB_POOL_SIZE 16
91#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
92#define AMDGPUFB_CONN_LIMIT 4
93#define AMDGPU_BIOS_NUM_SCRATCH 8
94
97b2e202
AD		 95/* max number of rings */
96#define AMDGPU_MAX_RINGS 16
97#define AMDGPU_MAX_GFX_RINGS 1
98#define AMDGPU_MAX_COMPUTE_RINGS 8
99#define AMDGPU_MAX_VCE_RINGS 2
100
101/* number of hw syncs before falling back on blocking */
102#define AMDGPU_NUM_SYNCS 4
103
104/* hardcode that limit for now */
105#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
106
107/* hard reset data */
108#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
109
110/* reset flags */
111#define AMDGPU_RESET_GFX (1 << 0)
112#define AMDGPU_RESET_COMPUTE (1 << 1)
113#define AMDGPU_RESET_DMA (1 << 2)
114#define AMDGPU_RESET_CP (1 << 3)
115#define AMDGPU_RESET_GRBM (1 << 4)
116#define AMDGPU_RESET_DMA1 (1 << 5)
117#define AMDGPU_RESET_RLC (1 << 6)
118#define AMDGPU_RESET_SEM (1 << 7)
119#define AMDGPU_RESET_IH (1 << 8)
120#define AMDGPU_RESET_VMC (1 << 9)
121#define AMDGPU_RESET_MC (1 << 10)
122#define AMDGPU_RESET_DISPLAY (1 << 11)
123#define AMDGPU_RESET_UVD (1 << 12)
124#define AMDGPU_RESET_VCE (1 << 13)
125#define AMDGPU_RESET_VCE1 (1 << 14)
126
127/* CG block flags */
128#define AMDGPU_CG_BLOCK_GFX (1 << 0)
129#define AMDGPU_CG_BLOCK_MC (1 << 1)
130#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
131#define AMDGPU_CG_BLOCK_UVD (1 << 3)
132#define AMDGPU_CG_BLOCK_VCE (1 << 4)
133#define AMDGPU_CG_BLOCK_HDP (1 << 5)
134#define AMDGPU_CG_BLOCK_BIF (1 << 6)
135
136/* CG flags */
137#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
138#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
139#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
140#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
141#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
142#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
143#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
144#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
145#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
146#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
147#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
148#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
149#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
150#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
151#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
152#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
153#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
154
155/* PG flags */
156#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
157#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
158#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
159#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
160#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
161#define AMDGPU_PG_SUPPORT_CP (1 << 5)
162#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
163#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
164#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
165#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
166#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
167
168/* GFX current status */
169#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
170#define AMDGPU_GFX_SAFE_MODE 0x00000001L
171#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
172#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
173#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
174
175/* max cursor sizes (in pixels) */
176#define CIK_CURSOR_WIDTH 128
177#define CIK_CURSOR_HEIGHT 128
178
179struct amdgpu_device;
180struct amdgpu_fence;
181struct amdgpu_ib;
182struct amdgpu_vm;
183struct amdgpu_ring;
184struct amdgpu_semaphore;
185struct amdgpu_cs_parser;
186struct amdgpu_irq_src;
0b492a4c 187struct amdgpu_fpriv;
97b2e202
AD		 188
189enum amdgpu_cp_irq {
190 AMDGPU_CP_IRQ_GFX_EOP = 0,
191 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
199
200 AMDGPU_CP_IRQ_LAST
201};
202
203enum amdgpu_sdma_irq {
204 AMDGPU_SDMA_IRQ_TRAP0 = 0,
205 AMDGPU_SDMA_IRQ_TRAP1,
206
207 AMDGPU_SDMA_IRQ_LAST
208};
209
210enum amdgpu_thermal_irq {
211 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
212 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
213
214 AMDGPU_THERMAL_IRQ_LAST
215};
216
97b2e202 217int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 218 enum amd_ip_block_type block_type,
219 enum amd_clockgating_state state);
97b2e202 220int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 221 enum amd_ip_block_type block_type,
222 enum amd_powergating_state state);
97b2e202
AD		 223
224struct amdgpu_ip_block_version {
5fc3aeeb 225 enum amd_ip_block_type type;
97b2e202
AD		 226 u32 major;
227 u32 minor;
228 u32 rev;
5fc3aeeb 229 const struct amd_ip_funcs *funcs;
97b2e202
AD		 230};
231
232int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 233 enum amd_ip_block_type type,
97b2e202
AD		 234 u32 major, u32 minor);
235
236const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
237 struct amdgpu_device *adev,
5fc3aeeb 238 enum amd_ip_block_type type);
97b2e202
AD		 239
240/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
241struct amdgpu_buffer_funcs {
242 /* maximum bytes in a single operation */
243 uint32_t copy_max_bytes;
244
245 /* number of dw to reserve per operation */
246 unsigned copy_num_dw;
247
248 /* used for buffer migration */
249 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
250 /* src addr in bytes */
251 uint64_t src_offset,
252 /* dst addr in bytes */
253 uint64_t dst_offset,
254 /* number of byte to transfer */
255 uint32_t byte_count);
256
257 /* maximum bytes in a single operation */
258 uint32_t fill_max_bytes;
259
260 /* number of dw to reserve per operation */
261 unsigned fill_num_dw;
262
263 /* used for buffer clearing */
264 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
265 /* value to write to memory */
266 uint32_t src_data,
267 /* dst addr in bytes */
268 uint64_t dst_offset,
269 /* number of byte to fill */
270 uint32_t byte_count);
271};
272
273/* provided by hw blocks that can write ptes, e.g., sdma */
274struct amdgpu_vm_pte_funcs {
275 /* copy pte entries from GART */
276 void (*copy_pte)(struct amdgpu_ib *ib,
277 uint64_t pe, uint64_t src,
278 unsigned count);
279 /* write pte one entry at a time with addr mapping */
280 void (*write_pte)(struct amdgpu_ib *ib,
281 uint64_t pe,
282 uint64_t addr, unsigned count,
283 uint32_t incr, uint32_t flags);
284 /* for linear pte/pde updates without addr mapping */
285 void (*set_pte_pde)(struct amdgpu_ib *ib,
286 uint64_t pe,
287 uint64_t addr, unsigned count,
288 uint32_t incr, uint32_t flags);
289 /* pad the indirect buffer to the necessary number of dw */
290 void (*pad_ib)(struct amdgpu_ib *ib);
291};
292
293/* provided by the gmc block */
294struct amdgpu_gart_funcs {
295 /* flush the vm tlb via mmio */
296 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
297 uint32_t vmid);
298 /* write pte/pde updates using the cpu */
299 int (*set_pte_pde)(struct amdgpu_device *adev,
300 void *cpu_pt_addr, /* cpu addr of page table */
301 uint32_t gpu_page_idx, /* pte/pde to update */
302 uint64_t addr, /* addr to write into pte/pde */
303 uint32_t flags); /* access flags */
304};
305
306/* provided by the ih block */
307struct amdgpu_ih_funcs {
308 /* ring read/write ptr handling, called from interrupt context */
309 u32 (*get_wptr)(struct amdgpu_device *adev);
310 void (*decode_iv)(struct amdgpu_device *adev,
311 struct amdgpu_iv_entry *entry);
312 void (*set_rptr)(struct amdgpu_device *adev);
313};
314
315/* provided by hw blocks that expose a ring buffer for commands */
316struct amdgpu_ring_funcs {
317 /* ring read/write ptr handling */
318 u32 (*get_rptr)(struct amdgpu_ring *ring);
319 u32 (*get_wptr)(struct amdgpu_ring *ring);
320 void (*set_wptr)(struct amdgpu_ring *ring);
321 /* validating and patching of IBs */
322 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
323 /* command emit functions */
324 void (*emit_ib)(struct amdgpu_ring *ring,
325 struct amdgpu_ib *ib);
326 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 327 uint64_t seq, unsigned flags);
97b2e202
AD		 328 bool (*emit_semaphore)(struct amdgpu_ring *ring,
329 struct amdgpu_semaphore *semaphore,
330 bool emit_wait);
331 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
332 uint64_t pd_addr);
d2edb07b 333 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 334 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
335 uint32_t gds_base, uint32_t gds_size,
336 uint32_t gws_base, uint32_t gws_size,
337 uint32_t oa_base, uint32_t oa_size);
338 /* testing functions */
339 int (*test_ring)(struct amdgpu_ring *ring);
340 int (*test_ib)(struct amdgpu_ring *ring);
341 bool (*is_lockup)(struct amdgpu_ring *ring);
342};
343
344/*
345 * BIOS.
346 */
347bool amdgpu_get_bios(struct amdgpu_device *adev);
348bool amdgpu_read_bios(struct amdgpu_device *adev);
349
350/*
351 * Dummy page
352 */
353struct amdgpu_dummy_page {
354 struct page *page;
355 dma_addr_t addr;
356};
357int amdgpu_dummy_page_init(struct amdgpu_device *adev);
358void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
359
360
361/*
362 * Clocks
363 */
364
365#define AMDGPU_MAX_PPLL 3
366
367struct amdgpu_clock {
368 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
369 struct amdgpu_pll spll;
370 struct amdgpu_pll mpll;
371 /* 10 Khz units */
372 uint32_t default_mclk;
373 uint32_t default_sclk;
374 uint32_t default_dispclk;
375 uint32_t current_dispclk;
376 uint32_t dp_extclk;
377 uint32_t max_pixel_clock;
378};
379
380/*
381 * Fences.
382 */
383struct amdgpu_fence_driver {
384 struct amdgpu_ring *ring;
385 uint64_t gpu_addr;
386 volatile uint32_t *cpu_addr;
387 /* sync_seq is protected by ring emission lock */
388 uint64_t sync_seq[AMDGPU_MAX_RINGS];
389 atomic64_t last_seq;
390 bool initialized;
97b2e202
AD		 391 struct amdgpu_irq_src *irq_src;
392 unsigned irq_type;
393 struct delayed_work lockup_work;
7f06c236 394 wait_queue_head_t fence_queue;
97b2e202
AD		 395};
396
397/* some special values for the owner field */
398#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
399#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
400#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
401
890ee23f
CZ		 402#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
403#define AMDGPU_FENCE_FLAG_INT (1 << 1)
404
97b2e202
AD		 405struct amdgpu_fence {
406 struct fence base;
4cef9267 407
97b2e202
AD		 408 /* RB, DMA, etc. */
409 struct amdgpu_ring *ring;
410 uint64_t seq;
411
412 /* filp or special value for fence creator */
413 void *owner;
414
415 wait_queue_t fence_wake;
416};
417
418struct amdgpu_user_fence {
419 /* write-back bo */
420 struct amdgpu_bo *bo;
421 /* write-back address offset to bo start */
422 uint32_t offset;
423};
424
425int amdgpu_fence_driver_init(struct amdgpu_device *adev);
426void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
427void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
428
429void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
430int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
431 struct amdgpu_irq_src *irq_src,
432 unsigned irq_type);
5ceb54c6
AD		 433void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
434void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 435int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
436 struct amdgpu_fence **fence);
437void amdgpu_fence_process(struct amdgpu_ring *ring);
438int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
439int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
440unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
441
332dfe90 442signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
97b2e202 443 struct amdgpu_fence **fences,
332dfe90 444 bool intr, long t);
97b2e202
AD		 445struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
446void amdgpu_fence_unref(struct amdgpu_fence **fence);
447
448bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
449 struct amdgpu_ring *ring);
450void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452
453static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
454 struct amdgpu_fence *b)
455{
456 if (!a) {
457 return b;
458 }
459
460 if (!b) {
461 return a;
462 }
463
464 BUG_ON(a->ring != b->ring);
465
466 if (a->seq > b->seq) {
467 return a;
468 } else {
469 return b;
470 }
471}
472
473static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
474 struct amdgpu_fence *b)
475{
476 if (!a) {
477 return false;
478 }
479
480 if (!b) {
481 return true;
482 }
483
484 BUG_ON(a->ring != b->ring);
485
486 return a->seq < b->seq;
487}
488
332dfe90 489int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
97b2e202
AD		 490 void *owner, struct amdgpu_fence **fence);
491
492/*
493 * TTM.
494 */
495struct amdgpu_mman {
496 struct ttm_bo_global_ref bo_global_ref;
497 struct drm_global_reference mem_global_ref;
498 struct ttm_bo_device bdev;
499 bool mem_global_referenced;
500 bool initialized;
501
502#if defined(CONFIG_DEBUG_FS)
503 struct dentry *vram;
504 struct dentry *gtt;
505#endif
506
507 /* buffer handling */
508 const struct amdgpu_buffer_funcs *buffer_funcs;
509 struct amdgpu_ring *buffer_funcs_ring;
510};
511
512int amdgpu_copy_buffer(struct amdgpu_ring *ring,
513 uint64_t src_offset,
514 uint64_t dst_offset,
515 uint32_t byte_count,
516 struct reservation_object *resv,
517 struct amdgpu_fence **fence);
518int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
519
520struct amdgpu_bo_list_entry {
521 struct amdgpu_bo *robj;
522 struct ttm_validate_buffer tv;
523 struct amdgpu_bo_va *bo_va;
524 unsigned prefered_domains;
525 unsigned allowed_domains;
526 uint32_t priority;
527};
528
529struct amdgpu_bo_va_mapping {
530 struct list_head list;
531 struct interval_tree_node it;
532 uint64_t offset;
533 uint32_t flags;
534};
535
536/* bo virtual addresses in a specific vm */
537struct amdgpu_bo_va {
538 /* protected by bo being reserved */
539 struct list_head bo_list;
bb1e38a4 540 struct fence *last_pt_update;
97b2e202
AD		 541 unsigned ref_count;
542
7fc11959 543 /* protected by vm mutex and spinlock */
97b2e202
AD		 544 struct list_head vm_status;
545
7fc11959
CK		 546 /* mappings for this bo_va */
547 struct list_head invalids;
548 struct list_head valids;
549
97b2e202
AD		 550 /* constant after initialization */
551 struct amdgpu_vm *vm;
552 struct amdgpu_bo *bo;
553};
554
7e5a547f
CZ		 555#define AMDGPU_GEM_DOMAIN_MAX 0x3
556
97b2e202
AD		 557struct amdgpu_bo {
558 /* Protected by gem.mutex */
559 struct list_head list;
560 /* Protected by tbo.reserved */
561 u32 initial_domain;
7e5a547f 562 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 563 struct ttm_placement placement;
564 struct ttm_buffer_object tbo;
565 struct ttm_bo_kmap_obj kmap;
566 u64 flags;
567 unsigned pin_count;
568 void *kptr;
569 u64 tiling_flags;
570 u64 metadata_flags;
571 void *metadata;
572 u32 metadata_size;
573 /* list of all virtual address to which this bo
574 * is associated to
575 */
576 struct list_head va;
577 /* Constant after initialization */
578 struct amdgpu_device *adev;
579 struct drm_gem_object gem_base;
580
581 struct ttm_bo_kmap_obj dma_buf_vmap;
582 pid_t pid;
583 struct amdgpu_mn *mn;
584 struct list_head mn_list;
585};
586#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
587
588void amdgpu_gem_object_free(struct drm_gem_object *obj);
589int amdgpu_gem_object_open(struct drm_gem_object *obj,
590 struct drm_file *file_priv);
591void amdgpu_gem_object_close(struct drm_gem_object *obj,
592 struct drm_file *file_priv);
593unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
594struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
595struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
596 struct dma_buf_attachment *attach,
597 struct sg_table *sg);
598struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
599 struct drm_gem_object *gobj,
600 int flags);
601int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
602void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
603struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
604void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
605void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
606int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
607
608/* sub-allocation manager, it has to be protected by another lock.
609 * By conception this is an helper for other part of the driver
610 * like the indirect buffer or semaphore, which both have their
611 * locking.
612 *
613 * Principe is simple, we keep a list of sub allocation in offset
614 * order (first entry has offset == 0, last entry has the highest
615 * offset).
616 *
617 * When allocating new object we first check if there is room at
618 * the end total_size - (last_object_offset + last_object_size) >=
619 * alloc_size. If so we allocate new object there.
620 *
621 * When there is not enough room at the end, we start waiting for
622 * each sub object until we reach object_offset+object_size >=
623 * alloc_size, this object then become the sub object we return.
624 *
625 * Alignment can't be bigger than page size.
626 *
627 * Hole are not considered for allocation to keep things simple.
628 * Assumption is that there won't be hole (all object on same
629 * alignment).
630 */
631struct amdgpu_sa_manager {
632 wait_queue_head_t wq;
633 struct amdgpu_bo *bo;
634 struct list_head *hole;
635 struct list_head flist[AMDGPU_MAX_RINGS];
636 struct list_head olist;
637 unsigned size;
638 uint64_t gpu_addr;
639 void *cpu_ptr;
640 uint32_t domain;
641 uint32_t align;
642};
643
644struct amdgpu_sa_bo;
645
646/* sub-allocation buffer */
647struct amdgpu_sa_bo {
648 struct list_head olist;
649 struct list_head flist;
650 struct amdgpu_sa_manager *manager;
651 unsigned soffset;
652 unsigned eoffset;
653 struct amdgpu_fence *fence;
654};
655
656/*
657 * GEM objects.
658 */
659struct amdgpu_gem {
660 struct mutex mutex;
661 struct list_head objects;
662};
663
664int amdgpu_gem_init(struct amdgpu_device *adev);
665void amdgpu_gem_fini(struct amdgpu_device *adev);
666int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
667 int alignment, u32 initial_domain,
668 u64 flags, bool kernel,
669 struct drm_gem_object **obj);
670
671int amdgpu_mode_dumb_create(struct drm_file *file_priv,
672 struct drm_device *dev,
673 struct drm_mode_create_dumb *args);
674int amdgpu_mode_dumb_mmap(struct drm_file *filp,
675 struct drm_device *dev,
676 uint32_t handle, uint64_t *offset_p);
677
678/*
679 * Semaphores.
680 */
681struct amdgpu_semaphore {
682 struct amdgpu_sa_bo *sa_bo;
683 signed waiters;
684 uint64_t gpu_addr;
685};
686
687int amdgpu_semaphore_create(struct amdgpu_device *adev,
688 struct amdgpu_semaphore **semaphore);
689bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
690 struct amdgpu_semaphore *semaphore);
691bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
692 struct amdgpu_semaphore *semaphore);
693void amdgpu_semaphore_free(struct amdgpu_device *adev,
694 struct amdgpu_semaphore **semaphore,
695 struct amdgpu_fence *fence);
696
697/*
698 * Synchronization
699 */
700struct amdgpu_sync {
701 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
702 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
703 struct amdgpu_fence *last_vm_update;
704};
705
706void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 707int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
708 struct fence *f);
97b2e202
AD		 709int amdgpu_sync_resv(struct amdgpu_device *adev,
710 struct amdgpu_sync *sync,
711 struct reservation_object *resv,
712 void *owner);
713int amdgpu_sync_rings(struct amdgpu_sync *sync,
714 struct amdgpu_ring *ring);
715void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
716 struct amdgpu_fence *fence);
717
718/*
719 * GART structures, functions & helpers
720 */
721struct amdgpu_mc;
722
723#define AMDGPU_GPU_PAGE_SIZE 4096
724#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
725#define AMDGPU_GPU_PAGE_SHIFT 12
726#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
727
728struct amdgpu_gart {
729 dma_addr_t table_addr;
730 struct amdgpu_bo *robj;
731 void *ptr;
732 unsigned num_gpu_pages;
733 unsigned num_cpu_pages;
734 unsigned table_size;
735 struct page **pages;
736 dma_addr_t *pages_addr;
737 bool ready;
738 const struct amdgpu_gart_funcs *gart_funcs;
739};
740
741int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
742void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
743int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
744void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
745int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
746void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
747int amdgpu_gart_init(struct amdgpu_device *adev);
748void amdgpu_gart_fini(struct amdgpu_device *adev);
749void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
750 int pages);
751int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
752 int pages, struct page **pagelist,
753 dma_addr_t *dma_addr, uint32_t flags);
754
755/*
756 * GPU MC structures, functions & helpers
757 */
758struct amdgpu_mc {
759 resource_size_t aper_size;
760 resource_size_t aper_base;
761 resource_size_t agp_base;
762 /* for some chips with <= 32MB we need to lie
763 * about vram size near mc fb location */
764 u64 mc_vram_size;
765 u64 visible_vram_size;
766 u64 gtt_size;
767 u64 gtt_start;
768 u64 gtt_end;
769 u64 vram_start;
770 u64 vram_end;
771 unsigned vram_width;
772 u64 real_vram_size;
773 int vram_mtrr;
774 u64 gtt_base_align;
775 u64 mc_mask;
776 const struct firmware *fw; /* MC firmware */
777 uint32_t fw_version;
778 struct amdgpu_irq_src vm_fault;
81c59f54 779 uint32_t vram_type;
97b2e202
AD		 780};
781
782/*
783 * GPU doorbell structures, functions & helpers
784 */
785typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
786{
787 AMDGPU_DOORBELL_KIQ = 0x000,
788 AMDGPU_DOORBELL_HIQ = 0x001,
789 AMDGPU_DOORBELL_DIQ = 0x002,
790 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
791 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
792 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
793 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
794 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
795 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
796 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
797 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
798 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
799 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
800 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
801 AMDGPU_DOORBELL_IH = 0x1E8,
802 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
803 AMDGPU_DOORBELL_INVALID = 0xFFFF
804} AMDGPU_DOORBELL_ASSIGNMENT;
805
806struct amdgpu_doorbell {
807 /* doorbell mmio */
808 resource_size_t base;
809 resource_size_t size;
810 u32 __iomem *ptr;
811 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
812};
813
814void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
815 phys_addr_t *aperture_base,
816 size_t *aperture_size,
817 size_t *start_offset);
818
819/*
820 * IRQS.
821 */
822
823struct amdgpu_flip_work {
824 struct work_struct flip_work;
825 struct work_struct unpin_work;
826 struct amdgpu_device *adev;
827 int crtc_id;
828 uint64_t base;
829 struct drm_pending_vblank_event *event;
830 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 831 struct fence *excl;
832 unsigned shared_count;
833 struct fence **shared;
97b2e202
AD		 834};
835
836
837/*
838 * CP & rings.
839 */
840
841struct amdgpu_ib {
842 struct amdgpu_sa_bo *sa_bo;
843 uint32_t length_dw;
844 uint64_t gpu_addr;
845 uint32_t *ptr;
846 struct amdgpu_ring *ring;
847 struct amdgpu_fence *fence;
848 struct amdgpu_user_fence *user;
849 struct amdgpu_vm *vm;
3cb485f3 850 struct amdgpu_ctx *ctx;
97b2e202 851 struct amdgpu_sync sync;
97b2e202
AD		 852 uint32_t gds_base, gds_size;
853 uint32_t gws_base, gws_size;
854 uint32_t oa_base, oa_size;
de807f81 855 uint32_t flags;
5430a3ff
CK		 856 /* resulting sequence number */
857 uint64_t sequence;
97b2e202
AD		 858};
859
860enum amdgpu_ring_type {
861 AMDGPU_RING_TYPE_GFX,
862 AMDGPU_RING_TYPE_COMPUTE,
863 AMDGPU_RING_TYPE_SDMA,
864 AMDGPU_RING_TYPE_UVD,
865 AMDGPU_RING_TYPE_VCE
866};
867
c1b69ed0
CZ		 868extern struct amd_sched_backend_ops amdgpu_sched_ops;
869
3c704e93
CZ		 870int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
871 struct amdgpu_ring *ring,
872 struct amdgpu_ib *ibs,
873 unsigned num_ibs,
874 int (*free_job)(struct amdgpu_cs_parser *),
1763552e
CZ		 875 void *owner,
876 struct fence **fence);
3c704e93 877
97b2e202
AD		 878struct amdgpu_ring {
879 struct amdgpu_device *adev;
880 const struct amdgpu_ring_funcs *funcs;
881 struct amdgpu_fence_driver fence_drv;
b80d8475 882 struct amd_gpu_scheduler *scheduler;
97b2e202 883
176e1ab1 884 spinlock_t fence_lock;
97b2e202
AD		 885 struct mutex *ring_lock;
886 struct amdgpu_bo *ring_obj;
887 volatile uint32_t *ring;
888 unsigned rptr_offs;
889 u64 next_rptr_gpu_addr;
890 volatile u32 *next_rptr_cpu_addr;
891 unsigned wptr;
892 unsigned wptr_old;
893 unsigned ring_size;
894 unsigned ring_free_dw;
895 int count_dw;
896 atomic_t last_rptr;
897 atomic64_t last_activity;
898 uint64_t gpu_addr;
899 uint32_t align_mask;
900 uint32_t ptr_mask;
901 bool ready;
902 u32 nop;
903 u32 idx;
904 u64 last_semaphore_signal_addr;
905 u64 last_semaphore_wait_addr;
906 u32 me;
907 u32 pipe;
908 u32 queue;
909 struct amdgpu_bo *mqd_obj;
910 u32 doorbell_index;
911 bool use_doorbell;
912 unsigned wptr_offs;
913 unsigned next_rptr_offs;
914 unsigned fence_offs;
3cb485f3 915 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 916 enum amdgpu_ring_type type;
917 char name[16];
4274f5d4 918 bool is_pte_ring;
97b2e202
AD		 919};
920
921/*
922 * VM
923 */
924
925/* maximum number of VMIDs */
926#define AMDGPU_NUM_VM 16
927
928/* number of entries in page table */
929#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
930
931/* PTBs (Page Table Blocks) need to be aligned to 32K */
932#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
933#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
934#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
935
936#define AMDGPU_PTE_VALID (1 << 0)
937#define AMDGPU_PTE_SYSTEM (1 << 1)
938#define AMDGPU_PTE_SNOOPED (1 << 2)
939
940/* VI only */
941#define AMDGPU_PTE_EXECUTABLE (1 << 4)
942
943#define AMDGPU_PTE_READABLE (1 << 5)
944#define AMDGPU_PTE_WRITEABLE (1 << 6)
945
946/* PTE (Page Table Entry) fragment field for different page sizes */
947#define AMDGPU_PTE_FRAG_4KB (0 << 7)
948#define AMDGPU_PTE_FRAG_64KB (4 << 7)
949#define AMDGPU_LOG2_PAGES_PER_FRAG 4
950
951struct amdgpu_vm_pt {
952 struct amdgpu_bo *bo;
953 uint64_t addr;
954};
955
956struct amdgpu_vm_id {
957 unsigned id;
958 uint64_t pd_gpu_addr;
959 /* last flushed PD/PT update */
960 struct amdgpu_fence *flushed_updates;
961 /* last use of vmid */
962 struct amdgpu_fence *last_id_use;
963};
964
965struct amdgpu_vm {
966 struct mutex mutex;
967
968 struct rb_root va;
969
7fc11959 970 /* protecting invalidated */
97b2e202
AD		 971 spinlock_t status_lock;
972
973 /* BOs moved, but not yet updated in the PT */
974 struct list_head invalidated;
975
7fc11959
CK		 976 /* BOs cleared in the PT because of a move */
977 struct list_head cleared;
978
979 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 980 struct list_head freed;
981
982 /* contains the page directory */
983 struct amdgpu_bo *page_directory;
984 unsigned max_pde_used;
05906dec 985 struct fence *page_directory_fence;
97b2e202
AD		 986
987 /* array of page tables, one for each page directory entry */
988 struct amdgpu_vm_pt *page_tables;
989
990 /* for id and flush management per ring */
991 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
992};
993
994struct amdgpu_vm_manager {
995 struct amdgpu_fence *active[AMDGPU_NUM_VM];
996 uint32_t max_pfn;
997 /* number of VMIDs */
998 unsigned nvm;
999 /* vram base address for page table entry */
1000 u64 vram_base_offset;
1001 /* is vm enabled? */
1002 bool enabled;
1003 /* for hw to save the PD addr on suspend/resume */
1004 uint32_t saved_table_addr[AMDGPU_NUM_VM];
1005 /* vm pte handling */
1006 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
1007 struct amdgpu_ring *vm_pte_funcs_ring;
1008};
1009
1010/*
1011 * context related structures
1012 */
1013
21c16bf6
CK		 1014#define AMDGPU_CTX_MAX_CS_PENDING 16
1015
1016struct amdgpu_ctx_ring {
91404fb2
CK		 1017 uint64_t sequence;
1018 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
1019 struct amd_sched_entity entity;
21c16bf6
CK		 1020};
1021
97b2e202 1022struct amdgpu_ctx {
0b492a4c 1023 struct kref refcount;
9cb7e5a9 1024 struct amdgpu_device *adev;
0b492a4c 1025 unsigned reset_counter;
21c16bf6
CK		 1026 spinlock_t ring_lock;
1027 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1028};
1029
1030struct amdgpu_ctx_mgr {
0b492a4c
AD		 1031 struct amdgpu_device *adev;
1032 struct mutex lock;
1033 /* protected by lock */
1034 struct idr ctx_handles;
97b2e202
AD		 1035};
1036
47f38501
CK		 1037int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel,
1038 struct amdgpu_ctx *ctx);
1039void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
0b492a4c 1040
0b492a4c
AD		 1041struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1042int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1043
21c16bf6 1044uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
d1ff9086 1045 struct fence *fence, uint64_t queued_seq);
21c16bf6
CK		 1046struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1047 struct amdgpu_ring *ring, uint64_t seq);
1048
0b492a4c
AD		 1049int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1050 struct drm_file *filp);
1051
efd4ccb5
CK		 1052void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1053void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1054
97b2e202
AD		 1055/*
1056 * file private structure
1057 */
1058
1059struct amdgpu_fpriv {
1060 struct amdgpu_vm vm;
1061 struct mutex bo_list_lock;
1062 struct idr bo_list_handles;
0b492a4c 1063 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1064};
1065
1066/*
1067 * residency list
1068 */
1069
1070struct amdgpu_bo_list {
1071 struct mutex lock;
1072 struct amdgpu_bo *gds_obj;
1073 struct amdgpu_bo *gws_obj;
1074 struct amdgpu_bo *oa_obj;
1075 bool has_userptr;
1076 unsigned num_entries;
1077 struct amdgpu_bo_list_entry *array;
1078};
1079
34cb581a
CK		 1080struct amdgpu_bo_list *
1081amdgpu_bo_list_clone(struct amdgpu_bo_list *list);
97b2e202
AD		 1082struct amdgpu_bo_list *
1083amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1084void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1085void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1086
1087/*
1088 * GFX stuff
1089 */
1090#include "clearstate_defs.h"
1091
1092struct amdgpu_rlc {
1093 /* for power gating */
1094 struct amdgpu_bo *save_restore_obj;
1095 uint64_t save_restore_gpu_addr;
1096 volatile uint32_t *sr_ptr;
1097 const u32 *reg_list;
1098 u32 reg_list_size;
1099 /* for clear state */
1100 struct amdgpu_bo *clear_state_obj;
1101 uint64_t clear_state_gpu_addr;
1102 volatile uint32_t *cs_ptr;
1103 const struct cs_section_def *cs_data;
1104 u32 clear_state_size;
1105 /* for cp tables */
1106 struct amdgpu_bo *cp_table_obj;
1107 uint64_t cp_table_gpu_addr;
1108 volatile uint32_t *cp_table_ptr;
1109 u32 cp_table_size;
1110};
1111
1112struct amdgpu_mec {
1113 struct amdgpu_bo *hpd_eop_obj;
1114 u64 hpd_eop_gpu_addr;
1115 u32 num_pipe;
1116 u32 num_mec;
1117 u32 num_queue;
1118};
1119
1120/*
1121 * GPU scratch registers structures, functions & helpers
1122 */
1123struct amdgpu_scratch {
1124 unsigned num_reg;
1125 uint32_t reg_base;
1126 bool free[32];
1127 uint32_t reg[32];
1128};
1129
1130/*
1131 * GFX configurations
1132 */
1133struct amdgpu_gca_config {
1134 unsigned max_shader_engines;
1135 unsigned max_tile_pipes;
1136 unsigned max_cu_per_sh;
1137 unsigned max_sh_per_se;
1138 unsigned max_backends_per_se;
1139 unsigned max_texture_channel_caches;
1140 unsigned max_gprs;
1141 unsigned max_gs_threads;
1142 unsigned max_hw_contexts;
1143 unsigned sc_prim_fifo_size_frontend;
1144 unsigned sc_prim_fifo_size_backend;
1145 unsigned sc_hiz_tile_fifo_size;
1146 unsigned sc_earlyz_tile_fifo_size;
1147
1148 unsigned num_tile_pipes;
1149 unsigned backend_enable_mask;
1150 unsigned mem_max_burst_length_bytes;
1151 unsigned mem_row_size_in_kb;
1152 unsigned shader_engine_tile_size;
1153 unsigned num_gpus;
1154 unsigned multi_gpu_tile_size;
1155 unsigned mc_arb_ramcfg;
1156 unsigned gb_addr_config;
1157
1158 uint32_t tile_mode_array[32];
1159 uint32_t macrotile_mode_array[16];
1160};
1161
1162struct amdgpu_gfx {
1163 struct mutex gpu_clock_mutex;
1164 struct amdgpu_gca_config config;
1165 struct amdgpu_rlc rlc;
1166 struct amdgpu_mec mec;
1167 struct amdgpu_scratch scratch;
1168 const struct firmware *me_fw; /* ME firmware */
1169 uint32_t me_fw_version;
1170 const struct firmware *pfp_fw; /* PFP firmware */
1171 uint32_t pfp_fw_version;
1172 const struct firmware *ce_fw; /* CE firmware */
1173 uint32_t ce_fw_version;
1174 const struct firmware *rlc_fw; /* RLC firmware */
1175 uint32_t rlc_fw_version;
1176 const struct firmware *mec_fw; /* MEC firmware */
1177 uint32_t mec_fw_version;
1178 const struct firmware *mec2_fw; /* MEC2 firmware */
1179 uint32_t mec2_fw_version;
02558a00
KW		 1180 uint32_t me_feature_version;
1181 uint32_t ce_feature_version;
1182 uint32_t pfp_feature_version;
351643d7
JZ		 1183 uint32_t rlc_feature_version;
1184 uint32_t mec_feature_version;
1185 uint32_t mec2_feature_version;
97b2e202
AD		 1186 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1187 unsigned num_gfx_rings;
1188 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1189 unsigned num_compute_rings;
1190 struct amdgpu_irq_src eop_irq;
1191 struct amdgpu_irq_src priv_reg_irq;
1192 struct amdgpu_irq_src priv_inst_irq;
1193 /* gfx status */
1194 uint32_t gfx_current_status;
1195 /* sync signal for const engine */
1196 unsigned ce_sync_offs;
a101a899
KW		 1197 /* ce ram size*/
1198 unsigned ce_ram_size;
97b2e202
AD		 1199};
1200
1201int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1202 unsigned size, struct amdgpu_ib *ib);
1203void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1204int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1205 struct amdgpu_ib *ib, void *owner);
1206int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1207void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1208int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1209/* Ring access between begin & end cannot sleep */
1210void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1211int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1212int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1213void amdgpu_ring_commit(struct amdgpu_ring *ring);
1214void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1215void amdgpu_ring_undo(struct amdgpu_ring *ring);
1216void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1217void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1218bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1219unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1220 uint32_t **data);
1221int amdgpu_ring_restore(struct amdgpu_ring *ring,
1222 unsigned size, uint32_t *data);
1223int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1224 unsigned ring_size, u32 nop, u32 align_mask,
1225 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1226 enum amdgpu_ring_type ring_type);
1227void amdgpu_ring_fini(struct amdgpu_ring *ring);
1228
1229/*
1230 * CS.
1231 */
1232struct amdgpu_cs_chunk {
1233 uint32_t chunk_id;
1234 uint32_t length_dw;
1235 uint32_t *kdata;
1236 void __user *user_ptr;
1237};
1238
1239struct amdgpu_cs_parser {
1240 struct amdgpu_device *adev;
1241 struct drm_file *filp;
3cb485f3 1242 struct amdgpu_ctx *ctx;
97b2e202
AD		 1243 struct amdgpu_bo_list *bo_list;
1244 /* chunks */
1245 unsigned nchunks;
1246 struct amdgpu_cs_chunk *chunks;
1247 /* relocations */
1248 struct amdgpu_bo_list_entry *vm_bos;
97b2e202
AD		 1249 struct list_head validated;
1250
1251 struct amdgpu_ib *ibs;
1252 uint32_t num_ibs;
1253
1254 struct ww_acquire_ctx ticket;
1255
1256 /* user fence */
1257 struct amdgpu_user_fence uf;
c1b69ed0 1258
4b559c90 1259 struct amdgpu_ring *ring;
c1b69ed0
CZ		 1260 struct mutex job_lock;
1261 struct work_struct job_work;
1262 int (*prepare_job)(struct amdgpu_cs_parser *sched_job);
1263 int (*run_job)(struct amdgpu_cs_parser *sched_job);
049fc527 1264 int (*free_job)(struct amdgpu_cs_parser *sched_job);
f556cb0c 1265 struct amd_sched_fence *s_fence;
97b2e202
AD		 1266};
1267
1268static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1269{
1270 return p->ibs[ib_idx].ptr[idx];
1271}
1272
1273/*
1274 * Writeback
1275 */
1276#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1277
1278struct amdgpu_wb {
1279 struct amdgpu_bo *wb_obj;
1280 volatile uint32_t *wb;
1281 uint64_t gpu_addr;
1282 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1283 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1284};
1285
1286int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1287void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1288
1289/**
1290 * struct amdgpu_pm - power management datas
1291 * It keeps track of various data needed to take powermanagement decision.
1292 */
1293
1294enum amdgpu_pm_state_type {
1295 /* not used for dpm */
1296 POWER_STATE_TYPE_DEFAULT,
1297 POWER_STATE_TYPE_POWERSAVE,
1298 /* user selectable states */
1299 POWER_STATE_TYPE_BATTERY,
1300 POWER_STATE_TYPE_BALANCED,
1301 POWER_STATE_TYPE_PERFORMANCE,
1302 /* internal states */
1303 POWER_STATE_TYPE_INTERNAL_UVD,
1304 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1305 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1306 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1307 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1308 POWER_STATE_TYPE_INTERNAL_BOOT,
1309 POWER_STATE_TYPE_INTERNAL_THERMAL,
1310 POWER_STATE_TYPE_INTERNAL_ACPI,
1311 POWER_STATE_TYPE_INTERNAL_ULV,
1312 POWER_STATE_TYPE_INTERNAL_3DPERF,
1313};
1314
1315enum amdgpu_int_thermal_type {
1316 THERMAL_TYPE_NONE,
1317 THERMAL_TYPE_EXTERNAL,
1318 THERMAL_TYPE_EXTERNAL_GPIO,
1319 THERMAL_TYPE_RV6XX,
1320 THERMAL_TYPE_RV770,
1321 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1322 THERMAL_TYPE_EVERGREEN,
1323 THERMAL_TYPE_SUMO,
1324 THERMAL_TYPE_NI,
1325 THERMAL_TYPE_SI,
1326 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1327 THERMAL_TYPE_CI,
1328 THERMAL_TYPE_KV,
1329};
1330
1331enum amdgpu_dpm_auto_throttle_src {
1332 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1333 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1334};
1335
1336enum amdgpu_dpm_event_src {
1337 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1338 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1339 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1340 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1341 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1342};
1343
1344#define AMDGPU_MAX_VCE_LEVELS 6
1345
1346enum amdgpu_vce_level {
1347 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1348 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1349 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1350 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1351 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1352 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1353};
1354
1355struct amdgpu_ps {
1356 u32 caps; /* vbios flags */
1357 u32 class; /* vbios flags */
1358 u32 class2; /* vbios flags */
1359 /* UVD clocks */
1360 u32 vclk;
1361 u32 dclk;
1362 /* VCE clocks */
1363 u32 evclk;
1364 u32 ecclk;
1365 bool vce_active;
1366 enum amdgpu_vce_level vce_level;
1367 /* asic priv */
1368 void *ps_priv;
1369};
1370
1371struct amdgpu_dpm_thermal {
1372 /* thermal interrupt work */
1373 struct work_struct work;
1374 /* low temperature threshold */
1375 int min_temp;
1376 /* high temperature threshold */
1377 int max_temp;
1378 /* was last interrupt low to high or high to low */
1379 bool high_to_low;
1380 /* interrupt source */
1381 struct amdgpu_irq_src irq;
1382};
1383
1384enum amdgpu_clk_action
1385{
1386 AMDGPU_SCLK_UP = 1,
1387 AMDGPU_SCLK_DOWN
1388};
1389
1390struct amdgpu_blacklist_clocks
1391{
1392 u32 sclk;
1393 u32 mclk;
1394 enum amdgpu_clk_action action;
1395};
1396
1397struct amdgpu_clock_and_voltage_limits {
1398 u32 sclk;
1399 u32 mclk;
1400 u16 vddc;
1401 u16 vddci;
1402};
1403
1404struct amdgpu_clock_array {
1405 u32 count;
1406 u32 *values;
1407};
1408
1409struct amdgpu_clock_voltage_dependency_entry {
1410 u32 clk;
1411 u16 v;
1412};
1413
1414struct amdgpu_clock_voltage_dependency_table {
1415 u32 count;
1416 struct amdgpu_clock_voltage_dependency_entry *entries;
1417};
1418
1419union amdgpu_cac_leakage_entry {
1420 struct {
1421 u16 vddc;
1422 u32 leakage;
1423 };
1424 struct {
1425 u16 vddc1;
1426 u16 vddc2;
1427 u16 vddc3;
1428 };
1429};
1430
1431struct amdgpu_cac_leakage_table {
1432 u32 count;
1433 union amdgpu_cac_leakage_entry *entries;
1434};
1435
1436struct amdgpu_phase_shedding_limits_entry {
1437 u16 voltage;
1438 u32 sclk;
1439 u32 mclk;
1440};
1441
1442struct amdgpu_phase_shedding_limits_table {
1443 u32 count;
1444 struct amdgpu_phase_shedding_limits_entry *entries;
1445};
1446
1447struct amdgpu_uvd_clock_voltage_dependency_entry {
1448 u32 vclk;
1449 u32 dclk;
1450 u16 v;
1451};
1452
1453struct amdgpu_uvd_clock_voltage_dependency_table {
1454 u8 count;
1455 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1456};
1457
1458struct amdgpu_vce_clock_voltage_dependency_entry {
1459 u32 ecclk;
1460 u32 evclk;
1461 u16 v;
1462};
1463
1464struct amdgpu_vce_clock_voltage_dependency_table {
1465 u8 count;
1466 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1467};
1468
1469struct amdgpu_ppm_table {
1470 u8 ppm_design;
1471 u16 cpu_core_number;
1472 u32 platform_tdp;
1473 u32 small_ac_platform_tdp;
1474 u32 platform_tdc;
1475 u32 small_ac_platform_tdc;
1476 u32 apu_tdp;
1477 u32 dgpu_tdp;
1478 u32 dgpu_ulv_power;
1479 u32 tj_max;
1480};
1481
1482struct amdgpu_cac_tdp_table {
1483 u16 tdp;
1484 u16 configurable_tdp;
1485 u16 tdc;
1486 u16 battery_power_limit;
1487 u16 small_power_limit;
1488 u16 low_cac_leakage;
1489 u16 high_cac_leakage;
1490 u16 maximum_power_delivery_limit;
1491};
1492
1493struct amdgpu_dpm_dynamic_state {
1494 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1495 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1496 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1497 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1498 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1499 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1500 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1501 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1502 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1503 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1504 struct amdgpu_clock_array valid_sclk_values;
1505 struct amdgpu_clock_array valid_mclk_values;
1506 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1507 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1508 u32 mclk_sclk_ratio;
1509 u32 sclk_mclk_delta;
1510 u16 vddc_vddci_delta;
1511 u16 min_vddc_for_pcie_gen2;
1512 struct amdgpu_cac_leakage_table cac_leakage_table;
1513 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1514 struct amdgpu_ppm_table *ppm_table;
1515 struct amdgpu_cac_tdp_table *cac_tdp_table;
1516};
1517
1518struct amdgpu_dpm_fan {
1519 u16 t_min;
1520 u16 t_med;
1521 u16 t_high;
1522 u16 pwm_min;
1523 u16 pwm_med;
1524 u16 pwm_high;
1525 u8 t_hyst;
1526 u32 cycle_delay;
1527 u16 t_max;
1528 u8 control_mode;
1529 u16 default_max_fan_pwm;
1530 u16 default_fan_output_sensitivity;
1531 u16 fan_output_sensitivity;
1532 bool ucode_fan_control;
1533};
1534
1535enum amdgpu_pcie_gen {
1536 AMDGPU_PCIE_GEN1 = 0,
1537 AMDGPU_PCIE_GEN2 = 1,
1538 AMDGPU_PCIE_GEN3 = 2,
1539 AMDGPU_PCIE_GEN_INVALID = 0xffff
1540};
1541
1542enum amdgpu_dpm_forced_level {
1543 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1544 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1545 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1546};
1547
1548struct amdgpu_vce_state {
1549 /* vce clocks */
1550 u32 evclk;
1551 u32 ecclk;
1552 /* gpu clocks */
1553 u32 sclk;
1554 u32 mclk;
1555 u8 clk_idx;
1556 u8 pstate;
1557};
1558
1559struct amdgpu_dpm_funcs {
1560 int (*get_temperature)(struct amdgpu_device *adev);
1561 int (*pre_set_power_state)(struct amdgpu_device *adev);
1562 int (*set_power_state)(struct amdgpu_device *adev);
1563 void (*post_set_power_state)(struct amdgpu_device *adev);
1564 void (*display_configuration_changed)(struct amdgpu_device *adev);
1565 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1566 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1567 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1568 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1569 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1570 bool (*vblank_too_short)(struct amdgpu_device *adev);
1571 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1572 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1573 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1574 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1575 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1576 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1577 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1578};
1579
1580struct amdgpu_dpm {
1581 struct amdgpu_ps *ps;
1582 /* number of valid power states */
1583 int num_ps;
1584 /* current power state that is active */
1585 struct amdgpu_ps *current_ps;
1586 /* requested power state */
1587 struct amdgpu_ps *requested_ps;
1588 /* boot up power state */
1589 struct amdgpu_ps *boot_ps;
1590 /* default uvd power state */
1591 struct amdgpu_ps *uvd_ps;
1592 /* vce requirements */
1593 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1594 enum amdgpu_vce_level vce_level;
1595 enum amdgpu_pm_state_type state;
1596 enum amdgpu_pm_state_type user_state;
1597 u32 platform_caps;
1598 u32 voltage_response_time;
1599 u32 backbias_response_time;
1600 void *priv;
1601 u32 new_active_crtcs;
1602 int new_active_crtc_count;
1603 u32 current_active_crtcs;
1604 int current_active_crtc_count;
1605 struct amdgpu_dpm_dynamic_state dyn_state;
1606 struct amdgpu_dpm_fan fan;
1607 u32 tdp_limit;
1608 u32 near_tdp_limit;
1609 u32 near_tdp_limit_adjusted;
1610 u32 sq_ramping_threshold;
1611 u32 cac_leakage;
1612 u16 tdp_od_limit;
1613 u32 tdp_adjustment;
1614 u16 load_line_slope;
1615 bool power_control;
1616 bool ac_power;
1617 /* special states active */
1618 bool thermal_active;
1619 bool uvd_active;
1620 bool vce_active;
1621 /* thermal handling */
1622 struct amdgpu_dpm_thermal thermal;
1623 /* forced levels */
1624 enum amdgpu_dpm_forced_level forced_level;
1625};
1626
1627struct amdgpu_pm {
1628 struct mutex mutex;
97b2e202
AD		 1629 u32 current_sclk;
1630 u32 current_mclk;
1631 u32 default_sclk;
1632 u32 default_mclk;
1633 struct amdgpu_i2c_chan *i2c_bus;
1634 /* internal thermal controller on rv6xx+ */
1635 enum amdgpu_int_thermal_type int_thermal_type;
1636 struct device *int_hwmon_dev;
1637 /* fan control parameters */
1638 bool no_fan;
1639 u8 fan_pulses_per_revolution;
1640 u8 fan_min_rpm;
1641 u8 fan_max_rpm;
1642 /* dpm */
1643 bool dpm_enabled;
1644 struct amdgpu_dpm dpm;
1645 const struct firmware *fw; /* SMC firmware */
1646 uint32_t fw_version;
1647 const struct amdgpu_dpm_funcs *funcs;
1648};
1649
1650/*
1651 * UVD
1652 */
1653#define AMDGPU_MAX_UVD_HANDLES 10
1654#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1655#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1656#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1657
1658struct amdgpu_uvd {
1659 struct amdgpu_bo *vcpu_bo;
1660 void *cpu_addr;
1661 uint64_t gpu_addr;
1662 void *saved_bo;
1663 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1664 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1665 struct delayed_work idle_work;
1666 const struct firmware *fw; /* UVD firmware */
1667 struct amdgpu_ring ring;
1668 struct amdgpu_irq_src irq;
1669 bool address_64_bit;
1670};
1671
1672/*
1673 * VCE
1674 */
1675#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1676#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1677
6a585777
AD		 1678#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1679#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1680
97b2e202
AD		 1681struct amdgpu_vce {
1682 struct amdgpu_bo *vcpu_bo;
1683 uint64_t gpu_addr;
1684 unsigned fw_version;
1685 unsigned fb_version;
1686 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1687 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1688 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1689 struct delayed_work idle_work;
1690 const struct firmware *fw; /* VCE firmware */
1691 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1692 struct amdgpu_irq_src irq;
6a585777 1693 unsigned harvest_config;
97b2e202
AD		 1694};
1695
1696/*
1697 * SDMA
1698 */
1699struct amdgpu_sdma {
1700 /* SDMA firmware */
1701 const struct firmware *fw;
1702 uint32_t fw_version;
cfa2104f 1703 uint32_t feature_version;
97b2e202
AD		 1704
1705 struct amdgpu_ring ring;
1706};
1707
1708/*
1709 * Firmware
1710 */
1711struct amdgpu_firmware {
1712 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1713 bool smu_load;
1714 struct amdgpu_bo *fw_buf;
1715 unsigned int fw_size;
1716};
1717
1718/*
1719 * Benchmarking
1720 */
1721void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1722
1723
1724/*
1725 * Testing
1726 */
1727void amdgpu_test_moves(struct amdgpu_device *adev);
1728void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1729 struct amdgpu_ring *cpA,
1730 struct amdgpu_ring *cpB);
1731void amdgpu_test_syncing(struct amdgpu_device *adev);
1732
1733/*
1734 * MMU Notifier
1735 */
1736#if defined(CONFIG_MMU_NOTIFIER)
1737int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1738void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1739#else
1740static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1741{
1742 return -ENODEV;
1743}
1744static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1745#endif
1746
1747/*
1748 * Debugfs
1749 */
1750struct amdgpu_debugfs {
1751 struct drm_info_list *files;
1752 unsigned num_files;
1753};
1754
1755int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1756 struct drm_info_list *files,
1757 unsigned nfiles);
1758int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1759
1760#if defined(CONFIG_DEBUG_FS)
1761int amdgpu_debugfs_init(struct drm_minor *minor);
1762void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1763#endif
1764
1765/*
1766 * amdgpu smumgr functions
1767 */
1768struct amdgpu_smumgr_funcs {
1769 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1770 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1771 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1772};
1773
1774/*
1775 * amdgpu smumgr
1776 */
1777struct amdgpu_smumgr {
1778 struct amdgpu_bo *toc_buf;
1779 struct amdgpu_bo *smu_buf;
1780 /* asic priv smu data */
1781 void *priv;
1782 spinlock_t smu_lock;
1783 /* smumgr functions */
1784 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1785 /* ucode loading complete flag */
1786 uint32_t fw_flags;
1787};
1788
1789/*
1790 * ASIC specific register table accessible by UMD
1791 */
1792struct amdgpu_allowed_register_entry {
1793 uint32_t reg_offset;
1794 bool untouched;
1795 bool grbm_indexed;
1796};
1797
1798struct amdgpu_cu_info {
1799 uint32_t number; /* total active CU number */
1800 uint32_t ao_cu_mask;
1801 uint32_t bitmap[4][4];
1802};
1803
1804
1805/*
1806 * ASIC specific functions.
1807 */
1808struct amdgpu_asic_funcs {
1809 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1810 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1811 u32 sh_num, u32 reg_offset, u32 *value);
1812 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1813 int (*reset)(struct amdgpu_device *adev);
1814 /* wait for mc_idle */
1815 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1816 /* get the reference clock */
1817 u32 (*get_xclk)(struct amdgpu_device *adev);
1818 /* get the gpu clock counter */
1819 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1820 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1821 /* MM block clocks */
1822 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1823 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1824};
1825
1826/*
1827 * IOCTL.
1828 */
1829int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1830 struct drm_file *filp);
1831int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1832 struct drm_file *filp);
1833
1834int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1835 struct drm_file *filp);
1836int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1837 struct drm_file *filp);
1838int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1839 struct drm_file *filp);
1840int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1841 struct drm_file *filp);
1842int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *filp);
1844int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1845 struct drm_file *filp);
1846int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1847int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1848
1849int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1851
1852/* VRAM scratch page for HDP bug, default vram page */
1853struct amdgpu_vram_scratch {
1854 struct amdgpu_bo *robj;
1855 volatile uint32_t *ptr;
1856 u64 gpu_addr;
1857};
1858
1859/*
1860 * ACPI
1861 */
1862struct amdgpu_atif_notification_cfg {
1863 bool enabled;
1864 int command_code;
1865};
1866
1867struct amdgpu_atif_notifications {
1868 bool display_switch;
1869 bool expansion_mode_change;
1870 bool thermal_state;
1871 bool forced_power_state;
1872 bool system_power_state;
1873 bool display_conf_change;
1874 bool px_gfx_switch;
1875 bool brightness_change;
1876 bool dgpu_display_event;
1877};
1878
1879struct amdgpu_atif_functions {
1880 bool system_params;
1881 bool sbios_requests;
1882 bool select_active_disp;
1883 bool lid_state;
1884 bool get_tv_standard;
1885 bool set_tv_standard;
1886 bool get_panel_expansion_mode;
1887 bool set_panel_expansion_mode;
1888 bool temperature_change;
1889 bool graphics_device_types;
1890};
1891
1892struct amdgpu_atif {
1893 struct amdgpu_atif_notifications notifications;
1894 struct amdgpu_atif_functions functions;
1895 struct amdgpu_atif_notification_cfg notification_cfg;
1896 struct amdgpu_encoder *encoder_for_bl;
1897};
1898
1899struct amdgpu_atcs_functions {
1900 bool get_ext_state;
1901 bool pcie_perf_req;
1902 bool pcie_dev_rdy;
1903 bool pcie_bus_width;
1904};
1905
1906struct amdgpu_atcs {
1907 struct amdgpu_atcs_functions functions;
1908};
1909
d03846af
CZ		 1910/*
1911 * CGS
1912 */
1913void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1914void amdgpu_cgs_destroy_device(void *cgs_device);
1915
1916
97b2e202
AD		 1917/*
1918 * Core structure, functions and helpers.
1919 */
1920typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1921typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1922
1923typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1924typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1925
8faf0e08
AD		 1926struct amdgpu_ip_block_status {
1927 bool valid;
1928 bool sw;
1929 bool hw;
1930};
1931
97b2e202
AD		 1932struct amdgpu_device {
1933 struct device *dev;
1934 struct drm_device *ddev;
1935 struct pci_dev *pdev;
1936 struct rw_semaphore exclusive_lock;
1937
1938 /* ASIC */
2f7d10b3 1939 enum amd_asic_type asic_type;
97b2e202
AD		 1940 uint32_t family;
1941 uint32_t rev_id;
1942 uint32_t external_rev_id;
1943 unsigned long flags;
1944 int usec_timeout;
1945 const struct amdgpu_asic_funcs *asic_funcs;
1946 bool shutdown;
1947 bool suspend;
1948 bool need_dma32;
1949 bool accel_working;
1950 bool needs_reset;
1951 struct work_struct reset_work;
1952 struct notifier_block acpi_nb;
1953 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1954 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1955 unsigned debugfs_count;
1956#if defined(CONFIG_DEBUG_FS)
1957 struct dentry *debugfs_regs;
1958#endif
1959 struct amdgpu_atif atif;
1960 struct amdgpu_atcs atcs;
1961 struct mutex srbm_mutex;
1962 /* GRBM index mutex. Protects concurrent access to GRBM index */
1963 struct mutex grbm_idx_mutex;
1964 struct dev_pm_domain vga_pm_domain;
1965 bool have_disp_power_ref;
1966
1967 /* BIOS */
1968 uint8_t *bios;
1969 bool is_atom_bios;
1970 uint16_t bios_header_start;
1971 struct amdgpu_bo *stollen_vga_memory;
1972 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1973
1974 /* Register/doorbell mmio */
1975 resource_size_t rmmio_base;
1976 resource_size_t rmmio_size;
1977 void __iomem *rmmio;
1978 /* protects concurrent MM_INDEX/DATA based register access */
1979 spinlock_t mmio_idx_lock;
1980 /* protects concurrent SMC based register access */
1981 spinlock_t smc_idx_lock;
1982 amdgpu_rreg_t smc_rreg;
1983 amdgpu_wreg_t smc_wreg;
1984 /* protects concurrent PCIE register access */
1985 spinlock_t pcie_idx_lock;
1986 amdgpu_rreg_t pcie_rreg;
1987 amdgpu_wreg_t pcie_wreg;
1988 /* protects concurrent UVD register access */
1989 spinlock_t uvd_ctx_idx_lock;
1990 amdgpu_rreg_t uvd_ctx_rreg;
1991 amdgpu_wreg_t uvd_ctx_wreg;
1992 /* protects concurrent DIDT register access */
1993 spinlock_t didt_idx_lock;
1994 amdgpu_rreg_t didt_rreg;
1995 amdgpu_wreg_t didt_wreg;
1996 /* protects concurrent ENDPOINT (audio) register access */
1997 spinlock_t audio_endpt_idx_lock;
1998 amdgpu_block_rreg_t audio_endpt_rreg;
1999 amdgpu_block_wreg_t audio_endpt_wreg;
2000 void __iomem *rio_mem;
2001 resource_size_t rio_mem_size;
2002 struct amdgpu_doorbell doorbell;
2003
2004 /* clock/pll info */
2005 struct amdgpu_clock clock;
2006
2007 /* MC */
2008 struct amdgpu_mc mc;
2009 struct amdgpu_gart gart;
2010 struct amdgpu_dummy_page dummy_page;
2011 struct amdgpu_vm_manager vm_manager;
2012
2013 /* memory management */
2014 struct amdgpu_mman mman;
2015 struct amdgpu_gem gem;
2016 struct amdgpu_vram_scratch vram_scratch;
2017 struct amdgpu_wb wb;
2018 atomic64_t vram_usage;
2019 atomic64_t vram_vis_usage;
2020 atomic64_t gtt_usage;
2021 atomic64_t num_bytes_moved;
d94aed5a 2022 atomic_t gpu_reset_counter;
97b2e202
AD		 2023
2024 /* display */
2025 struct amdgpu_mode_info mode_info;
2026 struct work_struct hotplug_work;
2027 struct amdgpu_irq_src crtc_irq;
2028 struct amdgpu_irq_src pageflip_irq;
2029 struct amdgpu_irq_src hpd_irq;
2030
2031 /* rings */
97b2e202
AD		 2032 unsigned fence_context;
2033 struct mutex ring_lock;
2034 unsigned num_rings;
2035 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2036 bool ib_pool_ready;
2037 struct amdgpu_sa_manager ring_tmp_bo;
2038
2039 /* interrupts */
2040 struct amdgpu_irq irq;
2041
2042 /* dpm */
2043 struct amdgpu_pm pm;
2044 u32 cg_flags;
2045 u32 pg_flags;
2046
2047 /* amdgpu smumgr */
2048 struct amdgpu_smumgr smu;
2049
2050 /* gfx */
2051 struct amdgpu_gfx gfx;
2052
2053 /* sdma */
2054 struct amdgpu_sdma sdma[2];
2055 struct amdgpu_irq_src sdma_trap_irq;
2056 struct amdgpu_irq_src sdma_illegal_inst_irq;
2057
2058 /* uvd */
2059 bool has_uvd;
2060 struct amdgpu_uvd uvd;
2061
2062 /* vce */
2063 struct amdgpu_vce vce;
2064
2065 /* firmwares */
2066 struct amdgpu_firmware firmware;
2067
2068 /* GDS */
2069 struct amdgpu_gds gds;
2070
2071 const struct amdgpu_ip_block_version *ip_blocks;
2072 int num_ip_blocks;
8faf0e08 2073 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2074 struct mutex mn_lock;
2075 DECLARE_HASHTABLE(mn_hash, 7);
2076
2077 /* tracking pinned memory */
2078 u64 vram_pin_size;
2079 u64 gart_pin_size;
130e0371
OG		 2080
2081 /* amdkfd interface */
2082 struct kfd_dev *kfd;
23ca0e4e
CZ		 2083
2084 /* kernel conext for IB submission */
47f38501 2085 struct amdgpu_ctx kernel_ctx;
97b2e202
AD		 2086};
2087
2088bool amdgpu_device_is_px(struct drm_device *dev);
2089int amdgpu_device_init(struct amdgpu_device *adev,
2090 struct drm_device *ddev,
2091 struct pci_dev *pdev,
2092 uint32_t flags);
2093void amdgpu_device_fini(struct amdgpu_device *adev);
2094int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2095
2096uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2097 bool always_indirect);
2098void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2099 bool always_indirect);
2100u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2101void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2102
2103u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2104void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2105
2106/*
2107 * Cast helper
2108 */
2109extern const struct fence_ops amdgpu_fence_ops;
2110static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2111{
2112 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2113
2114 if (__f->base.ops == &amdgpu_fence_ops)
2115 return __f;
2116
2117 return NULL;
2118}
2119
2120/*
2121 * Registers read & write functions.
2122 */
2123#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2124#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2125#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2126#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2127#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2128#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2129#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2130#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2131#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2132#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2133#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2134#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2135#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2136#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2137#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2138#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2139#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2140#define WREG32_P(reg, val, mask) \
2141 do { \
2142 uint32_t tmp_ = RREG32(reg); \
2143 tmp_ &= (mask); \
2144 tmp_ |= ((val) & ~(mask)); \
2145 WREG32(reg, tmp_); \
2146 } while (0)
2147#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2148#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2149#define WREG32_PLL_P(reg, val, mask) \
2150 do { \
2151 uint32_t tmp_ = RREG32_PLL(reg); \
2152 tmp_ &= (mask); \
2153 tmp_ |= ((val) & ~(mask)); \
2154 WREG32_PLL(reg, tmp_); \
2155 } while (0)
2156#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2157#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2158#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2159
2160#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2161#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2162
2163#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2164#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2165
2166#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2167 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2168 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2169
2170#define REG_GET_FIELD(value, reg, field) \
2171 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2172
2173/*
2174 * BIOS helpers.
2175 */
2176#define RBIOS8(i) (adev->bios[i])
2177#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2178#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2179
2180/*
2181 * RING helpers.
2182 */
2183static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2184{
2185 if (ring->count_dw <= 0)
86c2b790 2186 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2187 ring->ring[ring->wptr++] = v;
2188 ring->wptr &= ring->ptr_mask;
2189 ring->count_dw--;
2190 ring->ring_free_dw--;
2191}
2192
2193/*
2194 * ASICs macro.
2195 */
2196#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2197#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2198#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2199#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2200#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2201#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2202#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2203#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2204#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2205#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2206#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2207#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2208#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2209#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2210#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2211#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2212#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2213#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2214#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2215#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2216#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2217#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2218#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2219#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2220#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2221#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2222#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2223#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2224#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2225#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2226#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2227#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2228#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2229#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2230#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2231#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2232#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2233#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2234#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2235#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2236#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2237#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2238#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2239#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2240#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2241#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2242#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2243#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2244#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2245#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2246#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2247#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2248#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2249#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2250#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2251#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2252#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2253#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2254#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2255#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2256#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2257#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
b7a07769 2258#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
97b2e202
AD		 2259#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2260#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2261#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2262#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2263#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2264
2265#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2266
2267/* Common functions */
2268int amdgpu_gpu_reset(struct amdgpu_device *adev);
2269void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2270bool amdgpu_card_posted(struct amdgpu_device *adev);
2271void amdgpu_update_display_priority(struct amdgpu_device *adev);
2272bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82
CZ		 2273struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
2274 struct drm_file *filp,
2275 struct amdgpu_ctx *ctx,
2276 struct amdgpu_ib *ibs,
2277 uint32_t num_ibs);
2278
97b2e202
AD		 2279int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2280int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2281 u32 ip_instance, u32 ring,
2282 struct amdgpu_ring **out_ring);
2283void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2284bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2285int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2286 uint32_t flags);
2287bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2288bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2289uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2290 struct ttm_mem_reg *mem);
2291void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2292void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2293void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2294void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2295 const u32 *registers,
2296 const u32 array_size);
2297
2298bool amdgpu_device_is_px(struct drm_device *dev);
2299/* atpx handler */
2300#if defined(CONFIG_VGA_SWITCHEROO)
2301void amdgpu_register_atpx_handler(void);
2302void amdgpu_unregister_atpx_handler(void);
2303#else
2304static inline void amdgpu_register_atpx_handler(void) {}
2305static inline void amdgpu_unregister_atpx_handler(void) {}
2306#endif
2307
2308/*
2309 * KMS
2310 */
2311extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2312extern int amdgpu_max_kms_ioctl;
2313
2314int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2315int amdgpu_driver_unload_kms(struct drm_device *dev);
2316void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2317int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2318void amdgpu_driver_postclose_kms(struct drm_device *dev,
2319 struct drm_file *file_priv);
2320void amdgpu_driver_preclose_kms(struct drm_device *dev,
2321 struct drm_file *file_priv);
2322int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2323int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2324u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2325int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2326void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2327int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2328 int *max_error,
2329 struct timeval *vblank_time,
2330 unsigned flags);
2331long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2332 unsigned long arg);
2333
2334/*
2335 * vm
2336 */
2337int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2338void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2339struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2340 struct amdgpu_vm *vm,
2341 struct list_head *head);
7f8a5290
CK		 2342int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2343 struct amdgpu_sync *sync);
97b2e202
AD		 2344void amdgpu_vm_flush(struct amdgpu_ring *ring,
2345 struct amdgpu_vm *vm,
2346 struct amdgpu_fence *updates);
2347void amdgpu_vm_fence(struct amdgpu_device *adev,
2348 struct amdgpu_vm *vm,
2349 struct amdgpu_fence *fence);
2350uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2351int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2352 struct amdgpu_vm *vm);
2353int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2354 struct amdgpu_vm *vm);
2355int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
cfe2c978 2356 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
97b2e202
AD		 2357int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2358 struct amdgpu_bo_va *bo_va,
2359 struct ttm_mem_reg *mem);
2360void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2361 struct amdgpu_bo *bo);
2362struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2363 struct amdgpu_bo *bo);
2364struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2365 struct amdgpu_vm *vm,
2366 struct amdgpu_bo *bo);
2367int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2368 struct amdgpu_bo_va *bo_va,
2369 uint64_t addr, uint64_t offset,
2370 uint64_t size, uint32_t flags);
2371int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2372 struct amdgpu_bo_va *bo_va,
2373 uint64_t addr);
2374void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2375 struct amdgpu_bo_va *bo_va);
2376
2377/*
2378 * functions used by amdgpu_encoder.c
2379 */
2380struct amdgpu_afmt_acr {
2381 u32 clock;
2382
2383 int n_32khz;
2384 int cts_32khz;
2385
2386 int n_44_1khz;
2387 int cts_44_1khz;
2388
2389 int n_48khz;
2390 int cts_48khz;
2391
2392};
2393
2394struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2395
2396/* amdgpu_acpi.c */
2397#if defined(CONFIG_ACPI)
2398int amdgpu_acpi_init(struct amdgpu_device *adev);
2399void amdgpu_acpi_fini(struct amdgpu_device *adev);
2400bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2401int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2402 u8 perf_req, bool advertise);
2403int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2404#else
2405static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2406static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2407#endif
2408
2409struct amdgpu_bo_va_mapping *
2410amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2411 uint64_t addr, struct amdgpu_bo **bo);
2412
2413#include "amdgpu_object.h"
2414
2415#endif
Linux kernel - Deliverables
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