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drm/amdgpu: cleanup bo list bucket handling
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
97b2e202 56
b80d8475
AD		 57#include "gpu_scheduler.h"
58
97b2e202
AD		 59/*
60 * Modules parameters.
61 */
62extern int amdgpu_modeset;
63extern int amdgpu_vram_limit;
64extern int amdgpu_gart_size;
65extern int amdgpu_benchmarking;
66extern int amdgpu_testing;
67extern int amdgpu_audio;
68extern int amdgpu_disp_priority;
69extern int amdgpu_hw_i2c;
70extern int amdgpu_pcie_gen2;
71extern int amdgpu_msi;
72extern int amdgpu_lockup_timeout;
73extern int amdgpu_dpm;
74extern int amdgpu_smc_load_fw;
75extern int amdgpu_aspm;
76extern int amdgpu_runtime_pm;
77extern int amdgpu_hard_reset;
78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
b80d8475 85extern int amdgpu_enable_scheduler;
1333f723 86extern int amdgpu_sched_jobs;
4afcb303 87extern int amdgpu_sched_hw_submission;
3daea9e3 88extern int amdgpu_enable_semaphores;
1f7371b2 89extern int amdgpu_powerplay;
97b2e202 90
4b559c90 91#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 92#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95#define AMDGPU_IB_POOL_SIZE 16
96#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97#define AMDGPUFB_CONN_LIMIT 4
98#define AMDGPU_BIOS_NUM_SCRATCH 8
99
97b2e202
AD		 100/* max number of rings */
101#define AMDGPU_MAX_RINGS 16
102#define AMDGPU_MAX_GFX_RINGS 1
103#define AMDGPU_MAX_COMPUTE_RINGS 8
104#define AMDGPU_MAX_VCE_RINGS 2
105
36f523a7
JZ		 106/* max number of IP instances */
107#define AMDGPU_MAX_SDMA_INSTANCES 2
108
97b2e202
AD		 109/* number of hw syncs before falling back on blocking */
110#define AMDGPU_NUM_SYNCS 4
111
112/* hardcode that limit for now */
113#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
114
115/* hard reset data */
116#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
117
118/* reset flags */
119#define AMDGPU_RESET_GFX (1 << 0)
120#define AMDGPU_RESET_COMPUTE (1 << 1)
121#define AMDGPU_RESET_DMA (1 << 2)
122#define AMDGPU_RESET_CP (1 << 3)
123#define AMDGPU_RESET_GRBM (1 << 4)
124#define AMDGPU_RESET_DMA1 (1 << 5)
125#define AMDGPU_RESET_RLC (1 << 6)
126#define AMDGPU_RESET_SEM (1 << 7)
127#define AMDGPU_RESET_IH (1 << 8)
128#define AMDGPU_RESET_VMC (1 << 9)
129#define AMDGPU_RESET_MC (1 << 10)
130#define AMDGPU_RESET_DISPLAY (1 << 11)
131#define AMDGPU_RESET_UVD (1 << 12)
132#define AMDGPU_RESET_VCE (1 << 13)
133#define AMDGPU_RESET_VCE1 (1 << 14)
134
135/* CG block flags */
136#define AMDGPU_CG_BLOCK_GFX (1 << 0)
137#define AMDGPU_CG_BLOCK_MC (1 << 1)
138#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
139#define AMDGPU_CG_BLOCK_UVD (1 << 3)
140#define AMDGPU_CG_BLOCK_VCE (1 << 4)
141#define AMDGPU_CG_BLOCK_HDP (1 << 5)
142#define AMDGPU_CG_BLOCK_BIF (1 << 6)
143
144/* CG flags */
145#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
146#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
147#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
148#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
149#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
150#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
151#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
152#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
153#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
154#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
155#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
156#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
157#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
158#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
159#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
160#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
161#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
162
163/* PG flags */
164#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
165#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
166#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
167#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
168#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
169#define AMDGPU_PG_SUPPORT_CP (1 << 5)
170#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
171#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
172#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
173#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
174#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
175
176/* GFX current status */
177#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
178#define AMDGPU_GFX_SAFE_MODE 0x00000001L
179#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
180#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
181#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
182
183/* max cursor sizes (in pixels) */
184#define CIK_CURSOR_WIDTH 128
185#define CIK_CURSOR_HEIGHT 128
186
187struct amdgpu_device;
188struct amdgpu_fence;
189struct amdgpu_ib;
190struct amdgpu_vm;
191struct amdgpu_ring;
192struct amdgpu_semaphore;
193struct amdgpu_cs_parser;
bb977d37 194struct amdgpu_job;
97b2e202 195struct amdgpu_irq_src;
0b492a4c 196struct amdgpu_fpriv;
97b2e202
AD		 197
198enum amdgpu_cp_irq {
199 AMDGPU_CP_IRQ_GFX_EOP = 0,
200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
207 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
208
209 AMDGPU_CP_IRQ_LAST
210};
211
212enum amdgpu_sdma_irq {
213 AMDGPU_SDMA_IRQ_TRAP0 = 0,
214 AMDGPU_SDMA_IRQ_TRAP1,
215
216 AMDGPU_SDMA_IRQ_LAST
217};
218
219enum amdgpu_thermal_irq {
220 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
221 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
222
223 AMDGPU_THERMAL_IRQ_LAST
224};
225
97b2e202 226int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 227 enum amd_ip_block_type block_type,
228 enum amd_clockgating_state state);
97b2e202 229int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 230 enum amd_ip_block_type block_type,
231 enum amd_powergating_state state);
97b2e202
AD		 232
233struct amdgpu_ip_block_version {
5fc3aeeb 234 enum amd_ip_block_type type;
97b2e202
AD		 235 u32 major;
236 u32 minor;
237 u32 rev;
5fc3aeeb 238 const struct amd_ip_funcs *funcs;
97b2e202
AD		 239};
240
241int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 242 enum amd_ip_block_type type,
97b2e202
AD		 243 u32 major, u32 minor);
244
245const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
246 struct amdgpu_device *adev,
5fc3aeeb 247 enum amd_ip_block_type type);
97b2e202
AD		 248
249/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
250struct amdgpu_buffer_funcs {
251 /* maximum bytes in a single operation */
252 uint32_t copy_max_bytes;
253
254 /* number of dw to reserve per operation */
255 unsigned copy_num_dw;
256
257 /* used for buffer migration */
c7ae72c0 258 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 259 /* src addr in bytes */
260 uint64_t src_offset,
261 /* dst addr in bytes */
262 uint64_t dst_offset,
263 /* number of byte to transfer */
264 uint32_t byte_count);
265
266 /* maximum bytes in a single operation */
267 uint32_t fill_max_bytes;
268
269 /* number of dw to reserve per operation */
270 unsigned fill_num_dw;
271
272 /* used for buffer clearing */
6e7a3840 273 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 274 /* value to write to memory */
275 uint32_t src_data,
276 /* dst addr in bytes */
277 uint64_t dst_offset,
278 /* number of byte to fill */
279 uint32_t byte_count);
280};
281
282/* provided by hw blocks that can write ptes, e.g., sdma */
283struct amdgpu_vm_pte_funcs {
284 /* copy pte entries from GART */
285 void (*copy_pte)(struct amdgpu_ib *ib,
286 uint64_t pe, uint64_t src,
287 unsigned count);
288 /* write pte one entry at a time with addr mapping */
289 void (*write_pte)(struct amdgpu_ib *ib,
290 uint64_t pe,
291 uint64_t addr, unsigned count,
292 uint32_t incr, uint32_t flags);
293 /* for linear pte/pde updates without addr mapping */
294 void (*set_pte_pde)(struct amdgpu_ib *ib,
295 uint64_t pe,
296 uint64_t addr, unsigned count,
297 uint32_t incr, uint32_t flags);
298 /* pad the indirect buffer to the necessary number of dw */
299 void (*pad_ib)(struct amdgpu_ib *ib);
300};
301
302/* provided by the gmc block */
303struct amdgpu_gart_funcs {
304 /* flush the vm tlb via mmio */
305 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
306 uint32_t vmid);
307 /* write pte/pde updates using the cpu */
308 int (*set_pte_pde)(struct amdgpu_device *adev,
309 void *cpu_pt_addr, /* cpu addr of page table */
310 uint32_t gpu_page_idx, /* pte/pde to update */
311 uint64_t addr, /* addr to write into pte/pde */
312 uint32_t flags); /* access flags */
313};
314
315/* provided by the ih block */
316struct amdgpu_ih_funcs {
317 /* ring read/write ptr handling, called from interrupt context */
318 u32 (*get_wptr)(struct amdgpu_device *adev);
319 void (*decode_iv)(struct amdgpu_device *adev,
320 struct amdgpu_iv_entry *entry);
321 void (*set_rptr)(struct amdgpu_device *adev);
322};
323
324/* provided by hw blocks that expose a ring buffer for commands */
325struct amdgpu_ring_funcs {
326 /* ring read/write ptr handling */
327 u32 (*get_rptr)(struct amdgpu_ring *ring);
328 u32 (*get_wptr)(struct amdgpu_ring *ring);
329 void (*set_wptr)(struct amdgpu_ring *ring);
330 /* validating and patching of IBs */
331 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
332 /* command emit functions */
333 void (*emit_ib)(struct amdgpu_ring *ring,
334 struct amdgpu_ib *ib);
335 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 336 uint64_t seq, unsigned flags);
97b2e202
AD		 337 bool (*emit_semaphore)(struct amdgpu_ring *ring,
338 struct amdgpu_semaphore *semaphore,
339 bool emit_wait);
340 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
341 uint64_t pd_addr);
d2edb07b 342 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 343 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
344 uint32_t gds_base, uint32_t gds_size,
345 uint32_t gws_base, uint32_t gws_size,
346 uint32_t oa_base, uint32_t oa_size);
347 /* testing functions */
348 int (*test_ring)(struct amdgpu_ring *ring);
349 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 350 /* insert NOP packets */
351 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 352};
353
354/*
355 * BIOS.
356 */
357bool amdgpu_get_bios(struct amdgpu_device *adev);
358bool amdgpu_read_bios(struct amdgpu_device *adev);
359
360/*
361 * Dummy page
362 */
363struct amdgpu_dummy_page {
364 struct page *page;
365 dma_addr_t addr;
366};
367int amdgpu_dummy_page_init(struct amdgpu_device *adev);
368void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
369
370
371/*
372 * Clocks
373 */
374
375#define AMDGPU_MAX_PPLL 3
376
377struct amdgpu_clock {
378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
379 struct amdgpu_pll spll;
380 struct amdgpu_pll mpll;
381 /* 10 Khz units */
382 uint32_t default_mclk;
383 uint32_t default_sclk;
384 uint32_t default_dispclk;
385 uint32_t current_dispclk;
386 uint32_t dp_extclk;
387 uint32_t max_pixel_clock;
388};
389
390/*
391 * Fences.
392 */
393struct amdgpu_fence_driver {
97b2e202
AD		 394 uint64_t gpu_addr;
395 volatile uint32_t *cpu_addr;
396 /* sync_seq is protected by ring emission lock */
397 uint64_t sync_seq[AMDGPU_MAX_RINGS];
398 atomic64_t last_seq;
399 bool initialized;
97b2e202
AD		 400 struct amdgpu_irq_src *irq_src;
401 unsigned irq_type;
c2776afe 402 struct timer_list fallback_timer;
7f06c236 403 wait_queue_head_t fence_queue;
97b2e202
AD		 404};
405
406/* some special values for the owner field */
407#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
408#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 409
890ee23f
CZ		 410#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
411#define AMDGPU_FENCE_FLAG_INT (1 << 1)
412
97b2e202
AD		 413struct amdgpu_fence {
414 struct fence base;
4cef9267 415
97b2e202
AD		 416 /* RB, DMA, etc. */
417 struct amdgpu_ring *ring;
418 uint64_t seq;
419
420 /* filp or special value for fence creator */
421 void *owner;
422
423 wait_queue_t fence_wake;
424};
425
426struct amdgpu_user_fence {
427 /* write-back bo */
428 struct amdgpu_bo *bo;
429 /* write-back address offset to bo start */
430 uint32_t offset;
431};
432
433int amdgpu_fence_driver_init(struct amdgpu_device *adev);
434void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
435void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
436
4f839a24 437int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 438int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
439 struct amdgpu_irq_src *irq_src,
440 unsigned irq_type);
5ceb54c6
AD		 441void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
442void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 443int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
444 struct amdgpu_fence **fence);
445void amdgpu_fence_process(struct amdgpu_ring *ring);
446int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
447int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
448unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
449
97b2e202
AD		 450bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
453 struct amdgpu_ring *ring);
454
97b2e202
AD		 455/*
456 * TTM.
457 */
458struct amdgpu_mman {
459 struct ttm_bo_global_ref bo_global_ref;
460 struct drm_global_reference mem_global_ref;
461 struct ttm_bo_device bdev;
462 bool mem_global_referenced;
463 bool initialized;
464
465#if defined(CONFIG_DEBUG_FS)
466 struct dentry *vram;
467 struct dentry *gtt;
468#endif
469
470 /* buffer handling */
471 const struct amdgpu_buffer_funcs *buffer_funcs;
472 struct amdgpu_ring *buffer_funcs_ring;
473};
474
475int amdgpu_copy_buffer(struct amdgpu_ring *ring,
476 uint64_t src_offset,
477 uint64_t dst_offset,
478 uint32_t byte_count,
479 struct reservation_object *resv,
c7ae72c0 480 struct fence **fence);
97b2e202
AD		 481int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
482
483struct amdgpu_bo_list_entry {
484 struct amdgpu_bo *robj;
485 struct ttm_validate_buffer tv;
486 struct amdgpu_bo_va *bo_va;
487 unsigned prefered_domains;
488 unsigned allowed_domains;
489 uint32_t priority;
490};
491
492struct amdgpu_bo_va_mapping {
493 struct list_head list;
494 struct interval_tree_node it;
495 uint64_t offset;
496 uint32_t flags;
497};
498
499/* bo virtual addresses in a specific vm */
500struct amdgpu_bo_va {
69b576a1 501 struct mutex mutex;
97b2e202
AD		 502 /* protected by bo being reserved */
503 struct list_head bo_list;
bb1e38a4 504 struct fence *last_pt_update;
97b2e202
AD		 505 unsigned ref_count;
506
7fc11959 507 /* protected by vm mutex and spinlock */
97b2e202
AD		 508 struct list_head vm_status;
509
7fc11959
CK		 510 /* mappings for this bo_va */
511 struct list_head invalids;
512 struct list_head valids;
513
97b2e202
AD		 514 /* constant after initialization */
515 struct amdgpu_vm *vm;
516 struct amdgpu_bo *bo;
517};
518
7e5a547f
CZ		 519#define AMDGPU_GEM_DOMAIN_MAX 0x3
520
97b2e202
AD		 521struct amdgpu_bo {
522 /* Protected by gem.mutex */
523 struct list_head list;
524 /* Protected by tbo.reserved */
525 u32 initial_domain;
7e5a547f 526 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 527 struct ttm_placement placement;
528 struct ttm_buffer_object tbo;
529 struct ttm_bo_kmap_obj kmap;
530 u64 flags;
531 unsigned pin_count;
532 void *kptr;
533 u64 tiling_flags;
534 u64 metadata_flags;
535 void *metadata;
536 u32 metadata_size;
537 /* list of all virtual address to which this bo
538 * is associated to
539 */
540 struct list_head va;
541 /* Constant after initialization */
542 struct amdgpu_device *adev;
543 struct drm_gem_object gem_base;
82b9c55b 544 struct amdgpu_bo *parent;
97b2e202
AD		 545
546 struct ttm_bo_kmap_obj dma_buf_vmap;
547 pid_t pid;
548 struct amdgpu_mn *mn;
549 struct list_head mn_list;
550};
551#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
552
553void amdgpu_gem_object_free(struct drm_gem_object *obj);
554int amdgpu_gem_object_open(struct drm_gem_object *obj,
555 struct drm_file *file_priv);
556void amdgpu_gem_object_close(struct drm_gem_object *obj,
557 struct drm_file *file_priv);
558unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
559struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
560struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
561 struct dma_buf_attachment *attach,
562 struct sg_table *sg);
563struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
564 struct drm_gem_object *gobj,
565 int flags);
566int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
567void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
568struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
569void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
570void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
571int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
572
573/* sub-allocation manager, it has to be protected by another lock.
574 * By conception this is an helper for other part of the driver
575 * like the indirect buffer or semaphore, which both have their
576 * locking.
577 *
578 * Principe is simple, we keep a list of sub allocation in offset
579 * order (first entry has offset == 0, last entry has the highest
580 * offset).
581 *
582 * When allocating new object we first check if there is room at
583 * the end total_size - (last_object_offset + last_object_size) >=
584 * alloc_size. If so we allocate new object there.
585 *
586 * When there is not enough room at the end, we start waiting for
587 * each sub object until we reach object_offset+object_size >=
588 * alloc_size, this object then become the sub object we return.
589 *
590 * Alignment can't be bigger than page size.
591 *
592 * Hole are not considered for allocation to keep things simple.
593 * Assumption is that there won't be hole (all object on same
594 * alignment).
595 */
596struct amdgpu_sa_manager {
597 wait_queue_head_t wq;
598 struct amdgpu_bo *bo;
599 struct list_head *hole;
600 struct list_head flist[AMDGPU_MAX_RINGS];
601 struct list_head olist;
602 unsigned size;
603 uint64_t gpu_addr;
604 void *cpu_ptr;
605 uint32_t domain;
606 uint32_t align;
607};
608
609struct amdgpu_sa_bo;
610
611/* sub-allocation buffer */
612struct amdgpu_sa_bo {
613 struct list_head olist;
614 struct list_head flist;
615 struct amdgpu_sa_manager *manager;
616 unsigned soffset;
617 unsigned eoffset;
4ce9891e 618 struct fence *fence;
97b2e202
AD		 619};
620
621/*
622 * GEM objects.
623 */
624struct amdgpu_gem {
625 struct mutex mutex;
626 struct list_head objects;
627};
628
629int amdgpu_gem_init(struct amdgpu_device *adev);
630void amdgpu_gem_fini(struct amdgpu_device *adev);
631int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
632 int alignment, u32 initial_domain,
633 u64 flags, bool kernel,
634 struct drm_gem_object **obj);
635
636int amdgpu_mode_dumb_create(struct drm_file *file_priv,
637 struct drm_device *dev,
638 struct drm_mode_create_dumb *args);
639int amdgpu_mode_dumb_mmap(struct drm_file *filp,
640 struct drm_device *dev,
641 uint32_t handle, uint64_t *offset_p);
642
643/*
644 * Semaphores.
645 */
646struct amdgpu_semaphore {
647 struct amdgpu_sa_bo *sa_bo;
648 signed waiters;
649 uint64_t gpu_addr;
650};
651
652int amdgpu_semaphore_create(struct amdgpu_device *adev,
653 struct amdgpu_semaphore **semaphore);
654bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
655 struct amdgpu_semaphore *semaphore);
656bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
657 struct amdgpu_semaphore *semaphore);
658void amdgpu_semaphore_free(struct amdgpu_device *adev,
659 struct amdgpu_semaphore **semaphore,
4ce9891e 660 struct fence *fence);
97b2e202
AD		 661
662/*
663 * Synchronization
664 */
665struct amdgpu_sync {
666 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
16545c32 667 struct fence *sync_to[AMDGPU_MAX_RINGS];
f91b3a69 668 DECLARE_HASHTABLE(fences, 4);
3c62338c 669 struct fence *last_vm_update;
97b2e202
AD		 670};
671
672void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 673int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
674 struct fence *f);
97b2e202
AD		 675int amdgpu_sync_resv(struct amdgpu_device *adev,
676 struct amdgpu_sync *sync,
677 struct reservation_object *resv,
678 void *owner);
679int amdgpu_sync_rings(struct amdgpu_sync *sync,
680 struct amdgpu_ring *ring);
e61235db 681struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 682int amdgpu_sync_wait(struct amdgpu_sync *sync);
97b2e202 683void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
4ce9891e 684 struct fence *fence);
97b2e202
AD		 685
686/*
687 * GART structures, functions & helpers
688 */
689struct amdgpu_mc;
690
691#define AMDGPU_GPU_PAGE_SIZE 4096
692#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
693#define AMDGPU_GPU_PAGE_SHIFT 12
694#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
695
696struct amdgpu_gart {
697 dma_addr_t table_addr;
698 struct amdgpu_bo *robj;
699 void *ptr;
700 unsigned num_gpu_pages;
701 unsigned num_cpu_pages;
702 unsigned table_size;
703 struct page **pages;
704 dma_addr_t *pages_addr;
705 bool ready;
706 const struct amdgpu_gart_funcs *gart_funcs;
707};
708
709int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
710void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
711int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
712void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
713int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
714void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
715int amdgpu_gart_init(struct amdgpu_device *adev);
716void amdgpu_gart_fini(struct amdgpu_device *adev);
717void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
718 int pages);
719int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
720 int pages, struct page **pagelist,
721 dma_addr_t *dma_addr, uint32_t flags);
722
723/*
724 * GPU MC structures, functions & helpers
725 */
726struct amdgpu_mc {
727 resource_size_t aper_size;
728 resource_size_t aper_base;
729 resource_size_t agp_base;
730 /* for some chips with <= 32MB we need to lie
731 * about vram size near mc fb location */
732 u64 mc_vram_size;
733 u64 visible_vram_size;
734 u64 gtt_size;
735 u64 gtt_start;
736 u64 gtt_end;
737 u64 vram_start;
738 u64 vram_end;
739 unsigned vram_width;
740 u64 real_vram_size;
741 int vram_mtrr;
742 u64 gtt_base_align;
743 u64 mc_mask;
744 const struct firmware *fw; /* MC firmware */
745 uint32_t fw_version;
746 struct amdgpu_irq_src vm_fault;
81c59f54 747 uint32_t vram_type;
97b2e202
AD		 748};
749
750/*
751 * GPU doorbell structures, functions & helpers
752 */
753typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
754{
755 AMDGPU_DOORBELL_KIQ = 0x000,
756 AMDGPU_DOORBELL_HIQ = 0x001,
757 AMDGPU_DOORBELL_DIQ = 0x002,
758 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
759 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
760 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
761 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
762 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
763 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
764 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
765 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
766 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
767 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
768 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
769 AMDGPU_DOORBELL_IH = 0x1E8,
770 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
771 AMDGPU_DOORBELL_INVALID = 0xFFFF
772} AMDGPU_DOORBELL_ASSIGNMENT;
773
774struct amdgpu_doorbell {
775 /* doorbell mmio */
776 resource_size_t base;
777 resource_size_t size;
778 u32 __iomem *ptr;
779 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
780};
781
782void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
783 phys_addr_t *aperture_base,
784 size_t *aperture_size,
785 size_t *start_offset);
786
787/*
788 * IRQS.
789 */
790
791struct amdgpu_flip_work {
792 struct work_struct flip_work;
793 struct work_struct unpin_work;
794 struct amdgpu_device *adev;
795 int crtc_id;
796 uint64_t base;
797 struct drm_pending_vblank_event *event;
798 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 799 struct fence *excl;
800 unsigned shared_count;
801 struct fence **shared;
97b2e202
AD		 802};
803
804
805/*
806 * CP & rings.
807 */
808
809struct amdgpu_ib {
810 struct amdgpu_sa_bo *sa_bo;
811 uint32_t length_dw;
812 uint64_t gpu_addr;
813 uint32_t *ptr;
814 struct amdgpu_ring *ring;
815 struct amdgpu_fence *fence;
816 struct amdgpu_user_fence *user;
817 struct amdgpu_vm *vm;
3cb485f3 818 struct amdgpu_ctx *ctx;
97b2e202 819 struct amdgpu_sync sync;
97b2e202
AD		 820 uint32_t gds_base, gds_size;
821 uint32_t gws_base, gws_size;
822 uint32_t oa_base, oa_size;
de807f81 823 uint32_t flags;
5430a3ff
CK		 824 /* resulting sequence number */
825 uint64_t sequence;
97b2e202
AD		 826};
827
828enum amdgpu_ring_type {
829 AMDGPU_RING_TYPE_GFX,
830 AMDGPU_RING_TYPE_COMPUTE,
831 AMDGPU_RING_TYPE_SDMA,
832 AMDGPU_RING_TYPE_UVD,
833 AMDGPU_RING_TYPE_VCE
834};
835
c1b69ed0
CZ		 836extern struct amd_sched_backend_ops amdgpu_sched_ops;
837
3c704e93
CZ		 838int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
839 struct amdgpu_ring *ring,
840 struct amdgpu_ib *ibs,
841 unsigned num_ibs,
bb977d37 842 int (*free_job)(struct amdgpu_job *),
1763552e
CZ		 843 void *owner,
844 struct fence **fence);
3c704e93 845
97b2e202
AD		 846struct amdgpu_ring {
847 struct amdgpu_device *adev;
848 const struct amdgpu_ring_funcs *funcs;
849 struct amdgpu_fence_driver fence_drv;
4f839a24 850 struct amd_gpu_scheduler sched;
97b2e202 851
176e1ab1 852 spinlock_t fence_lock;
97b2e202
AD		 853 struct mutex *ring_lock;
854 struct amdgpu_bo *ring_obj;
855 volatile uint32_t *ring;
856 unsigned rptr_offs;
857 u64 next_rptr_gpu_addr;
858 volatile u32 *next_rptr_cpu_addr;
859 unsigned wptr;
860 unsigned wptr_old;
861 unsigned ring_size;
862 unsigned ring_free_dw;
863 int count_dw;
97b2e202
AD		 864 uint64_t gpu_addr;
865 uint32_t align_mask;
866 uint32_t ptr_mask;
867 bool ready;
868 u32 nop;
869 u32 idx;
870 u64 last_semaphore_signal_addr;
871 u64 last_semaphore_wait_addr;
872 u32 me;
873 u32 pipe;
874 u32 queue;
875 struct amdgpu_bo *mqd_obj;
876 u32 doorbell_index;
877 bool use_doorbell;
878 unsigned wptr_offs;
879 unsigned next_rptr_offs;
880 unsigned fence_offs;
3cb485f3 881 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 882 enum amdgpu_ring_type type;
883 char name[16];
4274f5d4 884 bool is_pte_ring;
97b2e202
AD		 885};
886
887/*
888 * VM
889 */
890
891/* maximum number of VMIDs */
892#define AMDGPU_NUM_VM 16
893
894/* number of entries in page table */
895#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
896
897/* PTBs (Page Table Blocks) need to be aligned to 32K */
898#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
899#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
900#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
901
902#define AMDGPU_PTE_VALID (1 << 0)
903#define AMDGPU_PTE_SYSTEM (1 << 1)
904#define AMDGPU_PTE_SNOOPED (1 << 2)
905
906/* VI only */
907#define AMDGPU_PTE_EXECUTABLE (1 << 4)
908
909#define AMDGPU_PTE_READABLE (1 << 5)
910#define AMDGPU_PTE_WRITEABLE (1 << 6)
911
912/* PTE (Page Table Entry) fragment field for different page sizes */
913#define AMDGPU_PTE_FRAG_4KB (0 << 7)
914#define AMDGPU_PTE_FRAG_64KB (4 << 7)
915#define AMDGPU_LOG2_PAGES_PER_FRAG 4
916
d9c13156
CK		 917/* How to programm VM fault handling */
918#define AMDGPU_VM_FAULT_STOP_NEVER 0
919#define AMDGPU_VM_FAULT_STOP_FIRST 1
920#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
921
97b2e202 922struct amdgpu_vm_pt {
ee1782c3
CK		 923 struct amdgpu_bo_list_entry entry;
924 uint64_t addr;
97b2e202
AD		 925};
926
927struct amdgpu_vm_id {
928 unsigned id;
929 uint64_t pd_gpu_addr;
930 /* last flushed PD/PT update */
3c62338c 931 struct fence *flushed_updates;
97b2e202
AD		 932};
933
934struct amdgpu_vm {
25cfc3c2
CK		 935 /* tree of virtual addresses mapped */
936 spinlock_t it_lock;
97b2e202
AD		 937 struct rb_root va;
938
7fc11959 939 /* protecting invalidated */
97b2e202
AD		 940 spinlock_t status_lock;
941
942 /* BOs moved, but not yet updated in the PT */
943 struct list_head invalidated;
944
7fc11959
CK		 945 /* BOs cleared in the PT because of a move */
946 struct list_head cleared;
947
948 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 949 struct list_head freed;
950
951 /* contains the page directory */
952 struct amdgpu_bo *page_directory;
953 unsigned max_pde_used;
05906dec 954 struct fence *page_directory_fence;
97b2e202
AD		 955
956 /* array of page tables, one for each page directory entry */
957 struct amdgpu_vm_pt *page_tables;
958
959 /* for id and flush management per ring */
960 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 961
81d75a30 962 /* protecting freed */
963 spinlock_t freed_lock;
97b2e202
AD		 964};
965
966struct amdgpu_vm_manager {
1c16c0a7
CK		 967 struct {
968 struct fence *active;
969 atomic_long_t owner;
970 } ids[AMDGPU_NUM_VM];
971
8b4fb00b 972 uint32_t max_pfn;
97b2e202 973 /* number of VMIDs */
8b4fb00b 974 unsigned nvm;
97b2e202 975 /* vram base address for page table entry */
8b4fb00b 976 u64 vram_base_offset;
97b2e202 977 /* is vm enabled? */
8b4fb00b 978 bool enabled;
97b2e202
AD		 979 /* vm pte handling */
980 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
981 struct amdgpu_ring *vm_pte_funcs_ring;
982};
983
ea89f8c9 984void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 985int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
986void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 987void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
988 struct list_head *validated,
989 struct amdgpu_bo_list_entry *entry);
ee1782c3 990void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 991void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
992 struct amdgpu_vm *vm);
8b4fb00b
CK		 993int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
994 struct amdgpu_sync *sync);
995void amdgpu_vm_flush(struct amdgpu_ring *ring,
996 struct amdgpu_vm *vm,
997 struct fence *updates);
998void amdgpu_vm_fence(struct amdgpu_device *adev,
999 struct amdgpu_vm *vm,
1000 struct fence *fence);
1001uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
1002int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
1003 struct amdgpu_vm *vm);
1004int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1005 struct amdgpu_vm *vm);
1006int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1007 struct amdgpu_sync *sync);
1008int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1009 struct amdgpu_bo_va *bo_va,
1010 struct ttm_mem_reg *mem);
1011void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1012 struct amdgpu_bo *bo);
1013struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1014 struct amdgpu_bo *bo);
1015struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1016 struct amdgpu_vm *vm,
1017 struct amdgpu_bo *bo);
1018int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1019 struct amdgpu_bo_va *bo_va,
1020 uint64_t addr, uint64_t offset,
1021 uint64_t size, uint32_t flags);
1022int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1023 struct amdgpu_bo_va *bo_va,
1024 uint64_t addr);
1025void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1026 struct amdgpu_bo_va *bo_va);
1027int amdgpu_vm_free_job(struct amdgpu_job *job);
1028
97b2e202
AD		 1029/*
1030 * context related structures
1031 */
1032
21c16bf6 1033struct amdgpu_ctx_ring {
91404fb2 1034 uint64_t sequence;
37cd0ca2 1035 struct fence **fences;
91404fb2 1036 struct amd_sched_entity entity;
21c16bf6
CK		 1037};
1038
97b2e202 1039struct amdgpu_ctx {
0b492a4c 1040 struct kref refcount;
9cb7e5a9 1041 struct amdgpu_device *adev;
0b492a4c 1042 unsigned reset_counter;
21c16bf6 1043 spinlock_t ring_lock;
37cd0ca2 1044 struct fence **fences;
21c16bf6 1045 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1046};
1047
1048struct amdgpu_ctx_mgr {
0b492a4c
AD		 1049 struct amdgpu_device *adev;
1050 struct mutex lock;
1051 /* protected by lock */
1052 struct idr ctx_handles;
97b2e202
AD		 1053};
1054
d033a6de 1055int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
47f38501
CK		 1056 struct amdgpu_ctx *ctx);
1057void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
0b492a4c 1058
0b492a4c
AD		 1059struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1060int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1061
21c16bf6 1062uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1063 struct fence *fence);
21c16bf6
CK		 1064struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1065 struct amdgpu_ring *ring, uint64_t seq);
1066
0b492a4c
AD		 1067int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *filp);
1069
efd4ccb5
CK		 1070void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1071void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1072
97b2e202
AD		 1073/*
1074 * file private structure
1075 */
1076
1077struct amdgpu_fpriv {
1078 struct amdgpu_vm vm;
1079 struct mutex bo_list_lock;
1080 struct idr bo_list_handles;
0b492a4c 1081 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1082};
1083
1084/*
1085 * residency list
1086 */
1087
1088struct amdgpu_bo_list {
1089 struct mutex lock;
1090 struct amdgpu_bo *gds_obj;
1091 struct amdgpu_bo *gws_obj;
1092 struct amdgpu_bo *oa_obj;
1093 bool has_userptr;
1094 unsigned num_entries;
1095 struct amdgpu_bo_list_entry *array;
1096};
1097
1098struct amdgpu_bo_list *
1099amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1100void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1101 struct list_head *validated);
97b2e202
AD		 1102void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1103void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1104
1105/*
1106 * GFX stuff
1107 */
1108#include "clearstate_defs.h"
1109
1110struct amdgpu_rlc {
1111 /* for power gating */
1112 struct amdgpu_bo *save_restore_obj;
1113 uint64_t save_restore_gpu_addr;
1114 volatile uint32_t *sr_ptr;
1115 const u32 *reg_list;
1116 u32 reg_list_size;
1117 /* for clear state */
1118 struct amdgpu_bo *clear_state_obj;
1119 uint64_t clear_state_gpu_addr;
1120 volatile uint32_t *cs_ptr;
1121 const struct cs_section_def *cs_data;
1122 u32 clear_state_size;
1123 /* for cp tables */
1124 struct amdgpu_bo *cp_table_obj;
1125 uint64_t cp_table_gpu_addr;
1126 volatile uint32_t *cp_table_ptr;
1127 u32 cp_table_size;
1128};
1129
1130struct amdgpu_mec {
1131 struct amdgpu_bo *hpd_eop_obj;
1132 u64 hpd_eop_gpu_addr;
1133 u32 num_pipe;
1134 u32 num_mec;
1135 u32 num_queue;
1136};
1137
1138/*
1139 * GPU scratch registers structures, functions & helpers
1140 */
1141struct amdgpu_scratch {
1142 unsigned num_reg;
1143 uint32_t reg_base;
1144 bool free[32];
1145 uint32_t reg[32];
1146};
1147
1148/*
1149 * GFX configurations
1150 */
1151struct amdgpu_gca_config {
1152 unsigned max_shader_engines;
1153 unsigned max_tile_pipes;
1154 unsigned max_cu_per_sh;
1155 unsigned max_sh_per_se;
1156 unsigned max_backends_per_se;
1157 unsigned max_texture_channel_caches;
1158 unsigned max_gprs;
1159 unsigned max_gs_threads;
1160 unsigned max_hw_contexts;
1161 unsigned sc_prim_fifo_size_frontend;
1162 unsigned sc_prim_fifo_size_backend;
1163 unsigned sc_hiz_tile_fifo_size;
1164 unsigned sc_earlyz_tile_fifo_size;
1165
1166 unsigned num_tile_pipes;
1167 unsigned backend_enable_mask;
1168 unsigned mem_max_burst_length_bytes;
1169 unsigned mem_row_size_in_kb;
1170 unsigned shader_engine_tile_size;
1171 unsigned num_gpus;
1172 unsigned multi_gpu_tile_size;
1173 unsigned mc_arb_ramcfg;
1174 unsigned gb_addr_config;
1175
1176 uint32_t tile_mode_array[32];
1177 uint32_t macrotile_mode_array[16];
1178};
1179
1180struct amdgpu_gfx {
1181 struct mutex gpu_clock_mutex;
1182 struct amdgpu_gca_config config;
1183 struct amdgpu_rlc rlc;
1184 struct amdgpu_mec mec;
1185 struct amdgpu_scratch scratch;
1186 const struct firmware *me_fw; /* ME firmware */
1187 uint32_t me_fw_version;
1188 const struct firmware *pfp_fw; /* PFP firmware */
1189 uint32_t pfp_fw_version;
1190 const struct firmware *ce_fw; /* CE firmware */
1191 uint32_t ce_fw_version;
1192 const struct firmware *rlc_fw; /* RLC firmware */
1193 uint32_t rlc_fw_version;
1194 const struct firmware *mec_fw; /* MEC firmware */
1195 uint32_t mec_fw_version;
1196 const struct firmware *mec2_fw; /* MEC2 firmware */
1197 uint32_t mec2_fw_version;
02558a00
KW		 1198 uint32_t me_feature_version;
1199 uint32_t ce_feature_version;
1200 uint32_t pfp_feature_version;
351643d7
JZ		 1201 uint32_t rlc_feature_version;
1202 uint32_t mec_feature_version;
1203 uint32_t mec2_feature_version;
97b2e202
AD		 1204 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1205 unsigned num_gfx_rings;
1206 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1207 unsigned num_compute_rings;
1208 struct amdgpu_irq_src eop_irq;
1209 struct amdgpu_irq_src priv_reg_irq;
1210 struct amdgpu_irq_src priv_inst_irq;
1211 /* gfx status */
1212 uint32_t gfx_current_status;
a101a899
KW		 1213 /* ce ram size*/
1214 unsigned ce_ram_size;
97b2e202
AD		 1215};
1216
1217int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1218 unsigned size, struct amdgpu_ib *ib);
1219void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1220int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1221 struct amdgpu_ib *ib, void *owner);
1222int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1223void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1224int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1225/* Ring access between begin & end cannot sleep */
1226void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1227int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1228int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1229void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 1230void amdgpu_ring_commit(struct amdgpu_ring *ring);
1231void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1232void amdgpu_ring_undo(struct amdgpu_ring *ring);
1233void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1234unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1235 uint32_t **data);
1236int amdgpu_ring_restore(struct amdgpu_ring *ring,
1237 unsigned size, uint32_t *data);
1238int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1239 unsigned ring_size, u32 nop, u32 align_mask,
1240 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1241 enum amdgpu_ring_type ring_type);
1242void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1243struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1244
1245/*
1246 * CS.
1247 */
1248struct amdgpu_cs_chunk {
1249 uint32_t chunk_id;
1250 uint32_t length_dw;
1251 uint32_t *kdata;
97b2e202
AD		 1252};
1253
1254struct amdgpu_cs_parser {
1255 struct amdgpu_device *adev;
1256 struct drm_file *filp;
3cb485f3 1257 struct amdgpu_ctx *ctx;
c3cca41e 1258
97b2e202
AD		 1259 /* chunks */
1260 unsigned nchunks;
1261 struct amdgpu_cs_chunk *chunks;
97b2e202 1262
c3cca41e 1263 /* indirect buffers */
97b2e202 1264 uint32_t num_ibs;
c3cca41e 1265 struct amdgpu_ib *ibs;
97b2e202 1266
c3cca41e
CK		 1267 /* buffer objects */
1268 struct ww_acquire_ctx ticket;
1269 struct amdgpu_bo_list *bo_list;
1270 struct amdgpu_bo_list_entry vm_pd;
1271 struct list_head validated;
1272 struct fence *fence;
1273 uint64_t bytes_moved_threshold;
1274 uint64_t bytes_moved;
97b2e202
AD		 1275
1276 /* user fence */
91acbeb6
CK		 1277 struct amdgpu_user_fence uf;
1278 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1279};
1280
bb977d37
CZ		 1281struct amdgpu_job {
1282 struct amd_sched_job base;
1283 struct amdgpu_device *adev;
bb977d37
CZ		 1284 struct amdgpu_ib *ibs;
1285 uint32_t num_ibs;
e2840221 1286 void *owner;
bb977d37 1287 struct amdgpu_user_fence uf;
4c7eb91c 1288 int (*free_job)(struct amdgpu_job *job);
bb977d37 1289};
a6db8a33
JZ		 1290#define to_amdgpu_job(sched_job) \
1291 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1292
97b2e202
AD		 1293static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1294{
1295 return p->ibs[ib_idx].ptr[idx];
1296}
1297
1298/*
1299 * Writeback
1300 */
1301#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1302
1303struct amdgpu_wb {
1304 struct amdgpu_bo *wb_obj;
1305 volatile uint32_t *wb;
1306 uint64_t gpu_addr;
1307 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1308 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1309};
1310
1311int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1312void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1313
97b2e202 1314
97b2e202
AD		 1315
1316enum amdgpu_int_thermal_type {
1317 THERMAL_TYPE_NONE,
1318 THERMAL_TYPE_EXTERNAL,
1319 THERMAL_TYPE_EXTERNAL_GPIO,
1320 THERMAL_TYPE_RV6XX,
1321 THERMAL_TYPE_RV770,
1322 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1323 THERMAL_TYPE_EVERGREEN,
1324 THERMAL_TYPE_SUMO,
1325 THERMAL_TYPE_NI,
1326 THERMAL_TYPE_SI,
1327 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1328 THERMAL_TYPE_CI,
1329 THERMAL_TYPE_KV,
1330};
1331
1332enum amdgpu_dpm_auto_throttle_src {
1333 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1334 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1335};
1336
1337enum amdgpu_dpm_event_src {
1338 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1339 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1340 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1341 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1342 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1343};
1344
1345#define AMDGPU_MAX_VCE_LEVELS 6
1346
1347enum amdgpu_vce_level {
1348 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1349 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1350 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1351 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1352 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1353 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1354};
1355
1356struct amdgpu_ps {
1357 u32 caps; /* vbios flags */
1358 u32 class; /* vbios flags */
1359 u32 class2; /* vbios flags */
1360 /* UVD clocks */
1361 u32 vclk;
1362 u32 dclk;
1363 /* VCE clocks */
1364 u32 evclk;
1365 u32 ecclk;
1366 bool vce_active;
1367 enum amdgpu_vce_level vce_level;
1368 /* asic priv */
1369 void *ps_priv;
1370};
1371
1372struct amdgpu_dpm_thermal {
1373 /* thermal interrupt work */
1374 struct work_struct work;
1375 /* low temperature threshold */
1376 int min_temp;
1377 /* high temperature threshold */
1378 int max_temp;
1379 /* was last interrupt low to high or high to low */
1380 bool high_to_low;
1381 /* interrupt source */
1382 struct amdgpu_irq_src irq;
1383};
1384
1385enum amdgpu_clk_action
1386{
1387 AMDGPU_SCLK_UP = 1,
1388 AMDGPU_SCLK_DOWN
1389};
1390
1391struct amdgpu_blacklist_clocks
1392{
1393 u32 sclk;
1394 u32 mclk;
1395 enum amdgpu_clk_action action;
1396};
1397
1398struct amdgpu_clock_and_voltage_limits {
1399 u32 sclk;
1400 u32 mclk;
1401 u16 vddc;
1402 u16 vddci;
1403};
1404
1405struct amdgpu_clock_array {
1406 u32 count;
1407 u32 *values;
1408};
1409
1410struct amdgpu_clock_voltage_dependency_entry {
1411 u32 clk;
1412 u16 v;
1413};
1414
1415struct amdgpu_clock_voltage_dependency_table {
1416 u32 count;
1417 struct amdgpu_clock_voltage_dependency_entry *entries;
1418};
1419
1420union amdgpu_cac_leakage_entry {
1421 struct {
1422 u16 vddc;
1423 u32 leakage;
1424 };
1425 struct {
1426 u16 vddc1;
1427 u16 vddc2;
1428 u16 vddc3;
1429 };
1430};
1431
1432struct amdgpu_cac_leakage_table {
1433 u32 count;
1434 union amdgpu_cac_leakage_entry *entries;
1435};
1436
1437struct amdgpu_phase_shedding_limits_entry {
1438 u16 voltage;
1439 u32 sclk;
1440 u32 mclk;
1441};
1442
1443struct amdgpu_phase_shedding_limits_table {
1444 u32 count;
1445 struct amdgpu_phase_shedding_limits_entry *entries;
1446};
1447
1448struct amdgpu_uvd_clock_voltage_dependency_entry {
1449 u32 vclk;
1450 u32 dclk;
1451 u16 v;
1452};
1453
1454struct amdgpu_uvd_clock_voltage_dependency_table {
1455 u8 count;
1456 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1457};
1458
1459struct amdgpu_vce_clock_voltage_dependency_entry {
1460 u32 ecclk;
1461 u32 evclk;
1462 u16 v;
1463};
1464
1465struct amdgpu_vce_clock_voltage_dependency_table {
1466 u8 count;
1467 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1468};
1469
1470struct amdgpu_ppm_table {
1471 u8 ppm_design;
1472 u16 cpu_core_number;
1473 u32 platform_tdp;
1474 u32 small_ac_platform_tdp;
1475 u32 platform_tdc;
1476 u32 small_ac_platform_tdc;
1477 u32 apu_tdp;
1478 u32 dgpu_tdp;
1479 u32 dgpu_ulv_power;
1480 u32 tj_max;
1481};
1482
1483struct amdgpu_cac_tdp_table {
1484 u16 tdp;
1485 u16 configurable_tdp;
1486 u16 tdc;
1487 u16 battery_power_limit;
1488 u16 small_power_limit;
1489 u16 low_cac_leakage;
1490 u16 high_cac_leakage;
1491 u16 maximum_power_delivery_limit;
1492};
1493
1494struct amdgpu_dpm_dynamic_state {
1495 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1496 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1497 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1498 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1499 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1500 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1501 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1502 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1503 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1504 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1505 struct amdgpu_clock_array valid_sclk_values;
1506 struct amdgpu_clock_array valid_mclk_values;
1507 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1508 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1509 u32 mclk_sclk_ratio;
1510 u32 sclk_mclk_delta;
1511 u16 vddc_vddci_delta;
1512 u16 min_vddc_for_pcie_gen2;
1513 struct amdgpu_cac_leakage_table cac_leakage_table;
1514 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1515 struct amdgpu_ppm_table *ppm_table;
1516 struct amdgpu_cac_tdp_table *cac_tdp_table;
1517};
1518
1519struct amdgpu_dpm_fan {
1520 u16 t_min;
1521 u16 t_med;
1522 u16 t_high;
1523 u16 pwm_min;
1524 u16 pwm_med;
1525 u16 pwm_high;
1526 u8 t_hyst;
1527 u32 cycle_delay;
1528 u16 t_max;
1529 u8 control_mode;
1530 u16 default_max_fan_pwm;
1531 u16 default_fan_output_sensitivity;
1532 u16 fan_output_sensitivity;
1533 bool ucode_fan_control;
1534};
1535
1536enum amdgpu_pcie_gen {
1537 AMDGPU_PCIE_GEN1 = 0,
1538 AMDGPU_PCIE_GEN2 = 1,
1539 AMDGPU_PCIE_GEN3 = 2,
1540 AMDGPU_PCIE_GEN_INVALID = 0xffff
1541};
1542
1543enum amdgpu_dpm_forced_level {
1544 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1545 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1546 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1547};
1548
1549struct amdgpu_vce_state {
1550 /* vce clocks */
1551 u32 evclk;
1552 u32 ecclk;
1553 /* gpu clocks */
1554 u32 sclk;
1555 u32 mclk;
1556 u8 clk_idx;
1557 u8 pstate;
1558};
1559
1560struct amdgpu_dpm_funcs {
1561 int (*get_temperature)(struct amdgpu_device *adev);
1562 int (*pre_set_power_state)(struct amdgpu_device *adev);
1563 int (*set_power_state)(struct amdgpu_device *adev);
1564 void (*post_set_power_state)(struct amdgpu_device *adev);
1565 void (*display_configuration_changed)(struct amdgpu_device *adev);
1566 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1567 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1568 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1569 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1570 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1571 bool (*vblank_too_short)(struct amdgpu_device *adev);
1572 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1573 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1574 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1575 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1576 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1577 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1578 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1579};
1580
1581struct amdgpu_dpm {
1582 struct amdgpu_ps *ps;
1583 /* number of valid power states */
1584 int num_ps;
1585 /* current power state that is active */
1586 struct amdgpu_ps *current_ps;
1587 /* requested power state */
1588 struct amdgpu_ps *requested_ps;
1589 /* boot up power state */
1590 struct amdgpu_ps *boot_ps;
1591 /* default uvd power state */
1592 struct amdgpu_ps *uvd_ps;
1593 /* vce requirements */
1594 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1595 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1596 enum amd_pm_state_type state;
1597 enum amd_pm_state_type user_state;
97b2e202
AD		 1598 u32 platform_caps;
1599 u32 voltage_response_time;
1600 u32 backbias_response_time;
1601 void *priv;
1602 u32 new_active_crtcs;
1603 int new_active_crtc_count;
1604 u32 current_active_crtcs;
1605 int current_active_crtc_count;
1606 struct amdgpu_dpm_dynamic_state dyn_state;
1607 struct amdgpu_dpm_fan fan;
1608 u32 tdp_limit;
1609 u32 near_tdp_limit;
1610 u32 near_tdp_limit_adjusted;
1611 u32 sq_ramping_threshold;
1612 u32 cac_leakage;
1613 u16 tdp_od_limit;
1614 u32 tdp_adjustment;
1615 u16 load_line_slope;
1616 bool power_control;
1617 bool ac_power;
1618 /* special states active */
1619 bool thermal_active;
1620 bool uvd_active;
1621 bool vce_active;
1622 /* thermal handling */
1623 struct amdgpu_dpm_thermal thermal;
1624 /* forced levels */
1625 enum amdgpu_dpm_forced_level forced_level;
1626};
1627
1628struct amdgpu_pm {
1629 struct mutex mutex;
97b2e202
AD		 1630 u32 current_sclk;
1631 u32 current_mclk;
1632 u32 default_sclk;
1633 u32 default_mclk;
1634 struct amdgpu_i2c_chan *i2c_bus;
1635 /* internal thermal controller on rv6xx+ */
1636 enum amdgpu_int_thermal_type int_thermal_type;
1637 struct device *int_hwmon_dev;
1638 /* fan control parameters */
1639 bool no_fan;
1640 u8 fan_pulses_per_revolution;
1641 u8 fan_min_rpm;
1642 u8 fan_max_rpm;
1643 /* dpm */
1644 bool dpm_enabled;
c86f5ebf 1645 bool sysfs_initialized;
97b2e202
AD		 1646 struct amdgpu_dpm dpm;
1647 const struct firmware *fw; /* SMC firmware */
1648 uint32_t fw_version;
1649 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1650 uint32_t pcie_gen_mask;
1651 uint32_t pcie_mlw_mask;
7fb72a1f 1652 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1653};
1654
d0dd7f0c
AD		 1655void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1656
97b2e202
AD		 1657/*
1658 * UVD
1659 */
1660#define AMDGPU_MAX_UVD_HANDLES 10
1661#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1662#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1663#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1664
1665struct amdgpu_uvd {
1666 struct amdgpu_bo *vcpu_bo;
1667 void *cpu_addr;
1668 uint64_t gpu_addr;
97b2e202
AD		 1669 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1670 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1671 struct delayed_work idle_work;
1672 const struct firmware *fw; /* UVD firmware */
1673 struct amdgpu_ring ring;
1674 struct amdgpu_irq_src irq;
1675 bool address_64_bit;
1676};
1677
1678/*
1679 * VCE
1680 */
1681#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1682#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1683
6a585777
AD		 1684#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1685#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1686
97b2e202
AD		 1687struct amdgpu_vce {
1688 struct amdgpu_bo *vcpu_bo;
1689 uint64_t gpu_addr;
1690 unsigned fw_version;
1691 unsigned fb_version;
1692 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1693 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1694 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1695 struct delayed_work idle_work;
1696 const struct firmware *fw; /* VCE firmware */
1697 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1698 struct amdgpu_irq_src irq;
6a585777 1699 unsigned harvest_config;
97b2e202
AD		 1700};
1701
1702/*
1703 * SDMA
1704 */
c113ea1c 1705struct amdgpu_sdma_instance {
97b2e202
AD		 1706 /* SDMA firmware */
1707 const struct firmware *fw;
1708 uint32_t fw_version;
cfa2104f 1709 uint32_t feature_version;
97b2e202
AD		 1710
1711 struct amdgpu_ring ring;
18111de0 1712 bool burst_nop;
97b2e202
AD		 1713};
1714
c113ea1c
AD		 1715struct amdgpu_sdma {
1716 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1717 struct amdgpu_irq_src trap_irq;
1718 struct amdgpu_irq_src illegal_inst_irq;
1719 int num_instances;
1720};
1721
97b2e202
AD		 1722/*
1723 * Firmware
1724 */
1725struct amdgpu_firmware {
1726 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1727 bool smu_load;
1728 struct amdgpu_bo *fw_buf;
1729 unsigned int fw_size;
1730};
1731
1732/*
1733 * Benchmarking
1734 */
1735void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1736
1737
1738/*
1739 * Testing
1740 */
1741void amdgpu_test_moves(struct amdgpu_device *adev);
1742void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1743 struct amdgpu_ring *cpA,
1744 struct amdgpu_ring *cpB);
1745void amdgpu_test_syncing(struct amdgpu_device *adev);
1746
1747/*
1748 * MMU Notifier
1749 */
1750#if defined(CONFIG_MMU_NOTIFIER)
1751int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1752void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1753#else
1d1106b0 1754static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1755{
1756 return -ENODEV;
1757}
1d1106b0 1758static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1759#endif
1760
1761/*
1762 * Debugfs
1763 */
1764struct amdgpu_debugfs {
1765 struct drm_info_list *files;
1766 unsigned num_files;
1767};
1768
1769int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1770 struct drm_info_list *files,
1771 unsigned nfiles);
1772int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1773
1774#if defined(CONFIG_DEBUG_FS)
1775int amdgpu_debugfs_init(struct drm_minor *minor);
1776void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1777#endif
1778
1779/*
1780 * amdgpu smumgr functions
1781 */
1782struct amdgpu_smumgr_funcs {
1783 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1784 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1785 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1786};
1787
1788/*
1789 * amdgpu smumgr
1790 */
1791struct amdgpu_smumgr {
1792 struct amdgpu_bo *toc_buf;
1793 struct amdgpu_bo *smu_buf;
1794 /* asic priv smu data */
1795 void *priv;
1796 spinlock_t smu_lock;
1797 /* smumgr functions */
1798 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1799 /* ucode loading complete flag */
1800 uint32_t fw_flags;
1801};
1802
1803/*
1804 * ASIC specific register table accessible by UMD
1805 */
1806struct amdgpu_allowed_register_entry {
1807 uint32_t reg_offset;
1808 bool untouched;
1809 bool grbm_indexed;
1810};
1811
1812struct amdgpu_cu_info {
1813 uint32_t number; /* total active CU number */
1814 uint32_t ao_cu_mask;
1815 uint32_t bitmap[4][4];
1816};
1817
1818
1819/*
1820 * ASIC specific functions.
1821 */
1822struct amdgpu_asic_funcs {
1823 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1824 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1825 u8 *bios, u32 length_bytes);
97b2e202
AD		 1826 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1827 u32 sh_num, u32 reg_offset, u32 *value);
1828 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1829 int (*reset)(struct amdgpu_device *adev);
1830 /* wait for mc_idle */
1831 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1832 /* get the reference clock */
1833 u32 (*get_xclk)(struct amdgpu_device *adev);
1834 /* get the gpu clock counter */
1835 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1836 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1837 /* MM block clocks */
1838 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1839 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1840};
1841
1842/*
1843 * IOCTL.
1844 */
1845int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1846 struct drm_file *filp);
1847int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1848 struct drm_file *filp);
1849
1850int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1851 struct drm_file *filp);
1852int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1853 struct drm_file *filp);
1854int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *filp);
1856int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1857 struct drm_file *filp);
1858int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *filp);
1860int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1863int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1864
1865int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1866 struct drm_file *filp);
1867
1868/* VRAM scratch page for HDP bug, default vram page */
1869struct amdgpu_vram_scratch {
1870 struct amdgpu_bo *robj;
1871 volatile uint32_t *ptr;
1872 u64 gpu_addr;
1873};
1874
1875/*
1876 * ACPI
1877 */
1878struct amdgpu_atif_notification_cfg {
1879 bool enabled;
1880 int command_code;
1881};
1882
1883struct amdgpu_atif_notifications {
1884 bool display_switch;
1885 bool expansion_mode_change;
1886 bool thermal_state;
1887 bool forced_power_state;
1888 bool system_power_state;
1889 bool display_conf_change;
1890 bool px_gfx_switch;
1891 bool brightness_change;
1892 bool dgpu_display_event;
1893};
1894
1895struct amdgpu_atif_functions {
1896 bool system_params;
1897 bool sbios_requests;
1898 bool select_active_disp;
1899 bool lid_state;
1900 bool get_tv_standard;
1901 bool set_tv_standard;
1902 bool get_panel_expansion_mode;
1903 bool set_panel_expansion_mode;
1904 bool temperature_change;
1905 bool graphics_device_types;
1906};
1907
1908struct amdgpu_atif {
1909 struct amdgpu_atif_notifications notifications;
1910 struct amdgpu_atif_functions functions;
1911 struct amdgpu_atif_notification_cfg notification_cfg;
1912 struct amdgpu_encoder *encoder_for_bl;
1913};
1914
1915struct amdgpu_atcs_functions {
1916 bool get_ext_state;
1917 bool pcie_perf_req;
1918 bool pcie_dev_rdy;
1919 bool pcie_bus_width;
1920};
1921
1922struct amdgpu_atcs {
1923 struct amdgpu_atcs_functions functions;
1924};
1925
d03846af
CZ		 1926/*
1927 * CGS
1928 */
1929void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1930void amdgpu_cgs_destroy_device(void *cgs_device);
1931
1932
97b2e202
AD		 1933/*
1934 * Core structure, functions and helpers.
1935 */
1936typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1937typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1938
1939typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1940typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1941
8faf0e08
AD		 1942struct amdgpu_ip_block_status {
1943 bool valid;
1944 bool sw;
1945 bool hw;
1946};
1947
97b2e202
AD		 1948struct amdgpu_device {
1949 struct device *dev;
1950 struct drm_device *ddev;
1951 struct pci_dev *pdev;
97b2e202
AD		 1952
1953 /* ASIC */
2f7d10b3 1954 enum amd_asic_type asic_type;
97b2e202
AD		 1955 uint32_t family;
1956 uint32_t rev_id;
1957 uint32_t external_rev_id;
1958 unsigned long flags;
1959 int usec_timeout;
1960 const struct amdgpu_asic_funcs *asic_funcs;
1961 bool shutdown;
1962 bool suspend;
1963 bool need_dma32;
1964 bool accel_working;
97b2e202
AD		 1965 struct work_struct reset_work;
1966 struct notifier_block acpi_nb;
1967 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1968 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1969 unsigned debugfs_count;
1970#if defined(CONFIG_DEBUG_FS)
1971 struct dentry *debugfs_regs;
1972#endif
1973 struct amdgpu_atif atif;
1974 struct amdgpu_atcs atcs;
1975 struct mutex srbm_mutex;
1976 /* GRBM index mutex. Protects concurrent access to GRBM index */
1977 struct mutex grbm_idx_mutex;
1978 struct dev_pm_domain vga_pm_domain;
1979 bool have_disp_power_ref;
1980
1981 /* BIOS */
1982 uint8_t *bios;
1983 bool is_atom_bios;
1984 uint16_t bios_header_start;
1985 struct amdgpu_bo *stollen_vga_memory;
1986 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1987
1988 /* Register/doorbell mmio */
1989 resource_size_t rmmio_base;
1990 resource_size_t rmmio_size;
1991 void __iomem *rmmio;
1992 /* protects concurrent MM_INDEX/DATA based register access */
1993 spinlock_t mmio_idx_lock;
1994 /* protects concurrent SMC based register access */
1995 spinlock_t smc_idx_lock;
1996 amdgpu_rreg_t smc_rreg;
1997 amdgpu_wreg_t smc_wreg;
1998 /* protects concurrent PCIE register access */
1999 spinlock_t pcie_idx_lock;
2000 amdgpu_rreg_t pcie_rreg;
2001 amdgpu_wreg_t pcie_wreg;
2002 /* protects concurrent UVD register access */
2003 spinlock_t uvd_ctx_idx_lock;
2004 amdgpu_rreg_t uvd_ctx_rreg;
2005 amdgpu_wreg_t uvd_ctx_wreg;
2006 /* protects concurrent DIDT register access */
2007 spinlock_t didt_idx_lock;
2008 amdgpu_rreg_t didt_rreg;
2009 amdgpu_wreg_t didt_wreg;
2010 /* protects concurrent ENDPOINT (audio) register access */
2011 spinlock_t audio_endpt_idx_lock;
2012 amdgpu_block_rreg_t audio_endpt_rreg;
2013 amdgpu_block_wreg_t audio_endpt_wreg;
2014 void __iomem *rio_mem;
2015 resource_size_t rio_mem_size;
2016 struct amdgpu_doorbell doorbell;
2017
2018 /* clock/pll info */
2019 struct amdgpu_clock clock;
2020
2021 /* MC */
2022 struct amdgpu_mc mc;
2023 struct amdgpu_gart gart;
2024 struct amdgpu_dummy_page dummy_page;
2025 struct amdgpu_vm_manager vm_manager;
2026
2027 /* memory management */
2028 struct amdgpu_mman mman;
2029 struct amdgpu_gem gem;
2030 struct amdgpu_vram_scratch vram_scratch;
2031 struct amdgpu_wb wb;
2032 atomic64_t vram_usage;
2033 atomic64_t vram_vis_usage;
2034 atomic64_t gtt_usage;
2035 atomic64_t num_bytes_moved;
d94aed5a 2036 atomic_t gpu_reset_counter;
97b2e202
AD		 2037
2038 /* display */
2039 struct amdgpu_mode_info mode_info;
2040 struct work_struct hotplug_work;
2041 struct amdgpu_irq_src crtc_irq;
2042 struct amdgpu_irq_src pageflip_irq;
2043 struct amdgpu_irq_src hpd_irq;
2044
2045 /* rings */
97b2e202
AD		 2046 unsigned fence_context;
2047 struct mutex ring_lock;
2048 unsigned num_rings;
2049 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2050 bool ib_pool_ready;
2051 struct amdgpu_sa_manager ring_tmp_bo;
2052
2053 /* interrupts */
2054 struct amdgpu_irq irq;
2055
1f7371b2
AD		 2056 /* powerplay */
2057 struct amd_powerplay powerplay;
e61710c5 2058 bool pp_enabled;
1f7371b2 2059
97b2e202
AD		 2060 /* dpm */
2061 struct amdgpu_pm pm;
2062 u32 cg_flags;
2063 u32 pg_flags;
2064
2065 /* amdgpu smumgr */
2066 struct amdgpu_smumgr smu;
2067
2068 /* gfx */
2069 struct amdgpu_gfx gfx;
2070
2071 /* sdma */
c113ea1c 2072 struct amdgpu_sdma sdma;
97b2e202
AD		 2073
2074 /* uvd */
2075 bool has_uvd;
2076 struct amdgpu_uvd uvd;
2077
2078 /* vce */
2079 struct amdgpu_vce vce;
2080
2081 /* firmwares */
2082 struct amdgpu_firmware firmware;
2083
2084 /* GDS */
2085 struct amdgpu_gds gds;
2086
2087 const struct amdgpu_ip_block_version *ip_blocks;
2088 int num_ip_blocks;
8faf0e08 2089 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2090 struct mutex mn_lock;
2091 DECLARE_HASHTABLE(mn_hash, 7);
2092
2093 /* tracking pinned memory */
2094 u64 vram_pin_size;
2095 u64 gart_pin_size;
130e0371
OG		 2096
2097 /* amdkfd interface */
2098 struct kfd_dev *kfd;
23ca0e4e
CZ		 2099
2100 /* kernel conext for IB submission */
47f38501 2101 struct amdgpu_ctx kernel_ctx;
97b2e202
AD		 2102};
2103
2104bool amdgpu_device_is_px(struct drm_device *dev);
2105int amdgpu_device_init(struct amdgpu_device *adev,
2106 struct drm_device *ddev,
2107 struct pci_dev *pdev,
2108 uint32_t flags);
2109void amdgpu_device_fini(struct amdgpu_device *adev);
2110int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2111
2112uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2113 bool always_indirect);
2114void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2115 bool always_indirect);
2116u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2117void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2118
2119u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2120void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2121
2122/*
2123 * Cast helper
2124 */
2125extern const struct fence_ops amdgpu_fence_ops;
2126static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2127{
2128 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2129
2130 if (__f->base.ops == &amdgpu_fence_ops)
2131 return __f;
2132
2133 return NULL;
2134}
2135
2136/*
2137 * Registers read & write functions.
2138 */
2139#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2140#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2141#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2142#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2143#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2144#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2145#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2146#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2147#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2148#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2149#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2150#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2151#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2152#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2153#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2154#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2155#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2156#define WREG32_P(reg, val, mask) \
2157 do { \
2158 uint32_t tmp_ = RREG32(reg); \
2159 tmp_ &= (mask); \
2160 tmp_ |= ((val) & ~(mask)); \
2161 WREG32(reg, tmp_); \
2162 } while (0)
2163#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2164#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2165#define WREG32_PLL_P(reg, val, mask) \
2166 do { \
2167 uint32_t tmp_ = RREG32_PLL(reg); \
2168 tmp_ &= (mask); \
2169 tmp_ |= ((val) & ~(mask)); \
2170 WREG32_PLL(reg, tmp_); \
2171 } while (0)
2172#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2173#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2174#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2175
2176#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2177#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2178
2179#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2180#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2181
2182#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2183 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2184 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2185
2186#define REG_GET_FIELD(value, reg, field) \
2187 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2188
2189/*
2190 * BIOS helpers.
2191 */
2192#define RBIOS8(i) (adev->bios[i])
2193#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2194#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2195
2196/*
2197 * RING helpers.
2198 */
2199static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2200{
2201 if (ring->count_dw <= 0)
86c2b790 2202 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2203 ring->ring[ring->wptr++] = v;
2204 ring->wptr &= ring->ptr_mask;
2205 ring->count_dw--;
2206 ring->ring_free_dw--;
2207}
2208
c113ea1c
AD		 2209static inline struct amdgpu_sdma_instance *
2210amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2211{
2212 struct amdgpu_device *adev = ring->adev;
2213 int i;
2214
c113ea1c
AD		 2215 for (i = 0; i < adev->sdma.num_instances; i++)
2216 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2217 break;
2218
2219 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2220 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2221 else
2222 return NULL;
2223}
2224
97b2e202
AD		 2225/*
2226 * ASICs macro.
2227 */
2228#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2229#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2230#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2231#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2232#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2233#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2234#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2235#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2236#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2237#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2238#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2239#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2240#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2241#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2242#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2243#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2244#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2245#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2246#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2247#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2248#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2249#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2250#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2251#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2252#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2253#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2254#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2255#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2256#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2257#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2258#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2259#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2260#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2261#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2262#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2263#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2264#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2265#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2266#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2267#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2268#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2269#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2270#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2271#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2272#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2273#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2274#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2275#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2276#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2277#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2278#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2279#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2280#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2281#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2282#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2283#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2284#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2285
2286#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2287 ((adev)->pp_enabled ? \
e61710c5 2288 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2289 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2290
2291#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2292 ((adev)->pp_enabled ? \
e61710c5 2293 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2294 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2295
2296#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2297 ((adev)->pp_enabled ? \
e61710c5 2298 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2299 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2300
2301#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2302 ((adev)->pp_enabled ? \
e61710c5 2303 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2304 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2305
2306#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2307 ((adev)->pp_enabled ? \
e61710c5 2308 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2309 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2310
1b5708ff 2311#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2312 ((adev)->pp_enabled ? \
e61710c5 2313 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2314 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2315
2316#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2317 ((adev)->pp_enabled ? \
e61710c5 2318 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2319 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2320
2321
2322#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2323 ((adev)->pp_enabled ? \
e61710c5 2324 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2325 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2326
2327#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2328 ((adev)->pp_enabled ? \
e61710c5 2329 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2330 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2331
2332#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2333 ((adev)->pp_enabled ? \
e61710c5 2334 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2335 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2336
2337#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2338 ((adev)->pp_enabled ? \
e61710c5 2339 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2340 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2341
2342#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2343 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2344
2345#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2346 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2347
e61710c5 2348#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2349 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2350
2351#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2352
2353/* Common functions */
2354int amdgpu_gpu_reset(struct amdgpu_device *adev);
2355void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2356bool amdgpu_card_posted(struct amdgpu_device *adev);
2357void amdgpu_update_display_priority(struct amdgpu_device *adev);
2358bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82 2359
97b2e202
AD		 2360int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2361int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2362 u32 ip_instance, u32 ring,
2363 struct amdgpu_ring **out_ring);
2364void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2365bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2366int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2367 uint32_t flags);
2368bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
d7006964
CK		 2369bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2370 unsigned long end);
97b2e202
AD		 2371bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2372uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2373 struct ttm_mem_reg *mem);
2374void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2375void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2376void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2377void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2378 const u32 *registers,
2379 const u32 array_size);
2380
2381bool amdgpu_device_is_px(struct drm_device *dev);
2382/* atpx handler */
2383#if defined(CONFIG_VGA_SWITCHEROO)
2384void amdgpu_register_atpx_handler(void);
2385void amdgpu_unregister_atpx_handler(void);
2386#else
2387static inline void amdgpu_register_atpx_handler(void) {}
2388static inline void amdgpu_unregister_atpx_handler(void) {}
2389#endif
2390
2391/*
2392 * KMS
2393 */
2394extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2395extern int amdgpu_max_kms_ioctl;
2396
2397int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2398int amdgpu_driver_unload_kms(struct drm_device *dev);
2399void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2400int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2401void amdgpu_driver_postclose_kms(struct drm_device *dev,
2402 struct drm_file *file_priv);
2403void amdgpu_driver_preclose_kms(struct drm_device *dev,
2404 struct drm_file *file_priv);
2405int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2406int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2407u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2408int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2409void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2410int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2411 int *max_error,
2412 struct timeval *vblank_time,
2413 unsigned flags);
2414long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2415 unsigned long arg);
2416
97b2e202
AD		 2417/*
2418 * functions used by amdgpu_encoder.c
2419 */
2420struct amdgpu_afmt_acr {
2421 u32 clock;
2422
2423 int n_32khz;
2424 int cts_32khz;
2425
2426 int n_44_1khz;
2427 int cts_44_1khz;
2428
2429 int n_48khz;
2430 int cts_48khz;
2431
2432};
2433
2434struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2435
2436/* amdgpu_acpi.c */
2437#if defined(CONFIG_ACPI)
2438int amdgpu_acpi_init(struct amdgpu_device *adev);
2439void amdgpu_acpi_fini(struct amdgpu_device *adev);
2440bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2441int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2442 u8 perf_req, bool advertise);
2443int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2444#else
2445static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2446static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2447#endif
2448
2449struct amdgpu_bo_va_mapping *
2450amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2451 uint64_t addr, struct amdgpu_bo **bo);
2452
2453#include "amdgpu_object.h"
2454
2455#endif
Linux kernel - Deliverables
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