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drm/amdgpu: remove the ring lock v2
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
97b2e202 56
b80d8475
AD		 57#include "gpu_scheduler.h"
58
97b2e202
AD		 59/*
60 * Modules parameters.
61 */
62extern int amdgpu_modeset;
63extern int amdgpu_vram_limit;
64extern int amdgpu_gart_size;
65extern int amdgpu_benchmarking;
66extern int amdgpu_testing;
67extern int amdgpu_audio;
68extern int amdgpu_disp_priority;
69extern int amdgpu_hw_i2c;
70extern int amdgpu_pcie_gen2;
71extern int amdgpu_msi;
72extern int amdgpu_lockup_timeout;
73extern int amdgpu_dpm;
74extern int amdgpu_smc_load_fw;
75extern int amdgpu_aspm;
76extern int amdgpu_runtime_pm;
97b2e202
AD		 77extern unsigned amdgpu_ip_block_mask;
78extern int amdgpu_bapm;
79extern int amdgpu_deep_color;
80extern int amdgpu_vm_size;
81extern int amdgpu_vm_block_size;
d9c13156 82extern int amdgpu_vm_fault_stop;
b495bd3a 83extern int amdgpu_vm_debug;
1333f723 84extern int amdgpu_sched_jobs;
4afcb303 85extern int amdgpu_sched_hw_submission;
1f7371b2 86extern int amdgpu_powerplay;
97b2e202 87
4b559c90 88#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 89#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
90#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
91/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
92#define AMDGPU_IB_POOL_SIZE 16
93#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
94#define AMDGPUFB_CONN_LIMIT 4
95#define AMDGPU_BIOS_NUM_SCRATCH 8
96
97b2e202
AD		 97/* max number of rings */
98#define AMDGPU_MAX_RINGS 16
99#define AMDGPU_MAX_GFX_RINGS 1
100#define AMDGPU_MAX_COMPUTE_RINGS 8
101#define AMDGPU_MAX_VCE_RINGS 2
102
36f523a7
JZ		 103/* max number of IP instances */
104#define AMDGPU_MAX_SDMA_INSTANCES 2
105
97b2e202
AD		 106/* number of hw syncs before falling back on blocking */
107#define AMDGPU_NUM_SYNCS 4
108
109/* hardcode that limit for now */
110#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
111
112/* hard reset data */
113#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114
115/* reset flags */
116#define AMDGPU_RESET_GFX (1 << 0)
117#define AMDGPU_RESET_COMPUTE (1 << 1)
118#define AMDGPU_RESET_DMA (1 << 2)
119#define AMDGPU_RESET_CP (1 << 3)
120#define AMDGPU_RESET_GRBM (1 << 4)
121#define AMDGPU_RESET_DMA1 (1 << 5)
122#define AMDGPU_RESET_RLC (1 << 6)
123#define AMDGPU_RESET_SEM (1 << 7)
124#define AMDGPU_RESET_IH (1 << 8)
125#define AMDGPU_RESET_VMC (1 << 9)
126#define AMDGPU_RESET_MC (1 << 10)
127#define AMDGPU_RESET_DISPLAY (1 << 11)
128#define AMDGPU_RESET_UVD (1 << 12)
129#define AMDGPU_RESET_VCE (1 << 13)
130#define AMDGPU_RESET_VCE1 (1 << 14)
131
132/* CG block flags */
133#define AMDGPU_CG_BLOCK_GFX (1 << 0)
134#define AMDGPU_CG_BLOCK_MC (1 << 1)
135#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
136#define AMDGPU_CG_BLOCK_UVD (1 << 3)
137#define AMDGPU_CG_BLOCK_VCE (1 << 4)
138#define AMDGPU_CG_BLOCK_HDP (1 << 5)
139#define AMDGPU_CG_BLOCK_BIF (1 << 6)
140
141/* CG flags */
142#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
143#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
144#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
145#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
146#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
147#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
148#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
149#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
150#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
151#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
152#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
153#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
154#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
155#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
156#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
157#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
158#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
159
160/* PG flags */
161#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
162#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
163#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
164#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
165#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
166#define AMDGPU_PG_SUPPORT_CP (1 << 5)
167#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
168#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
169#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
170#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
171#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
172
173/* GFX current status */
174#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
175#define AMDGPU_GFX_SAFE_MODE 0x00000001L
176#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
177#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
178#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
179
180/* max cursor sizes (in pixels) */
181#define CIK_CURSOR_WIDTH 128
182#define CIK_CURSOR_HEIGHT 128
183
184struct amdgpu_device;
185struct amdgpu_fence;
186struct amdgpu_ib;
187struct amdgpu_vm;
188struct amdgpu_ring;
97b2e202 189struct amdgpu_cs_parser;
bb977d37 190struct amdgpu_job;
97b2e202 191struct amdgpu_irq_src;
0b492a4c 192struct amdgpu_fpriv;
97b2e202
AD		 193
194enum amdgpu_cp_irq {
195 AMDGPU_CP_IRQ_GFX_EOP = 0,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
204
205 AMDGPU_CP_IRQ_LAST
206};
207
208enum amdgpu_sdma_irq {
209 AMDGPU_SDMA_IRQ_TRAP0 = 0,
210 AMDGPU_SDMA_IRQ_TRAP1,
211
212 AMDGPU_SDMA_IRQ_LAST
213};
214
215enum amdgpu_thermal_irq {
216 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
217 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
218
219 AMDGPU_THERMAL_IRQ_LAST
220};
221
97b2e202 222int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 223 enum amd_ip_block_type block_type,
224 enum amd_clockgating_state state);
97b2e202 225int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 226 enum amd_ip_block_type block_type,
227 enum amd_powergating_state state);
97b2e202
AD		 228
229struct amdgpu_ip_block_version {
5fc3aeeb 230 enum amd_ip_block_type type;
97b2e202
AD		 231 u32 major;
232 u32 minor;
233 u32 rev;
5fc3aeeb 234 const struct amd_ip_funcs *funcs;
97b2e202
AD		 235};
236
237int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 238 enum amd_ip_block_type type,
97b2e202
AD		 239 u32 major, u32 minor);
240
241const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
242 struct amdgpu_device *adev,
5fc3aeeb 243 enum amd_ip_block_type type);
97b2e202
AD		 244
245/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
246struct amdgpu_buffer_funcs {
247 /* maximum bytes in a single operation */
248 uint32_t copy_max_bytes;
249
250 /* number of dw to reserve per operation */
251 unsigned copy_num_dw;
252
253 /* used for buffer migration */
c7ae72c0 254 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 255 /* src addr in bytes */
256 uint64_t src_offset,
257 /* dst addr in bytes */
258 uint64_t dst_offset,
259 /* number of byte to transfer */
260 uint32_t byte_count);
261
262 /* maximum bytes in a single operation */
263 uint32_t fill_max_bytes;
264
265 /* number of dw to reserve per operation */
266 unsigned fill_num_dw;
267
268 /* used for buffer clearing */
6e7a3840 269 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 270 /* value to write to memory */
271 uint32_t src_data,
272 /* dst addr in bytes */
273 uint64_t dst_offset,
274 /* number of byte to fill */
275 uint32_t byte_count);
276};
277
278/* provided by hw blocks that can write ptes, e.g., sdma */
279struct amdgpu_vm_pte_funcs {
280 /* copy pte entries from GART */
281 void (*copy_pte)(struct amdgpu_ib *ib,
282 uint64_t pe, uint64_t src,
283 unsigned count);
284 /* write pte one entry at a time with addr mapping */
285 void (*write_pte)(struct amdgpu_ib *ib,
286 uint64_t pe,
287 uint64_t addr, unsigned count,
288 uint32_t incr, uint32_t flags);
289 /* for linear pte/pde updates without addr mapping */
290 void (*set_pte_pde)(struct amdgpu_ib *ib,
291 uint64_t pe,
292 uint64_t addr, unsigned count,
293 uint32_t incr, uint32_t flags);
294 /* pad the indirect buffer to the necessary number of dw */
295 void (*pad_ib)(struct amdgpu_ib *ib);
296};
297
298/* provided by the gmc block */
299struct amdgpu_gart_funcs {
300 /* flush the vm tlb via mmio */
301 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
302 uint32_t vmid);
303 /* write pte/pde updates using the cpu */
304 int (*set_pte_pde)(struct amdgpu_device *adev,
305 void *cpu_pt_addr, /* cpu addr of page table */
306 uint32_t gpu_page_idx, /* pte/pde to update */
307 uint64_t addr, /* addr to write into pte/pde */
308 uint32_t flags); /* access flags */
309};
310
311/* provided by the ih block */
312struct amdgpu_ih_funcs {
313 /* ring read/write ptr handling, called from interrupt context */
314 u32 (*get_wptr)(struct amdgpu_device *adev);
315 void (*decode_iv)(struct amdgpu_device *adev,
316 struct amdgpu_iv_entry *entry);
317 void (*set_rptr)(struct amdgpu_device *adev);
318};
319
320/* provided by hw blocks that expose a ring buffer for commands */
321struct amdgpu_ring_funcs {
322 /* ring read/write ptr handling */
323 u32 (*get_rptr)(struct amdgpu_ring *ring);
324 u32 (*get_wptr)(struct amdgpu_ring *ring);
325 void (*set_wptr)(struct amdgpu_ring *ring);
326 /* validating and patching of IBs */
327 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
328 /* command emit functions */
329 void (*emit_ib)(struct amdgpu_ring *ring,
330 struct amdgpu_ib *ib);
331 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 332 uint64_t seq, unsigned flags);
97b2e202
AD		 333 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
334 uint64_t pd_addr);
d2edb07b 335 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 336 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
337 uint32_t gds_base, uint32_t gds_size,
338 uint32_t gws_base, uint32_t gws_size,
339 uint32_t oa_base, uint32_t oa_size);
340 /* testing functions */
341 int (*test_ring)(struct amdgpu_ring *ring);
342 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 343 /* insert NOP packets */
344 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
97b2e202
AD		 345};
346
347/*
348 * BIOS.
349 */
350bool amdgpu_get_bios(struct amdgpu_device *adev);
351bool amdgpu_read_bios(struct amdgpu_device *adev);
352
353/*
354 * Dummy page
355 */
356struct amdgpu_dummy_page {
357 struct page *page;
358 dma_addr_t addr;
359};
360int amdgpu_dummy_page_init(struct amdgpu_device *adev);
361void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
362
363
364/*
365 * Clocks
366 */
367
368#define AMDGPU_MAX_PPLL 3
369
370struct amdgpu_clock {
371 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
372 struct amdgpu_pll spll;
373 struct amdgpu_pll mpll;
374 /* 10 Khz units */
375 uint32_t default_mclk;
376 uint32_t default_sclk;
377 uint32_t default_dispclk;
378 uint32_t current_dispclk;
379 uint32_t dp_extclk;
380 uint32_t max_pixel_clock;
381};
382
383/*
384 * Fences.
385 */
386struct amdgpu_fence_driver {
97b2e202
AD		 387 uint64_t gpu_addr;
388 volatile uint32_t *cpu_addr;
389 /* sync_seq is protected by ring emission lock */
5907a0d8 390 uint64_t sync_seq;
97b2e202
AD		 391 atomic64_t last_seq;
392 bool initialized;
97b2e202
AD		 393 struct amdgpu_irq_src *irq_src;
394 unsigned irq_type;
c2776afe 395 struct timer_list fallback_timer;
7f06c236 396 wait_queue_head_t fence_queue;
97b2e202
AD		 397};
398
399/* some special values for the owner field */
400#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
401#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 402
890ee23f
CZ		 403#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
404#define AMDGPU_FENCE_FLAG_INT (1 << 1)
405
97b2e202
AD		 406struct amdgpu_fence {
407 struct fence base;
4cef9267 408
97b2e202
AD		 409 /* RB, DMA, etc. */
410 struct amdgpu_ring *ring;
411 uint64_t seq;
412
413 /* filp or special value for fence creator */
414 void *owner;
415
416 wait_queue_t fence_wake;
417};
418
419struct amdgpu_user_fence {
420 /* write-back bo */
421 struct amdgpu_bo *bo;
422 /* write-back address offset to bo start */
423 uint32_t offset;
424};
425
426int amdgpu_fence_driver_init(struct amdgpu_device *adev);
427void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
428void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
429
4f839a24 430int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 431int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
432 struct amdgpu_irq_src *irq_src,
433 unsigned irq_type);
5ceb54c6
AD		 434void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
435void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 436int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
437 struct amdgpu_fence **fence);
438void amdgpu_fence_process(struct amdgpu_ring *ring);
439int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
440int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
441unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
442
97b2e202
AD		 443/*
444 * TTM.
445 */
446struct amdgpu_mman {
447 struct ttm_bo_global_ref bo_global_ref;
448 struct drm_global_reference mem_global_ref;
449 struct ttm_bo_device bdev;
450 bool mem_global_referenced;
451 bool initialized;
452
453#if defined(CONFIG_DEBUG_FS)
454 struct dentry *vram;
455 struct dentry *gtt;
456#endif
457
458 /* buffer handling */
459 const struct amdgpu_buffer_funcs *buffer_funcs;
460 struct amdgpu_ring *buffer_funcs_ring;
461};
462
463int amdgpu_copy_buffer(struct amdgpu_ring *ring,
464 uint64_t src_offset,
465 uint64_t dst_offset,
466 uint32_t byte_count,
467 struct reservation_object *resv,
c7ae72c0 468 struct fence **fence);
97b2e202
AD		 469int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
470
471struct amdgpu_bo_list_entry {
472 struct amdgpu_bo *robj;
473 struct ttm_validate_buffer tv;
474 struct amdgpu_bo_va *bo_va;
97b2e202
AD		 475 uint32_t priority;
476};
477
478struct amdgpu_bo_va_mapping {
479 struct list_head list;
480 struct interval_tree_node it;
481 uint64_t offset;
482 uint32_t flags;
483};
484
485/* bo virtual addresses in a specific vm */
486struct amdgpu_bo_va {
69b576a1 487 struct mutex mutex;
97b2e202
AD		 488 /* protected by bo being reserved */
489 struct list_head bo_list;
bb1e38a4 490 struct fence *last_pt_update;
97b2e202
AD		 491 unsigned ref_count;
492
7fc11959 493 /* protected by vm mutex and spinlock */
97b2e202
AD		 494 struct list_head vm_status;
495
7fc11959
CK		 496 /* mappings for this bo_va */
497 struct list_head invalids;
498 struct list_head valids;
499
97b2e202
AD		 500 /* constant after initialization */
501 struct amdgpu_vm *vm;
502 struct amdgpu_bo *bo;
503};
504
7e5a547f
CZ		 505#define AMDGPU_GEM_DOMAIN_MAX 0x3
506
97b2e202
AD		 507struct amdgpu_bo {
508 /* Protected by gem.mutex */
509 struct list_head list;
510 /* Protected by tbo.reserved */
1ea863fd
CK		 511 u32 prefered_domains;
512 u32 allowed_domains;
7e5a547f 513 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 514 struct ttm_placement placement;
515 struct ttm_buffer_object tbo;
516 struct ttm_bo_kmap_obj kmap;
517 u64 flags;
518 unsigned pin_count;
519 void *kptr;
520 u64 tiling_flags;
521 u64 metadata_flags;
522 void *metadata;
523 u32 metadata_size;
524 /* list of all virtual address to which this bo
525 * is associated to
526 */
527 struct list_head va;
528 /* Constant after initialization */
529 struct amdgpu_device *adev;
530 struct drm_gem_object gem_base;
82b9c55b 531 struct amdgpu_bo *parent;
97b2e202
AD		 532
533 struct ttm_bo_kmap_obj dma_buf_vmap;
534 pid_t pid;
535 struct amdgpu_mn *mn;
536 struct list_head mn_list;
537};
538#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
539
540void amdgpu_gem_object_free(struct drm_gem_object *obj);
541int amdgpu_gem_object_open(struct drm_gem_object *obj,
542 struct drm_file *file_priv);
543void amdgpu_gem_object_close(struct drm_gem_object *obj,
544 struct drm_file *file_priv);
545unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
546struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
547struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
548 struct dma_buf_attachment *attach,
549 struct sg_table *sg);
550struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
551 struct drm_gem_object *gobj,
552 int flags);
553int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
554void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
555struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
556void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
557void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
558int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
559
560/* sub-allocation manager, it has to be protected by another lock.
561 * By conception this is an helper for other part of the driver
562 * like the indirect buffer or semaphore, which both have their
563 * locking.
564 *
565 * Principe is simple, we keep a list of sub allocation in offset
566 * order (first entry has offset == 0, last entry has the highest
567 * offset).
568 *
569 * When allocating new object we first check if there is room at
570 * the end total_size - (last_object_offset + last_object_size) >=
571 * alloc_size. If so we allocate new object there.
572 *
573 * When there is not enough room at the end, we start waiting for
574 * each sub object until we reach object_offset+object_size >=
575 * alloc_size, this object then become the sub object we return.
576 *
577 * Alignment can't be bigger than page size.
578 *
579 * Hole are not considered for allocation to keep things simple.
580 * Assumption is that there won't be hole (all object on same
581 * alignment).
582 */
583struct amdgpu_sa_manager {
584 wait_queue_head_t wq;
585 struct amdgpu_bo *bo;
586 struct list_head *hole;
587 struct list_head flist[AMDGPU_MAX_RINGS];
588 struct list_head olist;
589 unsigned size;
590 uint64_t gpu_addr;
591 void *cpu_ptr;
592 uint32_t domain;
593 uint32_t align;
594};
595
596struct amdgpu_sa_bo;
597
598/* sub-allocation buffer */
599struct amdgpu_sa_bo {
600 struct list_head olist;
601 struct list_head flist;
602 struct amdgpu_sa_manager *manager;
603 unsigned soffset;
604 unsigned eoffset;
4ce9891e 605 struct fence *fence;
97b2e202
AD		 606};
607
608/*
609 * GEM objects.
610 */
611struct amdgpu_gem {
612 struct mutex mutex;
613 struct list_head objects;
614};
615
616int amdgpu_gem_init(struct amdgpu_device *adev);
617void amdgpu_gem_fini(struct amdgpu_device *adev);
618int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
619 int alignment, u32 initial_domain,
620 u64 flags, bool kernel,
621 struct drm_gem_object **obj);
622
623int amdgpu_mode_dumb_create(struct drm_file *file_priv,
624 struct drm_device *dev,
625 struct drm_mode_create_dumb *args);
626int amdgpu_mode_dumb_mmap(struct drm_file *filp,
627 struct drm_device *dev,
628 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 629/*
630 * Synchronization
631 */
632struct amdgpu_sync {
f91b3a69 633 DECLARE_HASHTABLE(fences, 4);
3c62338c 634 struct fence *last_vm_update;
97b2e202
AD		 635};
636
637void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 638int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
639 struct fence *f);
97b2e202
AD		 640int amdgpu_sync_resv(struct amdgpu_device *adev,
641 struct amdgpu_sync *sync,
642 struct reservation_object *resv,
643 void *owner);
e61235db 644struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 645int amdgpu_sync_wait(struct amdgpu_sync *sync);
97b2e202 646void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
4ce9891e 647 struct fence *fence);
97b2e202
AD		 648
649/*
650 * GART structures, functions & helpers
651 */
652struct amdgpu_mc;
653
654#define AMDGPU_GPU_PAGE_SIZE 4096
655#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
656#define AMDGPU_GPU_PAGE_SHIFT 12
657#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
658
659struct amdgpu_gart {
660 dma_addr_t table_addr;
661 struct amdgpu_bo *robj;
662 void *ptr;
663 unsigned num_gpu_pages;
664 unsigned num_cpu_pages;
665 unsigned table_size;
666 struct page **pages;
667 dma_addr_t *pages_addr;
668 bool ready;
669 const struct amdgpu_gart_funcs *gart_funcs;
670};
671
672int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
673void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
674int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
675void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
676int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
677void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
678int amdgpu_gart_init(struct amdgpu_device *adev);
679void amdgpu_gart_fini(struct amdgpu_device *adev);
680void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
681 int pages);
682int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
683 int pages, struct page **pagelist,
684 dma_addr_t *dma_addr, uint32_t flags);
685
686/*
687 * GPU MC structures, functions & helpers
688 */
689struct amdgpu_mc {
690 resource_size_t aper_size;
691 resource_size_t aper_base;
692 resource_size_t agp_base;
693 /* for some chips with <= 32MB we need to lie
694 * about vram size near mc fb location */
695 u64 mc_vram_size;
696 u64 visible_vram_size;
697 u64 gtt_size;
698 u64 gtt_start;
699 u64 gtt_end;
700 u64 vram_start;
701 u64 vram_end;
702 unsigned vram_width;
703 u64 real_vram_size;
704 int vram_mtrr;
705 u64 gtt_base_align;
706 u64 mc_mask;
707 const struct firmware *fw; /* MC firmware */
708 uint32_t fw_version;
709 struct amdgpu_irq_src vm_fault;
81c59f54 710 uint32_t vram_type;
97b2e202
AD		 711};
712
713/*
714 * GPU doorbell structures, functions & helpers
715 */
716typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
717{
718 AMDGPU_DOORBELL_KIQ = 0x000,
719 AMDGPU_DOORBELL_HIQ = 0x001,
720 AMDGPU_DOORBELL_DIQ = 0x002,
721 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
722 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
723 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
724 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
725 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
726 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
727 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
728 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
729 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
730 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
731 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
732 AMDGPU_DOORBELL_IH = 0x1E8,
733 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
734 AMDGPU_DOORBELL_INVALID = 0xFFFF
735} AMDGPU_DOORBELL_ASSIGNMENT;
736
737struct amdgpu_doorbell {
738 /* doorbell mmio */
739 resource_size_t base;
740 resource_size_t size;
741 u32 __iomem *ptr;
742 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
743};
744
745void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
746 phys_addr_t *aperture_base,
747 size_t *aperture_size,
748 size_t *start_offset);
749
750/*
751 * IRQS.
752 */
753
754struct amdgpu_flip_work {
755 struct work_struct flip_work;
756 struct work_struct unpin_work;
757 struct amdgpu_device *adev;
758 int crtc_id;
759 uint64_t base;
760 struct drm_pending_vblank_event *event;
761 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 762 struct fence *excl;
763 unsigned shared_count;
764 struct fence **shared;
97b2e202
AD		 765};
766
767
768/*
769 * CP & rings.
770 */
771
772struct amdgpu_ib {
773 struct amdgpu_sa_bo *sa_bo;
774 uint32_t length_dw;
775 uint64_t gpu_addr;
776 uint32_t *ptr;
777 struct amdgpu_ring *ring;
778 struct amdgpu_fence *fence;
779 struct amdgpu_user_fence *user;
8d0a7cea 780 bool grabbed_vmid;
97b2e202 781 struct amdgpu_vm *vm;
3cb485f3 782 struct amdgpu_ctx *ctx;
97b2e202 783 struct amdgpu_sync sync;
97b2e202
AD		 784 uint32_t gds_base, gds_size;
785 uint32_t gws_base, gws_size;
786 uint32_t oa_base, oa_size;
de807f81 787 uint32_t flags;
5430a3ff
CK		 788 /* resulting sequence number */
789 uint64_t sequence;
97b2e202
AD		 790};
791
792enum amdgpu_ring_type {
793 AMDGPU_RING_TYPE_GFX,
794 AMDGPU_RING_TYPE_COMPUTE,
795 AMDGPU_RING_TYPE_SDMA,
796 AMDGPU_RING_TYPE_UVD,
797 AMDGPU_RING_TYPE_VCE
798};
799
c1b69ed0
CZ		 800extern struct amd_sched_backend_ops amdgpu_sched_ops;
801
3c704e93
CZ		 802int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
803 struct amdgpu_ring *ring,
804 struct amdgpu_ib *ibs,
805 unsigned num_ibs,
bb977d37 806 int (*free_job)(struct amdgpu_job *),
1763552e
CZ		 807 void *owner,
808 struct fence **fence);
3c704e93 809
97b2e202
AD		 810struct amdgpu_ring {
811 struct amdgpu_device *adev;
812 const struct amdgpu_ring_funcs *funcs;
813 struct amdgpu_fence_driver fence_drv;
4f839a24 814 struct amd_gpu_scheduler sched;
97b2e202 815
176e1ab1 816 spinlock_t fence_lock;
97b2e202
AD		 817 struct amdgpu_bo *ring_obj;
818 volatile uint32_t *ring;
819 unsigned rptr_offs;
820 u64 next_rptr_gpu_addr;
821 volatile u32 *next_rptr_cpu_addr;
822 unsigned wptr;
823 unsigned wptr_old;
824 unsigned ring_size;
825 unsigned ring_free_dw;
826 int count_dw;
97b2e202
AD		 827 uint64_t gpu_addr;
828 uint32_t align_mask;
829 uint32_t ptr_mask;
830 bool ready;
831 u32 nop;
832 u32 idx;
97b2e202
AD		 833 u32 me;
834 u32 pipe;
835 u32 queue;
836 struct amdgpu_bo *mqd_obj;
837 u32 doorbell_index;
838 bool use_doorbell;
839 unsigned wptr_offs;
840 unsigned next_rptr_offs;
841 unsigned fence_offs;
3cb485f3 842 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 843 enum amdgpu_ring_type type;
844 char name[16];
4274f5d4 845 bool is_pte_ring;
97b2e202
AD		 846};
847
848/*
849 * VM
850 */
851
852/* maximum number of VMIDs */
853#define AMDGPU_NUM_VM 16
854
855/* number of entries in page table */
856#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
857
858/* PTBs (Page Table Blocks) need to be aligned to 32K */
859#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
860#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
861#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
862
863#define AMDGPU_PTE_VALID (1 << 0)
864#define AMDGPU_PTE_SYSTEM (1 << 1)
865#define AMDGPU_PTE_SNOOPED (1 << 2)
866
867/* VI only */
868#define AMDGPU_PTE_EXECUTABLE (1 << 4)
869
870#define AMDGPU_PTE_READABLE (1 << 5)
871#define AMDGPU_PTE_WRITEABLE (1 << 6)
872
873/* PTE (Page Table Entry) fragment field for different page sizes */
874#define AMDGPU_PTE_FRAG_4KB (0 << 7)
875#define AMDGPU_PTE_FRAG_64KB (4 << 7)
876#define AMDGPU_LOG2_PAGES_PER_FRAG 4
877
d9c13156
CK		 878/* How to programm VM fault handling */
879#define AMDGPU_VM_FAULT_STOP_NEVER 0
880#define AMDGPU_VM_FAULT_STOP_FIRST 1
881#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
882
97b2e202 883struct amdgpu_vm_pt {
ee1782c3
CK		 884 struct amdgpu_bo_list_entry entry;
885 uint64_t addr;
97b2e202
AD		 886};
887
888struct amdgpu_vm_id {
889 unsigned id;
890 uint64_t pd_gpu_addr;
891 /* last flushed PD/PT update */
3c62338c 892 struct fence *flushed_updates;
97b2e202
AD		 893};
894
895struct amdgpu_vm {
25cfc3c2
CK		 896 /* tree of virtual addresses mapped */
897 spinlock_t it_lock;
97b2e202
AD		 898 struct rb_root va;
899
7fc11959 900 /* protecting invalidated */
97b2e202
AD		 901 spinlock_t status_lock;
902
903 /* BOs moved, but not yet updated in the PT */
904 struct list_head invalidated;
905
7fc11959
CK		 906 /* BOs cleared in the PT because of a move */
907 struct list_head cleared;
908
909 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 910 struct list_head freed;
911
912 /* contains the page directory */
913 struct amdgpu_bo *page_directory;
914 unsigned max_pde_used;
05906dec 915 struct fence *page_directory_fence;
97b2e202
AD		 916
917 /* array of page tables, one for each page directory entry */
918 struct amdgpu_vm_pt *page_tables;
919
920 /* for id and flush management per ring */
921 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 922
81d75a30 923 /* protecting freed */
924 spinlock_t freed_lock;
97b2e202
AD		 925};
926
a9a78b32
CK		 927struct amdgpu_vm_manager_id {
928 struct list_head list;
929 struct fence *active;
930 atomic_long_t owner;
931};
932
97b2e202 933struct amdgpu_vm_manager {
a9a78b32 934 /* Handling of VMIDs */
8d0a7cea 935 struct mutex lock;
a9a78b32
CK		 936 unsigned num_ids;
937 struct list_head ids_lru;
938 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM];
1c16c0a7 939
8b4fb00b 940 uint32_t max_pfn;
97b2e202 941 /* vram base address for page table entry */
8b4fb00b 942 u64 vram_base_offset;
97b2e202 943 /* is vm enabled? */
8b4fb00b 944 bool enabled;
97b2e202
AD		 945 /* vm pte handling */
946 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
947 struct amdgpu_ring *vm_pte_funcs_ring;
948};
949
a9a78b32 950void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 951void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 952int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
953void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 954void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
955 struct list_head *validated,
956 struct amdgpu_bo_list_entry *entry);
ee1782c3 957void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 958void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
959 struct amdgpu_vm *vm);
8b4fb00b 960int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
94dd0a4a 961 struct amdgpu_sync *sync, struct fence *fence);
8b4fb00b
CK		 962void amdgpu_vm_flush(struct amdgpu_ring *ring,
963 struct amdgpu_vm *vm,
964 struct fence *updates);
8b4fb00b
CK		 965uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
966int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
967 struct amdgpu_vm *vm);
968int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
969 struct amdgpu_vm *vm);
970int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
971 struct amdgpu_sync *sync);
972int amdgpu_vm_bo_update(struct amdgpu_device *adev,
973 struct amdgpu_bo_va *bo_va,
974 struct ttm_mem_reg *mem);
975void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
976 struct amdgpu_bo *bo);
977struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
978 struct amdgpu_bo *bo);
979struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
980 struct amdgpu_vm *vm,
981 struct amdgpu_bo *bo);
982int amdgpu_vm_bo_map(struct amdgpu_device *adev,
983 struct amdgpu_bo_va *bo_va,
984 uint64_t addr, uint64_t offset,
985 uint64_t size, uint32_t flags);
986int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
987 struct amdgpu_bo_va *bo_va,
988 uint64_t addr);
989void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
990 struct amdgpu_bo_va *bo_va);
991int amdgpu_vm_free_job(struct amdgpu_job *job);
992
97b2e202
AD		 993/*
994 * context related structures
995 */
996
21c16bf6 997struct amdgpu_ctx_ring {
91404fb2 998 uint64_t sequence;
37cd0ca2 999 struct fence **fences;
91404fb2 1000 struct amd_sched_entity entity;
21c16bf6
CK		 1001};
1002
97b2e202 1003struct amdgpu_ctx {
0b492a4c 1004 struct kref refcount;
9cb7e5a9 1005 struct amdgpu_device *adev;
0b492a4c 1006 unsigned reset_counter;
21c16bf6 1007 spinlock_t ring_lock;
37cd0ca2 1008 struct fence **fences;
21c16bf6 1009 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1010};
1011
1012struct amdgpu_ctx_mgr {
0b492a4c
AD		 1013 struct amdgpu_device *adev;
1014 struct mutex lock;
1015 /* protected by lock */
1016 struct idr ctx_handles;
97b2e202
AD		 1017};
1018
d033a6de 1019int amdgpu_ctx_init(struct amdgpu_device *adev, enum amd_sched_priority pri,
47f38501
CK		 1020 struct amdgpu_ctx *ctx);
1021void amdgpu_ctx_fini(struct amdgpu_ctx *ctx);
0b492a4c 1022
0b492a4c
AD		 1023struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1024int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1025
21c16bf6 1026uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1027 struct fence *fence);
21c16bf6
CK		 1028struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1029 struct amdgpu_ring *ring, uint64_t seq);
1030
0b492a4c
AD		 1031int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1032 struct drm_file *filp);
1033
efd4ccb5
CK		 1034void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1035void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1036
97b2e202
AD		 1037/*
1038 * file private structure
1039 */
1040
1041struct amdgpu_fpriv {
1042 struct amdgpu_vm vm;
1043 struct mutex bo_list_lock;
1044 struct idr bo_list_handles;
0b492a4c 1045 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1046};
1047
1048/*
1049 * residency list
1050 */
1051
1052struct amdgpu_bo_list {
1053 struct mutex lock;
1054 struct amdgpu_bo *gds_obj;
1055 struct amdgpu_bo *gws_obj;
1056 struct amdgpu_bo *oa_obj;
1057 bool has_userptr;
1058 unsigned num_entries;
1059 struct amdgpu_bo_list_entry *array;
1060};
1061
1062struct amdgpu_bo_list *
1063amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1064void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1065 struct list_head *validated);
97b2e202
AD		 1066void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1067void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1068
1069/*
1070 * GFX stuff
1071 */
1072#include "clearstate_defs.h"
1073
1074struct amdgpu_rlc {
1075 /* for power gating */
1076 struct amdgpu_bo *save_restore_obj;
1077 uint64_t save_restore_gpu_addr;
1078 volatile uint32_t *sr_ptr;
1079 const u32 *reg_list;
1080 u32 reg_list_size;
1081 /* for clear state */
1082 struct amdgpu_bo *clear_state_obj;
1083 uint64_t clear_state_gpu_addr;
1084 volatile uint32_t *cs_ptr;
1085 const struct cs_section_def *cs_data;
1086 u32 clear_state_size;
1087 /* for cp tables */
1088 struct amdgpu_bo *cp_table_obj;
1089 uint64_t cp_table_gpu_addr;
1090 volatile uint32_t *cp_table_ptr;
1091 u32 cp_table_size;
1092};
1093
1094struct amdgpu_mec {
1095 struct amdgpu_bo *hpd_eop_obj;
1096 u64 hpd_eop_gpu_addr;
1097 u32 num_pipe;
1098 u32 num_mec;
1099 u32 num_queue;
1100};
1101
1102/*
1103 * GPU scratch registers structures, functions & helpers
1104 */
1105struct amdgpu_scratch {
1106 unsigned num_reg;
1107 uint32_t reg_base;
1108 bool free[32];
1109 uint32_t reg[32];
1110};
1111
1112/*
1113 * GFX configurations
1114 */
1115struct amdgpu_gca_config {
1116 unsigned max_shader_engines;
1117 unsigned max_tile_pipes;
1118 unsigned max_cu_per_sh;
1119 unsigned max_sh_per_se;
1120 unsigned max_backends_per_se;
1121 unsigned max_texture_channel_caches;
1122 unsigned max_gprs;
1123 unsigned max_gs_threads;
1124 unsigned max_hw_contexts;
1125 unsigned sc_prim_fifo_size_frontend;
1126 unsigned sc_prim_fifo_size_backend;
1127 unsigned sc_hiz_tile_fifo_size;
1128 unsigned sc_earlyz_tile_fifo_size;
1129
1130 unsigned num_tile_pipes;
1131 unsigned backend_enable_mask;
1132 unsigned mem_max_burst_length_bytes;
1133 unsigned mem_row_size_in_kb;
1134 unsigned shader_engine_tile_size;
1135 unsigned num_gpus;
1136 unsigned multi_gpu_tile_size;
1137 unsigned mc_arb_ramcfg;
1138 unsigned gb_addr_config;
1139
1140 uint32_t tile_mode_array[32];
1141 uint32_t macrotile_mode_array[16];
1142};
1143
1144struct amdgpu_gfx {
1145 struct mutex gpu_clock_mutex;
1146 struct amdgpu_gca_config config;
1147 struct amdgpu_rlc rlc;
1148 struct amdgpu_mec mec;
1149 struct amdgpu_scratch scratch;
1150 const struct firmware *me_fw; /* ME firmware */
1151 uint32_t me_fw_version;
1152 const struct firmware *pfp_fw; /* PFP firmware */
1153 uint32_t pfp_fw_version;
1154 const struct firmware *ce_fw; /* CE firmware */
1155 uint32_t ce_fw_version;
1156 const struct firmware *rlc_fw; /* RLC firmware */
1157 uint32_t rlc_fw_version;
1158 const struct firmware *mec_fw; /* MEC firmware */
1159 uint32_t mec_fw_version;
1160 const struct firmware *mec2_fw; /* MEC2 firmware */
1161 uint32_t mec2_fw_version;
02558a00
KW		 1162 uint32_t me_feature_version;
1163 uint32_t ce_feature_version;
1164 uint32_t pfp_feature_version;
351643d7
JZ		 1165 uint32_t rlc_feature_version;
1166 uint32_t mec_feature_version;
1167 uint32_t mec2_feature_version;
97b2e202
AD		 1168 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1169 unsigned num_gfx_rings;
1170 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1171 unsigned num_compute_rings;
1172 struct amdgpu_irq_src eop_irq;
1173 struct amdgpu_irq_src priv_reg_irq;
1174 struct amdgpu_irq_src priv_inst_irq;
1175 /* gfx status */
1176 uint32_t gfx_current_status;
a101a899
KW		 1177 /* ce ram size*/
1178 unsigned ce_ram_size;
97b2e202
AD		 1179};
1180
1181int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1182 unsigned size, struct amdgpu_ib *ib);
1183void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1184int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1185 struct amdgpu_ib *ib, void *owner);
1186int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1187void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1188int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1189/* Ring access between begin & end cannot sleep */
1190void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1191int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1192void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
97b2e202 1193void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1194void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1195unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1196 uint32_t **data);
1197int amdgpu_ring_restore(struct amdgpu_ring *ring,
1198 unsigned size, uint32_t *data);
1199int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1200 unsigned ring_size, u32 nop, u32 align_mask,
1201 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1202 enum amdgpu_ring_type ring_type);
1203void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1204struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1205
1206/*
1207 * CS.
1208 */
1209struct amdgpu_cs_chunk {
1210 uint32_t chunk_id;
1211 uint32_t length_dw;
1212 uint32_t *kdata;
97b2e202
AD		 1213};
1214
1215struct amdgpu_cs_parser {
1216 struct amdgpu_device *adev;
1217 struct drm_file *filp;
3cb485f3 1218 struct amdgpu_ctx *ctx;
c3cca41e 1219
97b2e202
AD		 1220 /* chunks */
1221 unsigned nchunks;
1222 struct amdgpu_cs_chunk *chunks;
97b2e202 1223
c3cca41e 1224 /* indirect buffers */
97b2e202 1225 uint32_t num_ibs;
c3cca41e 1226 struct amdgpu_ib *ibs;
97b2e202 1227
c3cca41e
CK		 1228 /* buffer objects */
1229 struct ww_acquire_ctx ticket;
1230 struct amdgpu_bo_list *bo_list;
1231 struct amdgpu_bo_list_entry vm_pd;
1232 struct list_head validated;
1233 struct fence *fence;
1234 uint64_t bytes_moved_threshold;
1235 uint64_t bytes_moved;
97b2e202
AD		 1236
1237 /* user fence */
91acbeb6
CK		 1238 struct amdgpu_user_fence uf;
1239 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1240};
1241
bb977d37
CZ		 1242struct amdgpu_job {
1243 struct amd_sched_job base;
1244 struct amdgpu_device *adev;
bb977d37
CZ		 1245 struct amdgpu_ib *ibs;
1246 uint32_t num_ibs;
e2840221 1247 void *owner;
bb977d37 1248 struct amdgpu_user_fence uf;
4c7eb91c 1249 int (*free_job)(struct amdgpu_job *job);
bb977d37 1250};
a6db8a33
JZ		 1251#define to_amdgpu_job(sched_job) \
1252 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1253
97b2e202
AD		 1254static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1255{
1256 return p->ibs[ib_idx].ptr[idx];
1257}
1258
1259/*
1260 * Writeback
1261 */
1262#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1263
1264struct amdgpu_wb {
1265 struct amdgpu_bo *wb_obj;
1266 volatile uint32_t *wb;
1267 uint64_t gpu_addr;
1268 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1269 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1270};
1271
1272int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1273void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1274
97b2e202 1275
97b2e202
AD		 1276
1277enum amdgpu_int_thermal_type {
1278 THERMAL_TYPE_NONE,
1279 THERMAL_TYPE_EXTERNAL,
1280 THERMAL_TYPE_EXTERNAL_GPIO,
1281 THERMAL_TYPE_RV6XX,
1282 THERMAL_TYPE_RV770,
1283 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1284 THERMAL_TYPE_EVERGREEN,
1285 THERMAL_TYPE_SUMO,
1286 THERMAL_TYPE_NI,
1287 THERMAL_TYPE_SI,
1288 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1289 THERMAL_TYPE_CI,
1290 THERMAL_TYPE_KV,
1291};
1292
1293enum amdgpu_dpm_auto_throttle_src {
1294 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1295 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1296};
1297
1298enum amdgpu_dpm_event_src {
1299 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1300 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1301 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1302 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1303 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1304};
1305
1306#define AMDGPU_MAX_VCE_LEVELS 6
1307
1308enum amdgpu_vce_level {
1309 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1310 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1311 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1312 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1313 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1314 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1315};
1316
1317struct amdgpu_ps {
1318 u32 caps; /* vbios flags */
1319 u32 class; /* vbios flags */
1320 u32 class2; /* vbios flags */
1321 /* UVD clocks */
1322 u32 vclk;
1323 u32 dclk;
1324 /* VCE clocks */
1325 u32 evclk;
1326 u32 ecclk;
1327 bool vce_active;
1328 enum amdgpu_vce_level vce_level;
1329 /* asic priv */
1330 void *ps_priv;
1331};
1332
1333struct amdgpu_dpm_thermal {
1334 /* thermal interrupt work */
1335 struct work_struct work;
1336 /* low temperature threshold */
1337 int min_temp;
1338 /* high temperature threshold */
1339 int max_temp;
1340 /* was last interrupt low to high or high to low */
1341 bool high_to_low;
1342 /* interrupt source */
1343 struct amdgpu_irq_src irq;
1344};
1345
1346enum amdgpu_clk_action
1347{
1348 AMDGPU_SCLK_UP = 1,
1349 AMDGPU_SCLK_DOWN
1350};
1351
1352struct amdgpu_blacklist_clocks
1353{
1354 u32 sclk;
1355 u32 mclk;
1356 enum amdgpu_clk_action action;
1357};
1358
1359struct amdgpu_clock_and_voltage_limits {
1360 u32 sclk;
1361 u32 mclk;
1362 u16 vddc;
1363 u16 vddci;
1364};
1365
1366struct amdgpu_clock_array {
1367 u32 count;
1368 u32 *values;
1369};
1370
1371struct amdgpu_clock_voltage_dependency_entry {
1372 u32 clk;
1373 u16 v;
1374};
1375
1376struct amdgpu_clock_voltage_dependency_table {
1377 u32 count;
1378 struct amdgpu_clock_voltage_dependency_entry *entries;
1379};
1380
1381union amdgpu_cac_leakage_entry {
1382 struct {
1383 u16 vddc;
1384 u32 leakage;
1385 };
1386 struct {
1387 u16 vddc1;
1388 u16 vddc2;
1389 u16 vddc3;
1390 };
1391};
1392
1393struct amdgpu_cac_leakage_table {
1394 u32 count;
1395 union amdgpu_cac_leakage_entry *entries;
1396};
1397
1398struct amdgpu_phase_shedding_limits_entry {
1399 u16 voltage;
1400 u32 sclk;
1401 u32 mclk;
1402};
1403
1404struct amdgpu_phase_shedding_limits_table {
1405 u32 count;
1406 struct amdgpu_phase_shedding_limits_entry *entries;
1407};
1408
1409struct amdgpu_uvd_clock_voltage_dependency_entry {
1410 u32 vclk;
1411 u32 dclk;
1412 u16 v;
1413};
1414
1415struct amdgpu_uvd_clock_voltage_dependency_table {
1416 u8 count;
1417 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1418};
1419
1420struct amdgpu_vce_clock_voltage_dependency_entry {
1421 u32 ecclk;
1422 u32 evclk;
1423 u16 v;
1424};
1425
1426struct amdgpu_vce_clock_voltage_dependency_table {
1427 u8 count;
1428 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1429};
1430
1431struct amdgpu_ppm_table {
1432 u8 ppm_design;
1433 u16 cpu_core_number;
1434 u32 platform_tdp;
1435 u32 small_ac_platform_tdp;
1436 u32 platform_tdc;
1437 u32 small_ac_platform_tdc;
1438 u32 apu_tdp;
1439 u32 dgpu_tdp;
1440 u32 dgpu_ulv_power;
1441 u32 tj_max;
1442};
1443
1444struct amdgpu_cac_tdp_table {
1445 u16 tdp;
1446 u16 configurable_tdp;
1447 u16 tdc;
1448 u16 battery_power_limit;
1449 u16 small_power_limit;
1450 u16 low_cac_leakage;
1451 u16 high_cac_leakage;
1452 u16 maximum_power_delivery_limit;
1453};
1454
1455struct amdgpu_dpm_dynamic_state {
1456 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1457 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1458 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1459 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1460 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1461 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1462 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1463 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1464 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1465 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1466 struct amdgpu_clock_array valid_sclk_values;
1467 struct amdgpu_clock_array valid_mclk_values;
1468 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1469 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1470 u32 mclk_sclk_ratio;
1471 u32 sclk_mclk_delta;
1472 u16 vddc_vddci_delta;
1473 u16 min_vddc_for_pcie_gen2;
1474 struct amdgpu_cac_leakage_table cac_leakage_table;
1475 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1476 struct amdgpu_ppm_table *ppm_table;
1477 struct amdgpu_cac_tdp_table *cac_tdp_table;
1478};
1479
1480struct amdgpu_dpm_fan {
1481 u16 t_min;
1482 u16 t_med;
1483 u16 t_high;
1484 u16 pwm_min;
1485 u16 pwm_med;
1486 u16 pwm_high;
1487 u8 t_hyst;
1488 u32 cycle_delay;
1489 u16 t_max;
1490 u8 control_mode;
1491 u16 default_max_fan_pwm;
1492 u16 default_fan_output_sensitivity;
1493 u16 fan_output_sensitivity;
1494 bool ucode_fan_control;
1495};
1496
1497enum amdgpu_pcie_gen {
1498 AMDGPU_PCIE_GEN1 = 0,
1499 AMDGPU_PCIE_GEN2 = 1,
1500 AMDGPU_PCIE_GEN3 = 2,
1501 AMDGPU_PCIE_GEN_INVALID = 0xffff
1502};
1503
1504enum amdgpu_dpm_forced_level {
1505 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1506 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1507 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1508};
1509
1510struct amdgpu_vce_state {
1511 /* vce clocks */
1512 u32 evclk;
1513 u32 ecclk;
1514 /* gpu clocks */
1515 u32 sclk;
1516 u32 mclk;
1517 u8 clk_idx;
1518 u8 pstate;
1519};
1520
1521struct amdgpu_dpm_funcs {
1522 int (*get_temperature)(struct amdgpu_device *adev);
1523 int (*pre_set_power_state)(struct amdgpu_device *adev);
1524 int (*set_power_state)(struct amdgpu_device *adev);
1525 void (*post_set_power_state)(struct amdgpu_device *adev);
1526 void (*display_configuration_changed)(struct amdgpu_device *adev);
1527 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1528 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1529 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1530 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1531 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1532 bool (*vblank_too_short)(struct amdgpu_device *adev);
1533 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1534 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1535 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1536 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1537 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1538 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1539 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1540};
1541
1542struct amdgpu_dpm {
1543 struct amdgpu_ps *ps;
1544 /* number of valid power states */
1545 int num_ps;
1546 /* current power state that is active */
1547 struct amdgpu_ps *current_ps;
1548 /* requested power state */
1549 struct amdgpu_ps *requested_ps;
1550 /* boot up power state */
1551 struct amdgpu_ps *boot_ps;
1552 /* default uvd power state */
1553 struct amdgpu_ps *uvd_ps;
1554 /* vce requirements */
1555 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1556 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1557 enum amd_pm_state_type state;
1558 enum amd_pm_state_type user_state;
97b2e202
AD		 1559 u32 platform_caps;
1560 u32 voltage_response_time;
1561 u32 backbias_response_time;
1562 void *priv;
1563 u32 new_active_crtcs;
1564 int new_active_crtc_count;
1565 u32 current_active_crtcs;
1566 int current_active_crtc_count;
1567 struct amdgpu_dpm_dynamic_state dyn_state;
1568 struct amdgpu_dpm_fan fan;
1569 u32 tdp_limit;
1570 u32 near_tdp_limit;
1571 u32 near_tdp_limit_adjusted;
1572 u32 sq_ramping_threshold;
1573 u32 cac_leakage;
1574 u16 tdp_od_limit;
1575 u32 tdp_adjustment;
1576 u16 load_line_slope;
1577 bool power_control;
1578 bool ac_power;
1579 /* special states active */
1580 bool thermal_active;
1581 bool uvd_active;
1582 bool vce_active;
1583 /* thermal handling */
1584 struct amdgpu_dpm_thermal thermal;
1585 /* forced levels */
1586 enum amdgpu_dpm_forced_level forced_level;
1587};
1588
1589struct amdgpu_pm {
1590 struct mutex mutex;
97b2e202
AD		 1591 u32 current_sclk;
1592 u32 current_mclk;
1593 u32 default_sclk;
1594 u32 default_mclk;
1595 struct amdgpu_i2c_chan *i2c_bus;
1596 /* internal thermal controller on rv6xx+ */
1597 enum amdgpu_int_thermal_type int_thermal_type;
1598 struct device *int_hwmon_dev;
1599 /* fan control parameters */
1600 bool no_fan;
1601 u8 fan_pulses_per_revolution;
1602 u8 fan_min_rpm;
1603 u8 fan_max_rpm;
1604 /* dpm */
1605 bool dpm_enabled;
c86f5ebf 1606 bool sysfs_initialized;
97b2e202
AD		 1607 struct amdgpu_dpm dpm;
1608 const struct firmware *fw; /* SMC firmware */
1609 uint32_t fw_version;
1610 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1611 uint32_t pcie_gen_mask;
1612 uint32_t pcie_mlw_mask;
7fb72a1f 1613 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1614};
1615
d0dd7f0c
AD		 1616void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1617
97b2e202
AD		 1618/*
1619 * UVD
1620 */
1621#define AMDGPU_MAX_UVD_HANDLES 10
1622#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1623#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1624#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1625
1626struct amdgpu_uvd {
1627 struct amdgpu_bo *vcpu_bo;
1628 void *cpu_addr;
1629 uint64_t gpu_addr;
97b2e202
AD		 1630 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1631 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1632 struct delayed_work idle_work;
1633 const struct firmware *fw; /* UVD firmware */
1634 struct amdgpu_ring ring;
1635 struct amdgpu_irq_src irq;
1636 bool address_64_bit;
1637};
1638
1639/*
1640 * VCE
1641 */
1642#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1643#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1644
6a585777
AD		 1645#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1646#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1647
97b2e202
AD		 1648struct amdgpu_vce {
1649 struct amdgpu_bo *vcpu_bo;
1650 uint64_t gpu_addr;
1651 unsigned fw_version;
1652 unsigned fb_version;
1653 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1654 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1655 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1656 struct delayed_work idle_work;
1657 const struct firmware *fw; /* VCE firmware */
1658 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1659 struct amdgpu_irq_src irq;
6a585777 1660 unsigned harvest_config;
97b2e202
AD		 1661};
1662
1663/*
1664 * SDMA
1665 */
c113ea1c 1666struct amdgpu_sdma_instance {
97b2e202
AD		 1667 /* SDMA firmware */
1668 const struct firmware *fw;
1669 uint32_t fw_version;
cfa2104f 1670 uint32_t feature_version;
97b2e202
AD		 1671
1672 struct amdgpu_ring ring;
18111de0 1673 bool burst_nop;
97b2e202
AD		 1674};
1675
c113ea1c
AD		 1676struct amdgpu_sdma {
1677 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1678 struct amdgpu_irq_src trap_irq;
1679 struct amdgpu_irq_src illegal_inst_irq;
1680 int num_instances;
1681};
1682
97b2e202
AD		 1683/*
1684 * Firmware
1685 */
1686struct amdgpu_firmware {
1687 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1688 bool smu_load;
1689 struct amdgpu_bo *fw_buf;
1690 unsigned int fw_size;
1691};
1692
1693/*
1694 * Benchmarking
1695 */
1696void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1697
1698
1699/*
1700 * Testing
1701 */
1702void amdgpu_test_moves(struct amdgpu_device *adev);
1703void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1704 struct amdgpu_ring *cpA,
1705 struct amdgpu_ring *cpB);
1706void amdgpu_test_syncing(struct amdgpu_device *adev);
1707
1708/*
1709 * MMU Notifier
1710 */
1711#if defined(CONFIG_MMU_NOTIFIER)
1712int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1713void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1714#else
1d1106b0 1715static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1716{
1717 return -ENODEV;
1718}
1d1106b0 1719static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1720#endif
1721
1722/*
1723 * Debugfs
1724 */
1725struct amdgpu_debugfs {
1726 struct drm_info_list *files;
1727 unsigned num_files;
1728};
1729
1730int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1731 struct drm_info_list *files,
1732 unsigned nfiles);
1733int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1734
1735#if defined(CONFIG_DEBUG_FS)
1736int amdgpu_debugfs_init(struct drm_minor *minor);
1737void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1738#endif
1739
1740/*
1741 * amdgpu smumgr functions
1742 */
1743struct amdgpu_smumgr_funcs {
1744 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1745 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1746 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1747};
1748
1749/*
1750 * amdgpu smumgr
1751 */
1752struct amdgpu_smumgr {
1753 struct amdgpu_bo *toc_buf;
1754 struct amdgpu_bo *smu_buf;
1755 /* asic priv smu data */
1756 void *priv;
1757 spinlock_t smu_lock;
1758 /* smumgr functions */
1759 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1760 /* ucode loading complete flag */
1761 uint32_t fw_flags;
1762};
1763
1764/*
1765 * ASIC specific register table accessible by UMD
1766 */
1767struct amdgpu_allowed_register_entry {
1768 uint32_t reg_offset;
1769 bool untouched;
1770 bool grbm_indexed;
1771};
1772
1773struct amdgpu_cu_info {
1774 uint32_t number; /* total active CU number */
1775 uint32_t ao_cu_mask;
1776 uint32_t bitmap[4][4];
1777};
1778
1779
1780/*
1781 * ASIC specific functions.
1782 */
1783struct amdgpu_asic_funcs {
1784 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1785 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1786 u8 *bios, u32 length_bytes);
97b2e202
AD		 1787 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1788 u32 sh_num, u32 reg_offset, u32 *value);
1789 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1790 int (*reset)(struct amdgpu_device *adev);
1791 /* wait for mc_idle */
1792 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1793 /* get the reference clock */
1794 u32 (*get_xclk)(struct amdgpu_device *adev);
1795 /* get the gpu clock counter */
1796 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1797 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1798 /* MM block clocks */
1799 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1800 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1801};
1802
1803/*
1804 * IOCTL.
1805 */
1806int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1807 struct drm_file *filp);
1808int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1809 struct drm_file *filp);
1810
1811int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1812 struct drm_file *filp);
1813int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1814 struct drm_file *filp);
1815int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *filp);
1817int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1820 struct drm_file *filp);
1821int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1822 struct drm_file *filp);
1823int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1824int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1825
1826int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1827 struct drm_file *filp);
1828
1829/* VRAM scratch page for HDP bug, default vram page */
1830struct amdgpu_vram_scratch {
1831 struct amdgpu_bo *robj;
1832 volatile uint32_t *ptr;
1833 u64 gpu_addr;
1834};
1835
1836/*
1837 * ACPI
1838 */
1839struct amdgpu_atif_notification_cfg {
1840 bool enabled;
1841 int command_code;
1842};
1843
1844struct amdgpu_atif_notifications {
1845 bool display_switch;
1846 bool expansion_mode_change;
1847 bool thermal_state;
1848 bool forced_power_state;
1849 bool system_power_state;
1850 bool display_conf_change;
1851 bool px_gfx_switch;
1852 bool brightness_change;
1853 bool dgpu_display_event;
1854};
1855
1856struct amdgpu_atif_functions {
1857 bool system_params;
1858 bool sbios_requests;
1859 bool select_active_disp;
1860 bool lid_state;
1861 bool get_tv_standard;
1862 bool set_tv_standard;
1863 bool get_panel_expansion_mode;
1864 bool set_panel_expansion_mode;
1865 bool temperature_change;
1866 bool graphics_device_types;
1867};
1868
1869struct amdgpu_atif {
1870 struct amdgpu_atif_notifications notifications;
1871 struct amdgpu_atif_functions functions;
1872 struct amdgpu_atif_notification_cfg notification_cfg;
1873 struct amdgpu_encoder *encoder_for_bl;
1874};
1875
1876struct amdgpu_atcs_functions {
1877 bool get_ext_state;
1878 bool pcie_perf_req;
1879 bool pcie_dev_rdy;
1880 bool pcie_bus_width;
1881};
1882
1883struct amdgpu_atcs {
1884 struct amdgpu_atcs_functions functions;
1885};
1886
d03846af
CZ		 1887/*
1888 * CGS
1889 */
1890void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1891void amdgpu_cgs_destroy_device(void *cgs_device);
1892
1893
97b2e202
AD		 1894/*
1895 * Core structure, functions and helpers.
1896 */
1897typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1898typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1899
1900typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1901typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1902
8faf0e08
AD		 1903struct amdgpu_ip_block_status {
1904 bool valid;
1905 bool sw;
1906 bool hw;
1907};
1908
97b2e202
AD		 1909struct amdgpu_device {
1910 struct device *dev;
1911 struct drm_device *ddev;
1912 struct pci_dev *pdev;
97b2e202
AD		 1913
1914 /* ASIC */
2f7d10b3 1915 enum amd_asic_type asic_type;
97b2e202
AD		 1916 uint32_t family;
1917 uint32_t rev_id;
1918 uint32_t external_rev_id;
1919 unsigned long flags;
1920 int usec_timeout;
1921 const struct amdgpu_asic_funcs *asic_funcs;
1922 bool shutdown;
1923 bool suspend;
1924 bool need_dma32;
1925 bool accel_working;
97b2e202
AD		 1926 struct work_struct reset_work;
1927 struct notifier_block acpi_nb;
1928 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1929 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1930 unsigned debugfs_count;
1931#if defined(CONFIG_DEBUG_FS)
1932 struct dentry *debugfs_regs;
1933#endif
1934 struct amdgpu_atif atif;
1935 struct amdgpu_atcs atcs;
1936 struct mutex srbm_mutex;
1937 /* GRBM index mutex. Protects concurrent access to GRBM index */
1938 struct mutex grbm_idx_mutex;
1939 struct dev_pm_domain vga_pm_domain;
1940 bool have_disp_power_ref;
1941
1942 /* BIOS */
1943 uint8_t *bios;
1944 bool is_atom_bios;
1945 uint16_t bios_header_start;
1946 struct amdgpu_bo *stollen_vga_memory;
1947 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1948
1949 /* Register/doorbell mmio */
1950 resource_size_t rmmio_base;
1951 resource_size_t rmmio_size;
1952 void __iomem *rmmio;
1953 /* protects concurrent MM_INDEX/DATA based register access */
1954 spinlock_t mmio_idx_lock;
1955 /* protects concurrent SMC based register access */
1956 spinlock_t smc_idx_lock;
1957 amdgpu_rreg_t smc_rreg;
1958 amdgpu_wreg_t smc_wreg;
1959 /* protects concurrent PCIE register access */
1960 spinlock_t pcie_idx_lock;
1961 amdgpu_rreg_t pcie_rreg;
1962 amdgpu_wreg_t pcie_wreg;
1963 /* protects concurrent UVD register access */
1964 spinlock_t uvd_ctx_idx_lock;
1965 amdgpu_rreg_t uvd_ctx_rreg;
1966 amdgpu_wreg_t uvd_ctx_wreg;
1967 /* protects concurrent DIDT register access */
1968 spinlock_t didt_idx_lock;
1969 amdgpu_rreg_t didt_rreg;
1970 amdgpu_wreg_t didt_wreg;
1971 /* protects concurrent ENDPOINT (audio) register access */
1972 spinlock_t audio_endpt_idx_lock;
1973 amdgpu_block_rreg_t audio_endpt_rreg;
1974 amdgpu_block_wreg_t audio_endpt_wreg;
1975 void __iomem *rio_mem;
1976 resource_size_t rio_mem_size;
1977 struct amdgpu_doorbell doorbell;
1978
1979 /* clock/pll info */
1980 struct amdgpu_clock clock;
1981
1982 /* MC */
1983 struct amdgpu_mc mc;
1984 struct amdgpu_gart gart;
1985 struct amdgpu_dummy_page dummy_page;
1986 struct amdgpu_vm_manager vm_manager;
1987
1988 /* memory management */
1989 struct amdgpu_mman mman;
1990 struct amdgpu_gem gem;
1991 struct amdgpu_vram_scratch vram_scratch;
1992 struct amdgpu_wb wb;
1993 atomic64_t vram_usage;
1994 atomic64_t vram_vis_usage;
1995 atomic64_t gtt_usage;
1996 atomic64_t num_bytes_moved;
d94aed5a 1997 atomic_t gpu_reset_counter;
97b2e202
AD		 1998
1999 /* display */
2000 struct amdgpu_mode_info mode_info;
2001 struct work_struct hotplug_work;
2002 struct amdgpu_irq_src crtc_irq;
2003 struct amdgpu_irq_src pageflip_irq;
2004 struct amdgpu_irq_src hpd_irq;
2005
2006 /* rings */
97b2e202 2007 unsigned fence_context;
97b2e202
AD		 2008 unsigned num_rings;
2009 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2010 bool ib_pool_ready;
2011 struct amdgpu_sa_manager ring_tmp_bo;
2012
2013 /* interrupts */
2014 struct amdgpu_irq irq;
2015
1f7371b2
AD		 2016 /* powerplay */
2017 struct amd_powerplay powerplay;
e61710c5 2018 bool pp_enabled;
1f7371b2 2019
97b2e202
AD		 2020 /* dpm */
2021 struct amdgpu_pm pm;
2022 u32 cg_flags;
2023 u32 pg_flags;
2024
2025 /* amdgpu smumgr */
2026 struct amdgpu_smumgr smu;
2027
2028 /* gfx */
2029 struct amdgpu_gfx gfx;
2030
2031 /* sdma */
c113ea1c 2032 struct amdgpu_sdma sdma;
97b2e202
AD		 2033
2034 /* uvd */
2035 bool has_uvd;
2036 struct amdgpu_uvd uvd;
2037
2038 /* vce */
2039 struct amdgpu_vce vce;
2040
2041 /* firmwares */
2042 struct amdgpu_firmware firmware;
2043
2044 /* GDS */
2045 struct amdgpu_gds gds;
2046
2047 const struct amdgpu_ip_block_version *ip_blocks;
2048 int num_ip_blocks;
8faf0e08 2049 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2050 struct mutex mn_lock;
2051 DECLARE_HASHTABLE(mn_hash, 7);
2052
2053 /* tracking pinned memory */
2054 u64 vram_pin_size;
2055 u64 gart_pin_size;
130e0371
OG		 2056
2057 /* amdkfd interface */
2058 struct kfd_dev *kfd;
23ca0e4e
CZ		 2059
2060 /* kernel conext for IB submission */
47f38501 2061 struct amdgpu_ctx kernel_ctx;
97b2e202
AD		 2062};
2063
2064bool amdgpu_device_is_px(struct drm_device *dev);
2065int amdgpu_device_init(struct amdgpu_device *adev,
2066 struct drm_device *ddev,
2067 struct pci_dev *pdev,
2068 uint32_t flags);
2069void amdgpu_device_fini(struct amdgpu_device *adev);
2070int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2071
2072uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2073 bool always_indirect);
2074void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2075 bool always_indirect);
2076u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2077void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2078
2079u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2080void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2081
2082/*
2083 * Cast helper
2084 */
2085extern const struct fence_ops amdgpu_fence_ops;
2086static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2087{
2088 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2089
2090 if (__f->base.ops == &amdgpu_fence_ops)
2091 return __f;
2092
2093 return NULL;
2094}
2095
2096/*
2097 * Registers read & write functions.
2098 */
2099#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2100#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2101#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2102#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2103#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2104#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2105#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2106#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2107#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2108#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2109#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2110#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2111#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2112#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2113#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2114#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2115#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2116#define WREG32_P(reg, val, mask) \
2117 do { \
2118 uint32_t tmp_ = RREG32(reg); \
2119 tmp_ &= (mask); \
2120 tmp_ |= ((val) & ~(mask)); \
2121 WREG32(reg, tmp_); \
2122 } while (0)
2123#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2124#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2125#define WREG32_PLL_P(reg, val, mask) \
2126 do { \
2127 uint32_t tmp_ = RREG32_PLL(reg); \
2128 tmp_ &= (mask); \
2129 tmp_ |= ((val) & ~(mask)); \
2130 WREG32_PLL(reg, tmp_); \
2131 } while (0)
2132#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2133#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2134#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2135
2136#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2137#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2138
2139#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2140#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2141
2142#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2143 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2144 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2145
2146#define REG_GET_FIELD(value, reg, field) \
2147 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2148
2149/*
2150 * BIOS helpers.
2151 */
2152#define RBIOS8(i) (adev->bios[i])
2153#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2154#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2155
2156/*
2157 * RING helpers.
2158 */
2159static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2160{
2161 if (ring->count_dw <= 0)
86c2b790 2162 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2163 ring->ring[ring->wptr++] = v;
2164 ring->wptr &= ring->ptr_mask;
2165 ring->count_dw--;
2166 ring->ring_free_dw--;
2167}
2168
c113ea1c
AD		 2169static inline struct amdgpu_sdma_instance *
2170amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2171{
2172 struct amdgpu_device *adev = ring->adev;
2173 int i;
2174
c113ea1c
AD		 2175 for (i = 0; i < adev->sdma.num_instances; i++)
2176 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2177 break;
2178
2179 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2180 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2181 else
2182 return NULL;
2183}
2184
97b2e202
AD		 2185/*
2186 * ASICs macro.
2187 */
2188#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2189#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2190#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2191#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2192#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2193#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2194#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2195#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2196#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2197#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2198#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2199#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2200#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2201#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2202#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2203#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2204#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2205#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2206#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2207#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2208#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2209#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2210#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2211#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2212#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2213#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2214#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2215#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2216#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2217#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2218#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2219#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2220#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2221#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2222#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2223#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2224#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2225#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2226#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2227#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2228#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2229#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2230#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2231#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2232#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2233#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2234#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2235#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2236#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2237#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2238#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2239#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2240#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2241#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2242#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2243#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2244
2245#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2246 ((adev)->pp_enabled ? \
e61710c5 2247 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2248 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2249
2250#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2251 ((adev)->pp_enabled ? \
e61710c5 2252 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2253 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2254
2255#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2256 ((adev)->pp_enabled ? \
e61710c5 2257 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2258 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2259
2260#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2261 ((adev)->pp_enabled ? \
e61710c5 2262 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2263 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2264
2265#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2266 ((adev)->pp_enabled ? \
e61710c5 2267 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2268 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2269
1b5708ff 2270#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2271 ((adev)->pp_enabled ? \
e61710c5 2272 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2273 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2274
2275#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2276 ((adev)->pp_enabled ? \
e61710c5 2277 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2278 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2279
2280
2281#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2282 ((adev)->pp_enabled ? \
e61710c5 2283 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2284 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2285
2286#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2287 ((adev)->pp_enabled ? \
e61710c5 2288 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2289 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2290
2291#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2292 ((adev)->pp_enabled ? \
e61710c5 2293 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2294 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2295
2296#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2297 ((adev)->pp_enabled ? \
e61710c5 2298 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2299 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2300
2301#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2302 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2303
2304#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2305 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2306
e61710c5 2307#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2308 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2309
2310#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2311
2312/* Common functions */
2313int amdgpu_gpu_reset(struct amdgpu_device *adev);
2314void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2315bool amdgpu_card_posted(struct amdgpu_device *adev);
2316void amdgpu_update_display_priority(struct amdgpu_device *adev);
2317bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82 2318
97b2e202
AD		 2319int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2320int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2321 u32 ip_instance, u32 ring,
2322 struct amdgpu_ring **out_ring);
2323void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2324bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2325int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2326 uint32_t flags);
2327bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
d7006964
CK		 2328bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2329 unsigned long end);
97b2e202
AD		 2330bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2331uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2332 struct ttm_mem_reg *mem);
2333void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2334void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2335void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2336void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2337 const u32 *registers,
2338 const u32 array_size);
2339
2340bool amdgpu_device_is_px(struct drm_device *dev);
2341/* atpx handler */
2342#if defined(CONFIG_VGA_SWITCHEROO)
2343void amdgpu_register_atpx_handler(void);
2344void amdgpu_unregister_atpx_handler(void);
2345#else
2346static inline void amdgpu_register_atpx_handler(void) {}
2347static inline void amdgpu_unregister_atpx_handler(void) {}
2348#endif
2349
2350/*
2351 * KMS
2352 */
2353extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2354extern int amdgpu_max_kms_ioctl;
2355
2356int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2357int amdgpu_driver_unload_kms(struct drm_device *dev);
2358void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2359int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2360void amdgpu_driver_postclose_kms(struct drm_device *dev,
2361 struct drm_file *file_priv);
2362void amdgpu_driver_preclose_kms(struct drm_device *dev,
2363 struct drm_file *file_priv);
2364int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2365int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2366u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2367int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2368void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2369int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2370 int *max_error,
2371 struct timeval *vblank_time,
2372 unsigned flags);
2373long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2374 unsigned long arg);
2375
97b2e202
AD		 2376/*
2377 * functions used by amdgpu_encoder.c
2378 */
2379struct amdgpu_afmt_acr {
2380 u32 clock;
2381
2382 int n_32khz;
2383 int cts_32khz;
2384
2385 int n_44_1khz;
2386 int cts_44_1khz;
2387
2388 int n_48khz;
2389 int cts_48khz;
2390
2391};
2392
2393struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2394
2395/* amdgpu_acpi.c */
2396#if defined(CONFIG_ACPI)
2397int amdgpu_acpi_init(struct amdgpu_device *adev);
2398void amdgpu_acpi_fini(struct amdgpu_device *adev);
2399bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2400int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2401 u8 perf_req, bool advertise);
2402int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2403#else
2404static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2405static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2406#endif
2407
2408struct amdgpu_bo_va_mapping *
2409amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2410 uint64_t addr, struct amdgpu_bo **bo);
2411
2412#include "amdgpu_object.h"
2413
2414#endif
Linux kernel - Deliverables
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