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drm/amdgpu: switch to amdgpu folder for firmware files v2
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
45#include <drm/drm_gem.h>
46
47#include "amdgpu_family.h"
48#include "amdgpu_mode.h"
49#include "amdgpu_ih.h"
50#include "amdgpu_irq.h"
51#include "amdgpu_ucode.h"
52#include "amdgpu_gds.h"
53
54/*
55 * Modules parameters.
56 */
57extern int amdgpu_modeset;
58extern int amdgpu_vram_limit;
59extern int amdgpu_gart_size;
60extern int amdgpu_benchmarking;
61extern int amdgpu_testing;
62extern int amdgpu_audio;
63extern int amdgpu_disp_priority;
64extern int amdgpu_hw_i2c;
65extern int amdgpu_pcie_gen2;
66extern int amdgpu_msi;
67extern int amdgpu_lockup_timeout;
68extern int amdgpu_dpm;
69extern int amdgpu_smc_load_fw;
70extern int amdgpu_aspm;
71extern int amdgpu_runtime_pm;
72extern int amdgpu_hard_reset;
73extern unsigned amdgpu_ip_block_mask;
74extern int amdgpu_bapm;
75extern int amdgpu_deep_color;
76extern int amdgpu_vm_size;
77extern int amdgpu_vm_block_size;
78
79#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
80#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
81/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
82#define AMDGPU_IB_POOL_SIZE 16
83#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
84#define AMDGPUFB_CONN_LIMIT 4
85#define AMDGPU_BIOS_NUM_SCRATCH 8
86
87/* fence seq are set to this number when signaled */
88#define AMDGPU_FENCE_SIGNALED_SEQ 0LL
89
90/* max number of rings */
91#define AMDGPU_MAX_RINGS 16
92#define AMDGPU_MAX_GFX_RINGS 1
93#define AMDGPU_MAX_COMPUTE_RINGS 8
94#define AMDGPU_MAX_VCE_RINGS 2
95
96/* number of hw syncs before falling back on blocking */
97#define AMDGPU_NUM_SYNCS 4
98
99/* hardcode that limit for now */
100#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
101
102/* hard reset data */
103#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
104
105/* reset flags */
106#define AMDGPU_RESET_GFX (1 << 0)
107#define AMDGPU_RESET_COMPUTE (1 << 1)
108#define AMDGPU_RESET_DMA (1 << 2)
109#define AMDGPU_RESET_CP (1 << 3)
110#define AMDGPU_RESET_GRBM (1 << 4)
111#define AMDGPU_RESET_DMA1 (1 << 5)
112#define AMDGPU_RESET_RLC (1 << 6)
113#define AMDGPU_RESET_SEM (1 << 7)
114#define AMDGPU_RESET_IH (1 << 8)
115#define AMDGPU_RESET_VMC (1 << 9)
116#define AMDGPU_RESET_MC (1 << 10)
117#define AMDGPU_RESET_DISPLAY (1 << 11)
118#define AMDGPU_RESET_UVD (1 << 12)
119#define AMDGPU_RESET_VCE (1 << 13)
120#define AMDGPU_RESET_VCE1 (1 << 14)
121
122/* CG block flags */
123#define AMDGPU_CG_BLOCK_GFX (1 << 0)
124#define AMDGPU_CG_BLOCK_MC (1 << 1)
125#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
126#define AMDGPU_CG_BLOCK_UVD (1 << 3)
127#define AMDGPU_CG_BLOCK_VCE (1 << 4)
128#define AMDGPU_CG_BLOCK_HDP (1 << 5)
129#define AMDGPU_CG_BLOCK_BIF (1 << 6)
130
131/* CG flags */
132#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
133#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
134#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
135#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
136#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
137#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
138#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
139#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
140#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
141#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
142#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
143#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
144#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
145#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
146#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
147#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
148#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
149
150/* PG flags */
151#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
152#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
153#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
154#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
155#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
156#define AMDGPU_PG_SUPPORT_CP (1 << 5)
157#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
158#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
159#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
160#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
161#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
162
163/* GFX current status */
164#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
165#define AMDGPU_GFX_SAFE_MODE 0x00000001L
166#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
167#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
168#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
169
170/* max cursor sizes (in pixels) */
171#define CIK_CURSOR_WIDTH 128
172#define CIK_CURSOR_HEIGHT 128
173
174struct amdgpu_device;
175struct amdgpu_fence;
176struct amdgpu_ib;
177struct amdgpu_vm;
178struct amdgpu_ring;
179struct amdgpu_semaphore;
180struct amdgpu_cs_parser;
181struct amdgpu_irq_src;
182
183enum amdgpu_cp_irq {
184 AMDGPU_CP_IRQ_GFX_EOP = 0,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
193
194 AMDGPU_CP_IRQ_LAST
195};
196
197enum amdgpu_sdma_irq {
198 AMDGPU_SDMA_IRQ_TRAP0 = 0,
199 AMDGPU_SDMA_IRQ_TRAP1,
200
201 AMDGPU_SDMA_IRQ_LAST
202};
203
204enum amdgpu_thermal_irq {
205 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
206 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
207
208 AMDGPU_THERMAL_IRQ_LAST
209};
210
211/*
212 * IP block functions
213 */
214enum amdgpu_ip_block_type {
215 AMDGPU_IP_BLOCK_TYPE_COMMON,
216 AMDGPU_IP_BLOCK_TYPE_GMC,
217 AMDGPU_IP_BLOCK_TYPE_IH,
218 AMDGPU_IP_BLOCK_TYPE_SMC,
219 AMDGPU_IP_BLOCK_TYPE_DCE,
220 AMDGPU_IP_BLOCK_TYPE_GFX,
221 AMDGPU_IP_BLOCK_TYPE_SDMA,
222 AMDGPU_IP_BLOCK_TYPE_UVD,
223 AMDGPU_IP_BLOCK_TYPE_VCE,
224};
225
226enum amdgpu_clockgating_state {
227 AMDGPU_CG_STATE_GATE = 0,
228 AMDGPU_CG_STATE_UNGATE,
229};
230
231enum amdgpu_powergating_state {
232 AMDGPU_PG_STATE_GATE = 0,
233 AMDGPU_PG_STATE_UNGATE,
234};
235
236struct amdgpu_ip_funcs {
237 /* sets up early driver state (pre sw_init), does not configure hw - Optional */
238 int (*early_init)(struct amdgpu_device *adev);
239 /* sets up late driver/hw state (post hw_init) - Optional */
240 int (*late_init)(struct amdgpu_device *adev);
241 /* sets up driver state, does not configure hw */
242 int (*sw_init)(struct amdgpu_device *adev);
243 /* tears down driver state, does not configure hw */
244 int (*sw_fini)(struct amdgpu_device *adev);
245 /* sets up the hw state */
246 int (*hw_init)(struct amdgpu_device *adev);
247 /* tears down the hw state */
248 int (*hw_fini)(struct amdgpu_device *adev);
249 /* handles IP specific hw/sw changes for suspend */
250 int (*suspend)(struct amdgpu_device *adev);
251 /* handles IP specific hw/sw changes for resume */
252 int (*resume)(struct amdgpu_device *adev);
253 /* returns current IP block idle status */
254 bool (*is_idle)(struct amdgpu_device *adev);
255 /* poll for idle */
256 int (*wait_for_idle)(struct amdgpu_device *adev);
257 /* soft reset the IP block */
258 int (*soft_reset)(struct amdgpu_device *adev);
259 /* dump the IP block status registers */
260 void (*print_status)(struct amdgpu_device *adev);
261 /* enable/disable cg for the IP block */
262 int (*set_clockgating_state)(struct amdgpu_device *adev,
263 enum amdgpu_clockgating_state state);
264 /* enable/disable pg for the IP block */
265 int (*set_powergating_state)(struct amdgpu_device *adev,
266 enum amdgpu_powergating_state state);
267};
268
269int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
270 enum amdgpu_ip_block_type block_type,
271 enum amdgpu_clockgating_state state);
272int amdgpu_set_powergating_state(struct amdgpu_device *adev,
273 enum amdgpu_ip_block_type block_type,
274 enum amdgpu_powergating_state state);
275
276struct amdgpu_ip_block_version {
277 enum amdgpu_ip_block_type type;
278 u32 major;
279 u32 minor;
280 u32 rev;
281 const struct amdgpu_ip_funcs *funcs;
282};
283
284int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
285 enum amdgpu_ip_block_type type,
286 u32 major, u32 minor);
287
288const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
289 struct amdgpu_device *adev,
290 enum amdgpu_ip_block_type type);
291
292/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
293struct amdgpu_buffer_funcs {
294 /* maximum bytes in a single operation */
295 uint32_t copy_max_bytes;
296
297 /* number of dw to reserve per operation */
298 unsigned copy_num_dw;
299
300 /* used for buffer migration */
301 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
302 /* src addr in bytes */
303 uint64_t src_offset,
304 /* dst addr in bytes */
305 uint64_t dst_offset,
306 /* number of byte to transfer */
307 uint32_t byte_count);
308
309 /* maximum bytes in a single operation */
310 uint32_t fill_max_bytes;
311
312 /* number of dw to reserve per operation */
313 unsigned fill_num_dw;
314
315 /* used for buffer clearing */
316 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
317 /* value to write to memory */
318 uint32_t src_data,
319 /* dst addr in bytes */
320 uint64_t dst_offset,
321 /* number of byte to fill */
322 uint32_t byte_count);
323};
324
325/* provided by hw blocks that can write ptes, e.g., sdma */
326struct amdgpu_vm_pte_funcs {
327 /* copy pte entries from GART */
328 void (*copy_pte)(struct amdgpu_ib *ib,
329 uint64_t pe, uint64_t src,
330 unsigned count);
331 /* write pte one entry at a time with addr mapping */
332 void (*write_pte)(struct amdgpu_ib *ib,
333 uint64_t pe,
334 uint64_t addr, unsigned count,
335 uint32_t incr, uint32_t flags);
336 /* for linear pte/pde updates without addr mapping */
337 void (*set_pte_pde)(struct amdgpu_ib *ib,
338 uint64_t pe,
339 uint64_t addr, unsigned count,
340 uint32_t incr, uint32_t flags);
341 /* pad the indirect buffer to the necessary number of dw */
342 void (*pad_ib)(struct amdgpu_ib *ib);
343};
344
345/* provided by the gmc block */
346struct amdgpu_gart_funcs {
347 /* flush the vm tlb via mmio */
348 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
349 uint32_t vmid);
350 /* write pte/pde updates using the cpu */
351 int (*set_pte_pde)(struct amdgpu_device *adev,
352 void *cpu_pt_addr, /* cpu addr of page table */
353 uint32_t gpu_page_idx, /* pte/pde to update */
354 uint64_t addr, /* addr to write into pte/pde */
355 uint32_t flags); /* access flags */
356};
357
358/* provided by the ih block */
359struct amdgpu_ih_funcs {
360 /* ring read/write ptr handling, called from interrupt context */
361 u32 (*get_wptr)(struct amdgpu_device *adev);
362 void (*decode_iv)(struct amdgpu_device *adev,
363 struct amdgpu_iv_entry *entry);
364 void (*set_rptr)(struct amdgpu_device *adev);
365};
366
367/* provided by hw blocks that expose a ring buffer for commands */
368struct amdgpu_ring_funcs {
369 /* ring read/write ptr handling */
370 u32 (*get_rptr)(struct amdgpu_ring *ring);
371 u32 (*get_wptr)(struct amdgpu_ring *ring);
372 void (*set_wptr)(struct amdgpu_ring *ring);
373 /* validating and patching of IBs */
374 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
375 /* command emit functions */
376 void (*emit_ib)(struct amdgpu_ring *ring,
377 struct amdgpu_ib *ib);
378 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
379 uint64_t seq, bool write64bit);
380 bool (*emit_semaphore)(struct amdgpu_ring *ring,
381 struct amdgpu_semaphore *semaphore,
382 bool emit_wait);
383 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
384 uint64_t pd_addr);
d2edb07b 385 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 386 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
387 uint32_t gds_base, uint32_t gds_size,
388 uint32_t gws_base, uint32_t gws_size,
389 uint32_t oa_base, uint32_t oa_size);
390 /* testing functions */
391 int (*test_ring)(struct amdgpu_ring *ring);
392 int (*test_ib)(struct amdgpu_ring *ring);
393 bool (*is_lockup)(struct amdgpu_ring *ring);
394};
395
396/*
397 * BIOS.
398 */
399bool amdgpu_get_bios(struct amdgpu_device *adev);
400bool amdgpu_read_bios(struct amdgpu_device *adev);
401
402/*
403 * Dummy page
404 */
405struct amdgpu_dummy_page {
406 struct page *page;
407 dma_addr_t addr;
408};
409int amdgpu_dummy_page_init(struct amdgpu_device *adev);
410void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
411
412
413/*
414 * Clocks
415 */
416
417#define AMDGPU_MAX_PPLL 3
418
419struct amdgpu_clock {
420 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
421 struct amdgpu_pll spll;
422 struct amdgpu_pll mpll;
423 /* 10 Khz units */
424 uint32_t default_mclk;
425 uint32_t default_sclk;
426 uint32_t default_dispclk;
427 uint32_t current_dispclk;
428 uint32_t dp_extclk;
429 uint32_t max_pixel_clock;
430};
431
432/*
433 * Fences.
434 */
435struct amdgpu_fence_driver {
436 struct amdgpu_ring *ring;
437 uint64_t gpu_addr;
438 volatile uint32_t *cpu_addr;
439 /* sync_seq is protected by ring emission lock */
440 uint64_t sync_seq[AMDGPU_MAX_RINGS];
441 atomic64_t last_seq;
442 bool initialized;
443 bool delayed_irq;
444 struct amdgpu_irq_src *irq_src;
445 unsigned irq_type;
446 struct delayed_work lockup_work;
447};
448
449/* some special values for the owner field */
450#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
451#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
452#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
453
454struct amdgpu_fence {
455 struct fence base;
456
457 /* RB, DMA, etc. */
458 struct amdgpu_ring *ring;
459 uint64_t seq;
460
461 /* filp or special value for fence creator */
462 void *owner;
463
464 wait_queue_t fence_wake;
465};
466
467struct amdgpu_user_fence {
468 /* write-back bo */
469 struct amdgpu_bo *bo;
470 /* write-back address offset to bo start */
471 uint32_t offset;
472};
473
474int amdgpu_fence_driver_init(struct amdgpu_device *adev);
475void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
476void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
477
478void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
479int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
480 struct amdgpu_irq_src *irq_src,
481 unsigned irq_type);
482int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
483 struct amdgpu_fence **fence);
484void amdgpu_fence_process(struct amdgpu_ring *ring);
485int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
486int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
487unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
488
489bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
490int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
491int amdgpu_fence_wait_any(struct amdgpu_device *adev,
492 struct amdgpu_fence **fences,
493 bool intr);
494long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev,
495 u64 *target_seq, bool intr,
496 long timeout);
497struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
498void amdgpu_fence_unref(struct amdgpu_fence **fence);
499
500bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
501 struct amdgpu_ring *ring);
502void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
503 struct amdgpu_ring *ring);
504
505static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
506 struct amdgpu_fence *b)
507{
508 if (!a) {
509 return b;
510 }
511
512 if (!b) {
513 return a;
514 }
515
516 BUG_ON(a->ring != b->ring);
517
518 if (a->seq > b->seq) {
519 return a;
520 } else {
521 return b;
522 }
523}
524
525static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
526 struct amdgpu_fence *b)
527{
528 if (!a) {
529 return false;
530 }
531
532 if (!b) {
533 return true;
534 }
535
536 BUG_ON(a->ring != b->ring);
537
538 return a->seq < b->seq;
539}
540
541int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
542 void *owner, struct amdgpu_fence **fence);
543
544/*
545 * TTM.
546 */
547struct amdgpu_mman {
548 struct ttm_bo_global_ref bo_global_ref;
549 struct drm_global_reference mem_global_ref;
550 struct ttm_bo_device bdev;
551 bool mem_global_referenced;
552 bool initialized;
553
554#if defined(CONFIG_DEBUG_FS)
555 struct dentry *vram;
556 struct dentry *gtt;
557#endif
558
559 /* buffer handling */
560 const struct amdgpu_buffer_funcs *buffer_funcs;
561 struct amdgpu_ring *buffer_funcs_ring;
562};
563
564int amdgpu_copy_buffer(struct amdgpu_ring *ring,
565 uint64_t src_offset,
566 uint64_t dst_offset,
567 uint32_t byte_count,
568 struct reservation_object *resv,
569 struct amdgpu_fence **fence);
570int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
571
572struct amdgpu_bo_list_entry {
573 struct amdgpu_bo *robj;
574 struct ttm_validate_buffer tv;
575 struct amdgpu_bo_va *bo_va;
576 unsigned prefered_domains;
577 unsigned allowed_domains;
578 uint32_t priority;
579};
580
581struct amdgpu_bo_va_mapping {
582 struct list_head list;
583 struct interval_tree_node it;
584 uint64_t offset;
585 uint32_t flags;
586};
587
588/* bo virtual addresses in a specific vm */
589struct amdgpu_bo_va {
590 /* protected by bo being reserved */
591 struct list_head bo_list;
592 uint64_t addr;
593 struct amdgpu_fence *last_pt_update;
594 unsigned ref_count;
595
596 /* protected by vm mutex */
597 struct list_head mappings;
598 struct list_head vm_status;
599
600 /* constant after initialization */
601 struct amdgpu_vm *vm;
602 struct amdgpu_bo *bo;
603};
604
605struct amdgpu_bo {
606 /* Protected by gem.mutex */
607 struct list_head list;
608 /* Protected by tbo.reserved */
609 u32 initial_domain;
610 struct ttm_place placements[4];
611 struct ttm_placement placement;
612 struct ttm_buffer_object tbo;
613 struct ttm_bo_kmap_obj kmap;
614 u64 flags;
615 unsigned pin_count;
616 void *kptr;
617 u64 tiling_flags;
618 u64 metadata_flags;
619 void *metadata;
620 u32 metadata_size;
621 /* list of all virtual address to which this bo
622 * is associated to
623 */
624 struct list_head va;
625 /* Constant after initialization */
626 struct amdgpu_device *adev;
627 struct drm_gem_object gem_base;
628
629 struct ttm_bo_kmap_obj dma_buf_vmap;
630 pid_t pid;
631 struct amdgpu_mn *mn;
632 struct list_head mn_list;
633};
634#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
635
636void amdgpu_gem_object_free(struct drm_gem_object *obj);
637int amdgpu_gem_object_open(struct drm_gem_object *obj,
638 struct drm_file *file_priv);
639void amdgpu_gem_object_close(struct drm_gem_object *obj,
640 struct drm_file *file_priv);
641unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
642struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
643struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
644 struct dma_buf_attachment *attach,
645 struct sg_table *sg);
646struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
647 struct drm_gem_object *gobj,
648 int flags);
649int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
650void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
651struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
652void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
653void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
654int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
655
656/* sub-allocation manager, it has to be protected by another lock.
657 * By conception this is an helper for other part of the driver
658 * like the indirect buffer or semaphore, which both have their
659 * locking.
660 *
661 * Principe is simple, we keep a list of sub allocation in offset
662 * order (first entry has offset == 0, last entry has the highest
663 * offset).
664 *
665 * When allocating new object we first check if there is room at
666 * the end total_size - (last_object_offset + last_object_size) >=
667 * alloc_size. If so we allocate new object there.
668 *
669 * When there is not enough room at the end, we start waiting for
670 * each sub object until we reach object_offset+object_size >=
671 * alloc_size, this object then become the sub object we return.
672 *
673 * Alignment can't be bigger than page size.
674 *
675 * Hole are not considered for allocation to keep things simple.
676 * Assumption is that there won't be hole (all object on same
677 * alignment).
678 */
679struct amdgpu_sa_manager {
680 wait_queue_head_t wq;
681 struct amdgpu_bo *bo;
682 struct list_head *hole;
683 struct list_head flist[AMDGPU_MAX_RINGS];
684 struct list_head olist;
685 unsigned size;
686 uint64_t gpu_addr;
687 void *cpu_ptr;
688 uint32_t domain;
689 uint32_t align;
690};
691
692struct amdgpu_sa_bo;
693
694/* sub-allocation buffer */
695struct amdgpu_sa_bo {
696 struct list_head olist;
697 struct list_head flist;
698 struct amdgpu_sa_manager *manager;
699 unsigned soffset;
700 unsigned eoffset;
701 struct amdgpu_fence *fence;
702};
703
704/*
705 * GEM objects.
706 */
707struct amdgpu_gem {
708 struct mutex mutex;
709 struct list_head objects;
710};
711
712int amdgpu_gem_init(struct amdgpu_device *adev);
713void amdgpu_gem_fini(struct amdgpu_device *adev);
714int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
715 int alignment, u32 initial_domain,
716 u64 flags, bool kernel,
717 struct drm_gem_object **obj);
718
719int amdgpu_mode_dumb_create(struct drm_file *file_priv,
720 struct drm_device *dev,
721 struct drm_mode_create_dumb *args);
722int amdgpu_mode_dumb_mmap(struct drm_file *filp,
723 struct drm_device *dev,
724 uint32_t handle, uint64_t *offset_p);
725
726/*
727 * Semaphores.
728 */
729struct amdgpu_semaphore {
730 struct amdgpu_sa_bo *sa_bo;
731 signed waiters;
732 uint64_t gpu_addr;
733};
734
735int amdgpu_semaphore_create(struct amdgpu_device *adev,
736 struct amdgpu_semaphore **semaphore);
737bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
738 struct amdgpu_semaphore *semaphore);
739bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
740 struct amdgpu_semaphore *semaphore);
741void amdgpu_semaphore_free(struct amdgpu_device *adev,
742 struct amdgpu_semaphore **semaphore,
743 struct amdgpu_fence *fence);
744
745/*
746 * Synchronization
747 */
748struct amdgpu_sync {
749 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
750 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
751 struct amdgpu_fence *last_vm_update;
752};
753
754void amdgpu_sync_create(struct amdgpu_sync *sync);
755void amdgpu_sync_fence(struct amdgpu_sync *sync,
756 struct amdgpu_fence *fence);
757int amdgpu_sync_resv(struct amdgpu_device *adev,
758 struct amdgpu_sync *sync,
759 struct reservation_object *resv,
760 void *owner);
761int amdgpu_sync_rings(struct amdgpu_sync *sync,
762 struct amdgpu_ring *ring);
763void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
764 struct amdgpu_fence *fence);
765
766/*
767 * GART structures, functions & helpers
768 */
769struct amdgpu_mc;
770
771#define AMDGPU_GPU_PAGE_SIZE 4096
772#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
773#define AMDGPU_GPU_PAGE_SHIFT 12
774#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
775
776struct amdgpu_gart {
777 dma_addr_t table_addr;
778 struct amdgpu_bo *robj;
779 void *ptr;
780 unsigned num_gpu_pages;
781 unsigned num_cpu_pages;
782 unsigned table_size;
783 struct page **pages;
784 dma_addr_t *pages_addr;
785 bool ready;
786 const struct amdgpu_gart_funcs *gart_funcs;
787};
788
789int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
790void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
791int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
792void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
793int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
794void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
795int amdgpu_gart_init(struct amdgpu_device *adev);
796void amdgpu_gart_fini(struct amdgpu_device *adev);
797void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
798 int pages);
799int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
800 int pages, struct page **pagelist,
801 dma_addr_t *dma_addr, uint32_t flags);
802
803/*
804 * GPU MC structures, functions & helpers
805 */
806struct amdgpu_mc {
807 resource_size_t aper_size;
808 resource_size_t aper_base;
809 resource_size_t agp_base;
810 /* for some chips with <= 32MB we need to lie
811 * about vram size near mc fb location */
812 u64 mc_vram_size;
813 u64 visible_vram_size;
814 u64 gtt_size;
815 u64 gtt_start;
816 u64 gtt_end;
817 u64 vram_start;
818 u64 vram_end;
819 unsigned vram_width;
820 u64 real_vram_size;
821 int vram_mtrr;
822 u64 gtt_base_align;
823 u64 mc_mask;
824 const struct firmware *fw; /* MC firmware */
825 uint32_t fw_version;
826 struct amdgpu_irq_src vm_fault;
827 bool is_gddr5;
828};
829
830/*
831 * GPU doorbell structures, functions & helpers
832 */
833typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
834{
835 AMDGPU_DOORBELL_KIQ = 0x000,
836 AMDGPU_DOORBELL_HIQ = 0x001,
837 AMDGPU_DOORBELL_DIQ = 0x002,
838 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
839 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
840 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
841 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
842 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
843 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
844 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
845 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
846 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
847 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
848 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
849 AMDGPU_DOORBELL_IH = 0x1E8,
850 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
851 AMDGPU_DOORBELL_INVALID = 0xFFFF
852} AMDGPU_DOORBELL_ASSIGNMENT;
853
854struct amdgpu_doorbell {
855 /* doorbell mmio */
856 resource_size_t base;
857 resource_size_t size;
858 u32 __iomem *ptr;
859 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
860};
861
862void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
863 phys_addr_t *aperture_base,
864 size_t *aperture_size,
865 size_t *start_offset);
866
867/*
868 * IRQS.
869 */
870
871struct amdgpu_flip_work {
872 struct work_struct flip_work;
873 struct work_struct unpin_work;
874 struct amdgpu_device *adev;
875 int crtc_id;
876 uint64_t base;
877 struct drm_pending_vblank_event *event;
878 struct amdgpu_bo *old_rbo;
879 struct fence *fence;
880};
881
882
883/*
884 * CP & rings.
885 */
886
887struct amdgpu_ib {
888 struct amdgpu_sa_bo *sa_bo;
889 uint32_t length_dw;
890 uint64_t gpu_addr;
891 uint32_t *ptr;
892 struct amdgpu_ring *ring;
893 struct amdgpu_fence *fence;
894 struct amdgpu_user_fence *user;
895 struct amdgpu_vm *vm;
3cb485f3 896 struct amdgpu_ctx *ctx;
97b2e202 897 struct amdgpu_sync sync;
97b2e202
AD		 898 uint32_t gds_base, gds_size;
899 uint32_t gws_base, gws_size;
900 uint32_t oa_base, oa_size;
de807f81 901 uint32_t flags;
97b2e202
AD		 902};
903
904enum amdgpu_ring_type {
905 AMDGPU_RING_TYPE_GFX,
906 AMDGPU_RING_TYPE_COMPUTE,
907 AMDGPU_RING_TYPE_SDMA,
908 AMDGPU_RING_TYPE_UVD,
909 AMDGPU_RING_TYPE_VCE
910};
911
912struct amdgpu_ring {
913 struct amdgpu_device *adev;
914 const struct amdgpu_ring_funcs *funcs;
915 struct amdgpu_fence_driver fence_drv;
916
917 struct mutex *ring_lock;
918 struct amdgpu_bo *ring_obj;
919 volatile uint32_t *ring;
920 unsigned rptr_offs;
921 u64 next_rptr_gpu_addr;
922 volatile u32 *next_rptr_cpu_addr;
923 unsigned wptr;
924 unsigned wptr_old;
925 unsigned ring_size;
926 unsigned ring_free_dw;
927 int count_dw;
928 atomic_t last_rptr;
929 atomic64_t last_activity;
930 uint64_t gpu_addr;
931 uint32_t align_mask;
932 uint32_t ptr_mask;
933 bool ready;
934 u32 nop;
935 u32 idx;
936 u64 last_semaphore_signal_addr;
937 u64 last_semaphore_wait_addr;
938 u32 me;
939 u32 pipe;
940 u32 queue;
941 struct amdgpu_bo *mqd_obj;
942 u32 doorbell_index;
943 bool use_doorbell;
944 unsigned wptr_offs;
945 unsigned next_rptr_offs;
946 unsigned fence_offs;
3cb485f3 947 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 948 enum amdgpu_ring_type type;
949 char name[16];
950};
951
952/*
953 * VM
954 */
955
956/* maximum number of VMIDs */
957#define AMDGPU_NUM_VM 16
958
959/* number of entries in page table */
960#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
961
962/* PTBs (Page Table Blocks) need to be aligned to 32K */
963#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
964#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
965#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
966
967#define AMDGPU_PTE_VALID (1 << 0)
968#define AMDGPU_PTE_SYSTEM (1 << 1)
969#define AMDGPU_PTE_SNOOPED (1 << 2)
970
971/* VI only */
972#define AMDGPU_PTE_EXECUTABLE (1 << 4)
973
974#define AMDGPU_PTE_READABLE (1 << 5)
975#define AMDGPU_PTE_WRITEABLE (1 << 6)
976
977/* PTE (Page Table Entry) fragment field for different page sizes */
978#define AMDGPU_PTE_FRAG_4KB (0 << 7)
979#define AMDGPU_PTE_FRAG_64KB (4 << 7)
980#define AMDGPU_LOG2_PAGES_PER_FRAG 4
981
982struct amdgpu_vm_pt {
983 struct amdgpu_bo *bo;
984 uint64_t addr;
985};
986
987struct amdgpu_vm_id {
988 unsigned id;
989 uint64_t pd_gpu_addr;
990 /* last flushed PD/PT update */
991 struct amdgpu_fence *flushed_updates;
992 /* last use of vmid */
993 struct amdgpu_fence *last_id_use;
994};
995
996struct amdgpu_vm {
997 struct mutex mutex;
998
999 struct rb_root va;
1000
1001 /* protecting invalidated and freed */
1002 spinlock_t status_lock;
1003
1004 /* BOs moved, but not yet updated in the PT */
1005 struct list_head invalidated;
1006
1007 /* BOs freed, but not yet updated in the PT */
1008 struct list_head freed;
1009
1010 /* contains the page directory */
1011 struct amdgpu_bo *page_directory;
1012 unsigned max_pde_used;
1013
1014 /* array of page tables, one for each page directory entry */
1015 struct amdgpu_vm_pt *page_tables;
1016
1017 /* for id and flush management per ring */
1018 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
1019};
1020
1021struct amdgpu_vm_manager {
1022 struct amdgpu_fence *active[AMDGPU_NUM_VM];
1023 uint32_t max_pfn;
1024 /* number of VMIDs */
1025 unsigned nvm;
1026 /* vram base address for page table entry */
1027 u64 vram_base_offset;
1028 /* is vm enabled? */
1029 bool enabled;
1030 /* for hw to save the PD addr on suspend/resume */
1031 uint32_t saved_table_addr[AMDGPU_NUM_VM];
1032 /* vm pte handling */
1033 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
1034 struct amdgpu_ring *vm_pte_funcs_ring;
1035};
1036
1037/*
1038 * context related structures
1039 */
1040
1041struct amdgpu_ctx_state {
1042 uint64_t flags;
1043 uint64_t hangs;
1044};
1045
1046struct amdgpu_ctx {
1047 /* call kref_get()before CS start and kref_put() after CS fence signaled */
1048 struct kref refcount;
1049 struct amdgpu_fpriv *fpriv;
1050 struct amdgpu_ctx_state state;
1051 uint32_t id;
1052};
1053
1054struct amdgpu_ctx_mgr {
1055 struct amdgpu_device *adev;
1056 struct idr ctx_handles;
1057 /* lock for IDR system */
0147ee0f 1058 struct mutex lock;
97b2e202
AD		 1059};
1060
1061/*
1062 * file private structure
1063 */
1064
1065struct amdgpu_fpriv {
1066 struct amdgpu_vm vm;
1067 struct mutex bo_list_lock;
1068 struct idr bo_list_handles;
1069 struct amdgpu_ctx_mgr ctx_mgr;
1070};
1071
1072/*
1073 * residency list
1074 */
1075
1076struct amdgpu_bo_list {
1077 struct mutex lock;
1078 struct amdgpu_bo *gds_obj;
1079 struct amdgpu_bo *gws_obj;
1080 struct amdgpu_bo *oa_obj;
1081 bool has_userptr;
1082 unsigned num_entries;
1083 struct amdgpu_bo_list_entry *array;
1084};
1085
1086struct amdgpu_bo_list *
1087amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1088void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1089void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1090
1091/*
1092 * GFX stuff
1093 */
1094#include "clearstate_defs.h"
1095
1096struct amdgpu_rlc {
1097 /* for power gating */
1098 struct amdgpu_bo *save_restore_obj;
1099 uint64_t save_restore_gpu_addr;
1100 volatile uint32_t *sr_ptr;
1101 const u32 *reg_list;
1102 u32 reg_list_size;
1103 /* for clear state */
1104 struct amdgpu_bo *clear_state_obj;
1105 uint64_t clear_state_gpu_addr;
1106 volatile uint32_t *cs_ptr;
1107 const struct cs_section_def *cs_data;
1108 u32 clear_state_size;
1109 /* for cp tables */
1110 struct amdgpu_bo *cp_table_obj;
1111 uint64_t cp_table_gpu_addr;
1112 volatile uint32_t *cp_table_ptr;
1113 u32 cp_table_size;
1114};
1115
1116struct amdgpu_mec {
1117 struct amdgpu_bo *hpd_eop_obj;
1118 u64 hpd_eop_gpu_addr;
1119 u32 num_pipe;
1120 u32 num_mec;
1121 u32 num_queue;
1122};
1123
1124/*
1125 * GPU scratch registers structures, functions & helpers
1126 */
1127struct amdgpu_scratch {
1128 unsigned num_reg;
1129 uint32_t reg_base;
1130 bool free[32];
1131 uint32_t reg[32];
1132};
1133
1134/*
1135 * GFX configurations
1136 */
1137struct amdgpu_gca_config {
1138 unsigned max_shader_engines;
1139 unsigned max_tile_pipes;
1140 unsigned max_cu_per_sh;
1141 unsigned max_sh_per_se;
1142 unsigned max_backends_per_se;
1143 unsigned max_texture_channel_caches;
1144 unsigned max_gprs;
1145 unsigned max_gs_threads;
1146 unsigned max_hw_contexts;
1147 unsigned sc_prim_fifo_size_frontend;
1148 unsigned sc_prim_fifo_size_backend;
1149 unsigned sc_hiz_tile_fifo_size;
1150 unsigned sc_earlyz_tile_fifo_size;
1151
1152 unsigned num_tile_pipes;
1153 unsigned backend_enable_mask;
1154 unsigned mem_max_burst_length_bytes;
1155 unsigned mem_row_size_in_kb;
1156 unsigned shader_engine_tile_size;
1157 unsigned num_gpus;
1158 unsigned multi_gpu_tile_size;
1159 unsigned mc_arb_ramcfg;
1160 unsigned gb_addr_config;
1161
1162 uint32_t tile_mode_array[32];
1163 uint32_t macrotile_mode_array[16];
1164};
1165
1166struct amdgpu_gfx {
1167 struct mutex gpu_clock_mutex;
1168 struct amdgpu_gca_config config;
1169 struct amdgpu_rlc rlc;
1170 struct amdgpu_mec mec;
1171 struct amdgpu_scratch scratch;
1172 const struct firmware *me_fw; /* ME firmware */
1173 uint32_t me_fw_version;
1174 const struct firmware *pfp_fw; /* PFP firmware */
1175 uint32_t pfp_fw_version;
1176 const struct firmware *ce_fw; /* CE firmware */
1177 uint32_t ce_fw_version;
1178 const struct firmware *rlc_fw; /* RLC firmware */
1179 uint32_t rlc_fw_version;
1180 const struct firmware *mec_fw; /* MEC firmware */
1181 uint32_t mec_fw_version;
1182 const struct firmware *mec2_fw; /* MEC2 firmware */
1183 uint32_t mec2_fw_version;
1184 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1185 unsigned num_gfx_rings;
1186 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1187 unsigned num_compute_rings;
1188 struct amdgpu_irq_src eop_irq;
1189 struct amdgpu_irq_src priv_reg_irq;
1190 struct amdgpu_irq_src priv_inst_irq;
1191 /* gfx status */
1192 uint32_t gfx_current_status;
1193 /* sync signal for const engine */
1194 unsigned ce_sync_offs;
1195};
1196
1197int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1198 unsigned size, struct amdgpu_ib *ib);
1199void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1200int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1201 struct amdgpu_ib *ib, void *owner);
1202int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1203void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1204int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1205/* Ring access between begin & end cannot sleep */
1206void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1207int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1208int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1209void amdgpu_ring_commit(struct amdgpu_ring *ring);
1210void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1211void amdgpu_ring_undo(struct amdgpu_ring *ring);
1212void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1213void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1214bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1215unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1216 uint32_t **data);
1217int amdgpu_ring_restore(struct amdgpu_ring *ring,
1218 unsigned size, uint32_t *data);
1219int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1220 unsigned ring_size, u32 nop, u32 align_mask,
1221 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1222 enum amdgpu_ring_type ring_type);
1223void amdgpu_ring_fini(struct amdgpu_ring *ring);
1224
1225/*
1226 * CS.
1227 */
1228struct amdgpu_cs_chunk {
1229 uint32_t chunk_id;
1230 uint32_t length_dw;
1231 uint32_t *kdata;
1232 void __user *user_ptr;
1233};
1234
1235struct amdgpu_cs_parser {
1236 struct amdgpu_device *adev;
1237 struct drm_file *filp;
3cb485f3 1238 struct amdgpu_ctx *ctx;
97b2e202
AD		 1239 struct amdgpu_bo_list *bo_list;
1240 /* chunks */
1241 unsigned nchunks;
1242 struct amdgpu_cs_chunk *chunks;
1243 /* relocations */
1244 struct amdgpu_bo_list_entry *vm_bos;
1245 struct amdgpu_bo_list_entry *ib_bos;
1246 struct list_head validated;
1247
1248 struct amdgpu_ib *ibs;
1249 uint32_t num_ibs;
1250
1251 struct ww_acquire_ctx ticket;
1252
1253 /* user fence */
1254 struct amdgpu_user_fence uf;
1255};
1256
1257static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1258{
1259 return p->ibs[ib_idx].ptr[idx];
1260}
1261
1262/*
1263 * Writeback
1264 */
1265#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1266
1267struct amdgpu_wb {
1268 struct amdgpu_bo *wb_obj;
1269 volatile uint32_t *wb;
1270 uint64_t gpu_addr;
1271 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1272 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1273};
1274
1275int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1276void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1277
1278/**
1279 * struct amdgpu_pm - power management datas
1280 * It keeps track of various data needed to take powermanagement decision.
1281 */
1282
1283enum amdgpu_pm_state_type {
1284 /* not used for dpm */
1285 POWER_STATE_TYPE_DEFAULT,
1286 POWER_STATE_TYPE_POWERSAVE,
1287 /* user selectable states */
1288 POWER_STATE_TYPE_BATTERY,
1289 POWER_STATE_TYPE_BALANCED,
1290 POWER_STATE_TYPE_PERFORMANCE,
1291 /* internal states */
1292 POWER_STATE_TYPE_INTERNAL_UVD,
1293 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1294 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1295 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1296 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1297 POWER_STATE_TYPE_INTERNAL_BOOT,
1298 POWER_STATE_TYPE_INTERNAL_THERMAL,
1299 POWER_STATE_TYPE_INTERNAL_ACPI,
1300 POWER_STATE_TYPE_INTERNAL_ULV,
1301 POWER_STATE_TYPE_INTERNAL_3DPERF,
1302};
1303
1304enum amdgpu_int_thermal_type {
1305 THERMAL_TYPE_NONE,
1306 THERMAL_TYPE_EXTERNAL,
1307 THERMAL_TYPE_EXTERNAL_GPIO,
1308 THERMAL_TYPE_RV6XX,
1309 THERMAL_TYPE_RV770,
1310 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1311 THERMAL_TYPE_EVERGREEN,
1312 THERMAL_TYPE_SUMO,
1313 THERMAL_TYPE_NI,
1314 THERMAL_TYPE_SI,
1315 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1316 THERMAL_TYPE_CI,
1317 THERMAL_TYPE_KV,
1318};
1319
1320enum amdgpu_dpm_auto_throttle_src {
1321 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1322 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1323};
1324
1325enum amdgpu_dpm_event_src {
1326 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1327 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1328 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1329 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1330 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1331};
1332
1333#define AMDGPU_MAX_VCE_LEVELS 6
1334
1335enum amdgpu_vce_level {
1336 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1337 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1338 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1339 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1340 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1341 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1342};
1343
1344struct amdgpu_ps {
1345 u32 caps; /* vbios flags */
1346 u32 class; /* vbios flags */
1347 u32 class2; /* vbios flags */
1348 /* UVD clocks */
1349 u32 vclk;
1350 u32 dclk;
1351 /* VCE clocks */
1352 u32 evclk;
1353 u32 ecclk;
1354 bool vce_active;
1355 enum amdgpu_vce_level vce_level;
1356 /* asic priv */
1357 void *ps_priv;
1358};
1359
1360struct amdgpu_dpm_thermal {
1361 /* thermal interrupt work */
1362 struct work_struct work;
1363 /* low temperature threshold */
1364 int min_temp;
1365 /* high temperature threshold */
1366 int max_temp;
1367 /* was last interrupt low to high or high to low */
1368 bool high_to_low;
1369 /* interrupt source */
1370 struct amdgpu_irq_src irq;
1371};
1372
1373enum amdgpu_clk_action
1374{
1375 AMDGPU_SCLK_UP = 1,
1376 AMDGPU_SCLK_DOWN
1377};
1378
1379struct amdgpu_blacklist_clocks
1380{
1381 u32 sclk;
1382 u32 mclk;
1383 enum amdgpu_clk_action action;
1384};
1385
1386struct amdgpu_clock_and_voltage_limits {
1387 u32 sclk;
1388 u32 mclk;
1389 u16 vddc;
1390 u16 vddci;
1391};
1392
1393struct amdgpu_clock_array {
1394 u32 count;
1395 u32 *values;
1396};
1397
1398struct amdgpu_clock_voltage_dependency_entry {
1399 u32 clk;
1400 u16 v;
1401};
1402
1403struct amdgpu_clock_voltage_dependency_table {
1404 u32 count;
1405 struct amdgpu_clock_voltage_dependency_entry *entries;
1406};
1407
1408union amdgpu_cac_leakage_entry {
1409 struct {
1410 u16 vddc;
1411 u32 leakage;
1412 };
1413 struct {
1414 u16 vddc1;
1415 u16 vddc2;
1416 u16 vddc3;
1417 };
1418};
1419
1420struct amdgpu_cac_leakage_table {
1421 u32 count;
1422 union amdgpu_cac_leakage_entry *entries;
1423};
1424
1425struct amdgpu_phase_shedding_limits_entry {
1426 u16 voltage;
1427 u32 sclk;
1428 u32 mclk;
1429};
1430
1431struct amdgpu_phase_shedding_limits_table {
1432 u32 count;
1433 struct amdgpu_phase_shedding_limits_entry *entries;
1434};
1435
1436struct amdgpu_uvd_clock_voltage_dependency_entry {
1437 u32 vclk;
1438 u32 dclk;
1439 u16 v;
1440};
1441
1442struct amdgpu_uvd_clock_voltage_dependency_table {
1443 u8 count;
1444 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1445};
1446
1447struct amdgpu_vce_clock_voltage_dependency_entry {
1448 u32 ecclk;
1449 u32 evclk;
1450 u16 v;
1451};
1452
1453struct amdgpu_vce_clock_voltage_dependency_table {
1454 u8 count;
1455 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1456};
1457
1458struct amdgpu_ppm_table {
1459 u8 ppm_design;
1460 u16 cpu_core_number;
1461 u32 platform_tdp;
1462 u32 small_ac_platform_tdp;
1463 u32 platform_tdc;
1464 u32 small_ac_platform_tdc;
1465 u32 apu_tdp;
1466 u32 dgpu_tdp;
1467 u32 dgpu_ulv_power;
1468 u32 tj_max;
1469};
1470
1471struct amdgpu_cac_tdp_table {
1472 u16 tdp;
1473 u16 configurable_tdp;
1474 u16 tdc;
1475 u16 battery_power_limit;
1476 u16 small_power_limit;
1477 u16 low_cac_leakage;
1478 u16 high_cac_leakage;
1479 u16 maximum_power_delivery_limit;
1480};
1481
1482struct amdgpu_dpm_dynamic_state {
1483 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1484 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1485 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1486 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1487 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1488 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1489 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1490 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1491 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1492 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1493 struct amdgpu_clock_array valid_sclk_values;
1494 struct amdgpu_clock_array valid_mclk_values;
1495 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1496 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1497 u32 mclk_sclk_ratio;
1498 u32 sclk_mclk_delta;
1499 u16 vddc_vddci_delta;
1500 u16 min_vddc_for_pcie_gen2;
1501 struct amdgpu_cac_leakage_table cac_leakage_table;
1502 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1503 struct amdgpu_ppm_table *ppm_table;
1504 struct amdgpu_cac_tdp_table *cac_tdp_table;
1505};
1506
1507struct amdgpu_dpm_fan {
1508 u16 t_min;
1509 u16 t_med;
1510 u16 t_high;
1511 u16 pwm_min;
1512 u16 pwm_med;
1513 u16 pwm_high;
1514 u8 t_hyst;
1515 u32 cycle_delay;
1516 u16 t_max;
1517 u8 control_mode;
1518 u16 default_max_fan_pwm;
1519 u16 default_fan_output_sensitivity;
1520 u16 fan_output_sensitivity;
1521 bool ucode_fan_control;
1522};
1523
1524enum amdgpu_pcie_gen {
1525 AMDGPU_PCIE_GEN1 = 0,
1526 AMDGPU_PCIE_GEN2 = 1,
1527 AMDGPU_PCIE_GEN3 = 2,
1528 AMDGPU_PCIE_GEN_INVALID = 0xffff
1529};
1530
1531enum amdgpu_dpm_forced_level {
1532 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1533 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1534 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1535};
1536
1537struct amdgpu_vce_state {
1538 /* vce clocks */
1539 u32 evclk;
1540 u32 ecclk;
1541 /* gpu clocks */
1542 u32 sclk;
1543 u32 mclk;
1544 u8 clk_idx;
1545 u8 pstate;
1546};
1547
1548struct amdgpu_dpm_funcs {
1549 int (*get_temperature)(struct amdgpu_device *adev);
1550 int (*pre_set_power_state)(struct amdgpu_device *adev);
1551 int (*set_power_state)(struct amdgpu_device *adev);
1552 void (*post_set_power_state)(struct amdgpu_device *adev);
1553 void (*display_configuration_changed)(struct amdgpu_device *adev);
1554 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1555 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1556 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1557 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1558 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1559 bool (*vblank_too_short)(struct amdgpu_device *adev);
1560 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1561 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1562 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1563 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1564 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1565 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1566};
1567
1568struct amdgpu_dpm {
1569 struct amdgpu_ps *ps;
1570 /* number of valid power states */
1571 int num_ps;
1572 /* current power state that is active */
1573 struct amdgpu_ps *current_ps;
1574 /* requested power state */
1575 struct amdgpu_ps *requested_ps;
1576 /* boot up power state */
1577 struct amdgpu_ps *boot_ps;
1578 /* default uvd power state */
1579 struct amdgpu_ps *uvd_ps;
1580 /* vce requirements */
1581 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1582 enum amdgpu_vce_level vce_level;
1583 enum amdgpu_pm_state_type state;
1584 enum amdgpu_pm_state_type user_state;
1585 u32 platform_caps;
1586 u32 voltage_response_time;
1587 u32 backbias_response_time;
1588 void *priv;
1589 u32 new_active_crtcs;
1590 int new_active_crtc_count;
1591 u32 current_active_crtcs;
1592 int current_active_crtc_count;
1593 struct amdgpu_dpm_dynamic_state dyn_state;
1594 struct amdgpu_dpm_fan fan;
1595 u32 tdp_limit;
1596 u32 near_tdp_limit;
1597 u32 near_tdp_limit_adjusted;
1598 u32 sq_ramping_threshold;
1599 u32 cac_leakage;
1600 u16 tdp_od_limit;
1601 u32 tdp_adjustment;
1602 u16 load_line_slope;
1603 bool power_control;
1604 bool ac_power;
1605 /* special states active */
1606 bool thermal_active;
1607 bool uvd_active;
1608 bool vce_active;
1609 /* thermal handling */
1610 struct amdgpu_dpm_thermal thermal;
1611 /* forced levels */
1612 enum amdgpu_dpm_forced_level forced_level;
1613};
1614
1615struct amdgpu_pm {
1616 struct mutex mutex;
1617 /* write locked while reprogramming mclk */
1618 struct rw_semaphore mclk_lock;
1619 u32 current_sclk;
1620 u32 current_mclk;
1621 u32 default_sclk;
1622 u32 default_mclk;
1623 struct amdgpu_i2c_chan *i2c_bus;
1624 /* internal thermal controller on rv6xx+ */
1625 enum amdgpu_int_thermal_type int_thermal_type;
1626 struct device *int_hwmon_dev;
1627 /* fan control parameters */
1628 bool no_fan;
1629 u8 fan_pulses_per_revolution;
1630 u8 fan_min_rpm;
1631 u8 fan_max_rpm;
1632 /* dpm */
1633 bool dpm_enabled;
1634 struct amdgpu_dpm dpm;
1635 const struct firmware *fw; /* SMC firmware */
1636 uint32_t fw_version;
1637 const struct amdgpu_dpm_funcs *funcs;
1638};
1639
1640/*
1641 * UVD
1642 */
1643#define AMDGPU_MAX_UVD_HANDLES 10
1644#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1645#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1646#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1647
1648struct amdgpu_uvd {
1649 struct amdgpu_bo *vcpu_bo;
1650 void *cpu_addr;
1651 uint64_t gpu_addr;
1652 void *saved_bo;
1653 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1654 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1655 struct delayed_work idle_work;
1656 const struct firmware *fw; /* UVD firmware */
1657 struct amdgpu_ring ring;
1658 struct amdgpu_irq_src irq;
1659 bool address_64_bit;
1660};
1661
1662/*
1663 * VCE
1664 */
1665#define AMDGPU_MAX_VCE_HANDLES 16
1666#define AMDGPU_VCE_STACK_SIZE (1024*1024)
1667#define AMDGPU_VCE_HEAP_SIZE (4*1024*1024)
1668#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1669
1670struct amdgpu_vce {
1671 struct amdgpu_bo *vcpu_bo;
1672 uint64_t gpu_addr;
1673 unsigned fw_version;
1674 unsigned fb_version;
1675 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1676 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1677 struct delayed_work idle_work;
1678 const struct firmware *fw; /* VCE firmware */
1679 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1680 struct amdgpu_irq_src irq;
1681};
1682
1683/*
1684 * SDMA
1685 */
1686struct amdgpu_sdma {
1687 /* SDMA firmware */
1688 const struct firmware *fw;
1689 uint32_t fw_version;
1690
1691 struct amdgpu_ring ring;
1692};
1693
1694/*
1695 * Firmware
1696 */
1697struct amdgpu_firmware {
1698 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1699 bool smu_load;
1700 struct amdgpu_bo *fw_buf;
1701 unsigned int fw_size;
1702};
1703
1704/*
1705 * Benchmarking
1706 */
1707void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1708
1709
1710/*
1711 * Testing
1712 */
1713void amdgpu_test_moves(struct amdgpu_device *adev);
1714void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1715 struct amdgpu_ring *cpA,
1716 struct amdgpu_ring *cpB);
1717void amdgpu_test_syncing(struct amdgpu_device *adev);
1718
1719/*
1720 * MMU Notifier
1721 */
1722#if defined(CONFIG_MMU_NOTIFIER)
1723int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1724void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1725#else
1726static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1727{
1728 return -ENODEV;
1729}
1730static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1731#endif
1732
1733/*
1734 * Debugfs
1735 */
1736struct amdgpu_debugfs {
1737 struct drm_info_list *files;
1738 unsigned num_files;
1739};
1740
1741int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1742 struct drm_info_list *files,
1743 unsigned nfiles);
1744int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1745
1746#if defined(CONFIG_DEBUG_FS)
1747int amdgpu_debugfs_init(struct drm_minor *minor);
1748void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1749#endif
1750
1751/*
1752 * amdgpu smumgr functions
1753 */
1754struct amdgpu_smumgr_funcs {
1755 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1756 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1757 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1758};
1759
1760/*
1761 * amdgpu smumgr
1762 */
1763struct amdgpu_smumgr {
1764 struct amdgpu_bo *toc_buf;
1765 struct amdgpu_bo *smu_buf;
1766 /* asic priv smu data */
1767 void *priv;
1768 spinlock_t smu_lock;
1769 /* smumgr functions */
1770 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1771 /* ucode loading complete flag */
1772 uint32_t fw_flags;
1773};
1774
1775/*
1776 * ASIC specific register table accessible by UMD
1777 */
1778struct amdgpu_allowed_register_entry {
1779 uint32_t reg_offset;
1780 bool untouched;
1781 bool grbm_indexed;
1782};
1783
1784struct amdgpu_cu_info {
1785 uint32_t number; /* total active CU number */
1786 uint32_t ao_cu_mask;
1787 uint32_t bitmap[4][4];
1788};
1789
1790
1791/*
1792 * ASIC specific functions.
1793 */
1794struct amdgpu_asic_funcs {
1795 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1796 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1797 u32 sh_num, u32 reg_offset, u32 *value);
1798 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1799 int (*reset)(struct amdgpu_device *adev);
1800 /* wait for mc_idle */
1801 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1802 /* get the reference clock */
1803 u32 (*get_xclk)(struct amdgpu_device *adev);
1804 /* get the gpu clock counter */
1805 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1806 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1807 /* MM block clocks */
1808 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1809 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1810};
1811
1812/*
1813 * IOCTL.
1814 */
1815int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *filp);
1817int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *filp);
1819
1820int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *filp);
1824int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1825 struct drm_file *filp);
1826int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1827 struct drm_file *filp);
1828int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1829 struct drm_file *filp);
1830int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1831 struct drm_file *filp);
1832int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1833int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1834
1835int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1836 struct drm_file *filp);
1837
1838/* VRAM scratch page for HDP bug, default vram page */
1839struct amdgpu_vram_scratch {
1840 struct amdgpu_bo *robj;
1841 volatile uint32_t *ptr;
1842 u64 gpu_addr;
1843};
1844
1845/*
1846 * ACPI
1847 */
1848struct amdgpu_atif_notification_cfg {
1849 bool enabled;
1850 int command_code;
1851};
1852
1853struct amdgpu_atif_notifications {
1854 bool display_switch;
1855 bool expansion_mode_change;
1856 bool thermal_state;
1857 bool forced_power_state;
1858 bool system_power_state;
1859 bool display_conf_change;
1860 bool px_gfx_switch;
1861 bool brightness_change;
1862 bool dgpu_display_event;
1863};
1864
1865struct amdgpu_atif_functions {
1866 bool system_params;
1867 bool sbios_requests;
1868 bool select_active_disp;
1869 bool lid_state;
1870 bool get_tv_standard;
1871 bool set_tv_standard;
1872 bool get_panel_expansion_mode;
1873 bool set_panel_expansion_mode;
1874 bool temperature_change;
1875 bool graphics_device_types;
1876};
1877
1878struct amdgpu_atif {
1879 struct amdgpu_atif_notifications notifications;
1880 struct amdgpu_atif_functions functions;
1881 struct amdgpu_atif_notification_cfg notification_cfg;
1882 struct amdgpu_encoder *encoder_for_bl;
1883};
1884
1885struct amdgpu_atcs_functions {
1886 bool get_ext_state;
1887 bool pcie_perf_req;
1888 bool pcie_dev_rdy;
1889 bool pcie_bus_width;
1890};
1891
1892struct amdgpu_atcs {
1893 struct amdgpu_atcs_functions functions;
1894};
1895
1896int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv,
1897 uint32_t *id,uint32_t flags);
1898int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1899 uint32_t id);
1900int amdgpu_ctx_query(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1901 uint32_t id,struct amdgpu_ctx_state *state);
1902
1903void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
66b3cf2a
JZ		 1904struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1905int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
97b2e202
AD		 1906
1907extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1908 struct drm_file *filp);
1909
1910/*
1911 * Core structure, functions and helpers.
1912 */
1913typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1914typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1915
1916typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1917typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1918
1919struct amdgpu_device {
1920 struct device *dev;
1921 struct drm_device *ddev;
1922 struct pci_dev *pdev;
1923 struct rw_semaphore exclusive_lock;
1924
1925 /* ASIC */
1926 enum amdgpu_asic_type asic_type;
1927 uint32_t family;
1928 uint32_t rev_id;
1929 uint32_t external_rev_id;
1930 unsigned long flags;
1931 int usec_timeout;
1932 const struct amdgpu_asic_funcs *asic_funcs;
1933 bool shutdown;
1934 bool suspend;
1935 bool need_dma32;
1936 bool accel_working;
1937 bool needs_reset;
1938 struct work_struct reset_work;
1939 struct notifier_block acpi_nb;
1940 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1941 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1942 unsigned debugfs_count;
1943#if defined(CONFIG_DEBUG_FS)
1944 struct dentry *debugfs_regs;
1945#endif
1946 struct amdgpu_atif atif;
1947 struct amdgpu_atcs atcs;
1948 struct mutex srbm_mutex;
1949 /* GRBM index mutex. Protects concurrent access to GRBM index */
1950 struct mutex grbm_idx_mutex;
1951 struct dev_pm_domain vga_pm_domain;
1952 bool have_disp_power_ref;
1953
1954 /* BIOS */
1955 uint8_t *bios;
1956 bool is_atom_bios;
1957 uint16_t bios_header_start;
1958 struct amdgpu_bo *stollen_vga_memory;
1959 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1960
1961 /* Register/doorbell mmio */
1962 resource_size_t rmmio_base;
1963 resource_size_t rmmio_size;
1964 void __iomem *rmmio;
1965 /* protects concurrent MM_INDEX/DATA based register access */
1966 spinlock_t mmio_idx_lock;
1967 /* protects concurrent SMC based register access */
1968 spinlock_t smc_idx_lock;
1969 amdgpu_rreg_t smc_rreg;
1970 amdgpu_wreg_t smc_wreg;
1971 /* protects concurrent PCIE register access */
1972 spinlock_t pcie_idx_lock;
1973 amdgpu_rreg_t pcie_rreg;
1974 amdgpu_wreg_t pcie_wreg;
1975 /* protects concurrent UVD register access */
1976 spinlock_t uvd_ctx_idx_lock;
1977 amdgpu_rreg_t uvd_ctx_rreg;
1978 amdgpu_wreg_t uvd_ctx_wreg;
1979 /* protects concurrent DIDT register access */
1980 spinlock_t didt_idx_lock;
1981 amdgpu_rreg_t didt_rreg;
1982 amdgpu_wreg_t didt_wreg;
1983 /* protects concurrent ENDPOINT (audio) register access */
1984 spinlock_t audio_endpt_idx_lock;
1985 amdgpu_block_rreg_t audio_endpt_rreg;
1986 amdgpu_block_wreg_t audio_endpt_wreg;
1987 void __iomem *rio_mem;
1988 resource_size_t rio_mem_size;
1989 struct amdgpu_doorbell doorbell;
1990
1991 /* clock/pll info */
1992 struct amdgpu_clock clock;
1993
1994 /* MC */
1995 struct amdgpu_mc mc;
1996 struct amdgpu_gart gart;
1997 struct amdgpu_dummy_page dummy_page;
1998 struct amdgpu_vm_manager vm_manager;
1999
2000 /* memory management */
2001 struct amdgpu_mman mman;
2002 struct amdgpu_gem gem;
2003 struct amdgpu_vram_scratch vram_scratch;
2004 struct amdgpu_wb wb;
2005 atomic64_t vram_usage;
2006 atomic64_t vram_vis_usage;
2007 atomic64_t gtt_usage;
2008 atomic64_t num_bytes_moved;
2009
2010 /* display */
2011 struct amdgpu_mode_info mode_info;
2012 struct work_struct hotplug_work;
2013 struct amdgpu_irq_src crtc_irq;
2014 struct amdgpu_irq_src pageflip_irq;
2015 struct amdgpu_irq_src hpd_irq;
2016
2017 /* rings */
2018 wait_queue_head_t fence_queue;
2019 unsigned fence_context;
2020 struct mutex ring_lock;
2021 unsigned num_rings;
2022 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2023 bool ib_pool_ready;
2024 struct amdgpu_sa_manager ring_tmp_bo;
2025
2026 /* interrupts */
2027 struct amdgpu_irq irq;
2028
2029 /* dpm */
2030 struct amdgpu_pm pm;
2031 u32 cg_flags;
2032 u32 pg_flags;
2033
2034 /* amdgpu smumgr */
2035 struct amdgpu_smumgr smu;
2036
2037 /* gfx */
2038 struct amdgpu_gfx gfx;
2039
2040 /* sdma */
2041 struct amdgpu_sdma sdma[2];
2042 struct amdgpu_irq_src sdma_trap_irq;
2043 struct amdgpu_irq_src sdma_illegal_inst_irq;
2044
2045 /* uvd */
2046 bool has_uvd;
2047 struct amdgpu_uvd uvd;
2048
2049 /* vce */
2050 struct amdgpu_vce vce;
2051
2052 /* firmwares */
2053 struct amdgpu_firmware firmware;
2054
2055 /* GDS */
2056 struct amdgpu_gds gds;
2057
2058 const struct amdgpu_ip_block_version *ip_blocks;
2059 int num_ip_blocks;
2060 bool *ip_block_enabled;
2061 struct mutex mn_lock;
2062 DECLARE_HASHTABLE(mn_hash, 7);
2063
2064 /* tracking pinned memory */
2065 u64 vram_pin_size;
2066 u64 gart_pin_size;
2067};
2068
2069bool amdgpu_device_is_px(struct drm_device *dev);
2070int amdgpu_device_init(struct amdgpu_device *adev,
2071 struct drm_device *ddev,
2072 struct pci_dev *pdev,
2073 uint32_t flags);
2074void amdgpu_device_fini(struct amdgpu_device *adev);
2075int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2076
2077uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2078 bool always_indirect);
2079void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2080 bool always_indirect);
2081u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2082void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2083
2084u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2085void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2086
2087/*
2088 * Cast helper
2089 */
2090extern const struct fence_ops amdgpu_fence_ops;
2091static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2092{
2093 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2094
2095 if (__f->base.ops == &amdgpu_fence_ops)
2096 return __f;
2097
2098 return NULL;
2099}
2100
2101/*
2102 * Registers read & write functions.
2103 */
2104#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2105#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2106#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2107#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2108#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2109#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2110#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2111#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2112#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2113#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2114#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2115#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2116#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2117#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2118#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2119#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2120#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2121#define WREG32_P(reg, val, mask) \
2122 do { \
2123 uint32_t tmp_ = RREG32(reg); \
2124 tmp_ &= (mask); \
2125 tmp_ |= ((val) & ~(mask)); \
2126 WREG32(reg, tmp_); \
2127 } while (0)
2128#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2129#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2130#define WREG32_PLL_P(reg, val, mask) \
2131 do { \
2132 uint32_t tmp_ = RREG32_PLL(reg); \
2133 tmp_ &= (mask); \
2134 tmp_ |= ((val) & ~(mask)); \
2135 WREG32_PLL(reg, tmp_); \
2136 } while (0)
2137#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2138#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2139#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2140
2141#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2142#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2143
2144#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2145#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2146
2147#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2148 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2149 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2150
2151#define REG_GET_FIELD(value, reg, field) \
2152 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2153
2154/*
2155 * BIOS helpers.
2156 */
2157#define RBIOS8(i) (adev->bios[i])
2158#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2159#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2160
2161/*
2162 * RING helpers.
2163 */
2164static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2165{
2166 if (ring->count_dw <= 0)
2167 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2168 ring->ring[ring->wptr++] = v;
2169 ring->wptr &= ring->ptr_mask;
2170 ring->count_dw--;
2171 ring->ring_free_dw--;
2172}
2173
2174/*
2175 * ASICs macro.
2176 */
2177#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2178#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2179#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2180#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2181#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2182#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2183#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2184#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2185#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2186#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2187#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2188#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2189#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2190#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2191#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2192#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2193#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2194#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2195#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2196#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2197#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2198#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2199#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2200#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2201#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2202#define amdgpu_ring_emit_fence(r, addr, seq, write64bit) (r)->funcs->emit_fence((r), (addr), (seq), (write64bit))
2203#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2204#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2205#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2206#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2207#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2208#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2209#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2210#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2211#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2212#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2213#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2214#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2215#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2216#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2217#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2218#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2219#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2220#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2221#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2222#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2223#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2224#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2225#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2226#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2227#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2228#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2229#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2230#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2231#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2232#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2233#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2234#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2235#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2236#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2237#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2238#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2239#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2240#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2241#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2242#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2243#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2244
2245#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2246
2247/* Common functions */
2248int amdgpu_gpu_reset(struct amdgpu_device *adev);
2249void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2250bool amdgpu_card_posted(struct amdgpu_device *adev);
2251void amdgpu_update_display_priority(struct amdgpu_device *adev);
2252bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2253int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2254int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2255 u32 ip_instance, u32 ring,
2256 struct amdgpu_ring **out_ring);
2257void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2258bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2259int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2260 uint32_t flags);
2261bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2262bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2263uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2264 struct ttm_mem_reg *mem);
2265void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2266void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2267void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2268void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2269 const u32 *registers,
2270 const u32 array_size);
2271
2272bool amdgpu_device_is_px(struct drm_device *dev);
2273/* atpx handler */
2274#if defined(CONFIG_VGA_SWITCHEROO)
2275void amdgpu_register_atpx_handler(void);
2276void amdgpu_unregister_atpx_handler(void);
2277#else
2278static inline void amdgpu_register_atpx_handler(void) {}
2279static inline void amdgpu_unregister_atpx_handler(void) {}
2280#endif
2281
2282/*
2283 * KMS
2284 */
2285extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2286extern int amdgpu_max_kms_ioctl;
2287
2288int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2289int amdgpu_driver_unload_kms(struct drm_device *dev);
2290void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2291int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2292void amdgpu_driver_postclose_kms(struct drm_device *dev,
2293 struct drm_file *file_priv);
2294void amdgpu_driver_preclose_kms(struct drm_device *dev,
2295 struct drm_file *file_priv);
2296int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2297int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2298u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2299int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2300void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2301int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2302 int *max_error,
2303 struct timeval *vblank_time,
2304 unsigned flags);
2305long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2306 unsigned long arg);
2307
2308/*
2309 * vm
2310 */
2311int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2312void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2313struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2314 struct amdgpu_vm *vm,
2315 struct list_head *head);
2316struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring,
2317 struct amdgpu_vm *vm);
2318void amdgpu_vm_flush(struct amdgpu_ring *ring,
2319 struct amdgpu_vm *vm,
2320 struct amdgpu_fence *updates);
2321void amdgpu_vm_fence(struct amdgpu_device *adev,
2322 struct amdgpu_vm *vm,
2323 struct amdgpu_fence *fence);
2324uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2325int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2326 struct amdgpu_vm *vm);
2327int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2328 struct amdgpu_vm *vm);
2329int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2330 struct amdgpu_vm *vm);
2331int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2332 struct amdgpu_bo_va *bo_va,
2333 struct ttm_mem_reg *mem);
2334void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2335 struct amdgpu_bo *bo);
2336struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2337 struct amdgpu_bo *bo);
2338struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2339 struct amdgpu_vm *vm,
2340 struct amdgpu_bo *bo);
2341int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2342 struct amdgpu_bo_va *bo_va,
2343 uint64_t addr, uint64_t offset,
2344 uint64_t size, uint32_t flags);
2345int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2346 struct amdgpu_bo_va *bo_va,
2347 uint64_t addr);
2348void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2349 struct amdgpu_bo_va *bo_va);
2350
2351/*
2352 * functions used by amdgpu_encoder.c
2353 */
2354struct amdgpu_afmt_acr {
2355 u32 clock;
2356
2357 int n_32khz;
2358 int cts_32khz;
2359
2360 int n_44_1khz;
2361 int cts_44_1khz;
2362
2363 int n_48khz;
2364 int cts_48khz;
2365
2366};
2367
2368struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2369
2370/* amdgpu_acpi.c */
2371#if defined(CONFIG_ACPI)
2372int amdgpu_acpi_init(struct amdgpu_device *adev);
2373void amdgpu_acpi_fini(struct amdgpu_device *adev);
2374bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2375int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2376 u8 perf_req, bool advertise);
2377int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2378#else
2379static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2380static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2381#endif
2382
2383struct amdgpu_bo_va_mapping *
2384amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2385 uint64_t addr, struct amdgpu_bo **bo);
2386
2387#include "amdgpu_object.h"
2388
2389#endif
Linux kernel - Deliverables
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