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drm/amdgpu: update radeon acpi header
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
1f7371b2 55#include "amd_powerplay.h"
a8fe58ce 56#include "amdgpu_acp.h"
97b2e202 57
b80d8475
AD		 58#include "gpu_scheduler.h"
59
97b2e202
AD		 60/*
61 * Modules parameters.
62 */
63extern int amdgpu_modeset;
64extern int amdgpu_vram_limit;
65extern int amdgpu_gart_size;
66extern int amdgpu_benchmarking;
67extern int amdgpu_testing;
68extern int amdgpu_audio;
69extern int amdgpu_disp_priority;
70extern int amdgpu_hw_i2c;
71extern int amdgpu_pcie_gen2;
72extern int amdgpu_msi;
73extern int amdgpu_lockup_timeout;
74extern int amdgpu_dpm;
75extern int amdgpu_smc_load_fw;
76extern int amdgpu_aspm;
77extern int amdgpu_runtime_pm;
97b2e202
AD		 78extern unsigned amdgpu_ip_block_mask;
79extern int amdgpu_bapm;
80extern int amdgpu_deep_color;
81extern int amdgpu_vm_size;
82extern int amdgpu_vm_block_size;
d9c13156 83extern int amdgpu_vm_fault_stop;
b495bd3a 84extern int amdgpu_vm_debug;
1333f723 85extern int amdgpu_sched_jobs;
4afcb303 86extern int amdgpu_sched_hw_submission;
1f7371b2 87extern int amdgpu_powerplay;
97b2e202 88
4b559c90 89#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 90#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93#define AMDGPU_IB_POOL_SIZE 16
94#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95#define AMDGPUFB_CONN_LIMIT 4
96#define AMDGPU_BIOS_NUM_SCRATCH 8
97
97b2e202
AD		 98/* max number of rings */
99#define AMDGPU_MAX_RINGS 16
100#define AMDGPU_MAX_GFX_RINGS 1
101#define AMDGPU_MAX_COMPUTE_RINGS 8
102#define AMDGPU_MAX_VCE_RINGS 2
103
36f523a7
JZ		 104/* max number of IP instances */
105#define AMDGPU_MAX_SDMA_INSTANCES 2
106
97b2e202
AD		 107/* hardcode that limit for now */
108#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
109
110/* hard reset data */
111#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
112
113/* reset flags */
114#define AMDGPU_RESET_GFX (1 << 0)
115#define AMDGPU_RESET_COMPUTE (1 << 1)
116#define AMDGPU_RESET_DMA (1 << 2)
117#define AMDGPU_RESET_CP (1 << 3)
118#define AMDGPU_RESET_GRBM (1 << 4)
119#define AMDGPU_RESET_DMA1 (1 << 5)
120#define AMDGPU_RESET_RLC (1 << 6)
121#define AMDGPU_RESET_SEM (1 << 7)
122#define AMDGPU_RESET_IH (1 << 8)
123#define AMDGPU_RESET_VMC (1 << 9)
124#define AMDGPU_RESET_MC (1 << 10)
125#define AMDGPU_RESET_DISPLAY (1 << 11)
126#define AMDGPU_RESET_UVD (1 << 12)
127#define AMDGPU_RESET_VCE (1 << 13)
128#define AMDGPU_RESET_VCE1 (1 << 14)
129
130/* CG block flags */
131#define AMDGPU_CG_BLOCK_GFX (1 << 0)
132#define AMDGPU_CG_BLOCK_MC (1 << 1)
133#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
134#define AMDGPU_CG_BLOCK_UVD (1 << 3)
135#define AMDGPU_CG_BLOCK_VCE (1 << 4)
136#define AMDGPU_CG_BLOCK_HDP (1 << 5)
137#define AMDGPU_CG_BLOCK_BIF (1 << 6)
138
139/* CG flags */
140#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
141#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
142#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
143#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
144#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
145#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
146#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
147#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
148#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
149#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
150#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
151#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
152#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
153#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
154#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
155#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
156#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
157
158/* PG flags */
159#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
160#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
161#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
162#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
163#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
164#define AMDGPU_PG_SUPPORT_CP (1 << 5)
165#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
166#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
167#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
168#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
169#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
170
171/* GFX current status */
172#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173#define AMDGPU_GFX_SAFE_MODE 0x00000001L
174#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
175#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
176#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
177
178/* max cursor sizes (in pixels) */
179#define CIK_CURSOR_WIDTH 128
180#define CIK_CURSOR_HEIGHT 128
181
182struct amdgpu_device;
183struct amdgpu_fence;
184struct amdgpu_ib;
185struct amdgpu_vm;
186struct amdgpu_ring;
97b2e202 187struct amdgpu_cs_parser;
bb977d37 188struct amdgpu_job;
97b2e202 189struct amdgpu_irq_src;
0b492a4c 190struct amdgpu_fpriv;
97b2e202
AD		 191
192enum amdgpu_cp_irq {
193 AMDGPU_CP_IRQ_GFX_EOP = 0,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
202
203 AMDGPU_CP_IRQ_LAST
204};
205
206enum amdgpu_sdma_irq {
207 AMDGPU_SDMA_IRQ_TRAP0 = 0,
208 AMDGPU_SDMA_IRQ_TRAP1,
209
210 AMDGPU_SDMA_IRQ_LAST
211};
212
213enum amdgpu_thermal_irq {
214 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
215 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
216
217 AMDGPU_THERMAL_IRQ_LAST
218};
219
97b2e202 220int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 221 enum amd_ip_block_type block_type,
222 enum amd_clockgating_state state);
97b2e202 223int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 224 enum amd_ip_block_type block_type,
225 enum amd_powergating_state state);
97b2e202
AD		 226
227struct amdgpu_ip_block_version {
5fc3aeeb 228 enum amd_ip_block_type type;
97b2e202
AD		 229 u32 major;
230 u32 minor;
231 u32 rev;
5fc3aeeb 232 const struct amd_ip_funcs *funcs;
97b2e202
AD		 233};
234
235int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 236 enum amd_ip_block_type type,
97b2e202
AD		 237 u32 major, u32 minor);
238
239const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
240 struct amdgpu_device *adev,
5fc3aeeb 241 enum amd_ip_block_type type);
97b2e202
AD		 242
243/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
244struct amdgpu_buffer_funcs {
245 /* maximum bytes in a single operation */
246 uint32_t copy_max_bytes;
247
248 /* number of dw to reserve per operation */
249 unsigned copy_num_dw;
250
251 /* used for buffer migration */
c7ae72c0 252 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 253 /* src addr in bytes */
254 uint64_t src_offset,
255 /* dst addr in bytes */
256 uint64_t dst_offset,
257 /* number of byte to transfer */
258 uint32_t byte_count);
259
260 /* maximum bytes in a single operation */
261 uint32_t fill_max_bytes;
262
263 /* number of dw to reserve per operation */
264 unsigned fill_num_dw;
265
266 /* used for buffer clearing */
6e7a3840 267 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
97b2e202
AD		 268 /* value to write to memory */
269 uint32_t src_data,
270 /* dst addr in bytes */
271 uint64_t dst_offset,
272 /* number of byte to fill */
273 uint32_t byte_count);
274};
275
276/* provided by hw blocks that can write ptes, e.g., sdma */
277struct amdgpu_vm_pte_funcs {
278 /* copy pte entries from GART */
279 void (*copy_pte)(struct amdgpu_ib *ib,
280 uint64_t pe, uint64_t src,
281 unsigned count);
282 /* write pte one entry at a time with addr mapping */
283 void (*write_pte)(struct amdgpu_ib *ib,
b07c9d2a 284 const dma_addr_t *pages_addr, uint64_t pe,
97b2e202
AD		 285 uint64_t addr, unsigned count,
286 uint32_t incr, uint32_t flags);
287 /* for linear pte/pde updates without addr mapping */
288 void (*set_pte_pde)(struct amdgpu_ib *ib,
289 uint64_t pe,
290 uint64_t addr, unsigned count,
291 uint32_t incr, uint32_t flags);
97b2e202
AD		 292};
293
294/* provided by the gmc block */
295struct amdgpu_gart_funcs {
296 /* flush the vm tlb via mmio */
297 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
298 uint32_t vmid);
299 /* write pte/pde updates using the cpu */
300 int (*set_pte_pde)(struct amdgpu_device *adev,
301 void *cpu_pt_addr, /* cpu addr of page table */
302 uint32_t gpu_page_idx, /* pte/pde to update */
303 uint64_t addr, /* addr to write into pte/pde */
304 uint32_t flags); /* access flags */
305};
306
307/* provided by the ih block */
308struct amdgpu_ih_funcs {
309 /* ring read/write ptr handling, called from interrupt context */
310 u32 (*get_wptr)(struct amdgpu_device *adev);
311 void (*decode_iv)(struct amdgpu_device *adev,
312 struct amdgpu_iv_entry *entry);
313 void (*set_rptr)(struct amdgpu_device *adev);
314};
315
316/* provided by hw blocks that expose a ring buffer for commands */
317struct amdgpu_ring_funcs {
318 /* ring read/write ptr handling */
319 u32 (*get_rptr)(struct amdgpu_ring *ring);
320 u32 (*get_wptr)(struct amdgpu_ring *ring);
321 void (*set_wptr)(struct amdgpu_ring *ring);
322 /* validating and patching of IBs */
323 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
324 /* command emit functions */
325 void (*emit_ib)(struct amdgpu_ring *ring,
326 struct amdgpu_ib *ib);
327 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 328 uint64_t seq, unsigned flags);
97b2e202
AD		 329 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
330 uint64_t pd_addr);
d2edb07b 331 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 332 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
333 uint32_t gds_base, uint32_t gds_size,
334 uint32_t gws_base, uint32_t gws_size,
335 uint32_t oa_base, uint32_t oa_size);
336 /* testing functions */
337 int (*test_ring)(struct amdgpu_ring *ring);
338 int (*test_ib)(struct amdgpu_ring *ring);
edff0e28
JZ		 339 /* insert NOP packets */
340 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
9e5d5309
CK		 341 /* pad the indirect buffer to the necessary number of dw */
342 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202
AD		 343};
344
345/*
346 * BIOS.
347 */
348bool amdgpu_get_bios(struct amdgpu_device *adev);
349bool amdgpu_read_bios(struct amdgpu_device *adev);
350
351/*
352 * Dummy page
353 */
354struct amdgpu_dummy_page {
355 struct page *page;
356 dma_addr_t addr;
357};
358int amdgpu_dummy_page_init(struct amdgpu_device *adev);
359void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
360
361
362/*
363 * Clocks
364 */
365
366#define AMDGPU_MAX_PPLL 3
367
368struct amdgpu_clock {
369 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
370 struct amdgpu_pll spll;
371 struct amdgpu_pll mpll;
372 /* 10 Khz units */
373 uint32_t default_mclk;
374 uint32_t default_sclk;
375 uint32_t default_dispclk;
376 uint32_t current_dispclk;
377 uint32_t dp_extclk;
378 uint32_t max_pixel_clock;
379};
380
381/*
382 * Fences.
383 */
384struct amdgpu_fence_driver {
97b2e202
AD		 385 uint64_t gpu_addr;
386 volatile uint32_t *cpu_addr;
387 /* sync_seq is protected by ring emission lock */
5907a0d8 388 uint64_t sync_seq;
97b2e202
AD		 389 atomic64_t last_seq;
390 bool initialized;
97b2e202
AD		 391 struct amdgpu_irq_src *irq_src;
392 unsigned irq_type;
c2776afe 393 struct timer_list fallback_timer;
7f06c236 394 wait_queue_head_t fence_queue;
97b2e202
AD		 395};
396
397/* some special values for the owner field */
398#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
399#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
97b2e202 400
890ee23f
CZ		 401#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
402#define AMDGPU_FENCE_FLAG_INT (1 << 1)
403
97b2e202
AD		 404struct amdgpu_fence {
405 struct fence base;
4cef9267 406
97b2e202
AD		 407 /* RB, DMA, etc. */
408 struct amdgpu_ring *ring;
409 uint64_t seq;
410
411 /* filp or special value for fence creator */
412 void *owner;
413
414 wait_queue_t fence_wake;
415};
416
417struct amdgpu_user_fence {
418 /* write-back bo */
419 struct amdgpu_bo *bo;
420 /* write-back address offset to bo start */
421 uint32_t offset;
422};
423
424int amdgpu_fence_driver_init(struct amdgpu_device *adev);
425void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
426void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
427
4f839a24 428int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
97b2e202
AD		 429int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
430 struct amdgpu_irq_src *irq_src,
431 unsigned irq_type);
5ceb54c6
AD		 432void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
433void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 434int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
435 struct amdgpu_fence **fence);
436void amdgpu_fence_process(struct amdgpu_ring *ring);
437int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
438int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
439unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
440
97b2e202
AD		 441/*
442 * TTM.
443 */
444struct amdgpu_mman {
445 struct ttm_bo_global_ref bo_global_ref;
446 struct drm_global_reference mem_global_ref;
447 struct ttm_bo_device bdev;
448 bool mem_global_referenced;
449 bool initialized;
450
451#if defined(CONFIG_DEBUG_FS)
452 struct dentry *vram;
453 struct dentry *gtt;
454#endif
455
456 /* buffer handling */
457 const struct amdgpu_buffer_funcs *buffer_funcs;
458 struct amdgpu_ring *buffer_funcs_ring;
703297c1
CK		 459 /* Scheduler entity for buffer moves */
460 struct amd_sched_entity entity;
97b2e202
AD		 461};
462
463int amdgpu_copy_buffer(struct amdgpu_ring *ring,
464 uint64_t src_offset,
465 uint64_t dst_offset,
466 uint32_t byte_count,
467 struct reservation_object *resv,
c7ae72c0 468 struct fence **fence);
97b2e202
AD		 469int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
470
471struct amdgpu_bo_list_entry {
472 struct amdgpu_bo *robj;
473 struct ttm_validate_buffer tv;
474 struct amdgpu_bo_va *bo_va;
97b2e202
AD		 475 uint32_t priority;
476};
477
478struct amdgpu_bo_va_mapping {
479 struct list_head list;
480 struct interval_tree_node it;
481 uint64_t offset;
482 uint32_t flags;
483};
484
485/* bo virtual addresses in a specific vm */
486struct amdgpu_bo_va {
69b576a1 487 struct mutex mutex;
97b2e202
AD		 488 /* protected by bo being reserved */
489 struct list_head bo_list;
bb1e38a4 490 struct fence *last_pt_update;
97b2e202
AD		 491 unsigned ref_count;
492
7fc11959 493 /* protected by vm mutex and spinlock */
97b2e202
AD		 494 struct list_head vm_status;
495
7fc11959
CK		 496 /* mappings for this bo_va */
497 struct list_head invalids;
498 struct list_head valids;
499
97b2e202
AD		 500 /* constant after initialization */
501 struct amdgpu_vm *vm;
502 struct amdgpu_bo *bo;
503};
504
7e5a547f
CZ		 505#define AMDGPU_GEM_DOMAIN_MAX 0x3
506
97b2e202
AD		 507struct amdgpu_bo {
508 /* Protected by gem.mutex */
509 struct list_head list;
510 /* Protected by tbo.reserved */
1ea863fd
CK		 511 u32 prefered_domains;
512 u32 allowed_domains;
7e5a547f 513 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 514 struct ttm_placement placement;
515 struct ttm_buffer_object tbo;
516 struct ttm_bo_kmap_obj kmap;
517 u64 flags;
518 unsigned pin_count;
519 void *kptr;
520 u64 tiling_flags;
521 u64 metadata_flags;
522 void *metadata;
523 u32 metadata_size;
524 /* list of all virtual address to which this bo
525 * is associated to
526 */
527 struct list_head va;
528 /* Constant after initialization */
529 struct amdgpu_device *adev;
530 struct drm_gem_object gem_base;
82b9c55b 531 struct amdgpu_bo *parent;
97b2e202
AD		 532
533 struct ttm_bo_kmap_obj dma_buf_vmap;
97b2e202
AD		 534 struct amdgpu_mn *mn;
535 struct list_head mn_list;
536};
537#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
538
539void amdgpu_gem_object_free(struct drm_gem_object *obj);
540int amdgpu_gem_object_open(struct drm_gem_object *obj,
541 struct drm_file *file_priv);
542void amdgpu_gem_object_close(struct drm_gem_object *obj,
543 struct drm_file *file_priv);
544unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
545struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
546struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
547 struct dma_buf_attachment *attach,
548 struct sg_table *sg);
549struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
550 struct drm_gem_object *gobj,
551 int flags);
552int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
553void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
554struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
555void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
556void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
557int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
558
559/* sub-allocation manager, it has to be protected by another lock.
560 * By conception this is an helper for other part of the driver
561 * like the indirect buffer or semaphore, which both have their
562 * locking.
563 *
564 * Principe is simple, we keep a list of sub allocation in offset
565 * order (first entry has offset == 0, last entry has the highest
566 * offset).
567 *
568 * When allocating new object we first check if there is room at
569 * the end total_size - (last_object_offset + last_object_size) >=
570 * alloc_size. If so we allocate new object there.
571 *
572 * When there is not enough room at the end, we start waiting for
573 * each sub object until we reach object_offset+object_size >=
574 * alloc_size, this object then become the sub object we return.
575 *
576 * Alignment can't be bigger than page size.
577 *
578 * Hole are not considered for allocation to keep things simple.
579 * Assumption is that there won't be hole (all object on same
580 * alignment).
581 */
582struct amdgpu_sa_manager {
583 wait_queue_head_t wq;
584 struct amdgpu_bo *bo;
585 struct list_head *hole;
586 struct list_head flist[AMDGPU_MAX_RINGS];
587 struct list_head olist;
588 unsigned size;
589 uint64_t gpu_addr;
590 void *cpu_ptr;
591 uint32_t domain;
592 uint32_t align;
593};
594
595struct amdgpu_sa_bo;
596
597/* sub-allocation buffer */
598struct amdgpu_sa_bo {
599 struct list_head olist;
600 struct list_head flist;
601 struct amdgpu_sa_manager *manager;
602 unsigned soffset;
603 unsigned eoffset;
4ce9891e 604 struct fence *fence;
97b2e202
AD		 605};
606
607/*
608 * GEM objects.
609 */
418aa0c2 610void amdgpu_gem_force_release(struct amdgpu_device *adev);
97b2e202
AD		 611int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
612 int alignment, u32 initial_domain,
613 u64 flags, bool kernel,
614 struct drm_gem_object **obj);
615
616int amdgpu_mode_dumb_create(struct drm_file *file_priv,
617 struct drm_device *dev,
618 struct drm_mode_create_dumb *args);
619int amdgpu_mode_dumb_mmap(struct drm_file *filp,
620 struct drm_device *dev,
621 uint32_t handle, uint64_t *offset_p);
97b2e202
AD		 622/*
623 * Synchronization
624 */
625struct amdgpu_sync {
f91b3a69 626 DECLARE_HASHTABLE(fences, 4);
3c62338c 627 struct fence *last_vm_update;
97b2e202
AD		 628};
629
630void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 631int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
632 struct fence *f);
97b2e202
AD		 633int amdgpu_sync_resv(struct amdgpu_device *adev,
634 struct amdgpu_sync *sync,
635 struct reservation_object *resv,
636 void *owner);
e61235db 637struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
f91b3a69 638int amdgpu_sync_wait(struct amdgpu_sync *sync);
8a8f0b48 639void amdgpu_sync_free(struct amdgpu_sync *sync);
97b2e202
AD		 640
641/*
642 * GART structures, functions & helpers
643 */
644struct amdgpu_mc;
645
646#define AMDGPU_GPU_PAGE_SIZE 4096
647#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
648#define AMDGPU_GPU_PAGE_SHIFT 12
649#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
650
651struct amdgpu_gart {
652 dma_addr_t table_addr;
653 struct amdgpu_bo *robj;
654 void *ptr;
655 unsigned num_gpu_pages;
656 unsigned num_cpu_pages;
657 unsigned table_size;
658 struct page **pages;
659 dma_addr_t *pages_addr;
660 bool ready;
661 const struct amdgpu_gart_funcs *gart_funcs;
662};
663
664int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
665void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
666int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
667void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
668int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
669void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
670int amdgpu_gart_init(struct amdgpu_device *adev);
671void amdgpu_gart_fini(struct amdgpu_device *adev);
672void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
673 int pages);
674int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
675 int pages, struct page **pagelist,
676 dma_addr_t *dma_addr, uint32_t flags);
677
678/*
679 * GPU MC structures, functions & helpers
680 */
681struct amdgpu_mc {
682 resource_size_t aper_size;
683 resource_size_t aper_base;
684 resource_size_t agp_base;
685 /* for some chips with <= 32MB we need to lie
686 * about vram size near mc fb location */
687 u64 mc_vram_size;
688 u64 visible_vram_size;
689 u64 gtt_size;
690 u64 gtt_start;
691 u64 gtt_end;
692 u64 vram_start;
693 u64 vram_end;
694 unsigned vram_width;
695 u64 real_vram_size;
696 int vram_mtrr;
697 u64 gtt_base_align;
698 u64 mc_mask;
699 const struct firmware *fw; /* MC firmware */
700 uint32_t fw_version;
701 struct amdgpu_irq_src vm_fault;
81c59f54 702 uint32_t vram_type;
97b2e202
AD		 703};
704
705/*
706 * GPU doorbell structures, functions & helpers
707 */
708typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
709{
710 AMDGPU_DOORBELL_KIQ = 0x000,
711 AMDGPU_DOORBELL_HIQ = 0x001,
712 AMDGPU_DOORBELL_DIQ = 0x002,
713 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
714 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
715 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
716 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
717 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
718 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
719 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
720 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
721 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
722 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
723 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
724 AMDGPU_DOORBELL_IH = 0x1E8,
725 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
726 AMDGPU_DOORBELL_INVALID = 0xFFFF
727} AMDGPU_DOORBELL_ASSIGNMENT;
728
729struct amdgpu_doorbell {
730 /* doorbell mmio */
731 resource_size_t base;
732 resource_size_t size;
733 u32 __iomem *ptr;
734 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
735};
736
737void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
738 phys_addr_t *aperture_base,
739 size_t *aperture_size,
740 size_t *start_offset);
741
742/*
743 * IRQS.
744 */
745
746struct amdgpu_flip_work {
747 struct work_struct flip_work;
748 struct work_struct unpin_work;
749 struct amdgpu_device *adev;
750 int crtc_id;
751 uint64_t base;
752 struct drm_pending_vblank_event *event;
753 struct amdgpu_bo *old_rbo;
1ffd2652
CK		 754 struct fence *excl;
755 unsigned shared_count;
756 struct fence **shared;
c3874b75 757 struct fence_cb cb;
97b2e202
AD		 758};
759
760
761/*
762 * CP & rings.
763 */
764
765struct amdgpu_ib {
766 struct amdgpu_sa_bo *sa_bo;
767 uint32_t length_dw;
768 uint64_t gpu_addr;
769 uint32_t *ptr;
97b2e202
AD		 770 struct amdgpu_fence *fence;
771 struct amdgpu_user_fence *user;
8d0a7cea 772 bool grabbed_vmid;
97b2e202 773 struct amdgpu_vm *vm;
3cb485f3 774 struct amdgpu_ctx *ctx;
97b2e202
AD		 775 uint32_t gds_base, gds_size;
776 uint32_t gws_base, gws_size;
777 uint32_t oa_base, oa_size;
de807f81 778 uint32_t flags;
5430a3ff
CK		 779 /* resulting sequence number */
780 uint64_t sequence;
97b2e202
AD		 781};
782
783enum amdgpu_ring_type {
784 AMDGPU_RING_TYPE_GFX,
785 AMDGPU_RING_TYPE_COMPUTE,
786 AMDGPU_RING_TYPE_SDMA,
787 AMDGPU_RING_TYPE_UVD,
788 AMDGPU_RING_TYPE_VCE
789};
790
c1b69ed0
CZ		 791extern struct amd_sched_backend_ops amdgpu_sched_ops;
792
50838c8c
CK		 793int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
794 struct amdgpu_job **job);
d71518b5
CK		 795int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
796 struct amdgpu_job **job);
50838c8c 797void amdgpu_job_free(struct amdgpu_job *job);
d71518b5 798int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
2bd9ccfa
CK		 799 struct amd_sched_entity *entity, void *owner,
800 struct fence **f);
3c704e93 801
97b2e202
AD		 802struct amdgpu_ring {
803 struct amdgpu_device *adev;
804 const struct amdgpu_ring_funcs *funcs;
805 struct amdgpu_fence_driver fence_drv;
4f839a24 806 struct amd_gpu_scheduler sched;
97b2e202 807
176e1ab1 808 spinlock_t fence_lock;
97b2e202
AD		 809 struct amdgpu_bo *ring_obj;
810 volatile uint32_t *ring;
811 unsigned rptr_offs;
812 u64 next_rptr_gpu_addr;
813 volatile u32 *next_rptr_cpu_addr;
814 unsigned wptr;
815 unsigned wptr_old;
816 unsigned ring_size;
c7e6be23 817 unsigned max_dw;
97b2e202 818 int count_dw;
97b2e202
AD		 819 uint64_t gpu_addr;
820 uint32_t align_mask;
821 uint32_t ptr_mask;
822 bool ready;
823 u32 nop;
824 u32 idx;
97b2e202
AD		 825 u32 me;
826 u32 pipe;
827 u32 queue;
828 struct amdgpu_bo *mqd_obj;
829 u32 doorbell_index;
830 bool use_doorbell;
831 unsigned wptr_offs;
832 unsigned next_rptr_offs;
833 unsigned fence_offs;
3cb485f3 834 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 835 enum amdgpu_ring_type type;
836 char name[16];
837};
838
839/*
840 * VM
841 */
842
843/* maximum number of VMIDs */
844#define AMDGPU_NUM_VM 16
845
846/* number of entries in page table */
847#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
848
849/* PTBs (Page Table Blocks) need to be aligned to 32K */
850#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
851#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
852#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
853
854#define AMDGPU_PTE_VALID (1 << 0)
855#define AMDGPU_PTE_SYSTEM (1 << 1)
856#define AMDGPU_PTE_SNOOPED (1 << 2)
857
858/* VI only */
859#define AMDGPU_PTE_EXECUTABLE (1 << 4)
860
861#define AMDGPU_PTE_READABLE (1 << 5)
862#define AMDGPU_PTE_WRITEABLE (1 << 6)
863
864/* PTE (Page Table Entry) fragment field for different page sizes */
865#define AMDGPU_PTE_FRAG_4KB (0 << 7)
866#define AMDGPU_PTE_FRAG_64KB (4 << 7)
867#define AMDGPU_LOG2_PAGES_PER_FRAG 4
868
d9c13156
CK		 869/* How to programm VM fault handling */
870#define AMDGPU_VM_FAULT_STOP_NEVER 0
871#define AMDGPU_VM_FAULT_STOP_FIRST 1
872#define AMDGPU_VM_FAULT_STOP_ALWAYS 2
873
97b2e202 874struct amdgpu_vm_pt {
ee1782c3
CK		 875 struct amdgpu_bo_list_entry entry;
876 uint64_t addr;
97b2e202
AD		 877};
878
879struct amdgpu_vm_id {
880 unsigned id;
881 uint64_t pd_gpu_addr;
882 /* last flushed PD/PT update */
3c62338c 883 struct fence *flushed_updates;
97b2e202
AD		 884};
885
886struct amdgpu_vm {
25cfc3c2
CK		 887 /* tree of virtual addresses mapped */
888 spinlock_t it_lock;
97b2e202
AD		 889 struct rb_root va;
890
7fc11959 891 /* protecting invalidated */
97b2e202
AD		 892 spinlock_t status_lock;
893
894 /* BOs moved, but not yet updated in the PT */
895 struct list_head invalidated;
896
7fc11959
CK		 897 /* BOs cleared in the PT because of a move */
898 struct list_head cleared;
899
900 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 901 struct list_head freed;
902
903 /* contains the page directory */
904 struct amdgpu_bo *page_directory;
905 unsigned max_pde_used;
05906dec 906 struct fence *page_directory_fence;
97b2e202
AD		 907
908 /* array of page tables, one for each page directory entry */
909 struct amdgpu_vm_pt *page_tables;
910
911 /* for id and flush management per ring */
912 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
25cfc3c2 913
81d75a30 914 /* protecting freed */
915 spinlock_t freed_lock;
2bd9ccfa
CK		 916
917 /* Scheduler entity for page table updates */
918 struct amd_sched_entity entity;
97b2e202
AD		 919};
920
a9a78b32
CK		 921struct amdgpu_vm_manager_id {
922 struct list_head list;
923 struct fence *active;
924 atomic_long_t owner;
925};
926
97b2e202 927struct amdgpu_vm_manager {
a9a78b32 928 /* Handling of VMIDs */
8d0a7cea 929 struct mutex lock;
a9a78b32
CK		 930 unsigned num_ids;
931 struct list_head ids_lru;
932 struct amdgpu_vm_manager_id ids[AMDGPU_NUM_VM];
1c16c0a7 933
8b4fb00b 934 uint32_t max_pfn;
97b2e202 935 /* vram base address for page table entry */
8b4fb00b 936 u64 vram_base_offset;
97b2e202 937 /* is vm enabled? */
8b4fb00b 938 bool enabled;
97b2e202
AD		 939 /* vm pte handling */
940 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
2d55e45a
CK		 941 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
942 unsigned vm_pte_num_rings;
943 atomic_t vm_pte_next_ring;
97b2e202
AD		 944};
945
a9a78b32 946void amdgpu_vm_manager_init(struct amdgpu_device *adev);
ea89f8c9 947void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
8b4fb00b
CK		 948int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
949void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
56467ebf
CK		 950void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
951 struct list_head *validated,
952 struct amdgpu_bo_list_entry *entry);
ee1782c3 953void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
eceb8a15
CK		 954void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
955 struct amdgpu_vm *vm);
8b4fb00b 956int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
94dd0a4a 957 struct amdgpu_sync *sync, struct fence *fence);
8b4fb00b
CK		 958void amdgpu_vm_flush(struct amdgpu_ring *ring,
959 struct amdgpu_vm *vm,
960 struct fence *updates);
b07c9d2a 961uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
8b4fb00b
CK		 962int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
963 struct amdgpu_vm *vm);
964int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
965 struct amdgpu_vm *vm);
966int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
967 struct amdgpu_sync *sync);
968int amdgpu_vm_bo_update(struct amdgpu_device *adev,
969 struct amdgpu_bo_va *bo_va,
970 struct ttm_mem_reg *mem);
971void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
972 struct amdgpu_bo *bo);
973struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
974 struct amdgpu_bo *bo);
975struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
976 struct amdgpu_vm *vm,
977 struct amdgpu_bo *bo);
978int amdgpu_vm_bo_map(struct amdgpu_device *adev,
979 struct amdgpu_bo_va *bo_va,
980 uint64_t addr, uint64_t offset,
981 uint64_t size, uint32_t flags);
982int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
983 struct amdgpu_bo_va *bo_va,
984 uint64_t addr);
985void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
986 struct amdgpu_bo_va *bo_va);
8b4fb00b 987
97b2e202
AD		 988/*
989 * context related structures
990 */
991
21c16bf6 992struct amdgpu_ctx_ring {
91404fb2 993 uint64_t sequence;
37cd0ca2 994 struct fence **fences;
91404fb2 995 struct amd_sched_entity entity;
21c16bf6
CK		 996};
997
97b2e202 998struct amdgpu_ctx {
0b492a4c 999 struct kref refcount;
9cb7e5a9 1000 struct amdgpu_device *adev;
0b492a4c 1001 unsigned reset_counter;
21c16bf6 1002 spinlock_t ring_lock;
37cd0ca2 1003 struct fence **fences;
21c16bf6 1004 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1005};
1006
1007struct amdgpu_ctx_mgr {
0b492a4c
AD		 1008 struct amdgpu_device *adev;
1009 struct mutex lock;
1010 /* protected by lock */
1011 struct idr ctx_handles;
97b2e202
AD		 1012};
1013
0b492a4c
AD		 1014struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1015int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1016
21c16bf6 1017uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
ce882e6d 1018 struct fence *fence);
21c16bf6
CK		 1019struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1020 struct amdgpu_ring *ring, uint64_t seq);
1021
0b492a4c
AD		 1022int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1023 struct drm_file *filp);
1024
efd4ccb5
CK		 1025void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1026void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
0b492a4c 1027
97b2e202
AD		 1028/*
1029 * file private structure
1030 */
1031
1032struct amdgpu_fpriv {
1033 struct amdgpu_vm vm;
1034 struct mutex bo_list_lock;
1035 struct idr bo_list_handles;
0b492a4c 1036 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1037};
1038
1039/*
1040 * residency list
1041 */
1042
1043struct amdgpu_bo_list {
1044 struct mutex lock;
1045 struct amdgpu_bo *gds_obj;
1046 struct amdgpu_bo *gws_obj;
1047 struct amdgpu_bo *oa_obj;
1048 bool has_userptr;
1049 unsigned num_entries;
1050 struct amdgpu_bo_list_entry *array;
1051};
1052
1053struct amdgpu_bo_list *
1054amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
636ce25c
CK		 1055void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1056 struct list_head *validated);
97b2e202
AD		 1057void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1058void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1059
1060/*
1061 * GFX stuff
1062 */
1063#include "clearstate_defs.h"
1064
1065struct amdgpu_rlc {
1066 /* for power gating */
1067 struct amdgpu_bo *save_restore_obj;
1068 uint64_t save_restore_gpu_addr;
1069 volatile uint32_t *sr_ptr;
1070 const u32 *reg_list;
1071 u32 reg_list_size;
1072 /* for clear state */
1073 struct amdgpu_bo *clear_state_obj;
1074 uint64_t clear_state_gpu_addr;
1075 volatile uint32_t *cs_ptr;
1076 const struct cs_section_def *cs_data;
1077 u32 clear_state_size;
1078 /* for cp tables */
1079 struct amdgpu_bo *cp_table_obj;
1080 uint64_t cp_table_gpu_addr;
1081 volatile uint32_t *cp_table_ptr;
1082 u32 cp_table_size;
1083};
1084
1085struct amdgpu_mec {
1086 struct amdgpu_bo *hpd_eop_obj;
1087 u64 hpd_eop_gpu_addr;
1088 u32 num_pipe;
1089 u32 num_mec;
1090 u32 num_queue;
1091};
1092
1093/*
1094 * GPU scratch registers structures, functions & helpers
1095 */
1096struct amdgpu_scratch {
1097 unsigned num_reg;
1098 uint32_t reg_base;
1099 bool free[32];
1100 uint32_t reg[32];
1101};
1102
1103/*
1104 * GFX configurations
1105 */
1106struct amdgpu_gca_config {
1107 unsigned max_shader_engines;
1108 unsigned max_tile_pipes;
1109 unsigned max_cu_per_sh;
1110 unsigned max_sh_per_se;
1111 unsigned max_backends_per_se;
1112 unsigned max_texture_channel_caches;
1113 unsigned max_gprs;
1114 unsigned max_gs_threads;
1115 unsigned max_hw_contexts;
1116 unsigned sc_prim_fifo_size_frontend;
1117 unsigned sc_prim_fifo_size_backend;
1118 unsigned sc_hiz_tile_fifo_size;
1119 unsigned sc_earlyz_tile_fifo_size;
1120
1121 unsigned num_tile_pipes;
1122 unsigned backend_enable_mask;
1123 unsigned mem_max_burst_length_bytes;
1124 unsigned mem_row_size_in_kb;
1125 unsigned shader_engine_tile_size;
1126 unsigned num_gpus;
1127 unsigned multi_gpu_tile_size;
1128 unsigned mc_arb_ramcfg;
1129 unsigned gb_addr_config;
8f8e00c1 1130 unsigned num_rbs;
97b2e202
AD		 1131
1132 uint32_t tile_mode_array[32];
1133 uint32_t macrotile_mode_array[16];
1134};
1135
1136struct amdgpu_gfx {
1137 struct mutex gpu_clock_mutex;
1138 struct amdgpu_gca_config config;
1139 struct amdgpu_rlc rlc;
1140 struct amdgpu_mec mec;
1141 struct amdgpu_scratch scratch;
1142 const struct firmware *me_fw; /* ME firmware */
1143 uint32_t me_fw_version;
1144 const struct firmware *pfp_fw; /* PFP firmware */
1145 uint32_t pfp_fw_version;
1146 const struct firmware *ce_fw; /* CE firmware */
1147 uint32_t ce_fw_version;
1148 const struct firmware *rlc_fw; /* RLC firmware */
1149 uint32_t rlc_fw_version;
1150 const struct firmware *mec_fw; /* MEC firmware */
1151 uint32_t mec_fw_version;
1152 const struct firmware *mec2_fw; /* MEC2 firmware */
1153 uint32_t mec2_fw_version;
02558a00
KW		 1154 uint32_t me_feature_version;
1155 uint32_t ce_feature_version;
1156 uint32_t pfp_feature_version;
351643d7
JZ		 1157 uint32_t rlc_feature_version;
1158 uint32_t mec_feature_version;
1159 uint32_t mec2_feature_version;
97b2e202
AD		 1160 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1161 unsigned num_gfx_rings;
1162 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1163 unsigned num_compute_rings;
1164 struct amdgpu_irq_src eop_irq;
1165 struct amdgpu_irq_src priv_reg_irq;
1166 struct amdgpu_irq_src priv_inst_irq;
1167 /* gfx status */
1168 uint32_t gfx_current_status;
a101a899
KW		 1169 /* ce ram size*/
1170 unsigned ce_ram_size;
97b2e202
AD		 1171};
1172
b07c60c0 1173int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
97b2e202
AD		 1174 unsigned size, struct amdgpu_ib *ib);
1175void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
b07c60c0 1176int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
ec72b800 1177 struct amdgpu_ib *ib, void *owner,
e86f9cee 1178 struct fence *last_vm_update,
ec72b800 1179 struct fence **f);
97b2e202
AD		 1180int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1181void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1182int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
97b2e202 1183int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
edff0e28 1184void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
9e5d5309 1185void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
97b2e202 1186void amdgpu_ring_commit(struct amdgpu_ring *ring);
97b2e202 1187void amdgpu_ring_undo(struct amdgpu_ring *ring);
97b2e202
AD		 1188unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1189 uint32_t **data);
1190int amdgpu_ring_restore(struct amdgpu_ring *ring,
1191 unsigned size, uint32_t *data);
1192int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1193 unsigned ring_size, u32 nop, u32 align_mask,
1194 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1195 enum amdgpu_ring_type ring_type);
1196void amdgpu_ring_fini(struct amdgpu_ring *ring);
8120b61f 1197struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
97b2e202
AD		 1198
1199/*
1200 * CS.
1201 */
1202struct amdgpu_cs_chunk {
1203 uint32_t chunk_id;
1204 uint32_t length_dw;
1205 uint32_t *kdata;
97b2e202
AD		 1206};
1207
1208struct amdgpu_cs_parser {
1209 struct amdgpu_device *adev;
1210 struct drm_file *filp;
3cb485f3 1211 struct amdgpu_ctx *ctx;
c3cca41e 1212
97b2e202
AD		 1213 /* chunks */
1214 unsigned nchunks;
1215 struct amdgpu_cs_chunk *chunks;
97b2e202 1216
50838c8c
CK		 1217 /* scheduler job object */
1218 struct amdgpu_job *job;
97b2e202 1219
c3cca41e
CK		 1220 /* buffer objects */
1221 struct ww_acquire_ctx ticket;
1222 struct amdgpu_bo_list *bo_list;
1223 struct amdgpu_bo_list_entry vm_pd;
1224 struct list_head validated;
1225 struct fence *fence;
1226 uint64_t bytes_moved_threshold;
1227 uint64_t bytes_moved;
97b2e202
AD		 1228
1229 /* user fence */
91acbeb6 1230 struct amdgpu_bo_list_entry uf_entry;
97b2e202
AD		 1231};
1232
bb977d37
CZ		 1233struct amdgpu_job {
1234 struct amd_sched_job base;
1235 struct amdgpu_device *adev;
b07c60c0 1236 struct amdgpu_ring *ring;
e86f9cee 1237 struct amdgpu_sync sync;
bb977d37
CZ		 1238 struct amdgpu_ib *ibs;
1239 uint32_t num_ibs;
e2840221 1240 void *owner;
bb977d37 1241 struct amdgpu_user_fence uf;
bb977d37 1242};
a6db8a33
JZ		 1243#define to_amdgpu_job(sched_job) \
1244 container_of((sched_job), struct amdgpu_job, base)
bb977d37 1245
7270f839
CK		 1246static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1247 uint32_t ib_idx, int idx)
97b2e202 1248{
50838c8c 1249 return p->job->ibs[ib_idx].ptr[idx];
97b2e202
AD		 1250}
1251
7270f839
CK		 1252static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1253 uint32_t ib_idx, int idx,
1254 uint32_t value)
1255{
50838c8c 1256 p->job->ibs[ib_idx].ptr[idx] = value;
7270f839
CK		 1257}
1258
97b2e202
AD		 1259/*
1260 * Writeback
1261 */
1262#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1263
1264struct amdgpu_wb {
1265 struct amdgpu_bo *wb_obj;
1266 volatile uint32_t *wb;
1267 uint64_t gpu_addr;
1268 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1269 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1270};
1271
1272int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1273void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1274
97b2e202 1275
97b2e202
AD		 1276
1277enum amdgpu_int_thermal_type {
1278 THERMAL_TYPE_NONE,
1279 THERMAL_TYPE_EXTERNAL,
1280 THERMAL_TYPE_EXTERNAL_GPIO,
1281 THERMAL_TYPE_RV6XX,
1282 THERMAL_TYPE_RV770,
1283 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1284 THERMAL_TYPE_EVERGREEN,
1285 THERMAL_TYPE_SUMO,
1286 THERMAL_TYPE_NI,
1287 THERMAL_TYPE_SI,
1288 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1289 THERMAL_TYPE_CI,
1290 THERMAL_TYPE_KV,
1291};
1292
1293enum amdgpu_dpm_auto_throttle_src {
1294 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1295 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1296};
1297
1298enum amdgpu_dpm_event_src {
1299 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1300 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1301 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1302 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1303 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1304};
1305
1306#define AMDGPU_MAX_VCE_LEVELS 6
1307
1308enum amdgpu_vce_level {
1309 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1310 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1311 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1312 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1313 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1314 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1315};
1316
1317struct amdgpu_ps {
1318 u32 caps; /* vbios flags */
1319 u32 class; /* vbios flags */
1320 u32 class2; /* vbios flags */
1321 /* UVD clocks */
1322 u32 vclk;
1323 u32 dclk;
1324 /* VCE clocks */
1325 u32 evclk;
1326 u32 ecclk;
1327 bool vce_active;
1328 enum amdgpu_vce_level vce_level;
1329 /* asic priv */
1330 void *ps_priv;
1331};
1332
1333struct amdgpu_dpm_thermal {
1334 /* thermal interrupt work */
1335 struct work_struct work;
1336 /* low temperature threshold */
1337 int min_temp;
1338 /* high temperature threshold */
1339 int max_temp;
1340 /* was last interrupt low to high or high to low */
1341 bool high_to_low;
1342 /* interrupt source */
1343 struct amdgpu_irq_src irq;
1344};
1345
1346enum amdgpu_clk_action
1347{
1348 AMDGPU_SCLK_UP = 1,
1349 AMDGPU_SCLK_DOWN
1350};
1351
1352struct amdgpu_blacklist_clocks
1353{
1354 u32 sclk;
1355 u32 mclk;
1356 enum amdgpu_clk_action action;
1357};
1358
1359struct amdgpu_clock_and_voltage_limits {
1360 u32 sclk;
1361 u32 mclk;
1362 u16 vddc;
1363 u16 vddci;
1364};
1365
1366struct amdgpu_clock_array {
1367 u32 count;
1368 u32 *values;
1369};
1370
1371struct amdgpu_clock_voltage_dependency_entry {
1372 u32 clk;
1373 u16 v;
1374};
1375
1376struct amdgpu_clock_voltage_dependency_table {
1377 u32 count;
1378 struct amdgpu_clock_voltage_dependency_entry *entries;
1379};
1380
1381union amdgpu_cac_leakage_entry {
1382 struct {
1383 u16 vddc;
1384 u32 leakage;
1385 };
1386 struct {
1387 u16 vddc1;
1388 u16 vddc2;
1389 u16 vddc3;
1390 };
1391};
1392
1393struct amdgpu_cac_leakage_table {
1394 u32 count;
1395 union amdgpu_cac_leakage_entry *entries;
1396};
1397
1398struct amdgpu_phase_shedding_limits_entry {
1399 u16 voltage;
1400 u32 sclk;
1401 u32 mclk;
1402};
1403
1404struct amdgpu_phase_shedding_limits_table {
1405 u32 count;
1406 struct amdgpu_phase_shedding_limits_entry *entries;
1407};
1408
1409struct amdgpu_uvd_clock_voltage_dependency_entry {
1410 u32 vclk;
1411 u32 dclk;
1412 u16 v;
1413};
1414
1415struct amdgpu_uvd_clock_voltage_dependency_table {
1416 u8 count;
1417 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1418};
1419
1420struct amdgpu_vce_clock_voltage_dependency_entry {
1421 u32 ecclk;
1422 u32 evclk;
1423 u16 v;
1424};
1425
1426struct amdgpu_vce_clock_voltage_dependency_table {
1427 u8 count;
1428 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1429};
1430
1431struct amdgpu_ppm_table {
1432 u8 ppm_design;
1433 u16 cpu_core_number;
1434 u32 platform_tdp;
1435 u32 small_ac_platform_tdp;
1436 u32 platform_tdc;
1437 u32 small_ac_platform_tdc;
1438 u32 apu_tdp;
1439 u32 dgpu_tdp;
1440 u32 dgpu_ulv_power;
1441 u32 tj_max;
1442};
1443
1444struct amdgpu_cac_tdp_table {
1445 u16 tdp;
1446 u16 configurable_tdp;
1447 u16 tdc;
1448 u16 battery_power_limit;
1449 u16 small_power_limit;
1450 u16 low_cac_leakage;
1451 u16 high_cac_leakage;
1452 u16 maximum_power_delivery_limit;
1453};
1454
1455struct amdgpu_dpm_dynamic_state {
1456 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1457 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1458 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1459 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1460 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1461 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1462 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1463 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1464 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1465 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1466 struct amdgpu_clock_array valid_sclk_values;
1467 struct amdgpu_clock_array valid_mclk_values;
1468 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1469 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1470 u32 mclk_sclk_ratio;
1471 u32 sclk_mclk_delta;
1472 u16 vddc_vddci_delta;
1473 u16 min_vddc_for_pcie_gen2;
1474 struct amdgpu_cac_leakage_table cac_leakage_table;
1475 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1476 struct amdgpu_ppm_table *ppm_table;
1477 struct amdgpu_cac_tdp_table *cac_tdp_table;
1478};
1479
1480struct amdgpu_dpm_fan {
1481 u16 t_min;
1482 u16 t_med;
1483 u16 t_high;
1484 u16 pwm_min;
1485 u16 pwm_med;
1486 u16 pwm_high;
1487 u8 t_hyst;
1488 u32 cycle_delay;
1489 u16 t_max;
1490 u8 control_mode;
1491 u16 default_max_fan_pwm;
1492 u16 default_fan_output_sensitivity;
1493 u16 fan_output_sensitivity;
1494 bool ucode_fan_control;
1495};
1496
1497enum amdgpu_pcie_gen {
1498 AMDGPU_PCIE_GEN1 = 0,
1499 AMDGPU_PCIE_GEN2 = 1,
1500 AMDGPU_PCIE_GEN3 = 2,
1501 AMDGPU_PCIE_GEN_INVALID = 0xffff
1502};
1503
1504enum amdgpu_dpm_forced_level {
1505 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1506 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1507 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1 1508 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
97b2e202
AD		 1509};
1510
1511struct amdgpu_vce_state {
1512 /* vce clocks */
1513 u32 evclk;
1514 u32 ecclk;
1515 /* gpu clocks */
1516 u32 sclk;
1517 u32 mclk;
1518 u8 clk_idx;
1519 u8 pstate;
1520};
1521
1522struct amdgpu_dpm_funcs {
1523 int (*get_temperature)(struct amdgpu_device *adev);
1524 int (*pre_set_power_state)(struct amdgpu_device *adev);
1525 int (*set_power_state)(struct amdgpu_device *adev);
1526 void (*post_set_power_state)(struct amdgpu_device *adev);
1527 void (*display_configuration_changed)(struct amdgpu_device *adev);
1528 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1529 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1530 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1531 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1532 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1533 bool (*vblank_too_short)(struct amdgpu_device *adev);
1534 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1535 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1536 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1537 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1538 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1539 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1540 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1541};
1542
1543struct amdgpu_dpm {
1544 struct amdgpu_ps *ps;
1545 /* number of valid power states */
1546 int num_ps;
1547 /* current power state that is active */
1548 struct amdgpu_ps *current_ps;
1549 /* requested power state */
1550 struct amdgpu_ps *requested_ps;
1551 /* boot up power state */
1552 struct amdgpu_ps *boot_ps;
1553 /* default uvd power state */
1554 struct amdgpu_ps *uvd_ps;
1555 /* vce requirements */
1556 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1557 enum amdgpu_vce_level vce_level;
3a2c788d
RZ		 1558 enum amd_pm_state_type state;
1559 enum amd_pm_state_type user_state;
97b2e202
AD		 1560 u32 platform_caps;
1561 u32 voltage_response_time;
1562 u32 backbias_response_time;
1563 void *priv;
1564 u32 new_active_crtcs;
1565 int new_active_crtc_count;
1566 u32 current_active_crtcs;
1567 int current_active_crtc_count;
1568 struct amdgpu_dpm_dynamic_state dyn_state;
1569 struct amdgpu_dpm_fan fan;
1570 u32 tdp_limit;
1571 u32 near_tdp_limit;
1572 u32 near_tdp_limit_adjusted;
1573 u32 sq_ramping_threshold;
1574 u32 cac_leakage;
1575 u16 tdp_od_limit;
1576 u32 tdp_adjustment;
1577 u16 load_line_slope;
1578 bool power_control;
1579 bool ac_power;
1580 /* special states active */
1581 bool thermal_active;
1582 bool uvd_active;
1583 bool vce_active;
1584 /* thermal handling */
1585 struct amdgpu_dpm_thermal thermal;
1586 /* forced levels */
1587 enum amdgpu_dpm_forced_level forced_level;
1588};
1589
1590struct amdgpu_pm {
1591 struct mutex mutex;
97b2e202
AD		 1592 u32 current_sclk;
1593 u32 current_mclk;
1594 u32 default_sclk;
1595 u32 default_mclk;
1596 struct amdgpu_i2c_chan *i2c_bus;
1597 /* internal thermal controller on rv6xx+ */
1598 enum amdgpu_int_thermal_type int_thermal_type;
1599 struct device *int_hwmon_dev;
1600 /* fan control parameters */
1601 bool no_fan;
1602 u8 fan_pulses_per_revolution;
1603 u8 fan_min_rpm;
1604 u8 fan_max_rpm;
1605 /* dpm */
1606 bool dpm_enabled;
c86f5ebf 1607 bool sysfs_initialized;
97b2e202
AD		 1608 struct amdgpu_dpm dpm;
1609 const struct firmware *fw; /* SMC firmware */
1610 uint32_t fw_version;
1611 const struct amdgpu_dpm_funcs *funcs;
d0dd7f0c
AD		 1612 uint32_t pcie_gen_mask;
1613 uint32_t pcie_mlw_mask;
7fb72a1f 1614 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
97b2e202
AD		 1615};
1616
d0dd7f0c
AD		 1617void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1618
97b2e202
AD		 1619/*
1620 * UVD
1621 */
1622#define AMDGPU_MAX_UVD_HANDLES 10
1623#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1624#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1625#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1626
1627struct amdgpu_uvd {
1628 struct amdgpu_bo *vcpu_bo;
1629 void *cpu_addr;
1630 uint64_t gpu_addr;
97b2e202
AD		 1631 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1632 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1633 struct delayed_work idle_work;
1634 const struct firmware *fw; /* UVD firmware */
1635 struct amdgpu_ring ring;
1636 struct amdgpu_irq_src irq;
1637 bool address_64_bit;
ead833ec 1638 struct amd_sched_entity entity;
97b2e202
AD		 1639};
1640
1641/*
1642 * VCE
1643 */
1644#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1645#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1646
6a585777
AD		 1647#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1648#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1649
97b2e202
AD		 1650struct amdgpu_vce {
1651 struct amdgpu_bo *vcpu_bo;
1652 uint64_t gpu_addr;
1653 unsigned fw_version;
1654 unsigned fb_version;
1655 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1656 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1657 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1658 struct delayed_work idle_work;
1659 const struct firmware *fw; /* VCE firmware */
1660 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1661 struct amdgpu_irq_src irq;
6a585777 1662 unsigned harvest_config;
c594989c 1663 struct amd_sched_entity entity;
97b2e202
AD		 1664};
1665
1666/*
1667 * SDMA
1668 */
c113ea1c 1669struct amdgpu_sdma_instance {
97b2e202
AD		 1670 /* SDMA firmware */
1671 const struct firmware *fw;
1672 uint32_t fw_version;
cfa2104f 1673 uint32_t feature_version;
97b2e202
AD		 1674
1675 struct amdgpu_ring ring;
18111de0 1676 bool burst_nop;
97b2e202
AD		 1677};
1678
c113ea1c
AD		 1679struct amdgpu_sdma {
1680 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1681 struct amdgpu_irq_src trap_irq;
1682 struct amdgpu_irq_src illegal_inst_irq;
1683 int num_instances;
1684};
1685
97b2e202
AD		 1686/*
1687 * Firmware
1688 */
1689struct amdgpu_firmware {
1690 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1691 bool smu_load;
1692 struct amdgpu_bo *fw_buf;
1693 unsigned int fw_size;
1694};
1695
1696/*
1697 * Benchmarking
1698 */
1699void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1700
1701
1702/*
1703 * Testing
1704 */
1705void amdgpu_test_moves(struct amdgpu_device *adev);
1706void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1707 struct amdgpu_ring *cpA,
1708 struct amdgpu_ring *cpB);
1709void amdgpu_test_syncing(struct amdgpu_device *adev);
1710
1711/*
1712 * MMU Notifier
1713 */
1714#if defined(CONFIG_MMU_NOTIFIER)
1715int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1716void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1717#else
1d1106b0 1718static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
97b2e202
AD		 1719{
1720 return -ENODEV;
1721}
1d1106b0 1722static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
97b2e202
AD		 1723#endif
1724
1725/*
1726 * Debugfs
1727 */
1728struct amdgpu_debugfs {
1729 struct drm_info_list *files;
1730 unsigned num_files;
1731};
1732
1733int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1734 struct drm_info_list *files,
1735 unsigned nfiles);
1736int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1737
1738#if defined(CONFIG_DEBUG_FS)
1739int amdgpu_debugfs_init(struct drm_minor *minor);
1740void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1741#endif
1742
1743/*
1744 * amdgpu smumgr functions
1745 */
1746struct amdgpu_smumgr_funcs {
1747 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1748 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1749 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1750};
1751
1752/*
1753 * amdgpu smumgr
1754 */
1755struct amdgpu_smumgr {
1756 struct amdgpu_bo *toc_buf;
1757 struct amdgpu_bo *smu_buf;
1758 /* asic priv smu data */
1759 void *priv;
1760 spinlock_t smu_lock;
1761 /* smumgr functions */
1762 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1763 /* ucode loading complete flag */
1764 uint32_t fw_flags;
1765};
1766
1767/*
1768 * ASIC specific register table accessible by UMD
1769 */
1770struct amdgpu_allowed_register_entry {
1771 uint32_t reg_offset;
1772 bool untouched;
1773 bool grbm_indexed;
1774};
1775
1776struct amdgpu_cu_info {
1777 uint32_t number; /* total active CU number */
1778 uint32_t ao_cu_mask;
1779 uint32_t bitmap[4][4];
1780};
1781
1782
1783/*
1784 * ASIC specific functions.
1785 */
1786struct amdgpu_asic_funcs {
1787 bool (*read_disabled_bios)(struct amdgpu_device *adev);
7946b878
AD		 1788 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1789 u8 *bios, u32 length_bytes);
97b2e202
AD		 1790 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1791 u32 sh_num, u32 reg_offset, u32 *value);
1792 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1793 int (*reset)(struct amdgpu_device *adev);
1794 /* wait for mc_idle */
1795 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1796 /* get the reference clock */
1797 u32 (*get_xclk)(struct amdgpu_device *adev);
1798 /* get the gpu clock counter */
1799 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1800 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1801 /* MM block clocks */
1802 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1803 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1804};
1805
1806/*
1807 * IOCTL.
1808 */
1809int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1810 struct drm_file *filp);
1811int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1812 struct drm_file *filp);
1813
1814int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1815 struct drm_file *filp);
1816int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1817 struct drm_file *filp);
1818int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1819 struct drm_file *filp);
1820int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1821 struct drm_file *filp);
1822int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1823 struct drm_file *filp);
1824int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1825 struct drm_file *filp);
1826int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1827int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1828
1829int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1830 struct drm_file *filp);
1831
1832/* VRAM scratch page for HDP bug, default vram page */
1833struct amdgpu_vram_scratch {
1834 struct amdgpu_bo *robj;
1835 volatile uint32_t *ptr;
1836 u64 gpu_addr;
1837};
1838
1839/*
1840 * ACPI
1841 */
1842struct amdgpu_atif_notification_cfg {
1843 bool enabled;
1844 int command_code;
1845};
1846
1847struct amdgpu_atif_notifications {
1848 bool display_switch;
1849 bool expansion_mode_change;
1850 bool thermal_state;
1851 bool forced_power_state;
1852 bool system_power_state;
1853 bool display_conf_change;
1854 bool px_gfx_switch;
1855 bool brightness_change;
1856 bool dgpu_display_event;
1857};
1858
1859struct amdgpu_atif_functions {
1860 bool system_params;
1861 bool sbios_requests;
1862 bool select_active_disp;
1863 bool lid_state;
1864 bool get_tv_standard;
1865 bool set_tv_standard;
1866 bool get_panel_expansion_mode;
1867 bool set_panel_expansion_mode;
1868 bool temperature_change;
1869 bool graphics_device_types;
1870};
1871
1872struct amdgpu_atif {
1873 struct amdgpu_atif_notifications notifications;
1874 struct amdgpu_atif_functions functions;
1875 struct amdgpu_atif_notification_cfg notification_cfg;
1876 struct amdgpu_encoder *encoder_for_bl;
1877};
1878
1879struct amdgpu_atcs_functions {
1880 bool get_ext_state;
1881 bool pcie_perf_req;
1882 bool pcie_dev_rdy;
1883 bool pcie_bus_width;
1884};
1885
1886struct amdgpu_atcs {
1887 struct amdgpu_atcs_functions functions;
1888};
1889
d03846af
CZ		 1890/*
1891 * CGS
1892 */
1893void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1894void amdgpu_cgs_destroy_device(void *cgs_device);
1895
1896
a8fe58ce
MB		 1897/*
1898 * CGS
1899 */
1900void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1901void amdgpu_cgs_destroy_device(void *cgs_device);
1902
1903
7e471e6f
AD		 1904/* GPU virtualization */
1905struct amdgpu_virtualization {
1906 bool supports_sr_iov;
1907};
1908
97b2e202
AD		 1909/*
1910 * Core structure, functions and helpers.
1911 */
1912typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1913typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1914
1915typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1916typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1917
8faf0e08
AD		 1918struct amdgpu_ip_block_status {
1919 bool valid;
1920 bool sw;
1921 bool hw;
1922};
1923
97b2e202
AD		 1924struct amdgpu_device {
1925 struct device *dev;
1926 struct drm_device *ddev;
1927 struct pci_dev *pdev;
97b2e202 1928
a8fe58ce
MB		 1929#ifdef CONFIG_DRM_AMD_ACP
1930 struct amdgpu_acp acp;
1931#endif
1932
97b2e202 1933 /* ASIC */
2f7d10b3 1934 enum amd_asic_type asic_type;
97b2e202
AD		 1935 uint32_t family;
1936 uint32_t rev_id;
1937 uint32_t external_rev_id;
1938 unsigned long flags;
1939 int usec_timeout;
1940 const struct amdgpu_asic_funcs *asic_funcs;
1941 bool shutdown;
1942 bool suspend;
1943 bool need_dma32;
1944 bool accel_working;
97b2e202
AD		 1945 struct work_struct reset_work;
1946 struct notifier_block acpi_nb;
1947 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1948 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1949 unsigned debugfs_count;
1950#if defined(CONFIG_DEBUG_FS)
1951 struct dentry *debugfs_regs;
1952#endif
1953 struct amdgpu_atif atif;
1954 struct amdgpu_atcs atcs;
1955 struct mutex srbm_mutex;
1956 /* GRBM index mutex. Protects concurrent access to GRBM index */
1957 struct mutex grbm_idx_mutex;
1958 struct dev_pm_domain vga_pm_domain;
1959 bool have_disp_power_ref;
1960
1961 /* BIOS */
1962 uint8_t *bios;
1963 bool is_atom_bios;
1964 uint16_t bios_header_start;
1965 struct amdgpu_bo *stollen_vga_memory;
1966 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1967
1968 /* Register/doorbell mmio */
1969 resource_size_t rmmio_base;
1970 resource_size_t rmmio_size;
1971 void __iomem *rmmio;
1972 /* protects concurrent MM_INDEX/DATA based register access */
1973 spinlock_t mmio_idx_lock;
1974 /* protects concurrent SMC based register access */
1975 spinlock_t smc_idx_lock;
1976 amdgpu_rreg_t smc_rreg;
1977 amdgpu_wreg_t smc_wreg;
1978 /* protects concurrent PCIE register access */
1979 spinlock_t pcie_idx_lock;
1980 amdgpu_rreg_t pcie_rreg;
1981 amdgpu_wreg_t pcie_wreg;
1982 /* protects concurrent UVD register access */
1983 spinlock_t uvd_ctx_idx_lock;
1984 amdgpu_rreg_t uvd_ctx_rreg;
1985 amdgpu_wreg_t uvd_ctx_wreg;
1986 /* protects concurrent DIDT register access */
1987 spinlock_t didt_idx_lock;
1988 amdgpu_rreg_t didt_rreg;
1989 amdgpu_wreg_t didt_wreg;
1990 /* protects concurrent ENDPOINT (audio) register access */
1991 spinlock_t audio_endpt_idx_lock;
1992 amdgpu_block_rreg_t audio_endpt_rreg;
1993 amdgpu_block_wreg_t audio_endpt_wreg;
1994 void __iomem *rio_mem;
1995 resource_size_t rio_mem_size;
1996 struct amdgpu_doorbell doorbell;
1997
1998 /* clock/pll info */
1999 struct amdgpu_clock clock;
2000
2001 /* MC */
2002 struct amdgpu_mc mc;
2003 struct amdgpu_gart gart;
2004 struct amdgpu_dummy_page dummy_page;
2005 struct amdgpu_vm_manager vm_manager;
2006
2007 /* memory management */
2008 struct amdgpu_mman mman;
97b2e202
AD		 2009 struct amdgpu_vram_scratch vram_scratch;
2010 struct amdgpu_wb wb;
2011 atomic64_t vram_usage;
2012 atomic64_t vram_vis_usage;
2013 atomic64_t gtt_usage;
2014 atomic64_t num_bytes_moved;
d94aed5a 2015 atomic_t gpu_reset_counter;
97b2e202
AD		 2016
2017 /* display */
2018 struct amdgpu_mode_info mode_info;
2019 struct work_struct hotplug_work;
2020 struct amdgpu_irq_src crtc_irq;
2021 struct amdgpu_irq_src pageflip_irq;
2022 struct amdgpu_irq_src hpd_irq;
2023
2024 /* rings */
97b2e202 2025 unsigned fence_context;
97b2e202
AD		 2026 unsigned num_rings;
2027 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2028 bool ib_pool_ready;
2029 struct amdgpu_sa_manager ring_tmp_bo;
2030
2031 /* interrupts */
2032 struct amdgpu_irq irq;
2033
1f7371b2
AD		 2034 /* powerplay */
2035 struct amd_powerplay powerplay;
e61710c5 2036 bool pp_enabled;
f3898ea1 2037 bool pp_force_state_enabled;
1f7371b2 2038
97b2e202
AD		 2039 /* dpm */
2040 struct amdgpu_pm pm;
2041 u32 cg_flags;
2042 u32 pg_flags;
2043
2044 /* amdgpu smumgr */
2045 struct amdgpu_smumgr smu;
2046
2047 /* gfx */
2048 struct amdgpu_gfx gfx;
2049
2050 /* sdma */
c113ea1c 2051 struct amdgpu_sdma sdma;
97b2e202
AD		 2052
2053 /* uvd */
2054 bool has_uvd;
2055 struct amdgpu_uvd uvd;
2056
2057 /* vce */
2058 struct amdgpu_vce vce;
2059
2060 /* firmwares */
2061 struct amdgpu_firmware firmware;
2062
2063 /* GDS */
2064 struct amdgpu_gds gds;
2065
2066 const struct amdgpu_ip_block_version *ip_blocks;
2067 int num_ip_blocks;
8faf0e08 2068 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2069 struct mutex mn_lock;
2070 DECLARE_HASHTABLE(mn_hash, 7);
2071
2072 /* tracking pinned memory */
2073 u64 vram_pin_size;
2074 u64 gart_pin_size;
130e0371
OG		 2075
2076 /* amdkfd interface */
2077 struct kfd_dev *kfd;
23ca0e4e 2078
7e471e6f 2079 struct amdgpu_virtualization virtualization;
97b2e202
AD		 2080};
2081
2082bool amdgpu_device_is_px(struct drm_device *dev);
2083int amdgpu_device_init(struct amdgpu_device *adev,
2084 struct drm_device *ddev,
2085 struct pci_dev *pdev,
2086 uint32_t flags);
2087void amdgpu_device_fini(struct amdgpu_device *adev);
2088int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2089
2090uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2091 bool always_indirect);
2092void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2093 bool always_indirect);
2094u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2095void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2096
2097u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2098void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2099
2100/*
2101 * Cast helper
2102 */
2103extern const struct fence_ops amdgpu_fence_ops;
2104static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2105{
2106 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2107
2108 if (__f->base.ops == &amdgpu_fence_ops)
2109 return __f;
2110
2111 return NULL;
2112}
2113
2114/*
2115 * Registers read & write functions.
2116 */
2117#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2118#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2119#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2120#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2121#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2122#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2123#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2124#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2125#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2126#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2127#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2128#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2129#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2130#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2131#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2132#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2133#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2134#define WREG32_P(reg, val, mask) \
2135 do { \
2136 uint32_t tmp_ = RREG32(reg); \
2137 tmp_ &= (mask); \
2138 tmp_ |= ((val) & ~(mask)); \
2139 WREG32(reg, tmp_); \
2140 } while (0)
2141#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2142#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2143#define WREG32_PLL_P(reg, val, mask) \
2144 do { \
2145 uint32_t tmp_ = RREG32_PLL(reg); \
2146 tmp_ &= (mask); \
2147 tmp_ |= ((val) & ~(mask)); \
2148 WREG32_PLL(reg, tmp_); \
2149 } while (0)
2150#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2151#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2152#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2153
2154#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2155#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2156
2157#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2158#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2159
2160#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2161 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2162 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2163
2164#define REG_GET_FIELD(value, reg, field) \
2165 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2166
2167/*
2168 * BIOS helpers.
2169 */
2170#define RBIOS8(i) (adev->bios[i])
2171#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2172#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2173
2174/*
2175 * RING helpers.
2176 */
2177static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2178{
2179 if (ring->count_dw <= 0)
86c2b790 2180 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2181 ring->ring[ring->wptr++] = v;
2182 ring->wptr &= ring->ptr_mask;
2183 ring->count_dw--;
97b2e202
AD		 2184}
2185
c113ea1c
AD		 2186static inline struct amdgpu_sdma_instance *
2187amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
4b2f7e2c
JZ		 2188{
2189 struct amdgpu_device *adev = ring->adev;
2190 int i;
2191
c113ea1c
AD		 2192 for (i = 0; i < adev->sdma.num_instances; i++)
2193 if (&adev->sdma.instance[i].ring == ring)
4b2f7e2c
JZ		 2194 break;
2195
2196 if (i < AMDGPU_MAX_SDMA_INSTANCES)
c113ea1c 2197 return &adev->sdma.instance[i];
4b2f7e2c
JZ		 2198 else
2199 return NULL;
2200}
2201
97b2e202
AD		 2202/*
2203 * ASICs macro.
2204 */
2205#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2206#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2207#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2208#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2209#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2210#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2211#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2212#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
7946b878 2213#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
97b2e202
AD		 2214#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2215#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2216#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2217#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2218#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
b07c9d2a 2219#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
97b2e202 2220#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
97b2e202
AD		 2221#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2222#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2223#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
97b2e202
AD		 2224#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2225#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2226#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2227#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2228#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2229#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202 2230#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2231#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
9e5d5309 2232#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
97b2e202
AD		 2233#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2234#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2235#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2236#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2237#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2238#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2239#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2240#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2241#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2242#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2243#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2244#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2245#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2246#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2247#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2248#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2249#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2250#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2251#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
c7ae72c0 2252#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
6e7a3840 2253#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
97b2e202
AD		 2254#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2255#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2256#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2257#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
97b2e202 2258#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
97b2e202 2259#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
97b2e202 2260#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
3af76f23
RZ		 2261
2262#define amdgpu_dpm_get_temperature(adev) \
4b5ece24 2263 ((adev)->pp_enabled ? \
e61710c5 2264 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
4b5ece24 2265 (adev)->pm.funcs->get_temperature((adev)))
3af76f23
RZ		 2266
2267#define amdgpu_dpm_set_fan_control_mode(adev, m) \
4b5ece24 2268 ((adev)->pp_enabled ? \
e61710c5 2269 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2270 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
3af76f23
RZ		 2271
2272#define amdgpu_dpm_get_fan_control_mode(adev) \
4b5ece24 2273 ((adev)->pp_enabled ? \
e61710c5 2274 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
4b5ece24 2275 (adev)->pm.funcs->get_fan_control_mode((adev)))
3af76f23
RZ		 2276
2277#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
4b5ece24 2278 ((adev)->pp_enabled ? \
e61710c5 2279 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2280 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
3af76f23
RZ		 2281
2282#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
4b5ece24 2283 ((adev)->pp_enabled ? \
e61710c5 2284 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
4b5ece24 2285 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
97b2e202 2286
1b5708ff 2287#define amdgpu_dpm_get_sclk(adev, l) \
4b5ece24 2288 ((adev)->pp_enabled ? \
e61710c5 2289 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2290 (adev)->pm.funcs->get_sclk((adev), (l)))
1b5708ff
RZ		 2291
2292#define amdgpu_dpm_get_mclk(adev, l) \
4b5ece24 2293 ((adev)->pp_enabled ? \
e61710c5 2294 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2295 (adev)->pm.funcs->get_mclk((adev), (l)))
1b5708ff
RZ		 2296
2297
2298#define amdgpu_dpm_force_performance_level(adev, l) \
4b5ece24 2299 ((adev)->pp_enabled ? \
e61710c5 2300 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
4b5ece24 2301 (adev)->pm.funcs->force_performance_level((adev), (l)))
1b5708ff
RZ		 2302
2303#define amdgpu_dpm_powergate_uvd(adev, g) \
4b5ece24 2304 ((adev)->pp_enabled ? \
e61710c5 2305 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2306 (adev)->pm.funcs->powergate_uvd((adev), (g)))
1b5708ff
RZ		 2307
2308#define amdgpu_dpm_powergate_vce(adev, g) \
4b5ece24 2309 ((adev)->pp_enabled ? \
e61710c5 2310 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
4b5ece24 2311 (adev)->pm.funcs->powergate_vce((adev), (g)))
1b5708ff
RZ		 2312
2313#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
4b5ece24 2314 ((adev)->pp_enabled ? \
e61710c5 2315 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
4b5ece24 2316 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
1b5708ff
RZ		 2317
2318#define amdgpu_dpm_get_current_power_state(adev) \
e61710c5 2319 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
1b5708ff
RZ		 2320
2321#define amdgpu_dpm_get_performance_level(adev) \
e61710c5 2322 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
1b5708ff 2323
f3898ea1
EH		 2324#define amdgpu_dpm_get_pp_num_states(adev, data) \
2325 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2326
2327#define amdgpu_dpm_get_pp_table(adev, table) \
2328 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2329
2330#define amdgpu_dpm_set_pp_table(adev, buf, size) \
2331 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2332
2333#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2334 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2335
2336#define amdgpu_dpm_force_clock_level(adev, type, level) \
2337 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2338
e61710c5 2339#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
1b5708ff 2340 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
97b2e202
AD		 2341
2342#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2343
2344/* Common functions */
2345int amdgpu_gpu_reset(struct amdgpu_device *adev);
2346void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2347bool amdgpu_card_posted(struct amdgpu_device *adev);
2348void amdgpu_update_display_priority(struct amdgpu_device *adev);
d5fc5e82 2349
97b2e202
AD		 2350int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2351int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2352 u32 ip_instance, u32 ring,
2353 struct amdgpu_ring **out_ring);
2354void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2355bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2356int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2357 uint32_t flags);
cc325d19 2358struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
d7006964
CK		 2359bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2360 unsigned long end);
97b2e202
AD		 2361bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2362uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2363 struct ttm_mem_reg *mem);
2364void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2365void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2366void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2367void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2368 const u32 *registers,
2369 const u32 array_size);
2370
2371bool amdgpu_device_is_px(struct drm_device *dev);
2372/* atpx handler */
2373#if defined(CONFIG_VGA_SWITCHEROO)
2374void amdgpu_register_atpx_handler(void);
2375void amdgpu_unregister_atpx_handler(void);
2376#else
2377static inline void amdgpu_register_atpx_handler(void) {}
2378static inline void amdgpu_unregister_atpx_handler(void) {}
2379#endif
2380
2381/*
2382 * KMS
2383 */
2384extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2385extern int amdgpu_max_kms_ioctl;
2386
2387int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2388int amdgpu_driver_unload_kms(struct drm_device *dev);
2389void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2390int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2391void amdgpu_driver_postclose_kms(struct drm_device *dev,
2392 struct drm_file *file_priv);
2393void amdgpu_driver_preclose_kms(struct drm_device *dev,
2394 struct drm_file *file_priv);
2395int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2396int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 2397u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2398int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2399void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2400int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
97b2e202
AD		 2401 int *max_error,
2402 struct timeval *vblank_time,
2403 unsigned flags);
2404long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2405 unsigned long arg);
2406
97b2e202
AD		 2407/*
2408 * functions used by amdgpu_encoder.c
2409 */
2410struct amdgpu_afmt_acr {
2411 u32 clock;
2412
2413 int n_32khz;
2414 int cts_32khz;
2415
2416 int n_44_1khz;
2417 int cts_44_1khz;
2418
2419 int n_48khz;
2420 int cts_48khz;
2421
2422};
2423
2424struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2425
2426/* amdgpu_acpi.c */
2427#if defined(CONFIG_ACPI)
2428int amdgpu_acpi_init(struct amdgpu_device *adev);
2429void amdgpu_acpi_fini(struct amdgpu_device *adev);
2430bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2431int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2432 u8 perf_req, bool advertise);
2433int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2434#else
2435static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2436static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2437#endif
2438
2439struct amdgpu_bo_va_mapping *
2440amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2441 uint64_t addr, struct amdgpu_bo **bo);
2442
2443#include "amdgpu_object.h"
2444
2445#endif
Linux kernel - Deliverables
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