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drm/amdgpu: use kernel fence diretly in amdgpu_bo_fence
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
CommitLineData
97b2e202
AD		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include <linux/atomic.h>
32#include <linux/wait.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/interval_tree.h>
36#include <linux/hashtable.h>
37#include <linux/fence.h>
38
39#include <ttm/ttm_bo_api.h>
40#include <ttm/ttm_bo_driver.h>
41#include <ttm/ttm_placement.h>
42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h>
44
d03846af 45#include <drm/drmP.h>
97b2e202 46#include <drm/drm_gem.h>
7e5a547f 47#include <drm/amdgpu_drm.h>
97b2e202 48
5fc3aeeb 49#include "amd_shared.h"
97b2e202
AD		 50#include "amdgpu_mode.h"
51#include "amdgpu_ih.h"
52#include "amdgpu_irq.h"
53#include "amdgpu_ucode.h"
54#include "amdgpu_gds.h"
55
b80d8475
AD		 56#include "gpu_scheduler.h"
57
97b2e202
AD		 58/*
59 * Modules parameters.
60 */
61extern int amdgpu_modeset;
62extern int amdgpu_vram_limit;
63extern int amdgpu_gart_size;
64extern int amdgpu_benchmarking;
65extern int amdgpu_testing;
66extern int amdgpu_audio;
67extern int amdgpu_disp_priority;
68extern int amdgpu_hw_i2c;
69extern int amdgpu_pcie_gen2;
70extern int amdgpu_msi;
71extern int amdgpu_lockup_timeout;
72extern int amdgpu_dpm;
73extern int amdgpu_smc_load_fw;
74extern int amdgpu_aspm;
75extern int amdgpu_runtime_pm;
76extern int amdgpu_hard_reset;
77extern unsigned amdgpu_ip_block_mask;
78extern int amdgpu_bapm;
79extern int amdgpu_deep_color;
80extern int amdgpu_vm_size;
81extern int amdgpu_vm_block_size;
b80d8475 82extern int amdgpu_enable_scheduler;
1333f723 83extern int amdgpu_sched_jobs;
4afcb303 84extern int amdgpu_sched_hw_submission;
97b2e202 85
4b559c90 86#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
97b2e202
AD		 87#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
88#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
89/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
90#define AMDGPU_IB_POOL_SIZE 16
91#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
92#define AMDGPUFB_CONN_LIMIT 4
93#define AMDGPU_BIOS_NUM_SCRATCH 8
94
97b2e202
AD		 95/* max number of rings */
96#define AMDGPU_MAX_RINGS 16
97#define AMDGPU_MAX_GFX_RINGS 1
98#define AMDGPU_MAX_COMPUTE_RINGS 8
99#define AMDGPU_MAX_VCE_RINGS 2
100
101/* number of hw syncs before falling back on blocking */
102#define AMDGPU_NUM_SYNCS 4
103
104/* hardcode that limit for now */
105#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
106
107/* hard reset data */
108#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
109
110/* reset flags */
111#define AMDGPU_RESET_GFX (1 << 0)
112#define AMDGPU_RESET_COMPUTE (1 << 1)
113#define AMDGPU_RESET_DMA (1 << 2)
114#define AMDGPU_RESET_CP (1 << 3)
115#define AMDGPU_RESET_GRBM (1 << 4)
116#define AMDGPU_RESET_DMA1 (1 << 5)
117#define AMDGPU_RESET_RLC (1 << 6)
118#define AMDGPU_RESET_SEM (1 << 7)
119#define AMDGPU_RESET_IH (1 << 8)
120#define AMDGPU_RESET_VMC (1 << 9)
121#define AMDGPU_RESET_MC (1 << 10)
122#define AMDGPU_RESET_DISPLAY (1 << 11)
123#define AMDGPU_RESET_UVD (1 << 12)
124#define AMDGPU_RESET_VCE (1 << 13)
125#define AMDGPU_RESET_VCE1 (1 << 14)
126
127/* CG block flags */
128#define AMDGPU_CG_BLOCK_GFX (1 << 0)
129#define AMDGPU_CG_BLOCK_MC (1 << 1)
130#define AMDGPU_CG_BLOCK_SDMA (1 << 2)
131#define AMDGPU_CG_BLOCK_UVD (1 << 3)
132#define AMDGPU_CG_BLOCK_VCE (1 << 4)
133#define AMDGPU_CG_BLOCK_HDP (1 << 5)
134#define AMDGPU_CG_BLOCK_BIF (1 << 6)
135
136/* CG flags */
137#define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
138#define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
139#define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
140#define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
141#define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
142#define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
143#define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
144#define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
145#define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
146#define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
147#define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
148#define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
149#define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
150#define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
151#define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
152#define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
153#define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
154
155/* PG flags */
156#define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
157#define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
158#define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
159#define AMDGPU_PG_SUPPORT_UVD (1 << 3)
160#define AMDGPU_PG_SUPPORT_VCE (1 << 4)
161#define AMDGPU_PG_SUPPORT_CP (1 << 5)
162#define AMDGPU_PG_SUPPORT_GDS (1 << 6)
163#define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
164#define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
165#define AMDGPU_PG_SUPPORT_ACP (1 << 9)
166#define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
167
168/* GFX current status */
169#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
170#define AMDGPU_GFX_SAFE_MODE 0x00000001L
171#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
172#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
173#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
174
175/* max cursor sizes (in pixels) */
176#define CIK_CURSOR_WIDTH 128
177#define CIK_CURSOR_HEIGHT 128
178
179struct amdgpu_device;
180struct amdgpu_fence;
181struct amdgpu_ib;
182struct amdgpu_vm;
183struct amdgpu_ring;
184struct amdgpu_semaphore;
185struct amdgpu_cs_parser;
186struct amdgpu_irq_src;
0b492a4c 187struct amdgpu_fpriv;
97b2e202
AD		 188
189enum amdgpu_cp_irq {
190 AMDGPU_CP_IRQ_GFX_EOP = 0,
191 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
199
200 AMDGPU_CP_IRQ_LAST
201};
202
203enum amdgpu_sdma_irq {
204 AMDGPU_SDMA_IRQ_TRAP0 = 0,
205 AMDGPU_SDMA_IRQ_TRAP1,
206
207 AMDGPU_SDMA_IRQ_LAST
208};
209
210enum amdgpu_thermal_irq {
211 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
212 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
213
214 AMDGPU_THERMAL_IRQ_LAST
215};
216
97b2e202 217int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
5fc3aeeb 218 enum amd_ip_block_type block_type,
219 enum amd_clockgating_state state);
97b2e202 220int amdgpu_set_powergating_state(struct amdgpu_device *adev,
5fc3aeeb 221 enum amd_ip_block_type block_type,
222 enum amd_powergating_state state);
97b2e202
AD		 223
224struct amdgpu_ip_block_version {
5fc3aeeb 225 enum amd_ip_block_type type;
97b2e202
AD		 226 u32 major;
227 u32 minor;
228 u32 rev;
5fc3aeeb 229 const struct amd_ip_funcs *funcs;
97b2e202
AD		 230};
231
232int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
5fc3aeeb 233 enum amd_ip_block_type type,
97b2e202
AD		 234 u32 major, u32 minor);
235
236const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
237 struct amdgpu_device *adev,
5fc3aeeb 238 enum amd_ip_block_type type);
97b2e202
AD		 239
240/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
241struct amdgpu_buffer_funcs {
242 /* maximum bytes in a single operation */
243 uint32_t copy_max_bytes;
244
245 /* number of dw to reserve per operation */
246 unsigned copy_num_dw;
247
248 /* used for buffer migration */
249 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
250 /* src addr in bytes */
251 uint64_t src_offset,
252 /* dst addr in bytes */
253 uint64_t dst_offset,
254 /* number of byte to transfer */
255 uint32_t byte_count);
256
257 /* maximum bytes in a single operation */
258 uint32_t fill_max_bytes;
259
260 /* number of dw to reserve per operation */
261 unsigned fill_num_dw;
262
263 /* used for buffer clearing */
264 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
265 /* value to write to memory */
266 uint32_t src_data,
267 /* dst addr in bytes */
268 uint64_t dst_offset,
269 /* number of byte to fill */
270 uint32_t byte_count);
271};
272
273/* provided by hw blocks that can write ptes, e.g., sdma */
274struct amdgpu_vm_pte_funcs {
275 /* copy pte entries from GART */
276 void (*copy_pte)(struct amdgpu_ib *ib,
277 uint64_t pe, uint64_t src,
278 unsigned count);
279 /* write pte one entry at a time with addr mapping */
280 void (*write_pte)(struct amdgpu_ib *ib,
281 uint64_t pe,
282 uint64_t addr, unsigned count,
283 uint32_t incr, uint32_t flags);
284 /* for linear pte/pde updates without addr mapping */
285 void (*set_pte_pde)(struct amdgpu_ib *ib,
286 uint64_t pe,
287 uint64_t addr, unsigned count,
288 uint32_t incr, uint32_t flags);
289 /* pad the indirect buffer to the necessary number of dw */
290 void (*pad_ib)(struct amdgpu_ib *ib);
291};
292
293/* provided by the gmc block */
294struct amdgpu_gart_funcs {
295 /* flush the vm tlb via mmio */
296 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
297 uint32_t vmid);
298 /* write pte/pde updates using the cpu */
299 int (*set_pte_pde)(struct amdgpu_device *adev,
300 void *cpu_pt_addr, /* cpu addr of page table */
301 uint32_t gpu_page_idx, /* pte/pde to update */
302 uint64_t addr, /* addr to write into pte/pde */
303 uint32_t flags); /* access flags */
304};
305
306/* provided by the ih block */
307struct amdgpu_ih_funcs {
308 /* ring read/write ptr handling, called from interrupt context */
309 u32 (*get_wptr)(struct amdgpu_device *adev);
310 void (*decode_iv)(struct amdgpu_device *adev,
311 struct amdgpu_iv_entry *entry);
312 void (*set_rptr)(struct amdgpu_device *adev);
313};
314
315/* provided by hw blocks that expose a ring buffer for commands */
316struct amdgpu_ring_funcs {
317 /* ring read/write ptr handling */
318 u32 (*get_rptr)(struct amdgpu_ring *ring);
319 u32 (*get_wptr)(struct amdgpu_ring *ring);
320 void (*set_wptr)(struct amdgpu_ring *ring);
321 /* validating and patching of IBs */
322 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
323 /* command emit functions */
324 void (*emit_ib)(struct amdgpu_ring *ring,
325 struct amdgpu_ib *ib);
326 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
890ee23f 327 uint64_t seq, unsigned flags);
97b2e202
AD		 328 bool (*emit_semaphore)(struct amdgpu_ring *ring,
329 struct amdgpu_semaphore *semaphore,
330 bool emit_wait);
331 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
332 uint64_t pd_addr);
d2edb07b 333 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
97b2e202
AD		 334 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
335 uint32_t gds_base, uint32_t gds_size,
336 uint32_t gws_base, uint32_t gws_size,
337 uint32_t oa_base, uint32_t oa_size);
338 /* testing functions */
339 int (*test_ring)(struct amdgpu_ring *ring);
340 int (*test_ib)(struct amdgpu_ring *ring);
341 bool (*is_lockup)(struct amdgpu_ring *ring);
342};
343
344/*
345 * BIOS.
346 */
347bool amdgpu_get_bios(struct amdgpu_device *adev);
348bool amdgpu_read_bios(struct amdgpu_device *adev);
349
350/*
351 * Dummy page
352 */
353struct amdgpu_dummy_page {
354 struct page *page;
355 dma_addr_t addr;
356};
357int amdgpu_dummy_page_init(struct amdgpu_device *adev);
358void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
359
360
361/*
362 * Clocks
363 */
364
365#define AMDGPU_MAX_PPLL 3
366
367struct amdgpu_clock {
368 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
369 struct amdgpu_pll spll;
370 struct amdgpu_pll mpll;
371 /* 10 Khz units */
372 uint32_t default_mclk;
373 uint32_t default_sclk;
374 uint32_t default_dispclk;
375 uint32_t current_dispclk;
376 uint32_t dp_extclk;
377 uint32_t max_pixel_clock;
378};
379
380/*
381 * Fences.
382 */
383struct amdgpu_fence_driver {
384 struct amdgpu_ring *ring;
385 uint64_t gpu_addr;
386 volatile uint32_t *cpu_addr;
387 /* sync_seq is protected by ring emission lock */
388 uint64_t sync_seq[AMDGPU_MAX_RINGS];
389 atomic64_t last_seq;
390 bool initialized;
97b2e202
AD		 391 struct amdgpu_irq_src *irq_src;
392 unsigned irq_type;
393 struct delayed_work lockup_work;
7f06c236 394 wait_queue_head_t fence_queue;
97b2e202
AD		 395};
396
397/* some special values for the owner field */
398#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
399#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
400#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
401
890ee23f
CZ		 402#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
403#define AMDGPU_FENCE_FLAG_INT (1 << 1)
404
97b2e202
AD		 405struct amdgpu_fence {
406 struct fence base;
407
408 /* RB, DMA, etc. */
409 struct amdgpu_ring *ring;
410 uint64_t seq;
411
412 /* filp or special value for fence creator */
413 void *owner;
414
415 wait_queue_t fence_wake;
416};
417
418struct amdgpu_user_fence {
419 /* write-back bo */
420 struct amdgpu_bo *bo;
421 /* write-back address offset to bo start */
422 uint32_t offset;
423};
424
425int amdgpu_fence_driver_init(struct amdgpu_device *adev);
426void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
427void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
428
429void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
430int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
431 struct amdgpu_irq_src *irq_src,
432 unsigned irq_type);
5ceb54c6
AD		 433void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
434void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
97b2e202
AD		 435int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
436 struct amdgpu_fence **fence);
437void amdgpu_fence_process(struct amdgpu_ring *ring);
438int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
439int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
440unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
441
442bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
443int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
332dfe90 444signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
97b2e202 445 struct amdgpu_fence **fences,
332dfe90 446 bool intr, long t);
97b2e202
AD		 447struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
448void amdgpu_fence_unref(struct amdgpu_fence **fence);
449
450bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
451 struct amdgpu_ring *ring);
452void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
453 struct amdgpu_ring *ring);
454
455static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
456 struct amdgpu_fence *b)
457{
458 if (!a) {
459 return b;
460 }
461
462 if (!b) {
463 return a;
464 }
465
466 BUG_ON(a->ring != b->ring);
467
468 if (a->seq > b->seq) {
469 return a;
470 } else {
471 return b;
472 }
473}
474
475static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
476 struct amdgpu_fence *b)
477{
478 if (!a) {
479 return false;
480 }
481
482 if (!b) {
483 return true;
484 }
485
486 BUG_ON(a->ring != b->ring);
487
488 return a->seq < b->seq;
489}
490
332dfe90 491int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
97b2e202
AD		 492 void *owner, struct amdgpu_fence **fence);
493
494/*
495 * TTM.
496 */
497struct amdgpu_mman {
498 struct ttm_bo_global_ref bo_global_ref;
499 struct drm_global_reference mem_global_ref;
500 struct ttm_bo_device bdev;
501 bool mem_global_referenced;
502 bool initialized;
503
504#if defined(CONFIG_DEBUG_FS)
505 struct dentry *vram;
506 struct dentry *gtt;
507#endif
508
509 /* buffer handling */
510 const struct amdgpu_buffer_funcs *buffer_funcs;
511 struct amdgpu_ring *buffer_funcs_ring;
512};
513
514int amdgpu_copy_buffer(struct amdgpu_ring *ring,
515 uint64_t src_offset,
516 uint64_t dst_offset,
517 uint32_t byte_count,
518 struct reservation_object *resv,
519 struct amdgpu_fence **fence);
520int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
521
522struct amdgpu_bo_list_entry {
523 struct amdgpu_bo *robj;
524 struct ttm_validate_buffer tv;
525 struct amdgpu_bo_va *bo_va;
526 unsigned prefered_domains;
527 unsigned allowed_domains;
528 uint32_t priority;
529};
530
531struct amdgpu_bo_va_mapping {
532 struct list_head list;
533 struct interval_tree_node it;
534 uint64_t offset;
535 uint32_t flags;
536};
537
538/* bo virtual addresses in a specific vm */
539struct amdgpu_bo_va {
540 /* protected by bo being reserved */
541 struct list_head bo_list;
97b2e202
AD		 542 struct amdgpu_fence *last_pt_update;
543 unsigned ref_count;
544
7fc11959 545 /* protected by vm mutex and spinlock */
97b2e202
AD		 546 struct list_head vm_status;
547
7fc11959
CK		 548 /* mappings for this bo_va */
549 struct list_head invalids;
550 struct list_head valids;
551
97b2e202
AD		 552 /* constant after initialization */
553 struct amdgpu_vm *vm;
554 struct amdgpu_bo *bo;
555};
556
7e5a547f
CZ		 557#define AMDGPU_GEM_DOMAIN_MAX 0x3
558
97b2e202
AD		 559struct amdgpu_bo {
560 /* Protected by gem.mutex */
561 struct list_head list;
562 /* Protected by tbo.reserved */
563 u32 initial_domain;
7e5a547f 564 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
97b2e202
AD		 565 struct ttm_placement placement;
566 struct ttm_buffer_object tbo;
567 struct ttm_bo_kmap_obj kmap;
568 u64 flags;
569 unsigned pin_count;
570 void *kptr;
571 u64 tiling_flags;
572 u64 metadata_flags;
573 void *metadata;
574 u32 metadata_size;
575 /* list of all virtual address to which this bo
576 * is associated to
577 */
578 struct list_head va;
579 /* Constant after initialization */
580 struct amdgpu_device *adev;
581 struct drm_gem_object gem_base;
582
583 struct ttm_bo_kmap_obj dma_buf_vmap;
584 pid_t pid;
585 struct amdgpu_mn *mn;
586 struct list_head mn_list;
587};
588#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
589
590void amdgpu_gem_object_free(struct drm_gem_object *obj);
591int amdgpu_gem_object_open(struct drm_gem_object *obj,
592 struct drm_file *file_priv);
593void amdgpu_gem_object_close(struct drm_gem_object *obj,
594 struct drm_file *file_priv);
595unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
596struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
597struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
598 struct dma_buf_attachment *attach,
599 struct sg_table *sg);
600struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
601 struct drm_gem_object *gobj,
602 int flags);
603int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
604void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
605struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
606void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
607void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
608int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
609
610/* sub-allocation manager, it has to be protected by another lock.
611 * By conception this is an helper for other part of the driver
612 * like the indirect buffer or semaphore, which both have their
613 * locking.
614 *
615 * Principe is simple, we keep a list of sub allocation in offset
616 * order (first entry has offset == 0, last entry has the highest
617 * offset).
618 *
619 * When allocating new object we first check if there is room at
620 * the end total_size - (last_object_offset + last_object_size) >=
621 * alloc_size. If so we allocate new object there.
622 *
623 * When there is not enough room at the end, we start waiting for
624 * each sub object until we reach object_offset+object_size >=
625 * alloc_size, this object then become the sub object we return.
626 *
627 * Alignment can't be bigger than page size.
628 *
629 * Hole are not considered for allocation to keep things simple.
630 * Assumption is that there won't be hole (all object on same
631 * alignment).
632 */
633struct amdgpu_sa_manager {
634 wait_queue_head_t wq;
635 struct amdgpu_bo *bo;
636 struct list_head *hole;
637 struct list_head flist[AMDGPU_MAX_RINGS];
638 struct list_head olist;
639 unsigned size;
640 uint64_t gpu_addr;
641 void *cpu_ptr;
642 uint32_t domain;
643 uint32_t align;
644};
645
646struct amdgpu_sa_bo;
647
648/* sub-allocation buffer */
649struct amdgpu_sa_bo {
650 struct list_head olist;
651 struct list_head flist;
652 struct amdgpu_sa_manager *manager;
653 unsigned soffset;
654 unsigned eoffset;
655 struct amdgpu_fence *fence;
656};
657
658/*
659 * GEM objects.
660 */
661struct amdgpu_gem {
662 struct mutex mutex;
663 struct list_head objects;
664};
665
666int amdgpu_gem_init(struct amdgpu_device *adev);
667void amdgpu_gem_fini(struct amdgpu_device *adev);
668int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
669 int alignment, u32 initial_domain,
670 u64 flags, bool kernel,
671 struct drm_gem_object **obj);
672
673int amdgpu_mode_dumb_create(struct drm_file *file_priv,
674 struct drm_device *dev,
675 struct drm_mode_create_dumb *args);
676int amdgpu_mode_dumb_mmap(struct drm_file *filp,
677 struct drm_device *dev,
678 uint32_t handle, uint64_t *offset_p);
679
680/*
681 * Semaphores.
682 */
683struct amdgpu_semaphore {
684 struct amdgpu_sa_bo *sa_bo;
685 signed waiters;
686 uint64_t gpu_addr;
687};
688
689int amdgpu_semaphore_create(struct amdgpu_device *adev,
690 struct amdgpu_semaphore **semaphore);
691bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
692 struct amdgpu_semaphore *semaphore);
693bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
694 struct amdgpu_semaphore *semaphore);
695void amdgpu_semaphore_free(struct amdgpu_device *adev,
696 struct amdgpu_semaphore **semaphore,
697 struct amdgpu_fence *fence);
698
699/*
700 * Synchronization
701 */
702struct amdgpu_sync {
703 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
704 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
705 struct amdgpu_fence *last_vm_update;
706};
707
708void amdgpu_sync_create(struct amdgpu_sync *sync);
91e1a520
CK		 709int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
710 struct fence *f);
97b2e202
AD		 711int amdgpu_sync_resv(struct amdgpu_device *adev,
712 struct amdgpu_sync *sync,
713 struct reservation_object *resv,
714 void *owner);
715int amdgpu_sync_rings(struct amdgpu_sync *sync,
716 struct amdgpu_ring *ring);
717void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
718 struct amdgpu_fence *fence);
719
720/*
721 * GART structures, functions & helpers
722 */
723struct amdgpu_mc;
724
725#define AMDGPU_GPU_PAGE_SIZE 4096
726#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
727#define AMDGPU_GPU_PAGE_SHIFT 12
728#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
729
730struct amdgpu_gart {
731 dma_addr_t table_addr;
732 struct amdgpu_bo *robj;
733 void *ptr;
734 unsigned num_gpu_pages;
735 unsigned num_cpu_pages;
736 unsigned table_size;
737 struct page **pages;
738 dma_addr_t *pages_addr;
739 bool ready;
740 const struct amdgpu_gart_funcs *gart_funcs;
741};
742
743int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
744void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
745int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
746void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
747int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
748void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
749int amdgpu_gart_init(struct amdgpu_device *adev);
750void amdgpu_gart_fini(struct amdgpu_device *adev);
751void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
752 int pages);
753int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
754 int pages, struct page **pagelist,
755 dma_addr_t *dma_addr, uint32_t flags);
756
757/*
758 * GPU MC structures, functions & helpers
759 */
760struct amdgpu_mc {
761 resource_size_t aper_size;
762 resource_size_t aper_base;
763 resource_size_t agp_base;
764 /* for some chips with <= 32MB we need to lie
765 * about vram size near mc fb location */
766 u64 mc_vram_size;
767 u64 visible_vram_size;
768 u64 gtt_size;
769 u64 gtt_start;
770 u64 gtt_end;
771 u64 vram_start;
772 u64 vram_end;
773 unsigned vram_width;
774 u64 real_vram_size;
775 int vram_mtrr;
776 u64 gtt_base_align;
777 u64 mc_mask;
778 const struct firmware *fw; /* MC firmware */
779 uint32_t fw_version;
780 struct amdgpu_irq_src vm_fault;
81c59f54 781 uint32_t vram_type;
97b2e202
AD		 782};
783
784/*
785 * GPU doorbell structures, functions & helpers
786 */
787typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
788{
789 AMDGPU_DOORBELL_KIQ = 0x000,
790 AMDGPU_DOORBELL_HIQ = 0x001,
791 AMDGPU_DOORBELL_DIQ = 0x002,
792 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
793 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
794 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
795 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
796 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
797 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
798 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
799 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
800 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
801 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
802 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
803 AMDGPU_DOORBELL_IH = 0x1E8,
804 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
805 AMDGPU_DOORBELL_INVALID = 0xFFFF
806} AMDGPU_DOORBELL_ASSIGNMENT;
807
808struct amdgpu_doorbell {
809 /* doorbell mmio */
810 resource_size_t base;
811 resource_size_t size;
812 u32 __iomem *ptr;
813 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
814};
815
816void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
817 phys_addr_t *aperture_base,
818 size_t *aperture_size,
819 size_t *start_offset);
820
821/*
822 * IRQS.
823 */
824
825struct amdgpu_flip_work {
826 struct work_struct flip_work;
827 struct work_struct unpin_work;
828 struct amdgpu_device *adev;
829 int crtc_id;
830 uint64_t base;
831 struct drm_pending_vblank_event *event;
832 struct amdgpu_bo *old_rbo;
833 struct fence *fence;
834};
835
836
837/*
838 * CP & rings.
839 */
840
841struct amdgpu_ib {
842 struct amdgpu_sa_bo *sa_bo;
843 uint32_t length_dw;
844 uint64_t gpu_addr;
845 uint32_t *ptr;
846 struct amdgpu_ring *ring;
847 struct amdgpu_fence *fence;
848 struct amdgpu_user_fence *user;
849 struct amdgpu_vm *vm;
3cb485f3 850 struct amdgpu_ctx *ctx;
97b2e202 851 struct amdgpu_sync sync;
97b2e202
AD		 852 uint32_t gds_base, gds_size;
853 uint32_t gws_base, gws_size;
854 uint32_t oa_base, oa_size;
de807f81 855 uint32_t flags;
5430a3ff
CK		 856 /* resulting sequence number */
857 uint64_t sequence;
97b2e202
AD		 858};
859
860enum amdgpu_ring_type {
861 AMDGPU_RING_TYPE_GFX,
862 AMDGPU_RING_TYPE_COMPUTE,
863 AMDGPU_RING_TYPE_SDMA,
864 AMDGPU_RING_TYPE_UVD,
865 AMDGPU_RING_TYPE_VCE
866};
867
c1b69ed0
CZ		 868extern struct amd_sched_backend_ops amdgpu_sched_ops;
869
3c704e93
CZ		 870int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev,
871 struct amdgpu_ring *ring,
872 struct amdgpu_ib *ibs,
873 unsigned num_ibs,
874 int (*free_job)(struct amdgpu_cs_parser *),
875 void *owner);
876
97b2e202
AD		 877struct amdgpu_ring {
878 struct amdgpu_device *adev;
879 const struct amdgpu_ring_funcs *funcs;
880 struct amdgpu_fence_driver fence_drv;
b80d8475 881 struct amd_gpu_scheduler *scheduler;
97b2e202 882
176e1ab1 883 spinlock_t fence_lock;
97b2e202
AD		 884 struct mutex *ring_lock;
885 struct amdgpu_bo *ring_obj;
886 volatile uint32_t *ring;
887 unsigned rptr_offs;
888 u64 next_rptr_gpu_addr;
889 volatile u32 *next_rptr_cpu_addr;
890 unsigned wptr;
891 unsigned wptr_old;
892 unsigned ring_size;
893 unsigned ring_free_dw;
894 int count_dw;
895 atomic_t last_rptr;
896 atomic64_t last_activity;
897 uint64_t gpu_addr;
898 uint32_t align_mask;
899 uint32_t ptr_mask;
900 bool ready;
901 u32 nop;
902 u32 idx;
903 u64 last_semaphore_signal_addr;
904 u64 last_semaphore_wait_addr;
905 u32 me;
906 u32 pipe;
907 u32 queue;
908 struct amdgpu_bo *mqd_obj;
909 u32 doorbell_index;
910 bool use_doorbell;
911 unsigned wptr_offs;
912 unsigned next_rptr_offs;
913 unsigned fence_offs;
3cb485f3 914 struct amdgpu_ctx *current_ctx;
97b2e202
AD		 915 enum amdgpu_ring_type type;
916 char name[16];
4274f5d4 917 bool is_pte_ring;
97b2e202
AD		 918};
919
920/*
921 * VM
922 */
923
924/* maximum number of VMIDs */
925#define AMDGPU_NUM_VM 16
926
927/* number of entries in page table */
928#define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
929
930/* PTBs (Page Table Blocks) need to be aligned to 32K */
931#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
932#define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
933#define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
934
935#define AMDGPU_PTE_VALID (1 << 0)
936#define AMDGPU_PTE_SYSTEM (1 << 1)
937#define AMDGPU_PTE_SNOOPED (1 << 2)
938
939/* VI only */
940#define AMDGPU_PTE_EXECUTABLE (1 << 4)
941
942#define AMDGPU_PTE_READABLE (1 << 5)
943#define AMDGPU_PTE_WRITEABLE (1 << 6)
944
945/* PTE (Page Table Entry) fragment field for different page sizes */
946#define AMDGPU_PTE_FRAG_4KB (0 << 7)
947#define AMDGPU_PTE_FRAG_64KB (4 << 7)
948#define AMDGPU_LOG2_PAGES_PER_FRAG 4
949
950struct amdgpu_vm_pt {
951 struct amdgpu_bo *bo;
952 uint64_t addr;
953};
954
955struct amdgpu_vm_id {
956 unsigned id;
957 uint64_t pd_gpu_addr;
958 /* last flushed PD/PT update */
959 struct amdgpu_fence *flushed_updates;
960 /* last use of vmid */
961 struct amdgpu_fence *last_id_use;
962};
963
964struct amdgpu_vm {
965 struct mutex mutex;
966
967 struct rb_root va;
968
7fc11959 969 /* protecting invalidated */
97b2e202
AD		 970 spinlock_t status_lock;
971
972 /* BOs moved, but not yet updated in the PT */
973 struct list_head invalidated;
974
7fc11959
CK		 975 /* BOs cleared in the PT because of a move */
976 struct list_head cleared;
977
978 /* BO mappings freed, but not yet updated in the PT */
97b2e202
AD		 979 struct list_head freed;
980
981 /* contains the page directory */
982 struct amdgpu_bo *page_directory;
983 unsigned max_pde_used;
984
985 /* array of page tables, one for each page directory entry */
986 struct amdgpu_vm_pt *page_tables;
987
988 /* for id and flush management per ring */
989 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
990};
991
992struct amdgpu_vm_manager {
993 struct amdgpu_fence *active[AMDGPU_NUM_VM];
994 uint32_t max_pfn;
995 /* number of VMIDs */
996 unsigned nvm;
997 /* vram base address for page table entry */
998 u64 vram_base_offset;
999 /* is vm enabled? */
1000 bool enabled;
1001 /* for hw to save the PD addr on suspend/resume */
1002 uint32_t saved_table_addr[AMDGPU_NUM_VM];
1003 /* vm pte handling */
1004 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
1005 struct amdgpu_ring *vm_pte_funcs_ring;
1006};
1007
1008/*
1009 * context related structures
1010 */
1011
21c16bf6
CK		 1012#define AMDGPU_CTX_MAX_CS_PENDING 16
1013
1014struct amdgpu_ctx_ring {
1015 uint64_t sequence;
1016 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
9cb7e5a9 1017 struct amd_context_entity c_entity;
21c16bf6
CK		 1018};
1019
97b2e202 1020struct amdgpu_ctx {
0b492a4c 1021 struct kref refcount;
9cb7e5a9 1022 struct amdgpu_device *adev;
0b492a4c 1023 unsigned reset_counter;
21c16bf6
CK		 1024 spinlock_t ring_lock;
1025 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
97b2e202
AD		 1026};
1027
1028struct amdgpu_ctx_mgr {
0b492a4c
AD		 1029 struct amdgpu_device *adev;
1030 struct mutex lock;
1031 /* protected by lock */
1032 struct idr ctx_handles;
97b2e202
AD		 1033};
1034
0b492a4c
AD		 1035int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1036 uint32_t *id);
1037int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1038 uint32_t id);
1039
1040void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
1041
1042struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1043int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1044
21c16bf6 1045uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
d1ff9086 1046 struct fence *fence, uint64_t queued_seq);
21c16bf6
CK		 1047struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1048 struct amdgpu_ring *ring, uint64_t seq);
1049
0b492a4c
AD		 1050int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1051 struct drm_file *filp);
1052
1053
97b2e202
AD		 1054/*
1055 * file private structure
1056 */
1057
1058struct amdgpu_fpriv {
1059 struct amdgpu_vm vm;
1060 struct mutex bo_list_lock;
1061 struct idr bo_list_handles;
0b492a4c 1062 struct amdgpu_ctx_mgr ctx_mgr;
97b2e202
AD		 1063};
1064
1065/*
1066 * residency list
1067 */
1068
1069struct amdgpu_bo_list {
1070 struct mutex lock;
1071 struct amdgpu_bo *gds_obj;
1072 struct amdgpu_bo *gws_obj;
1073 struct amdgpu_bo *oa_obj;
1074 bool has_userptr;
1075 unsigned num_entries;
1076 struct amdgpu_bo_list_entry *array;
1077};
1078
1079struct amdgpu_bo_list *
1080amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1081void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
372bc1e1
CZ		 1082void amdgpu_bo_list_copy(struct amdgpu_device *adev,
1083 struct amdgpu_bo_list *dst,
1084 struct amdgpu_bo_list *src);
97b2e202
AD		 1085void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1086
1087/*
1088 * GFX stuff
1089 */
1090#include "clearstate_defs.h"
1091
1092struct amdgpu_rlc {
1093 /* for power gating */
1094 struct amdgpu_bo *save_restore_obj;
1095 uint64_t save_restore_gpu_addr;
1096 volatile uint32_t *sr_ptr;
1097 const u32 *reg_list;
1098 u32 reg_list_size;
1099 /* for clear state */
1100 struct amdgpu_bo *clear_state_obj;
1101 uint64_t clear_state_gpu_addr;
1102 volatile uint32_t *cs_ptr;
1103 const struct cs_section_def *cs_data;
1104 u32 clear_state_size;
1105 /* for cp tables */
1106 struct amdgpu_bo *cp_table_obj;
1107 uint64_t cp_table_gpu_addr;
1108 volatile uint32_t *cp_table_ptr;
1109 u32 cp_table_size;
1110};
1111
1112struct amdgpu_mec {
1113 struct amdgpu_bo *hpd_eop_obj;
1114 u64 hpd_eop_gpu_addr;
1115 u32 num_pipe;
1116 u32 num_mec;
1117 u32 num_queue;
1118};
1119
1120/*
1121 * GPU scratch registers structures, functions & helpers
1122 */
1123struct amdgpu_scratch {
1124 unsigned num_reg;
1125 uint32_t reg_base;
1126 bool free[32];
1127 uint32_t reg[32];
1128};
1129
1130/*
1131 * GFX configurations
1132 */
1133struct amdgpu_gca_config {
1134 unsigned max_shader_engines;
1135 unsigned max_tile_pipes;
1136 unsigned max_cu_per_sh;
1137 unsigned max_sh_per_se;
1138 unsigned max_backends_per_se;
1139 unsigned max_texture_channel_caches;
1140 unsigned max_gprs;
1141 unsigned max_gs_threads;
1142 unsigned max_hw_contexts;
1143 unsigned sc_prim_fifo_size_frontend;
1144 unsigned sc_prim_fifo_size_backend;
1145 unsigned sc_hiz_tile_fifo_size;
1146 unsigned sc_earlyz_tile_fifo_size;
1147
1148 unsigned num_tile_pipes;
1149 unsigned backend_enable_mask;
1150 unsigned mem_max_burst_length_bytes;
1151 unsigned mem_row_size_in_kb;
1152 unsigned shader_engine_tile_size;
1153 unsigned num_gpus;
1154 unsigned multi_gpu_tile_size;
1155 unsigned mc_arb_ramcfg;
1156 unsigned gb_addr_config;
1157
1158 uint32_t tile_mode_array[32];
1159 uint32_t macrotile_mode_array[16];
1160};
1161
1162struct amdgpu_gfx {
1163 struct mutex gpu_clock_mutex;
1164 struct amdgpu_gca_config config;
1165 struct amdgpu_rlc rlc;
1166 struct amdgpu_mec mec;
1167 struct amdgpu_scratch scratch;
1168 const struct firmware *me_fw; /* ME firmware */
1169 uint32_t me_fw_version;
1170 const struct firmware *pfp_fw; /* PFP firmware */
1171 uint32_t pfp_fw_version;
1172 const struct firmware *ce_fw; /* CE firmware */
1173 uint32_t ce_fw_version;
1174 const struct firmware *rlc_fw; /* RLC firmware */
1175 uint32_t rlc_fw_version;
1176 const struct firmware *mec_fw; /* MEC firmware */
1177 uint32_t mec_fw_version;
1178 const struct firmware *mec2_fw; /* MEC2 firmware */
1179 uint32_t mec2_fw_version;
02558a00
KW		 1180 uint32_t me_feature_version;
1181 uint32_t ce_feature_version;
1182 uint32_t pfp_feature_version;
351643d7
JZ		 1183 uint32_t rlc_feature_version;
1184 uint32_t mec_feature_version;
1185 uint32_t mec2_feature_version;
97b2e202
AD		 1186 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1187 unsigned num_gfx_rings;
1188 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1189 unsigned num_compute_rings;
1190 struct amdgpu_irq_src eop_irq;
1191 struct amdgpu_irq_src priv_reg_irq;
1192 struct amdgpu_irq_src priv_inst_irq;
1193 /* gfx status */
1194 uint32_t gfx_current_status;
1195 /* sync signal for const engine */
1196 unsigned ce_sync_offs;
a101a899
KW		 1197 /* ce ram size*/
1198 unsigned ce_ram_size;
97b2e202
AD		 1199};
1200
1201int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1202 unsigned size, struct amdgpu_ib *ib);
1203void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1204int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1205 struct amdgpu_ib *ib, void *owner);
1206int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1207void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1208int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1209/* Ring access between begin & end cannot sleep */
1210void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1211int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1212int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1213void amdgpu_ring_commit(struct amdgpu_ring *ring);
1214void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1215void amdgpu_ring_undo(struct amdgpu_ring *ring);
1216void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1217void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1218bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1219unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1220 uint32_t **data);
1221int amdgpu_ring_restore(struct amdgpu_ring *ring,
1222 unsigned size, uint32_t *data);
1223int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1224 unsigned ring_size, u32 nop, u32 align_mask,
1225 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1226 enum amdgpu_ring_type ring_type);
1227void amdgpu_ring_fini(struct amdgpu_ring *ring);
1228
1229/*
1230 * CS.
1231 */
1232struct amdgpu_cs_chunk {
1233 uint32_t chunk_id;
1234 uint32_t length_dw;
1235 uint32_t *kdata;
1236 void __user *user_ptr;
1237};
1238
d5fc5e82
CZ		 1239union amdgpu_sched_job_param {
1240 struct {
1241 struct amdgpu_vm *vm;
1242 uint64_t start;
1243 uint64_t last;
1244 struct amdgpu_fence **fence;
1245
1246 } vm_mapping;
1247 struct {
1248 struct amdgpu_bo *bo;
1249 } vm;
1250};
1251
97b2e202
AD		 1252struct amdgpu_cs_parser {
1253 struct amdgpu_device *adev;
1254 struct drm_file *filp;
3cb485f3 1255 struct amdgpu_ctx *ctx;
97b2e202
AD		 1256 struct amdgpu_bo_list *bo_list;
1257 /* chunks */
1258 unsigned nchunks;
1259 struct amdgpu_cs_chunk *chunks;
1260 /* relocations */
1261 struct amdgpu_bo_list_entry *vm_bos;
97b2e202
AD		 1262 struct list_head validated;
1263
1264 struct amdgpu_ib *ibs;
1265 uint32_t num_ibs;
1266
1267 struct ww_acquire_ctx ticket;
1268
1269 /* user fence */
1270 struct amdgpu_user_fence uf;
c1b69ed0 1271
4b559c90 1272 struct amdgpu_ring *ring;
c1b69ed0
CZ		 1273 struct mutex job_lock;
1274 struct work_struct job_work;
1275 int (*prepare_job)(struct amdgpu_cs_parser *sched_job);
d5fc5e82 1276 union amdgpu_sched_job_param job_param;
c1b69ed0 1277 int (*run_job)(struct amdgpu_cs_parser *sched_job);
049fc527 1278 int (*free_job)(struct amdgpu_cs_parser *sched_job);
97b2e202
AD		 1279};
1280
1281static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1282{
1283 return p->ibs[ib_idx].ptr[idx];
1284}
1285
1286/*
1287 * Writeback
1288 */
1289#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1290
1291struct amdgpu_wb {
1292 struct amdgpu_bo *wb_obj;
1293 volatile uint32_t *wb;
1294 uint64_t gpu_addr;
1295 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1296 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1297};
1298
1299int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1300void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1301
1302/**
1303 * struct amdgpu_pm - power management datas
1304 * It keeps track of various data needed to take powermanagement decision.
1305 */
1306
1307enum amdgpu_pm_state_type {
1308 /* not used for dpm */
1309 POWER_STATE_TYPE_DEFAULT,
1310 POWER_STATE_TYPE_POWERSAVE,
1311 /* user selectable states */
1312 POWER_STATE_TYPE_BATTERY,
1313 POWER_STATE_TYPE_BALANCED,
1314 POWER_STATE_TYPE_PERFORMANCE,
1315 /* internal states */
1316 POWER_STATE_TYPE_INTERNAL_UVD,
1317 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1318 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1319 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1320 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1321 POWER_STATE_TYPE_INTERNAL_BOOT,
1322 POWER_STATE_TYPE_INTERNAL_THERMAL,
1323 POWER_STATE_TYPE_INTERNAL_ACPI,
1324 POWER_STATE_TYPE_INTERNAL_ULV,
1325 POWER_STATE_TYPE_INTERNAL_3DPERF,
1326};
1327
1328enum amdgpu_int_thermal_type {
1329 THERMAL_TYPE_NONE,
1330 THERMAL_TYPE_EXTERNAL,
1331 THERMAL_TYPE_EXTERNAL_GPIO,
1332 THERMAL_TYPE_RV6XX,
1333 THERMAL_TYPE_RV770,
1334 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1335 THERMAL_TYPE_EVERGREEN,
1336 THERMAL_TYPE_SUMO,
1337 THERMAL_TYPE_NI,
1338 THERMAL_TYPE_SI,
1339 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1340 THERMAL_TYPE_CI,
1341 THERMAL_TYPE_KV,
1342};
1343
1344enum amdgpu_dpm_auto_throttle_src {
1345 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1346 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1347};
1348
1349enum amdgpu_dpm_event_src {
1350 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1351 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1352 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1353 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1354 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1355};
1356
1357#define AMDGPU_MAX_VCE_LEVELS 6
1358
1359enum amdgpu_vce_level {
1360 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1361 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1362 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1363 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1364 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1365 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1366};
1367
1368struct amdgpu_ps {
1369 u32 caps; /* vbios flags */
1370 u32 class; /* vbios flags */
1371 u32 class2; /* vbios flags */
1372 /* UVD clocks */
1373 u32 vclk;
1374 u32 dclk;
1375 /* VCE clocks */
1376 u32 evclk;
1377 u32 ecclk;
1378 bool vce_active;
1379 enum amdgpu_vce_level vce_level;
1380 /* asic priv */
1381 void *ps_priv;
1382};
1383
1384struct amdgpu_dpm_thermal {
1385 /* thermal interrupt work */
1386 struct work_struct work;
1387 /* low temperature threshold */
1388 int min_temp;
1389 /* high temperature threshold */
1390 int max_temp;
1391 /* was last interrupt low to high or high to low */
1392 bool high_to_low;
1393 /* interrupt source */
1394 struct amdgpu_irq_src irq;
1395};
1396
1397enum amdgpu_clk_action
1398{
1399 AMDGPU_SCLK_UP = 1,
1400 AMDGPU_SCLK_DOWN
1401};
1402
1403struct amdgpu_blacklist_clocks
1404{
1405 u32 sclk;
1406 u32 mclk;
1407 enum amdgpu_clk_action action;
1408};
1409
1410struct amdgpu_clock_and_voltage_limits {
1411 u32 sclk;
1412 u32 mclk;
1413 u16 vddc;
1414 u16 vddci;
1415};
1416
1417struct amdgpu_clock_array {
1418 u32 count;
1419 u32 *values;
1420};
1421
1422struct amdgpu_clock_voltage_dependency_entry {
1423 u32 clk;
1424 u16 v;
1425};
1426
1427struct amdgpu_clock_voltage_dependency_table {
1428 u32 count;
1429 struct amdgpu_clock_voltage_dependency_entry *entries;
1430};
1431
1432union amdgpu_cac_leakage_entry {
1433 struct {
1434 u16 vddc;
1435 u32 leakage;
1436 };
1437 struct {
1438 u16 vddc1;
1439 u16 vddc2;
1440 u16 vddc3;
1441 };
1442};
1443
1444struct amdgpu_cac_leakage_table {
1445 u32 count;
1446 union amdgpu_cac_leakage_entry *entries;
1447};
1448
1449struct amdgpu_phase_shedding_limits_entry {
1450 u16 voltage;
1451 u32 sclk;
1452 u32 mclk;
1453};
1454
1455struct amdgpu_phase_shedding_limits_table {
1456 u32 count;
1457 struct amdgpu_phase_shedding_limits_entry *entries;
1458};
1459
1460struct amdgpu_uvd_clock_voltage_dependency_entry {
1461 u32 vclk;
1462 u32 dclk;
1463 u16 v;
1464};
1465
1466struct amdgpu_uvd_clock_voltage_dependency_table {
1467 u8 count;
1468 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1469};
1470
1471struct amdgpu_vce_clock_voltage_dependency_entry {
1472 u32 ecclk;
1473 u32 evclk;
1474 u16 v;
1475};
1476
1477struct amdgpu_vce_clock_voltage_dependency_table {
1478 u8 count;
1479 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1480};
1481
1482struct amdgpu_ppm_table {
1483 u8 ppm_design;
1484 u16 cpu_core_number;
1485 u32 platform_tdp;
1486 u32 small_ac_platform_tdp;
1487 u32 platform_tdc;
1488 u32 small_ac_platform_tdc;
1489 u32 apu_tdp;
1490 u32 dgpu_tdp;
1491 u32 dgpu_ulv_power;
1492 u32 tj_max;
1493};
1494
1495struct amdgpu_cac_tdp_table {
1496 u16 tdp;
1497 u16 configurable_tdp;
1498 u16 tdc;
1499 u16 battery_power_limit;
1500 u16 small_power_limit;
1501 u16 low_cac_leakage;
1502 u16 high_cac_leakage;
1503 u16 maximum_power_delivery_limit;
1504};
1505
1506struct amdgpu_dpm_dynamic_state {
1507 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1508 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1509 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1510 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1511 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1512 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1513 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1514 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1515 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1516 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1517 struct amdgpu_clock_array valid_sclk_values;
1518 struct amdgpu_clock_array valid_mclk_values;
1519 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1520 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1521 u32 mclk_sclk_ratio;
1522 u32 sclk_mclk_delta;
1523 u16 vddc_vddci_delta;
1524 u16 min_vddc_for_pcie_gen2;
1525 struct amdgpu_cac_leakage_table cac_leakage_table;
1526 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1527 struct amdgpu_ppm_table *ppm_table;
1528 struct amdgpu_cac_tdp_table *cac_tdp_table;
1529};
1530
1531struct amdgpu_dpm_fan {
1532 u16 t_min;
1533 u16 t_med;
1534 u16 t_high;
1535 u16 pwm_min;
1536 u16 pwm_med;
1537 u16 pwm_high;
1538 u8 t_hyst;
1539 u32 cycle_delay;
1540 u16 t_max;
1541 u8 control_mode;
1542 u16 default_max_fan_pwm;
1543 u16 default_fan_output_sensitivity;
1544 u16 fan_output_sensitivity;
1545 bool ucode_fan_control;
1546};
1547
1548enum amdgpu_pcie_gen {
1549 AMDGPU_PCIE_GEN1 = 0,
1550 AMDGPU_PCIE_GEN2 = 1,
1551 AMDGPU_PCIE_GEN3 = 2,
1552 AMDGPU_PCIE_GEN_INVALID = 0xffff
1553};
1554
1555enum amdgpu_dpm_forced_level {
1556 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1557 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1558 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1559};
1560
1561struct amdgpu_vce_state {
1562 /* vce clocks */
1563 u32 evclk;
1564 u32 ecclk;
1565 /* gpu clocks */
1566 u32 sclk;
1567 u32 mclk;
1568 u8 clk_idx;
1569 u8 pstate;
1570};
1571
1572struct amdgpu_dpm_funcs {
1573 int (*get_temperature)(struct amdgpu_device *adev);
1574 int (*pre_set_power_state)(struct amdgpu_device *adev);
1575 int (*set_power_state)(struct amdgpu_device *adev);
1576 void (*post_set_power_state)(struct amdgpu_device *adev);
1577 void (*display_configuration_changed)(struct amdgpu_device *adev);
1578 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1579 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1580 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1581 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1582 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1583 bool (*vblank_too_short)(struct amdgpu_device *adev);
1584 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
b7a07769 1585 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
97b2e202
AD		 1586 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1587 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1588 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1589 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1590 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1591};
1592
1593struct amdgpu_dpm {
1594 struct amdgpu_ps *ps;
1595 /* number of valid power states */
1596 int num_ps;
1597 /* current power state that is active */
1598 struct amdgpu_ps *current_ps;
1599 /* requested power state */
1600 struct amdgpu_ps *requested_ps;
1601 /* boot up power state */
1602 struct amdgpu_ps *boot_ps;
1603 /* default uvd power state */
1604 struct amdgpu_ps *uvd_ps;
1605 /* vce requirements */
1606 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1607 enum amdgpu_vce_level vce_level;
1608 enum amdgpu_pm_state_type state;
1609 enum amdgpu_pm_state_type user_state;
1610 u32 platform_caps;
1611 u32 voltage_response_time;
1612 u32 backbias_response_time;
1613 void *priv;
1614 u32 new_active_crtcs;
1615 int new_active_crtc_count;
1616 u32 current_active_crtcs;
1617 int current_active_crtc_count;
1618 struct amdgpu_dpm_dynamic_state dyn_state;
1619 struct amdgpu_dpm_fan fan;
1620 u32 tdp_limit;
1621 u32 near_tdp_limit;
1622 u32 near_tdp_limit_adjusted;
1623 u32 sq_ramping_threshold;
1624 u32 cac_leakage;
1625 u16 tdp_od_limit;
1626 u32 tdp_adjustment;
1627 u16 load_line_slope;
1628 bool power_control;
1629 bool ac_power;
1630 /* special states active */
1631 bool thermal_active;
1632 bool uvd_active;
1633 bool vce_active;
1634 /* thermal handling */
1635 struct amdgpu_dpm_thermal thermal;
1636 /* forced levels */
1637 enum amdgpu_dpm_forced_level forced_level;
1638};
1639
1640struct amdgpu_pm {
1641 struct mutex mutex;
97b2e202
AD		 1642 u32 current_sclk;
1643 u32 current_mclk;
1644 u32 default_sclk;
1645 u32 default_mclk;
1646 struct amdgpu_i2c_chan *i2c_bus;
1647 /* internal thermal controller on rv6xx+ */
1648 enum amdgpu_int_thermal_type int_thermal_type;
1649 struct device *int_hwmon_dev;
1650 /* fan control parameters */
1651 bool no_fan;
1652 u8 fan_pulses_per_revolution;
1653 u8 fan_min_rpm;
1654 u8 fan_max_rpm;
1655 /* dpm */
1656 bool dpm_enabled;
1657 struct amdgpu_dpm dpm;
1658 const struct firmware *fw; /* SMC firmware */
1659 uint32_t fw_version;
1660 const struct amdgpu_dpm_funcs *funcs;
1661};
1662
1663/*
1664 * UVD
1665 */
1666#define AMDGPU_MAX_UVD_HANDLES 10
1667#define AMDGPU_UVD_STACK_SIZE (1024*1024)
1668#define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1669#define AMDGPU_UVD_FIRMWARE_OFFSET 256
1670
1671struct amdgpu_uvd {
1672 struct amdgpu_bo *vcpu_bo;
1673 void *cpu_addr;
1674 uint64_t gpu_addr;
1675 void *saved_bo;
1676 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1677 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1678 struct delayed_work idle_work;
1679 const struct firmware *fw; /* UVD firmware */
1680 struct amdgpu_ring ring;
1681 struct amdgpu_irq_src irq;
1682 bool address_64_bit;
1683};
1684
1685/*
1686 * VCE
1687 */
1688#define AMDGPU_MAX_VCE_HANDLES 16
97b2e202
AD		 1689#define AMDGPU_VCE_FIRMWARE_OFFSET 256
1690
6a585777
AD		 1691#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1692#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1693
97b2e202
AD		 1694struct amdgpu_vce {
1695 struct amdgpu_bo *vcpu_bo;
1696 uint64_t gpu_addr;
1697 unsigned fw_version;
1698 unsigned fb_version;
1699 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1700 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
f1689ec1 1701 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
97b2e202
AD		 1702 struct delayed_work idle_work;
1703 const struct firmware *fw; /* VCE firmware */
1704 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1705 struct amdgpu_irq_src irq;
6a585777 1706 unsigned harvest_config;
97b2e202
AD		 1707};
1708
1709/*
1710 * SDMA
1711 */
1712struct amdgpu_sdma {
1713 /* SDMA firmware */
1714 const struct firmware *fw;
1715 uint32_t fw_version;
cfa2104f 1716 uint32_t feature_version;
97b2e202
AD		 1717
1718 struct amdgpu_ring ring;
1719};
1720
1721/*
1722 * Firmware
1723 */
1724struct amdgpu_firmware {
1725 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1726 bool smu_load;
1727 struct amdgpu_bo *fw_buf;
1728 unsigned int fw_size;
1729};
1730
1731/*
1732 * Benchmarking
1733 */
1734void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1735
1736
1737/*
1738 * Testing
1739 */
1740void amdgpu_test_moves(struct amdgpu_device *adev);
1741void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1742 struct amdgpu_ring *cpA,
1743 struct amdgpu_ring *cpB);
1744void amdgpu_test_syncing(struct amdgpu_device *adev);
1745
1746/*
1747 * MMU Notifier
1748 */
1749#if defined(CONFIG_MMU_NOTIFIER)
1750int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1751void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1752#else
1753static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1754{
1755 return -ENODEV;
1756}
1757static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1758#endif
1759
1760/*
1761 * Debugfs
1762 */
1763struct amdgpu_debugfs {
1764 struct drm_info_list *files;
1765 unsigned num_files;
1766};
1767
1768int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1769 struct drm_info_list *files,
1770 unsigned nfiles);
1771int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1772
1773#if defined(CONFIG_DEBUG_FS)
1774int amdgpu_debugfs_init(struct drm_minor *minor);
1775void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1776#endif
1777
1778/*
1779 * amdgpu smumgr functions
1780 */
1781struct amdgpu_smumgr_funcs {
1782 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1783 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1784 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1785};
1786
1787/*
1788 * amdgpu smumgr
1789 */
1790struct amdgpu_smumgr {
1791 struct amdgpu_bo *toc_buf;
1792 struct amdgpu_bo *smu_buf;
1793 /* asic priv smu data */
1794 void *priv;
1795 spinlock_t smu_lock;
1796 /* smumgr functions */
1797 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1798 /* ucode loading complete flag */
1799 uint32_t fw_flags;
1800};
1801
1802/*
1803 * ASIC specific register table accessible by UMD
1804 */
1805struct amdgpu_allowed_register_entry {
1806 uint32_t reg_offset;
1807 bool untouched;
1808 bool grbm_indexed;
1809};
1810
1811struct amdgpu_cu_info {
1812 uint32_t number; /* total active CU number */
1813 uint32_t ao_cu_mask;
1814 uint32_t bitmap[4][4];
1815};
1816
1817
1818/*
1819 * ASIC specific functions.
1820 */
1821struct amdgpu_asic_funcs {
1822 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1823 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1824 u32 sh_num, u32 reg_offset, u32 *value);
1825 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1826 int (*reset)(struct amdgpu_device *adev);
1827 /* wait for mc_idle */
1828 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1829 /* get the reference clock */
1830 u32 (*get_xclk)(struct amdgpu_device *adev);
1831 /* get the gpu clock counter */
1832 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1833 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1834 /* MM block clocks */
1835 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1836 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1837};
1838
1839/*
1840 * IOCTL.
1841 */
1842int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *filp);
1844int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1845 struct drm_file *filp);
1846
1847int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1848 struct drm_file *filp);
1849int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1851int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1852 struct drm_file *filp);
1853int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1854 struct drm_file *filp);
1855int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1856 struct drm_file *filp);
1857int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1858 struct drm_file *filp);
1859int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1860int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1861
1862int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864
1865/* VRAM scratch page for HDP bug, default vram page */
1866struct amdgpu_vram_scratch {
1867 struct amdgpu_bo *robj;
1868 volatile uint32_t *ptr;
1869 u64 gpu_addr;
1870};
1871
1872/*
1873 * ACPI
1874 */
1875struct amdgpu_atif_notification_cfg {
1876 bool enabled;
1877 int command_code;
1878};
1879
1880struct amdgpu_atif_notifications {
1881 bool display_switch;
1882 bool expansion_mode_change;
1883 bool thermal_state;
1884 bool forced_power_state;
1885 bool system_power_state;
1886 bool display_conf_change;
1887 bool px_gfx_switch;
1888 bool brightness_change;
1889 bool dgpu_display_event;
1890};
1891
1892struct amdgpu_atif_functions {
1893 bool system_params;
1894 bool sbios_requests;
1895 bool select_active_disp;
1896 bool lid_state;
1897 bool get_tv_standard;
1898 bool set_tv_standard;
1899 bool get_panel_expansion_mode;
1900 bool set_panel_expansion_mode;
1901 bool temperature_change;
1902 bool graphics_device_types;
1903};
1904
1905struct amdgpu_atif {
1906 struct amdgpu_atif_notifications notifications;
1907 struct amdgpu_atif_functions functions;
1908 struct amdgpu_atif_notification_cfg notification_cfg;
1909 struct amdgpu_encoder *encoder_for_bl;
1910};
1911
1912struct amdgpu_atcs_functions {
1913 bool get_ext_state;
1914 bool pcie_perf_req;
1915 bool pcie_dev_rdy;
1916 bool pcie_bus_width;
1917};
1918
1919struct amdgpu_atcs {
1920 struct amdgpu_atcs_functions functions;
1921};
1922
d03846af
CZ		 1923/*
1924 * CGS
1925 */
1926void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1927void amdgpu_cgs_destroy_device(void *cgs_device);
1928
1929
97b2e202
AD		 1930/*
1931 * Core structure, functions and helpers.
1932 */
1933typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1934typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1935
1936typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1937typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1938
8faf0e08
AD		 1939struct amdgpu_ip_block_status {
1940 bool valid;
1941 bool sw;
1942 bool hw;
1943};
1944
97b2e202
AD		 1945struct amdgpu_device {
1946 struct device *dev;
1947 struct drm_device *ddev;
1948 struct pci_dev *pdev;
1949 struct rw_semaphore exclusive_lock;
1950
1951 /* ASIC */
2f7d10b3 1952 enum amd_asic_type asic_type;
97b2e202
AD		 1953 uint32_t family;
1954 uint32_t rev_id;
1955 uint32_t external_rev_id;
1956 unsigned long flags;
1957 int usec_timeout;
1958 const struct amdgpu_asic_funcs *asic_funcs;
1959 bool shutdown;
1960 bool suspend;
1961 bool need_dma32;
1962 bool accel_working;
1963 bool needs_reset;
1964 struct work_struct reset_work;
1965 struct notifier_block acpi_nb;
1966 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1967 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1968 unsigned debugfs_count;
1969#if defined(CONFIG_DEBUG_FS)
1970 struct dentry *debugfs_regs;
1971#endif
1972 struct amdgpu_atif atif;
1973 struct amdgpu_atcs atcs;
1974 struct mutex srbm_mutex;
1975 /* GRBM index mutex. Protects concurrent access to GRBM index */
1976 struct mutex grbm_idx_mutex;
1977 struct dev_pm_domain vga_pm_domain;
1978 bool have_disp_power_ref;
1979
1980 /* BIOS */
1981 uint8_t *bios;
1982 bool is_atom_bios;
1983 uint16_t bios_header_start;
1984 struct amdgpu_bo *stollen_vga_memory;
1985 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1986
1987 /* Register/doorbell mmio */
1988 resource_size_t rmmio_base;
1989 resource_size_t rmmio_size;
1990 void __iomem *rmmio;
1991 /* protects concurrent MM_INDEX/DATA based register access */
1992 spinlock_t mmio_idx_lock;
1993 /* protects concurrent SMC based register access */
1994 spinlock_t smc_idx_lock;
1995 amdgpu_rreg_t smc_rreg;
1996 amdgpu_wreg_t smc_wreg;
1997 /* protects concurrent PCIE register access */
1998 spinlock_t pcie_idx_lock;
1999 amdgpu_rreg_t pcie_rreg;
2000 amdgpu_wreg_t pcie_wreg;
2001 /* protects concurrent UVD register access */
2002 spinlock_t uvd_ctx_idx_lock;
2003 amdgpu_rreg_t uvd_ctx_rreg;
2004 amdgpu_wreg_t uvd_ctx_wreg;
2005 /* protects concurrent DIDT register access */
2006 spinlock_t didt_idx_lock;
2007 amdgpu_rreg_t didt_rreg;
2008 amdgpu_wreg_t didt_wreg;
2009 /* protects concurrent ENDPOINT (audio) register access */
2010 spinlock_t audio_endpt_idx_lock;
2011 amdgpu_block_rreg_t audio_endpt_rreg;
2012 amdgpu_block_wreg_t audio_endpt_wreg;
2013 void __iomem *rio_mem;
2014 resource_size_t rio_mem_size;
2015 struct amdgpu_doorbell doorbell;
2016
2017 /* clock/pll info */
2018 struct amdgpu_clock clock;
2019
2020 /* MC */
2021 struct amdgpu_mc mc;
2022 struct amdgpu_gart gart;
2023 struct amdgpu_dummy_page dummy_page;
2024 struct amdgpu_vm_manager vm_manager;
2025
2026 /* memory management */
2027 struct amdgpu_mman mman;
2028 struct amdgpu_gem gem;
2029 struct amdgpu_vram_scratch vram_scratch;
2030 struct amdgpu_wb wb;
2031 atomic64_t vram_usage;
2032 atomic64_t vram_vis_usage;
2033 atomic64_t gtt_usage;
2034 atomic64_t num_bytes_moved;
d94aed5a 2035 atomic_t gpu_reset_counter;
97b2e202
AD		 2036
2037 /* display */
2038 struct amdgpu_mode_info mode_info;
2039 struct work_struct hotplug_work;
2040 struct amdgpu_irq_src crtc_irq;
2041 struct amdgpu_irq_src pageflip_irq;
2042 struct amdgpu_irq_src hpd_irq;
2043
2044 /* rings */
97b2e202
AD		 2045 unsigned fence_context;
2046 struct mutex ring_lock;
2047 unsigned num_rings;
2048 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2049 bool ib_pool_ready;
2050 struct amdgpu_sa_manager ring_tmp_bo;
2051
2052 /* interrupts */
2053 struct amdgpu_irq irq;
2054
2055 /* dpm */
2056 struct amdgpu_pm pm;
2057 u32 cg_flags;
2058 u32 pg_flags;
2059
2060 /* amdgpu smumgr */
2061 struct amdgpu_smumgr smu;
2062
2063 /* gfx */
2064 struct amdgpu_gfx gfx;
2065
2066 /* sdma */
2067 struct amdgpu_sdma sdma[2];
2068 struct amdgpu_irq_src sdma_trap_irq;
2069 struct amdgpu_irq_src sdma_illegal_inst_irq;
2070
2071 /* uvd */
2072 bool has_uvd;
2073 struct amdgpu_uvd uvd;
2074
2075 /* vce */
2076 struct amdgpu_vce vce;
2077
2078 /* firmwares */
2079 struct amdgpu_firmware firmware;
2080
2081 /* GDS */
2082 struct amdgpu_gds gds;
2083
2084 const struct amdgpu_ip_block_version *ip_blocks;
2085 int num_ip_blocks;
8faf0e08 2086 struct amdgpu_ip_block_status *ip_block_status;
97b2e202
AD		 2087 struct mutex mn_lock;
2088 DECLARE_HASHTABLE(mn_hash, 7);
2089
2090 /* tracking pinned memory */
2091 u64 vram_pin_size;
2092 u64 gart_pin_size;
130e0371
OG		 2093
2094 /* amdkfd interface */
2095 struct kfd_dev *kfd;
23ca0e4e
CZ		 2096
2097 /* kernel conext for IB submission */
2098 struct amdgpu_ctx *kernel_ctx;
97b2e202
AD		 2099};
2100
2101bool amdgpu_device_is_px(struct drm_device *dev);
2102int amdgpu_device_init(struct amdgpu_device *adev,
2103 struct drm_device *ddev,
2104 struct pci_dev *pdev,
2105 uint32_t flags);
2106void amdgpu_device_fini(struct amdgpu_device *adev);
2107int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2108
2109uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2110 bool always_indirect);
2111void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2112 bool always_indirect);
2113u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2114void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2115
2116u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2117void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2118
2119/*
2120 * Cast helper
2121 */
2122extern const struct fence_ops amdgpu_fence_ops;
2123static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2124{
2125 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2126
2127 if (__f->base.ops == &amdgpu_fence_ops)
2128 return __f;
2129
2130 return NULL;
2131}
2132
2133/*
2134 * Registers read & write functions.
2135 */
2136#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2137#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2138#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2139#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2140#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2141#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2142#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2143#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2144#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2145#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2146#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2147#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2148#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2149#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2150#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2151#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2152#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2153#define WREG32_P(reg, val, mask) \
2154 do { \
2155 uint32_t tmp_ = RREG32(reg); \
2156 tmp_ &= (mask); \
2157 tmp_ |= ((val) & ~(mask)); \
2158 WREG32(reg, tmp_); \
2159 } while (0)
2160#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2161#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2162#define WREG32_PLL_P(reg, val, mask) \
2163 do { \
2164 uint32_t tmp_ = RREG32_PLL(reg); \
2165 tmp_ &= (mask); \
2166 tmp_ |= ((val) & ~(mask)); \
2167 WREG32_PLL(reg, tmp_); \
2168 } while (0)
2169#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2170#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2171#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2172
2173#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2174#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2175
2176#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2177#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2178
2179#define REG_SET_FIELD(orig_val, reg, field, field_val) \
2180 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2181 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2182
2183#define REG_GET_FIELD(value, reg, field) \
2184 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2185
2186/*
2187 * BIOS helpers.
2188 */
2189#define RBIOS8(i) (adev->bios[i])
2190#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2191#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2192
2193/*
2194 * RING helpers.
2195 */
2196static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2197{
2198 if (ring->count_dw <= 0)
86c2b790 2199 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
97b2e202
AD		 2200 ring->ring[ring->wptr++] = v;
2201 ring->wptr &= ring->ptr_mask;
2202 ring->count_dw--;
2203 ring->ring_free_dw--;
2204}
2205
2206/*
2207 * ASICs macro.
2208 */
2209#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2210#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2211#define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2212#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2213#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2214#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2215#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2216#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2217#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2218#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2219#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2220#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2221#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2222#define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2223#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2224#define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2225#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2226#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2227#define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2228#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2229#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2230#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2231#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2232#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2233#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
890ee23f 2234#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
97b2e202
AD		 2235#define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2236#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
d2edb07b 2237#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
97b2e202
AD		 2238#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2239#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2240#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2241#define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2242#define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2243#define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2244#define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2245#define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2246#define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2247#define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2248#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2249#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2250#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2251#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2252#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2253#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2254#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2255#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2256#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2257#define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2258#define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2259#define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2260#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2261#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2262#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2263#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2264#define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2265#define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2266#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2267#define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2268#define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2269#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2270#define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
b7a07769 2271#define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
97b2e202
AD		 2272#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2273#define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2274#define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2275#define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2276#define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2277
2278#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2279
2280/* Common functions */
2281int amdgpu_gpu_reset(struct amdgpu_device *adev);
2282void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2283bool amdgpu_card_posted(struct amdgpu_device *adev);
2284void amdgpu_update_display_priority(struct amdgpu_device *adev);
2285bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
d5fc5e82
CZ		 2286struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
2287 struct drm_file *filp,
2288 struct amdgpu_ctx *ctx,
2289 struct amdgpu_ib *ibs,
2290 uint32_t num_ibs);
2291
97b2e202
AD		 2292int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2293int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2294 u32 ip_instance, u32 ring,
2295 struct amdgpu_ring **out_ring);
2296void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2297bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2298int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2299 uint32_t flags);
2300bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2301bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2302uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2303 struct ttm_mem_reg *mem);
2304void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2305void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2306void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2307void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2308 const u32 *registers,
2309 const u32 array_size);
2310
2311bool amdgpu_device_is_px(struct drm_device *dev);
2312/* atpx handler */
2313#if defined(CONFIG_VGA_SWITCHEROO)
2314void amdgpu_register_atpx_handler(void);
2315void amdgpu_unregister_atpx_handler(void);
2316#else
2317static inline void amdgpu_register_atpx_handler(void) {}
2318static inline void amdgpu_unregister_atpx_handler(void) {}
2319#endif
2320
2321/*
2322 * KMS
2323 */
2324extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2325extern int amdgpu_max_kms_ioctl;
2326
2327int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2328int amdgpu_driver_unload_kms(struct drm_device *dev);
2329void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2330int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2331void amdgpu_driver_postclose_kms(struct drm_device *dev,
2332 struct drm_file *file_priv);
2333void amdgpu_driver_preclose_kms(struct drm_device *dev,
2334 struct drm_file *file_priv);
2335int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2336int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2337u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2338int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2339void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2340int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2341 int *max_error,
2342 struct timeval *vblank_time,
2343 unsigned flags);
2344long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2345 unsigned long arg);
2346
2347/*
2348 * vm
2349 */
2350int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2351void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2352struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2353 struct amdgpu_vm *vm,
2354 struct list_head *head);
7f8a5290
CK		 2355int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2356 struct amdgpu_sync *sync);
97b2e202
AD		 2357void amdgpu_vm_flush(struct amdgpu_ring *ring,
2358 struct amdgpu_vm *vm,
2359 struct amdgpu_fence *updates);
2360void amdgpu_vm_fence(struct amdgpu_device *adev,
2361 struct amdgpu_vm *vm,
2362 struct amdgpu_fence *fence);
2363uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2364int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2365 struct amdgpu_vm *vm);
2366int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2367 struct amdgpu_vm *vm);
2368int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
cfe2c978 2369 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
97b2e202
AD		 2370int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2371 struct amdgpu_bo_va *bo_va,
2372 struct ttm_mem_reg *mem);
2373void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2374 struct amdgpu_bo *bo);
2375struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2376 struct amdgpu_bo *bo);
2377struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2378 struct amdgpu_vm *vm,
2379 struct amdgpu_bo *bo);
2380int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2381 struct amdgpu_bo_va *bo_va,
2382 uint64_t addr, uint64_t offset,
2383 uint64_t size, uint32_t flags);
2384int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2385 struct amdgpu_bo_va *bo_va,
2386 uint64_t addr);
2387void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2388 struct amdgpu_bo_va *bo_va);
2389
2390/*
2391 * functions used by amdgpu_encoder.c
2392 */
2393struct amdgpu_afmt_acr {
2394 u32 clock;
2395
2396 int n_32khz;
2397 int cts_32khz;
2398
2399 int n_44_1khz;
2400 int cts_44_1khz;
2401
2402 int n_48khz;
2403 int cts_48khz;
2404
2405};
2406
2407struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2408
2409/* amdgpu_acpi.c */
2410#if defined(CONFIG_ACPI)
2411int amdgpu_acpi_init(struct amdgpu_device *adev);
2412void amdgpu_acpi_fini(struct amdgpu_device *adev);
2413bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2414int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2415 u8 perf_req, bool advertise);
2416int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2417#else
2418static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2419static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2420#endif
2421
2422struct amdgpu_bo_va_mapping *
2423amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2424 uint64_t addr, struct amdgpu_bo **bo);
2425
2426#include "amdgpu_object.h"
2427
2428#endif
Linux kernel - Deliverables
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