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drm/amdgpu: implement new cgs interface for acpi function
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cgs.c
CommitLineData
d03846af
CZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
57ff96cf
CZ		 24#include <linux/list.h>
25#include <linux/slab.h>
97cb7f6e 26#include <linux/pci.h>
3f1d35a0 27#include <linux/acpi.h>
57ff96cf 28#include <drm/drmP.h>
bf3911b0 29#include <linux/firmware.h>
57ff96cf 30#include <drm/amdgpu_drm.h>
d03846af
CZ		 31#include "amdgpu.h"
32#include "cgs_linux.h"
25da4427 33#include "atom.h"
bf3911b0
JZ		 34#include "amdgpu_ucode.h"
35
d03846af
CZ		 36struct amdgpu_cgs_device {
37 struct cgs_device base;
38 struct amdgpu_device *adev;
39};
40
41#define CGS_FUNC_ADEV \
42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev
44
45static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
46 uint64_t *mc_start, uint64_t *mc_size,
47 uint64_t *mem_size)
48{
57ff96cf
CZ		 49 CGS_FUNC_ADEV;
50 switch(type) {
51 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
52 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
53 *mc_start = 0;
54 *mc_size = adev->mc.visible_vram_size;
55 *mem_size = adev->mc.visible_vram_size - adev->vram_pin_size;
56 break;
57 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
58 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
59 *mc_start = adev->mc.visible_vram_size;
60 *mc_size = adev->mc.real_vram_size - adev->mc.visible_vram_size;
61 *mem_size = *mc_size;
62 break;
63 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
64 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
65 *mc_start = adev->mc.gtt_start;
66 *mc_size = adev->mc.gtt_size;
67 *mem_size = adev->mc.gtt_size - adev->gart_pin_size;
68 break;
69 default:
70 return -EINVAL;
71 }
72
d03846af
CZ		 73 return 0;
74}
75
76static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
77 uint64_t size,
78 uint64_t min_offset, uint64_t max_offset,
79 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
80{
57ff96cf
CZ		 81 CGS_FUNC_ADEV;
82 int ret;
83 struct amdgpu_bo *bo;
84 struct page *kmem_page = vmalloc_to_page(kmem);
85 int npages = ALIGN(size, PAGE_SIZE) >> PAGE_SHIFT;
86
87 struct sg_table *sg = drm_prime_pages_to_sg(&kmem_page, npages);
88 ret = amdgpu_bo_create(adev, size, PAGE_SIZE, false,
72d7668b 89 AMDGPU_GEM_DOMAIN_GTT, 0, sg, NULL, &bo);
57ff96cf
CZ		 90 if (ret)
91 return ret;
92 ret = amdgpu_bo_reserve(bo, false);
93 if (unlikely(ret != 0))
94 return ret;
95
96 /* pin buffer into GTT */
97 ret = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_GTT,
98 min_offset, max_offset, mcaddr);
99 amdgpu_bo_unreserve(bo);
100
101 *kmem_handle = (cgs_handle_t)bo;
102 return ret;
d03846af
CZ		 103}
104
105static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
106{
57ff96cf
CZ		 107 struct amdgpu_bo *obj = (struct amdgpu_bo *)kmem_handle;
108
109 if (obj) {
110 int r = amdgpu_bo_reserve(obj, false);
111 if (likely(r == 0)) {
112 amdgpu_bo_unpin(obj);
113 amdgpu_bo_unreserve(obj);
114 }
115 amdgpu_bo_unref(&obj);
116
117 }
d03846af
CZ		 118 return 0;
119}
120
121static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
122 enum cgs_gpu_mem_type type,
123 uint64_t size, uint64_t align,
124 uint64_t min_offset, uint64_t max_offset,
125 cgs_handle_t *handle)
126{
57ff96cf
CZ		 127 CGS_FUNC_ADEV;
128 uint16_t flags = 0;
129 int ret = 0;
130 uint32_t domain = 0;
131 struct amdgpu_bo *obj;
132 struct ttm_placement placement;
133 struct ttm_place place;
134
135 if (min_offset > max_offset) {
136 BUG_ON(1);
137 return -EINVAL;
138 }
139
140 /* fail if the alignment is not a power of 2 */
141 if (((align != 1) && (align & (align - 1)))
142 || size == 0 || align == 0)
143 return -EINVAL;
144
145
146 switch(type) {
147 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
148 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
149 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
150 domain = AMDGPU_GEM_DOMAIN_VRAM;
151 if (max_offset > adev->mc.real_vram_size)
152 return -EINVAL;
153 place.fpfn = min_offset >> PAGE_SHIFT;
154 place.lpfn = max_offset >> PAGE_SHIFT;
155 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
156 TTM_PL_FLAG_VRAM;
157 break;
158 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
159 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
160 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
161 domain = AMDGPU_GEM_DOMAIN_VRAM;
162 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
163 place.fpfn =
164 max(min_offset, adev->mc.visible_vram_size) >> PAGE_SHIFT;
165 place.lpfn =
166 min(max_offset, adev->mc.real_vram_size) >> PAGE_SHIFT;
167 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
168 TTM_PL_FLAG_VRAM;
169 }
170
171 break;
172 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
173 domain = AMDGPU_GEM_DOMAIN_GTT;
174 place.fpfn = min_offset >> PAGE_SHIFT;
175 place.lpfn = max_offset >> PAGE_SHIFT;
176 place.flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
177 break;
178 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
179 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
180 domain = AMDGPU_GEM_DOMAIN_GTT;
181 place.fpfn = min_offset >> PAGE_SHIFT;
182 place.lpfn = max_offset >> PAGE_SHIFT;
183 place.flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
184 TTM_PL_FLAG_UNCACHED;
185 break;
186 default:
187 return -EINVAL;
188 }
189
190
191 *handle = 0;
192
193 placement.placement = &place;
194 placement.num_placement = 1;
195 placement.busy_placement = &place;
196 placement.num_busy_placement = 1;
197
198 ret = amdgpu_bo_create_restricted(adev, size, PAGE_SIZE,
199 true, domain, flags,
72d7668b
CK		 200 NULL, &placement, NULL,
201 &obj);
57ff96cf
CZ		 202 if (ret) {
203 DRM_ERROR("(%d) bo create failed\n", ret);
204 return ret;
205 }
206 *handle = (cgs_handle_t)obj;
207
208 return ret;
d03846af
CZ		 209}
210
d03846af
CZ		 211static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
212{
57ff96cf
CZ		 213 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
214
215 if (obj) {
216 int r = amdgpu_bo_reserve(obj, false);
217 if (likely(r == 0)) {
218 amdgpu_bo_kunmap(obj);
219 amdgpu_bo_unpin(obj);
220 amdgpu_bo_unreserve(obj);
221 }
222 amdgpu_bo_unref(&obj);
223
224 }
d03846af
CZ		 225 return 0;
226}
227
228static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
229 uint64_t *mcaddr)
230{
57ff96cf
CZ		 231 int r;
232 u64 min_offset, max_offset;
233 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
234
235 WARN_ON_ONCE(obj->placement.num_placement > 1);
236
237 min_offset = obj->placements[0].fpfn << PAGE_SHIFT;
238 max_offset = obj->placements[0].lpfn << PAGE_SHIFT;
239
240 r = amdgpu_bo_reserve(obj, false);
241 if (unlikely(r != 0))
242 return r;
243 r = amdgpu_bo_pin_restricted(obj, AMDGPU_GEM_DOMAIN_GTT,
244 min_offset, max_offset, mcaddr);
245 amdgpu_bo_unreserve(obj);
246 return r;
d03846af
CZ		 247}
248
249static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
250{
57ff96cf
CZ		 251 int r;
252 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
253 r = amdgpu_bo_reserve(obj, false);
254 if (unlikely(r != 0))
255 return r;
256 r = amdgpu_bo_unpin(obj);
257 amdgpu_bo_unreserve(obj);
258 return r;
d03846af
CZ		 259}
260
261static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
262 void **map)
263{
57ff96cf
CZ		 264 int r;
265 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
266 r = amdgpu_bo_reserve(obj, false);
267 if (unlikely(r != 0))
268 return r;
269 r = amdgpu_bo_kmap(obj, map);
270 amdgpu_bo_unreserve(obj);
271 return r;
d03846af
CZ		 272}
273
274static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
275{
57ff96cf
CZ		 276 int r;
277 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
278 r = amdgpu_bo_reserve(obj, false);
279 if (unlikely(r != 0))
280 return r;
281 amdgpu_bo_kunmap(obj);
282 amdgpu_bo_unreserve(obj);
283 return r;
d03846af
CZ		 284}
285
286static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
287{
aba684d8
CZ		 288 CGS_FUNC_ADEV;
289 return RREG32(offset);
d03846af
CZ		 290}
291
292static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
293 uint32_t value)
294{
aba684d8
CZ		 295 CGS_FUNC_ADEV;
296 WREG32(offset, value);
d03846af
CZ		 297}
298
299static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
300 enum cgs_ind_reg space,
301 unsigned index)
302{
aba684d8
CZ		 303 CGS_FUNC_ADEV;
304 switch (space) {
305 case CGS_IND_REG__MMIO:
306 return RREG32_IDX(index);
307 case CGS_IND_REG__PCIE:
308 return RREG32_PCIE(index);
309 case CGS_IND_REG__SMC:
310 return RREG32_SMC(index);
311 case CGS_IND_REG__UVD_CTX:
312 return RREG32_UVD_CTX(index);
313 case CGS_IND_REG__DIDT:
314 return RREG32_DIDT(index);
315 case CGS_IND_REG__AUDIO_ENDPT:
316 DRM_ERROR("audio endpt register access not implemented.\n");
317 return 0;
318 }
319 WARN(1, "Invalid indirect register space");
d03846af
CZ		 320 return 0;
321}
322
323static void amdgpu_cgs_write_ind_register(void *cgs_device,
324 enum cgs_ind_reg space,
325 unsigned index, uint32_t value)
326{
aba684d8
CZ		 327 CGS_FUNC_ADEV;
328 switch (space) {
329 case CGS_IND_REG__MMIO:
330 return WREG32_IDX(index, value);
331 case CGS_IND_REG__PCIE:
332 return WREG32_PCIE(index, value);
333 case CGS_IND_REG__SMC:
334 return WREG32_SMC(index, value);
335 case CGS_IND_REG__UVD_CTX:
336 return WREG32_UVD_CTX(index, value);
337 case CGS_IND_REG__DIDT:
338 return WREG32_DIDT(index, value);
339 case CGS_IND_REG__AUDIO_ENDPT:
340 DRM_ERROR("audio endpt register access not implemented.\n");
341 return;
342 }
343 WARN(1, "Invalid indirect register space");
d03846af
CZ		 344}
345
346static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
347{
97cb7f6e
CZ		 348 CGS_FUNC_ADEV;
349 uint8_t val;
350 int ret = pci_read_config_byte(adev->pdev, addr, &val);
351 if (WARN(ret, "pci_read_config_byte error"))
352 return 0;
353 return val;
d03846af
CZ		 354}
355
356static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
357{
97cb7f6e
CZ		 358 CGS_FUNC_ADEV;
359 uint16_t val;
360 int ret = pci_read_config_word(adev->pdev, addr, &val);
361 if (WARN(ret, "pci_read_config_word error"))
362 return 0;
363 return val;
d03846af
CZ		 364}
365
366static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
367 unsigned addr)
368{
97cb7f6e
CZ		 369 CGS_FUNC_ADEV;
370 uint32_t val;
371 int ret = pci_read_config_dword(adev->pdev, addr, &val);
372 if (WARN(ret, "pci_read_config_dword error"))
373 return 0;
374 return val;
d03846af
CZ		 375}
376
377static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
378 uint8_t value)
379{
97cb7f6e
CZ		 380 CGS_FUNC_ADEV;
381 int ret = pci_write_config_byte(adev->pdev, addr, value);
382 WARN(ret, "pci_write_config_byte error");
d03846af
CZ		 383}
384
385static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
386 uint16_t value)
387{
97cb7f6e
CZ		 388 CGS_FUNC_ADEV;
389 int ret = pci_write_config_word(adev->pdev, addr, value);
390 WARN(ret, "pci_write_config_word error");
d03846af
CZ		 391}
392
393static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
394 uint32_t value)
395{
97cb7f6e
CZ		 396 CGS_FUNC_ADEV;
397 int ret = pci_write_config_dword(adev->pdev, addr, value);
398 WARN(ret, "pci_write_config_dword error");
d03846af
CZ		 399}
400
401static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
402 unsigned table, uint16_t *size,
403 uint8_t *frev, uint8_t *crev)
404{
25da4427
CZ		 405 CGS_FUNC_ADEV;
406 uint16_t data_start;
407
408 if (amdgpu_atom_parse_data_header(
409 adev->mode_info.atom_context, table, size,
410 frev, crev, &data_start))
411 return (uint8_t*)adev->mode_info.atom_context->bios +
412 data_start;
413
d03846af
CZ		 414 return NULL;
415}
416
417static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
418 uint8_t *frev, uint8_t *crev)
419{
25da4427
CZ		 420 CGS_FUNC_ADEV;
421
422 if (amdgpu_atom_parse_cmd_header(
423 adev->mode_info.atom_context, table,
424 frev, crev))
425 return 0;
426
427 return -EINVAL;
d03846af
CZ		 428}
429
430static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
431 void *args)
432{
25da4427 433 CGS_FUNC_ADEV;
d03846af 434
25da4427
CZ		 435 return amdgpu_atom_execute_table(
436 adev->mode_info.atom_context, table, args);
437}
d03846af
CZ		 438
439static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request)
440{
441 /* TODO */
442 return 0;
443}
444
445static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
446{
447 /* TODO */
448 return 0;
449}
450
451static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
452 int active)
453{
454 /* TODO */
455 return 0;
456}
457
458static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
459 enum cgs_clock clock, unsigned freq)
460{
461 /* TODO */
462 return 0;
463}
464
465static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
466 enum cgs_engine engine, int powered)
467{
468 /* TODO */
469 return 0;
470}
471
472
473
474static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
475 enum cgs_clock clock,
476 struct cgs_clock_limits *limits)
477{
478 /* TODO */
479 return 0;
480}
481
482static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
483 const uint32_t *voltages)
484{
485 DRM_ERROR("not implemented");
486 return -EPERM;
487}
488
0cf3be21
AD		 489struct cgs_irq_params {
490 unsigned src_id;
491 cgs_irq_source_set_func_t set;
492 cgs_irq_handler_func_t handler;
493 void *private_data;
494};
495
496static int cgs_set_irq_state(struct amdgpu_device *adev,
497 struct amdgpu_irq_src *src,
498 unsigned type,
499 enum amdgpu_interrupt_state state)
500{
501 struct cgs_irq_params *irq_params =
502 (struct cgs_irq_params *)src->data;
503 if (!irq_params)
504 return -EINVAL;
505 if (!irq_params->set)
506 return -EINVAL;
507 return irq_params->set(irq_params->private_data,
508 irq_params->src_id,
509 type,
510 (int)state);
511}
512
513static int cgs_process_irq(struct amdgpu_device *adev,
514 struct amdgpu_irq_src *source,
515 struct amdgpu_iv_entry *entry)
516{
517 struct cgs_irq_params *irq_params =
518 (struct cgs_irq_params *)source->data;
519 if (!irq_params)
520 return -EINVAL;
521 if (!irq_params->handler)
522 return -EINVAL;
523 return irq_params->handler(irq_params->private_data,
524 irq_params->src_id,
525 entry->iv_entry);
526}
527
528static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
529 .set = cgs_set_irq_state,
530 .process = cgs_process_irq,
531};
532
d03846af
CZ		 533static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
534 unsigned num_types,
535 cgs_irq_source_set_func_t set,
536 cgs_irq_handler_func_t handler,
537 void *private_data)
538{
0cf3be21
AD		 539 CGS_FUNC_ADEV;
540 int ret = 0;
541 struct cgs_irq_params *irq_params;
542 struct amdgpu_irq_src *source =
543 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
544 if (!source)
545 return -ENOMEM;
546 irq_params =
547 kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
548 if (!irq_params) {
549 kfree(source);
550 return -ENOMEM;
551 }
552 source->num_types = num_types;
553 source->funcs = &cgs_irq_funcs;
554 irq_params->src_id = src_id;
555 irq_params->set = set;
556 irq_params->handler = handler;
557 irq_params->private_data = private_data;
558 source->data = (void *)irq_params;
559 ret = amdgpu_irq_add_id(adev, src_id, source);
560 if (ret) {
561 kfree(irq_params);
562 kfree(source);
563 }
564
565 return ret;
d03846af
CZ		 566}
567
568static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
569{
0cf3be21
AD		 570 CGS_FUNC_ADEV;
571 return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
d03846af
CZ		 572}
573
574static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
575{
0cf3be21
AD		 576 CGS_FUNC_ADEV;
577 return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
d03846af
CZ		 578}
579
404b2fa3 580int amdgpu_cgs_set_clockgating_state(void *cgs_device,
581 enum amd_ip_block_type block_type,
582 enum amd_clockgating_state state)
583{
584 CGS_FUNC_ADEV;
585 int i, r = -1;
586
587 for (i = 0; i < adev->num_ip_blocks; i++) {
588 if (!adev->ip_block_status[i].valid)
589 continue;
590
591 if (adev->ip_blocks[i].type == block_type) {
592 r = adev->ip_blocks[i].funcs->set_clockgating_state(
593 (void *)adev,
594 state);
595 break;
596 }
597 }
598 return r;
599}
600
601int amdgpu_cgs_set_powergating_state(void *cgs_device,
602 enum amd_ip_block_type block_type,
603 enum amd_powergating_state state)
604{
605 CGS_FUNC_ADEV;
606 int i, r = -1;
607
608 for (i = 0; i < adev->num_ip_blocks; i++) {
609 if (!adev->ip_block_status[i].valid)
610 continue;
611
612 if (adev->ip_blocks[i].type == block_type) {
613 r = adev->ip_blocks[i].funcs->set_powergating_state(
614 (void *)adev,
615 state);
616 break;
617 }
618 }
619 return r;
620}
621
622
bf3911b0
JZ		 623static uint32_t fw_type_convert(void *cgs_device, uint32_t fw_type)
624{
625 CGS_FUNC_ADEV;
626 enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
627
628 switch (fw_type) {
629 case CGS_UCODE_ID_SDMA0:
630 result = AMDGPU_UCODE_ID_SDMA0;
631 break;
632 case CGS_UCODE_ID_SDMA1:
633 result = AMDGPU_UCODE_ID_SDMA1;
634 break;
635 case CGS_UCODE_ID_CP_CE:
636 result = AMDGPU_UCODE_ID_CP_CE;
637 break;
638 case CGS_UCODE_ID_CP_PFP:
639 result = AMDGPU_UCODE_ID_CP_PFP;
640 break;
641 case CGS_UCODE_ID_CP_ME:
642 result = AMDGPU_UCODE_ID_CP_ME;
643 break;
644 case CGS_UCODE_ID_CP_MEC:
645 case CGS_UCODE_ID_CP_MEC_JT1:
646 result = AMDGPU_UCODE_ID_CP_MEC1;
647 break;
648 case CGS_UCODE_ID_CP_MEC_JT2:
649 if (adev->asic_type == CHIP_TONGA)
650 result = AMDGPU_UCODE_ID_CP_MEC2;
651 else if (adev->asic_type == CHIP_CARRIZO)
652 result = AMDGPU_UCODE_ID_CP_MEC1;
653 break;
654 case CGS_UCODE_ID_RLC_G:
655 result = AMDGPU_UCODE_ID_RLC_G;
656 break;
657 default:
658 DRM_ERROR("Firmware type not supported\n");
659 }
660 return result;
661}
662
663static int amdgpu_cgs_get_firmware_info(void *cgs_device,
664 enum cgs_ucode_id type,
665 struct cgs_firmware_info *info)
666{
667 CGS_FUNC_ADEV;
668
669 if (CGS_UCODE_ID_SMU != type) {
670 uint64_t gpu_addr;
671 uint32_t data_size;
672 const struct gfx_firmware_header_v1_0 *header;
673 enum AMDGPU_UCODE_ID id;
674 struct amdgpu_firmware_info *ucode;
675
676 id = fw_type_convert(cgs_device, type);
677 ucode = &adev->firmware.ucode[id];
678 if (ucode->fw == NULL)
679 return -EINVAL;
680
681 gpu_addr = ucode->mc_addr;
682 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
683 data_size = le32_to_cpu(header->header.ucode_size_bytes);
684
685 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
686 (type == CGS_UCODE_ID_CP_MEC_JT2)) {
687 gpu_addr += le32_to_cpu(header->jt_offset) << 2;
688 data_size = le32_to_cpu(header->jt_size) << 2;
689 }
690 info->mc_addr = gpu_addr;
691 info->image_size = data_size;
692 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
693 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
694 } else {
695 char fw_name[30] = {0};
696 int err = 0;
697 uint32_t ucode_size;
698 uint32_t ucode_start_address;
699 const uint8_t *src;
700 const struct smc_firmware_header_v1_0 *hdr;
701
702 switch (adev->asic_type) {
703 case CHIP_TONGA:
704 strcpy(fw_name, "amdgpu/tonga_smc.bin");
705 break;
706 default:
707 DRM_ERROR("SMC firmware not supported\n");
708 return -EINVAL;
709 }
710
711 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
712 if (err) {
713 DRM_ERROR("Failed to request firmware\n");
714 return err;
715 }
716
717 err = amdgpu_ucode_validate(adev->pm.fw);
718 if (err) {
719 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
720 release_firmware(adev->pm.fw);
721 adev->pm.fw = NULL;
722 return err;
723 }
724
725 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
726 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
727 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
728 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
729 src = (const uint8_t *)(adev->pm.fw->data +
730 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
731
732 info->version = adev->pm.fw_version;
733 info->image_size = ucode_size;
734 info->kptr = (void *)src;
735 }
736 return 0;
737}
738
3f1d35a0
RZ		 739/** \brief evaluate acpi namespace object, handle or pathname must be valid
740 * \param cgs_device
741 * \param info input/output arguments for the control method
742 * \return status
743 */
744
745#if defined(CONFIG_ACPI)
746static int amdgpu_cgs_acpi_eval_object(void *cgs_device,
747 struct cgs_acpi_method_info *info)
748{
749 CGS_FUNC_ADEV;
750 acpi_handle handle;
751 struct acpi_object_list input;
752 struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
753 union acpi_object *params = NULL;
754 union acpi_object *obj = NULL;
755 uint8_t name[5] = {'\0'};
756 struct cgs_acpi_method_argument *argument = NULL;
757 uint32_t i, count;
758 acpi_status status;
759 int result;
760 uint32_t func_no = 0xFFFFFFFF;
761
762 handle = ACPI_HANDLE(&adev->pdev->dev);
763 if (!handle)
764 return -ENODEV;
765
766 memset(&input, 0, sizeof(struct acpi_object_list));
767
768 /* validate input info */
769 if (info->size != sizeof(struct cgs_acpi_method_info))
770 return -EINVAL;
771
772 input.count = info->input_count;
773 if (info->input_count > 0) {
774 if (info->pinput_argument == NULL)
775 return -EINVAL;
776 argument = info->pinput_argument;
777 func_no = argument->value;
778 for (i = 0; i < info->input_count; i++) {
779 if (((argument->type == ACPI_TYPE_STRING) ||
780 (argument->type == ACPI_TYPE_BUFFER))
781 && (argument->pointer == NULL))
782 return -EINVAL;
783 argument++;
784 }
785 }
786
787 if (info->output_count > 0) {
788 if (info->poutput_argument == NULL)
789 return -EINVAL;
790 argument = info->poutput_argument;
791 for (i = 0; i < info->output_count; i++) {
792 if (((argument->type == ACPI_TYPE_STRING) ||
793 (argument->type == ACPI_TYPE_BUFFER))
794 && (argument->pointer == NULL))
795 return -EINVAL;
796 argument++;
797 }
798 }
799
800 /* The path name passed to acpi_evaluate_object should be null terminated */
801 if ((info->field & CGS_ACPI_FIELD_METHOD_NAME) != 0) {
802 strncpy(name, (char *)&(info->name), sizeof(uint32_t));
803 name[4] = '\0';
804 }
805
806 /* parse input parameters */
807 if (input.count > 0) {
808 input.pointer = params =
809 kzalloc(sizeof(union acpi_object) * input.count, GFP_KERNEL);
810 if (params == NULL)
811 return -EINVAL;
812
813 argument = info->pinput_argument;
814
815 for (i = 0; i < input.count; i++) {
816 params->type = argument->type;
817 switch (params->type) {
818 case ACPI_TYPE_INTEGER:
819 params->integer.value = argument->value;
820 break;
821 case ACPI_TYPE_STRING:
822 params->string.length = argument->method_length;
823 params->string.pointer = argument->pointer;
824 break;
825 case ACPI_TYPE_BUFFER:
826 params->buffer.length = argument->method_length;
827 params->buffer.pointer = argument->pointer;
828 break;
829 default:
830 break;
831 }
832 params++;
833 argument++;
834 }
835 }
836
837 /* parse output info */
838 count = info->output_count;
839 argument = info->poutput_argument;
840
841 /* evaluate the acpi method */
842 status = acpi_evaluate_object(handle, name, &input, &output);
843
844 if (ACPI_FAILURE(status)) {
845 result = -EIO;
846 goto error;
847 }
848
849 /* return the output info */
850 obj = output.pointer;
851
852 if (count > 1) {
853 if ((obj->type != ACPI_TYPE_PACKAGE) ||
854 (obj->package.count != count)) {
855 result = -EIO;
856 goto error;
857 }
858 params = obj->package.elements;
859 } else
860 params = obj;
861
862 if (params == NULL) {
863 result = -EIO;
864 goto error;
865 }
866
867 for (i = 0; i < count; i++) {
868 if (argument->type != params->type) {
869 result = -EIO;
870 goto error;
871 }
872 switch (params->type) {
873 case ACPI_TYPE_INTEGER:
874 argument->value = params->integer.value;
875 break;
876 case ACPI_TYPE_STRING:
877 if ((params->string.length != argument->data_length) ||
878 (params->string.pointer == NULL)) {
879 result = -EIO;
880 goto error;
881 }
882 strncpy(argument->pointer,
883 params->string.pointer,
884 params->string.length);
885 break;
886 case ACPI_TYPE_BUFFER:
887 if (params->buffer.pointer == NULL) {
888 result = -EIO;
889 goto error;
890 }
891 memcpy(argument->pointer,
892 params->buffer.pointer,
893 argument->data_length);
894 break;
895 default:
896 break;
897 }
898 argument++;
899 params++;
900 }
901
902error:
903 if (obj != NULL)
904 kfree(obj);
905 kfree((void *)input.pointer);
906 return result;
907}
908#else
909static int amdgpu_cgs_acpi_eval_object(void *cgs_device,
910 struct cgs_acpi_method_info *info)
911{
912 return -EIO;
913}
914#endif
915
916int amdgpu_cgs_call_acpi_method(void *cgs_device,
917 uint32_t acpi_method,
918 uint32_t acpi_function,
919 void *pinput, void *poutput,
920 uint32_t output_count,
921 uint32_t input_size,
922 uint32_t output_size)
923{
924 struct cgs_acpi_method_argument acpi_input[2] = { {0}, {0} };
925 struct cgs_acpi_method_argument acpi_output = {0};
926 struct cgs_acpi_method_info info = {0};
927
928 acpi_input[0].type = CGS_ACPI_TYPE_INTEGER;
929 acpi_input[0].method_length = sizeof(uint32_t);
930 acpi_input[0].data_length = sizeof(uint32_t);
931 acpi_input[0].value = acpi_function;
932
933 acpi_input[1].type = CGS_ACPI_TYPE_BUFFER;
934 acpi_input[1].method_length = CGS_ACPI_MAX_BUFFER_SIZE;
935 acpi_input[1].data_length = input_size;
936 acpi_input[1].pointer = pinput;
937
938 acpi_output.type = CGS_ACPI_TYPE_BUFFER;
939 acpi_output.method_length = CGS_ACPI_MAX_BUFFER_SIZE;
940 acpi_output.data_length = output_size;
941 acpi_output.pointer = poutput;
942
943 info.size = sizeof(struct cgs_acpi_method_info);
944 info.field = CGS_ACPI_FIELD_METHOD_NAME | CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT;
945 info.input_count = 2;
946 info.name = acpi_method;
947 info.pinput_argument = acpi_input;
948 info.output_count = output_count;
949 info.poutput_argument = &acpi_output;
950
951 return amdgpu_cgs_acpi_eval_object(cgs_device, &info);
952}
953
d03846af
CZ		 954static const struct cgs_ops amdgpu_cgs_ops = {
955 amdgpu_cgs_gpu_mem_info,
956 amdgpu_cgs_gmap_kmem,
957 amdgpu_cgs_gunmap_kmem,
958 amdgpu_cgs_alloc_gpu_mem,
959 amdgpu_cgs_free_gpu_mem,
960 amdgpu_cgs_gmap_gpu_mem,
961 amdgpu_cgs_gunmap_gpu_mem,
962 amdgpu_cgs_kmap_gpu_mem,
963 amdgpu_cgs_kunmap_gpu_mem,
964 amdgpu_cgs_read_register,
965 amdgpu_cgs_write_register,
966 amdgpu_cgs_read_ind_register,
967 amdgpu_cgs_write_ind_register,
968 amdgpu_cgs_read_pci_config_byte,
969 amdgpu_cgs_read_pci_config_word,
970 amdgpu_cgs_read_pci_config_dword,
971 amdgpu_cgs_write_pci_config_byte,
972 amdgpu_cgs_write_pci_config_word,
973 amdgpu_cgs_write_pci_config_dword,
974 amdgpu_cgs_atom_get_data_table,
975 amdgpu_cgs_atom_get_cmd_table_revs,
976 amdgpu_cgs_atom_exec_cmd_table,
977 amdgpu_cgs_create_pm_request,
978 amdgpu_cgs_destroy_pm_request,
979 amdgpu_cgs_set_pm_request,
980 amdgpu_cgs_pm_request_clock,
981 amdgpu_cgs_pm_request_engine,
982 amdgpu_cgs_pm_query_clock_limits,
bf3911b0 983 amdgpu_cgs_set_camera_voltages,
404b2fa3 984 amdgpu_cgs_get_firmware_info,
985 amdgpu_cgs_set_powergating_state,
3f1d35a0
RZ		 986 amdgpu_cgs_set_clockgating_state,
987 amdgpu_cgs_call_acpi_method,
d03846af
CZ		 988};
989
990static const struct cgs_os_ops amdgpu_cgs_os_ops = {
d03846af
CZ		 991 amdgpu_cgs_add_irq_source,
992 amdgpu_cgs_irq_get,
993 amdgpu_cgs_irq_put
994};
995
996void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
997{
998 struct amdgpu_cgs_device *cgs_device =
999 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
1000
1001 if (!cgs_device) {
1002 DRM_ERROR("Couldn't allocate CGS device structure\n");
1003 return NULL;
1004 }
1005
1006 cgs_device->base.ops = &amdgpu_cgs_ops;
1007 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
1008 cgs_device->adev = adev;
1009
1010 return cgs_device;
1011}
1012
1013void amdgpu_cgs_destroy_device(void *cgs_device)
1014{
1015 kfree(cgs_device);
1016}
Linux kernel - Deliverables
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