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Merge remote-tracking branch 'omap_dss2/for-next'
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 53 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
54 * at the end of IBs.
d347ce66 55 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 56 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 57 * - 3.5.0 - Add support for new UVD_NO_OP register.
d38ceaf9
AD		 58 */
59#define KMS_DRIVER_MAJOR 3
8dd31d74 60#define KMS_DRIVER_MINOR 5
d38ceaf9
AD		 61#define KMS_DRIVER_PATCHLEVEL 0
62
63int amdgpu_vram_limit = 0;
64int amdgpu_gart_size = -1; /* auto */
65int amdgpu_benchmarking = 0;
66int amdgpu_testing = 0;
67int amdgpu_audio = -1;
68int amdgpu_disp_priority = 0;
69int amdgpu_hw_i2c = 0;
70int amdgpu_pcie_gen2 = -1;
71int amdgpu_msi = -1;
a895c222 72int amdgpu_lockup_timeout = 0;
d38ceaf9
AD		 73int amdgpu_dpm = -1;
74int amdgpu_smc_load_fw = 1;
75int amdgpu_aspm = -1;
76int amdgpu_runtime_pm = -1;
d38ceaf9
AD		 77unsigned amdgpu_ip_block_mask = 0xffffffff;
78int amdgpu_bapm = -1;
79int amdgpu_deep_color = 0;
ed885b21 80int amdgpu_vm_size = 64;
d38ceaf9 81int amdgpu_vm_block_size = -1;
d9c13156 82int amdgpu_vm_fault_stop = 0;
b495bd3a 83int amdgpu_vm_debug = 0;
d38ceaf9 84int amdgpu_exp_hw_support = 0;
b70f014d 85int amdgpu_sched_jobs = 32;
4afcb303 86int amdgpu_sched_hw_submission = 2;
e61710c5 87int amdgpu_powerplay = -1;
6bb6b297 88int amdgpu_powercontainment = 1;
af223dfa 89int amdgpu_sclk_deep_sleep_en = 1;
cd474ba0
AD		 90unsigned amdgpu_pcie_gen_cap = 0;
91unsigned amdgpu_pcie_lane_cap = 0;
395d1fb9
NH		 92unsigned amdgpu_cg_mask = 0xffffffff;
93unsigned amdgpu_pg_mask = 0xffffffff;
6f8941a2 94char *amdgpu_disable_cu = NULL;
9accf2fd 95char *amdgpu_virtual_display = NULL;
d38ceaf9
AD		 96
97MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
98module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
99
100MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
101module_param_named(gartsize, amdgpu_gart_size, int, 0600);
102
103MODULE_PARM_DESC(benchmark, "Run benchmark");
104module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
105
106MODULE_PARM_DESC(test, "Run tests");
107module_param_named(test, amdgpu_testing, int, 0444);
108
109MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
110module_param_named(audio, amdgpu_audio, int, 0444);
111
112MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
113module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
114
115MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
116module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
117
118MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
119module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
120
121MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
122module_param_named(msi, amdgpu_msi, int, 0444);
123
a895c222 124MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 125module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
126
127MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
128module_param_named(dpm, amdgpu_dpm, int, 0444);
129
130MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
131module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
132
133MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
134module_param_named(aspm, amdgpu_aspm, int, 0444);
135
136MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
137module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
138
d38ceaf9
AD		 139MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
140module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
141
142MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
143module_param_named(bapm, amdgpu_bapm, int, 0444);
144
145MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
146module_param_named(deep_color, amdgpu_deep_color, int, 0444);
147
ed885b21 148MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9
AD		 149module_param_named(vm_size, amdgpu_vm_size, int, 0444);
150
151MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
152module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
153
d9c13156
CK		 154MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
155module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
156
b495bd3a
CK		 157MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
158module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
159
d38ceaf9
AD		 160MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
161module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
162
b70f014d 163MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 164module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
165
4afcb303
JZ		 166MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
167module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
168
3a74f6f2 169#ifdef CONFIG_DRM_AMD_POWERPLAY
e61710c5 170MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))");
3a74f6f2 171module_param_named(powerplay, amdgpu_powerplay, int, 0444);
6bb6b297
HR		 172
173MODULE_PARM_DESC(powercontainment, "Power Containment (1 = enable (default), 0 = disable)");
174module_param_named(powercontainment, amdgpu_powercontainment, int, 0444);
3a74f6f2
JZ		 175#endif
176
af223dfa
RZ		 177MODULE_PARM_DESC(sclkdeepsleep, "SCLK Deep Sleep (1 = enable (default), 0 = disable)");
178module_param_named(sclkdeepsleep, amdgpu_sclk_deep_sleep_en, int, 0444);
179
cd474ba0
AD		 180MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
181module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
182
183MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
184module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
185
395d1fb9
NH		 186MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
187module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
188
189MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
190module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
191
6f8941a2
NH		 192MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
193module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
194
9accf2fd
ED		 195MODULE_PARM_DESC(virtual_display, "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x;xxxx:xx:xx.x)");
196module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 197
f498d9ed 198static const struct pci_device_id pciidlist[] = {
89330c39
AD		 199#ifdef CONFIG_DRM_AMDGPU_CIK
200 /* Kaveri */
2f7d10b3
JZ		 201 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
202 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
203 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
204 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
205 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
206 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
207 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
208 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
209 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
210 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
211 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
212 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
213 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
214 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
215 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
216 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
217 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
218 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
219 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
220 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
221 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
222 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 223 /* Bonaire */
2f7d10b3
JZ		 224 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
225 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
226 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
227 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 228 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
229 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
230 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
231 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
232 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
233 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 234 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 235 /* Hawaii */
236 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
237 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
238 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
239 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
240 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
241 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
242 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
243 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
244 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
245 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
246 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
247 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
248 /* Kabini */
2f7d10b3
JZ		 249 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
250 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
251 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
252 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
253 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
254 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
255 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
256 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
257 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
258 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
259 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
260 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
261 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
262 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
263 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
264 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 265 /* mullins */
2f7d10b3
JZ		 266 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
267 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
268 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
269 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
270 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
271 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
272 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
273 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
274 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
275 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
276 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
277 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
278 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
279 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
280 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
281 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 282#endif
1256a8b8 283 /* topaz */
dba280b2
AD		 284 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
285 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
286 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
287 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
288 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 289 /* tonga */
290 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
291 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
292 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 293 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 294 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
295 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 296 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 297 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
298 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 299 /* fiji */
300 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 301 /* carrizo */
2f7d10b3
JZ		 302 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
303 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
304 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
305 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
306 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 307 /* stoney */
308 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 309 /* Polaris11 */
310 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 311 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 312 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 313 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 314 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 315 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 316 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
317 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
318 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 319 /* Polaris10 */
320 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 321 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
322 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
323 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
324 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 325 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 326 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
327 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
328 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
329 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
330 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
d38ceaf9
AD		 331
332 {0, 0, 0}
333};
334
335MODULE_DEVICE_TABLE(pci, pciidlist);
336
337static struct drm_driver kms_driver;
338
339static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
340{
341 struct apertures_struct *ap;
342 bool primary = false;
343
344 ap = alloc_apertures(1);
345 if (!ap)
346 return -ENOMEM;
347
348 ap->ranges[0].base = pci_resource_start(pdev, 0);
349 ap->ranges[0].size = pci_resource_len(pdev, 0);
350
351#ifdef CONFIG_X86
352 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
353#endif
44adece5 354 drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
d38ceaf9
AD		 355 kfree(ap);
356
357 return 0;
358}
359
360static int amdgpu_pci_probe(struct pci_dev *pdev,
361 const struct pci_device_id *ent)
362{
363 unsigned long flags = ent->driver_data;
364 int ret;
365
2f7d10b3 366 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 367 DRM_INFO("This hardware requires experimental hardware support.\n"
368 "See modparam exp_hw_support\n");
369 return -ENODEV;
370 }
371
efb1c658
OG		 372 /*
373 * Initialize amdkfd before starting radeon. If it was not loaded yet,
374 * defer radeon probing
375 */
376 ret = amdgpu_amdkfd_init();
377 if (ret == -EPROBE_DEFER)
378 return ret;
379
d38ceaf9
AD		 380 /* Get rid of things like offb */
381 ret = amdgpu_kick_out_firmware_fb(pdev);
382 if (ret)
383 return ret;
384
385 return drm_get_pci_dev(pdev, ent, &kms_driver);
386}
387
388static void
389amdgpu_pci_remove(struct pci_dev *pdev)
390{
391 struct drm_device *dev = pci_get_drvdata(pdev);
392
393 drm_put_dev(dev);
394}
395
396static int amdgpu_pmops_suspend(struct device *dev)
397{
398 struct pci_dev *pdev = to_pci_dev(dev);
399 struct drm_device *drm_dev = pci_get_drvdata(pdev);
400 return amdgpu_suspend_kms(drm_dev, true, true);
401}
402
403static int amdgpu_pmops_resume(struct device *dev)
404{
405 struct pci_dev *pdev = to_pci_dev(dev);
406 struct drm_device *drm_dev = pci_get_drvdata(pdev);
407 return amdgpu_resume_kms(drm_dev, true, true);
408}
409
410static int amdgpu_pmops_freeze(struct device *dev)
411{
412 struct pci_dev *pdev = to_pci_dev(dev);
413 struct drm_device *drm_dev = pci_get_drvdata(pdev);
414 return amdgpu_suspend_kms(drm_dev, false, true);
415}
416
417static int amdgpu_pmops_thaw(struct device *dev)
418{
419 struct pci_dev *pdev = to_pci_dev(dev);
420 struct drm_device *drm_dev = pci_get_drvdata(pdev);
421 return amdgpu_resume_kms(drm_dev, false, true);
422}
423
424static int amdgpu_pmops_runtime_suspend(struct device *dev)
425{
426 struct pci_dev *pdev = to_pci_dev(dev);
427 struct drm_device *drm_dev = pci_get_drvdata(pdev);
428 int ret;
429
430 if (!amdgpu_device_is_px(drm_dev)) {
431 pm_runtime_forbid(dev);
432 return -EBUSY;
433 }
434
435 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
436 drm_kms_helper_poll_disable(drm_dev);
437 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
438
439 ret = amdgpu_suspend_kms(drm_dev, false, false);
440 pci_save_state(pdev);
441 pci_disable_device(pdev);
442 pci_ignore_hotplug(pdev);
11670975
AD		 443 if (amdgpu_is_atpx_hybrid())
444 pci_set_power_state(pdev, PCI_D3cold);
522761cb 445 else if (!amdgpu_has_atpx_dgpu_power_cntl())
7e32aa61 446 pci_set_power_state(pdev, PCI_D3hot);
d38ceaf9
AD		 447 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
448
449 return 0;
450}
451
452static int amdgpu_pmops_runtime_resume(struct device *dev)
453{
454 struct pci_dev *pdev = to_pci_dev(dev);
455 struct drm_device *drm_dev = pci_get_drvdata(pdev);
456 int ret;
457
458 if (!amdgpu_device_is_px(drm_dev))
459 return -EINVAL;
460
461 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
462
522761cb
AD		 463 if (amdgpu_is_atpx_hybrid() ||
464 !amdgpu_has_atpx_dgpu_power_cntl())
465 pci_set_power_state(pdev, PCI_D0);
d38ceaf9
AD		 466 pci_restore_state(pdev);
467 ret = pci_enable_device(pdev);
468 if (ret)
469 return ret;
470 pci_set_master(pdev);
471
472 ret = amdgpu_resume_kms(drm_dev, false, false);
473 drm_kms_helper_poll_enable(drm_dev);
474 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
475 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
476 return 0;
477}
478
479static int amdgpu_pmops_runtime_idle(struct device *dev)
480{
481 struct pci_dev *pdev = to_pci_dev(dev);
482 struct drm_device *drm_dev = pci_get_drvdata(pdev);
483 struct drm_crtc *crtc;
484
485 if (!amdgpu_device_is_px(drm_dev)) {
486 pm_runtime_forbid(dev);
487 return -EBUSY;
488 }
489
490 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
491 if (crtc->enabled) {
492 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
493 return -EBUSY;
494 }
495 }
496
497 pm_runtime_mark_last_busy(dev);
498 pm_runtime_autosuspend(dev);
499 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
500 return 1;
501}
502
503long amdgpu_drm_ioctl(struct file *filp,
504 unsigned int cmd, unsigned long arg)
505{
506 struct drm_file *file_priv = filp->private_data;
507 struct drm_device *dev;
508 long ret;
509 dev = file_priv->minor->dev;
510 ret = pm_runtime_get_sync(dev->dev);
511 if (ret < 0)
512 return ret;
513
514 ret = drm_ioctl(filp, cmd, arg);
515
516 pm_runtime_mark_last_busy(dev->dev);
517 pm_runtime_put_autosuspend(dev->dev);
518 return ret;
519}
520
521static const struct dev_pm_ops amdgpu_pm_ops = {
522 .suspend = amdgpu_pmops_suspend,
523 .resume = amdgpu_pmops_resume,
524 .freeze = amdgpu_pmops_freeze,
525 .thaw = amdgpu_pmops_thaw,
526 .poweroff = amdgpu_pmops_freeze,
527 .restore = amdgpu_pmops_resume,
528 .runtime_suspend = amdgpu_pmops_runtime_suspend,
529 .runtime_resume = amdgpu_pmops_runtime_resume,
530 .runtime_idle = amdgpu_pmops_runtime_idle,
531};
532
533static const struct file_operations amdgpu_driver_kms_fops = {
534 .owner = THIS_MODULE,
535 .open = drm_open,
536 .release = drm_release,
537 .unlocked_ioctl = amdgpu_drm_ioctl,
538 .mmap = amdgpu_mmap,
539 .poll = drm_poll,
540 .read = drm_read,
541#ifdef CONFIG_COMPAT
542 .compat_ioctl = amdgpu_kms_compat_ioctl,
543#endif
544};
545
546static struct drm_driver kms_driver = {
547 .driver_features =
548 DRIVER_USE_AGP |
549 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
7056bb5c 550 DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET,
d38ceaf9
AD		 551 .dev_priv_size = 0,
552 .load = amdgpu_driver_load_kms,
553 .open = amdgpu_driver_open_kms,
554 .preclose = amdgpu_driver_preclose_kms,
555 .postclose = amdgpu_driver_postclose_kms,
556 .lastclose = amdgpu_driver_lastclose_kms,
557 .set_busid = drm_pci_set_busid,
558 .unload = amdgpu_driver_unload_kms,
559 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
560 .enable_vblank = amdgpu_enable_vblank_kms,
561 .disable_vblank = amdgpu_disable_vblank_kms,
562 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
563 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
564#if defined(CONFIG_DEBUG_FS)
565 .debugfs_init = amdgpu_debugfs_init,
566 .debugfs_cleanup = amdgpu_debugfs_cleanup,
567#endif
568 .irq_preinstall = amdgpu_irq_preinstall,
569 .irq_postinstall = amdgpu_irq_postinstall,
570 .irq_uninstall = amdgpu_irq_uninstall,
571 .irq_handler = amdgpu_irq_handler,
572 .ioctls = amdgpu_ioctls_kms,
e7294dee 573 .gem_free_object_unlocked = amdgpu_gem_object_free,
d38ceaf9
AD		 574 .gem_open_object = amdgpu_gem_object_open,
575 .gem_close_object = amdgpu_gem_object_close,
576 .dumb_create = amdgpu_mode_dumb_create,
577 .dumb_map_offset = amdgpu_mode_dumb_mmap,
578 .dumb_destroy = drm_gem_dumb_destroy,
579 .fops = &amdgpu_driver_kms_fops,
580
581 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
582 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
583 .gem_prime_export = amdgpu_gem_prime_export,
584 .gem_prime_import = drm_gem_prime_import,
585 .gem_prime_pin = amdgpu_gem_prime_pin,
586 .gem_prime_unpin = amdgpu_gem_prime_unpin,
587 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
588 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
589 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
590 .gem_prime_vmap = amdgpu_gem_prime_vmap,
591 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
592
593 .name = DRIVER_NAME,
594 .desc = DRIVER_DESC,
595 .date = DRIVER_DATE,
596 .major = KMS_DRIVER_MAJOR,
597 .minor = KMS_DRIVER_MINOR,
598 .patchlevel = KMS_DRIVER_PATCHLEVEL,
599};
600
601static struct drm_driver *driver;
602static struct pci_driver *pdriver;
603
604static struct pci_driver amdgpu_kms_pci_driver = {
605 .name = DRIVER_NAME,
606 .id_table = pciidlist,
607 .probe = amdgpu_pci_probe,
608 .remove = amdgpu_pci_remove,
609 .driver.pm = &amdgpu_pm_ops,
610};
611
d573de2d
RZ		 612
613
d38ceaf9
AD		 614static int __init amdgpu_init(void)
615{
257bf15a 616 amdgpu_sync_init();
d573de2d 617 amdgpu_fence_slab_init();
d38ceaf9
AD		 618 if (vgacon_text_force()) {
619 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
620 return -EINVAL;
621 }
d38ceaf9
AD		 622 DRM_INFO("amdgpu kernel modesetting enabled.\n");
623 driver = &kms_driver;
624 pdriver = &amdgpu_kms_pci_driver;
d38ceaf9
AD		 625 driver->num_ioctls = amdgpu_max_kms_ioctl;
626 amdgpu_register_atpx_handler();
d38ceaf9
AD		 627 /* let modprobe override vga console setting */
628 return drm_pci_init(driver, pdriver);
629}
630
631static void __exit amdgpu_exit(void)
632{
130e0371 633 amdgpu_amdkfd_fini();
d38ceaf9
AD		 634 drm_pci_exit(driver, pdriver);
635 amdgpu_unregister_atpx_handler();
257bf15a 636 amdgpu_sync_fini();
d573de2d 637 amdgpu_fence_slab_fini();
d38ceaf9
AD		 638}
639
640module_init(amdgpu_init);
641module_exit(amdgpu_exit);
642
643MODULE_AUTHOR(DRIVER_AUTHOR);
644MODULE_DESCRIPTION(DRIVER_DESC);
645MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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