Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <drm/drmP.h> | |
29 | #include "amdgpu.h" | |
30 | #include <drm/amdgpu_drm.h> | |
31 | #include "amdgpu_uvd.h" | |
32 | #include "amdgpu_vce.h" | |
33 | ||
34 | #include <linux/vga_switcheroo.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/pm_runtime.h> | |
130e0371 | 37 | #include "amdgpu_amdkfd.h" |
d38ceaf9 AD |
38 | |
39 | #if defined(CONFIG_VGA_SWITCHEROO) | |
40 | bool amdgpu_has_atpx(void); | |
41 | #else | |
42 | static inline bool amdgpu_has_atpx(void) { return false; } | |
43 | #endif | |
44 | ||
45 | /** | |
46 | * amdgpu_driver_unload_kms - Main unload function for KMS. | |
47 | * | |
48 | * @dev: drm dev pointer | |
49 | * | |
50 | * This is the main unload function for KMS (all asics). | |
51 | * Returns 0 on success. | |
52 | */ | |
53 | int amdgpu_driver_unload_kms(struct drm_device *dev) | |
54 | { | |
55 | struct amdgpu_device *adev = dev->dev_private; | |
56 | ||
57 | if (adev == NULL) | |
58 | return 0; | |
59 | ||
60 | if (adev->rmmio == NULL) | |
61 | goto done_free; | |
62 | ||
4a788547 LW |
63 | if (amdgpu_device_is_px(dev)) { |
64 | pm_runtime_get_sync(dev->dev); | |
6ce62d8b | 65 | pm_runtime_forbid(dev->dev); |
4a788547 | 66 | } |
d38ceaf9 | 67 | |
130e0371 OG |
68 | amdgpu_amdkfd_device_fini(adev); |
69 | ||
d38ceaf9 AD |
70 | amdgpu_acpi_fini(adev); |
71 | ||
72 | amdgpu_device_fini(adev); | |
73 | ||
74 | done_free: | |
75 | kfree(adev); | |
76 | dev->dev_private = NULL; | |
77 | return 0; | |
78 | } | |
79 | ||
80 | /** | |
81 | * amdgpu_driver_load_kms - Main load function for KMS. | |
82 | * | |
83 | * @dev: drm dev pointer | |
84 | * @flags: device flags | |
85 | * | |
86 | * This is the main load function for KMS (all asics). | |
87 | * Returns 0 on success, error on failure. | |
88 | */ | |
89 | int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) | |
90 | { | |
91 | struct amdgpu_device *adev; | |
92 | int r, acpi_status; | |
93 | ||
94 | adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); | |
95 | if (adev == NULL) { | |
96 | return -ENOMEM; | |
97 | } | |
98 | dev->dev_private = (void *)adev; | |
99 | ||
100 | if ((amdgpu_runtime_pm != 0) && | |
101 | amdgpu_has_atpx() && | |
2f7d10b3 JZ |
102 | ((flags & AMD_IS_APU) == 0)) |
103 | flags |= AMD_IS_PX; | |
d38ceaf9 AD |
104 | |
105 | /* amdgpu_device_init should report only fatal error | |
106 | * like memory allocation failure or iomapping failure, | |
107 | * or memory manager initialization failure, it must | |
108 | * properly initialize the GPU MC controller and permit | |
109 | * VRAM allocation | |
110 | */ | |
111 | r = amdgpu_device_init(adev, dev, dev->pdev, flags); | |
112 | if (r) { | |
113 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); | |
114 | goto out; | |
115 | } | |
116 | ||
117 | /* Call ACPI methods: require modeset init | |
118 | * but failure is not fatal | |
119 | */ | |
120 | if (!r) { | |
121 | acpi_status = amdgpu_acpi_init(adev); | |
122 | if (acpi_status) | |
123 | dev_dbg(&dev->pdev->dev, | |
124 | "Error during ACPI methods call\n"); | |
125 | } | |
126 | ||
130e0371 OG |
127 | amdgpu_amdkfd_load_interface(adev); |
128 | amdgpu_amdkfd_device_probe(adev); | |
129 | amdgpu_amdkfd_device_init(adev); | |
130 | ||
d38ceaf9 AD |
131 | if (amdgpu_device_is_px(dev)) { |
132 | pm_runtime_use_autosuspend(dev->dev); | |
133 | pm_runtime_set_autosuspend_delay(dev->dev, 5000); | |
134 | pm_runtime_set_active(dev->dev); | |
135 | pm_runtime_allow(dev->dev); | |
136 | pm_runtime_mark_last_busy(dev->dev); | |
137 | pm_runtime_put_autosuspend(dev->dev); | |
138 | } | |
139 | ||
140 | out: | |
c9c9bbd7 LW |
141 | if (r) { |
142 | /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ | |
143 | if (adev->rmmio && amdgpu_device_is_px(dev)) | |
144 | pm_runtime_put_noidle(dev->dev); | |
d38ceaf9 | 145 | amdgpu_driver_unload_kms(dev); |
c9c9bbd7 | 146 | } |
d38ceaf9 AD |
147 | |
148 | return r; | |
149 | } | |
150 | ||
000cab9a HR |
151 | static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, |
152 | struct drm_amdgpu_query_fw *query_fw, | |
153 | struct amdgpu_device *adev) | |
154 | { | |
155 | switch (query_fw->fw_type) { | |
156 | case AMDGPU_INFO_FW_VCE: | |
157 | fw_info->ver = adev->vce.fw_version; | |
158 | fw_info->feature = adev->vce.fb_version; | |
159 | break; | |
160 | case AMDGPU_INFO_FW_UVD: | |
161 | fw_info->ver = adev->uvd.fw_version; | |
162 | fw_info->feature = 0; | |
163 | break; | |
164 | case AMDGPU_INFO_FW_GMC: | |
165 | fw_info->ver = adev->mc.fw_version; | |
166 | fw_info->feature = 0; | |
167 | break; | |
168 | case AMDGPU_INFO_FW_GFX_ME: | |
169 | fw_info->ver = adev->gfx.me_fw_version; | |
170 | fw_info->feature = adev->gfx.me_feature_version; | |
171 | break; | |
172 | case AMDGPU_INFO_FW_GFX_PFP: | |
173 | fw_info->ver = adev->gfx.pfp_fw_version; | |
174 | fw_info->feature = adev->gfx.pfp_feature_version; | |
175 | break; | |
176 | case AMDGPU_INFO_FW_GFX_CE: | |
177 | fw_info->ver = adev->gfx.ce_fw_version; | |
178 | fw_info->feature = adev->gfx.ce_feature_version; | |
179 | break; | |
180 | case AMDGPU_INFO_FW_GFX_RLC: | |
181 | fw_info->ver = adev->gfx.rlc_fw_version; | |
182 | fw_info->feature = adev->gfx.rlc_feature_version; | |
183 | break; | |
184 | case AMDGPU_INFO_FW_GFX_MEC: | |
185 | if (query_fw->index == 0) { | |
186 | fw_info->ver = adev->gfx.mec_fw_version; | |
187 | fw_info->feature = adev->gfx.mec_feature_version; | |
188 | } else if (query_fw->index == 1) { | |
189 | fw_info->ver = adev->gfx.mec2_fw_version; | |
190 | fw_info->feature = adev->gfx.mec2_feature_version; | |
191 | } else | |
192 | return -EINVAL; | |
193 | break; | |
194 | case AMDGPU_INFO_FW_SMC: | |
195 | fw_info->ver = adev->pm.fw_version; | |
196 | fw_info->feature = 0; | |
197 | break; | |
198 | case AMDGPU_INFO_FW_SDMA: | |
199 | if (query_fw->index >= adev->sdma.num_instances) | |
200 | return -EINVAL; | |
201 | fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; | |
202 | fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; | |
203 | break; | |
204 | default: | |
205 | return -EINVAL; | |
206 | } | |
207 | return 0; | |
208 | } | |
209 | ||
d38ceaf9 AD |
210 | /* |
211 | * Userspace get information ioctl | |
212 | */ | |
213 | /** | |
214 | * amdgpu_info_ioctl - answer a device specific request. | |
215 | * | |
216 | * @adev: amdgpu device pointer | |
217 | * @data: request object | |
218 | * @filp: drm filp | |
219 | * | |
220 | * This function is used to pass device specific parameters to the userspace | |
221 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
222 | * etc. (all asics). | |
223 | * Returns 0 on success, -EINVAL on failure. | |
224 | */ | |
225 | static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |
226 | { | |
227 | struct amdgpu_device *adev = dev->dev_private; | |
228 | struct drm_amdgpu_info *info = data; | |
229 | struct amdgpu_mode_info *minfo = &adev->mode_info; | |
230 | void __user *out = (void __user *)(long)info->return_pointer; | |
231 | uint32_t size = info->return_size; | |
232 | struct drm_crtc *crtc; | |
233 | uint32_t ui32 = 0; | |
234 | uint64_t ui64 = 0; | |
235 | int i, found; | |
236 | ||
237 | if (!info->return_size || !info->return_pointer) | |
238 | return -EINVAL; | |
239 | ||
240 | switch (info->query) { | |
241 | case AMDGPU_INFO_ACCEL_WORKING: | |
242 | ui32 = adev->accel_working; | |
243 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
244 | case AMDGPU_INFO_CRTC_FROM_ID: | |
245 | for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { | |
246 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
247 | if (crtc && crtc->base.id == info->mode_crtc.id) { | |
248 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
249 | ui32 = amdgpu_crtc->crtc_id; | |
250 | found = 1; | |
251 | break; | |
252 | } | |
253 | } | |
254 | if (!found) { | |
255 | DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); | |
256 | return -EINVAL; | |
257 | } | |
258 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
259 | case AMDGPU_INFO_HW_IP_INFO: { | |
260 | struct drm_amdgpu_info_hw_ip ip = {}; | |
5fc3aeeb | 261 | enum amd_ip_block_type type; |
d38ceaf9 | 262 | uint32_t ring_mask = 0; |
71062f43 KW |
263 | uint32_t ib_start_alignment = 0; |
264 | uint32_t ib_size_alignment = 0; | |
d38ceaf9 AD |
265 | |
266 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) | |
267 | return -EINVAL; | |
268 | ||
269 | switch (info->query_hw_ip.type) { | |
270 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 271 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
272 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
273 | ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
274 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
275 | ib_size_alignment = 8; | |
d38ceaf9 AD |
276 | break; |
277 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 278 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
279 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
280 | ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); | |
71062f43 KW |
281 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
282 | ib_size_alignment = 8; | |
d38ceaf9 AD |
283 | break; |
284 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 285 | type = AMD_IP_BLOCK_TYPE_SDMA; |
c113ea1c AD |
286 | for (i = 0; i < adev->sdma.num_instances; i++) |
287 | ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); | |
71062f43 KW |
288 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
289 | ib_size_alignment = 1; | |
d38ceaf9 AD |
290 | break; |
291 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 292 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 | 293 | ring_mask = adev->uvd.ring.ready ? 1 : 0; |
71062f43 | 294 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
c4795ca6 | 295 | ib_size_alignment = 16; |
d38ceaf9 AD |
296 | break; |
297 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 298 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 AD |
299 | for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) |
300 | ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); | |
71062f43 | 301 | ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; |
a22f803c | 302 | ib_size_alignment = 1; |
d38ceaf9 AD |
303 | break; |
304 | default: | |
305 | return -EINVAL; | |
306 | } | |
307 | ||
308 | for (i = 0; i < adev->num_ip_blocks; i++) { | |
309 | if (adev->ip_blocks[i].type == type && | |
8faf0e08 | 310 | adev->ip_block_status[i].valid) { |
d38ceaf9 AD |
311 | ip.hw_ip_version_major = adev->ip_blocks[i].major; |
312 | ip.hw_ip_version_minor = adev->ip_blocks[i].minor; | |
313 | ip.capabilities_flags = 0; | |
314 | ip.available_rings = ring_mask; | |
71062f43 KW |
315 | ip.ib_start_alignment = ib_start_alignment; |
316 | ip.ib_size_alignment = ib_size_alignment; | |
d38ceaf9 AD |
317 | break; |
318 | } | |
319 | } | |
320 | return copy_to_user(out, &ip, | |
321 | min((size_t)size, sizeof(ip))) ? -EFAULT : 0; | |
322 | } | |
323 | case AMDGPU_INFO_HW_IP_COUNT: { | |
5fc3aeeb | 324 | enum amd_ip_block_type type; |
d38ceaf9 AD |
325 | uint32_t count = 0; |
326 | ||
327 | switch (info->query_hw_ip.type) { | |
328 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 329 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
330 | break; |
331 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 332 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
333 | break; |
334 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 335 | type = AMD_IP_BLOCK_TYPE_SDMA; |
d38ceaf9 AD |
336 | break; |
337 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 338 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 AD |
339 | break; |
340 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 341 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 AD |
342 | break; |
343 | default: | |
344 | return -EINVAL; | |
345 | } | |
346 | ||
347 | for (i = 0; i < adev->num_ip_blocks; i++) | |
348 | if (adev->ip_blocks[i].type == type && | |
8faf0e08 | 349 | adev->ip_block_status[i].valid && |
d38ceaf9 AD |
350 | count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) |
351 | count++; | |
352 | ||
353 | return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; | |
354 | } | |
355 | case AMDGPU_INFO_TIMESTAMP: | |
b95e31fd | 356 | ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); |
d38ceaf9 AD |
357 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
358 | case AMDGPU_INFO_FW_VERSION: { | |
359 | struct drm_amdgpu_info_firmware fw_info; | |
000cab9a | 360 | int ret; |
d38ceaf9 AD |
361 | |
362 | /* We only support one instance of each IP block right now. */ | |
363 | if (info->query_fw.ip_instance != 0) | |
364 | return -EINVAL; | |
365 | ||
000cab9a HR |
366 | ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); |
367 | if (ret) | |
368 | return ret; | |
369 | ||
d38ceaf9 AD |
370 | return copy_to_user(out, &fw_info, |
371 | min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; | |
372 | } | |
373 | case AMDGPU_INFO_NUM_BYTES_MOVED: | |
374 | ui64 = atomic64_read(&adev->num_bytes_moved); | |
375 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
83a59b63 MO |
376 | case AMDGPU_INFO_NUM_EVICTIONS: |
377 | ui64 = atomic64_read(&adev->num_evictions); | |
378 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
d38ceaf9 AD |
379 | case AMDGPU_INFO_VRAM_USAGE: |
380 | ui64 = atomic64_read(&adev->vram_usage); | |
381 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
382 | case AMDGPU_INFO_VIS_VRAM_USAGE: | |
383 | ui64 = atomic64_read(&adev->vram_vis_usage); | |
384 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
385 | case AMDGPU_INFO_GTT_USAGE: | |
386 | ui64 = atomic64_read(&adev->gtt_usage); | |
387 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
388 | case AMDGPU_INFO_GDS_CONFIG: { | |
389 | struct drm_amdgpu_info_gds gds_info; | |
390 | ||
c92b90cc | 391 | memset(&gds_info, 0, sizeof(gds_info)); |
d38ceaf9 AD |
392 | gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; |
393 | gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; | |
394 | gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; | |
395 | gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; | |
396 | gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; | |
397 | gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; | |
398 | gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; | |
399 | return copy_to_user(out, &gds_info, | |
400 | min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; | |
401 | } | |
402 | case AMDGPU_INFO_VRAM_GTT: { | |
403 | struct drm_amdgpu_info_vram_gtt vram_gtt; | |
404 | ||
405 | vram_gtt.vram_size = adev->mc.real_vram_size; | |
7c0ecda1 | 406 | vram_gtt.vram_size -= adev->vram_pin_size; |
d38ceaf9 | 407 | vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; |
e131b914 | 408 | vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); |
d38ceaf9 AD |
409 | vram_gtt.gtt_size = adev->mc.gtt_size; |
410 | vram_gtt.gtt_size -= adev->gart_pin_size; | |
411 | return copy_to_user(out, &vram_gtt, | |
412 | min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; | |
413 | } | |
414 | case AMDGPU_INFO_READ_MMR_REG: { | |
0d2edd37 | 415 | unsigned n, alloc_size; |
d38ceaf9 AD |
416 | uint32_t *regs; |
417 | unsigned se_num = (info->read_mmr_reg.instance >> | |
418 | AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & | |
419 | AMDGPU_INFO_MMR_SE_INDEX_MASK; | |
420 | unsigned sh_num = (info->read_mmr_reg.instance >> | |
421 | AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & | |
422 | AMDGPU_INFO_MMR_SH_INDEX_MASK; | |
423 | ||
424 | /* set full masks if the userspace set all bits | |
425 | * in the bitfields */ | |
426 | if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) | |
427 | se_num = 0xffffffff; | |
428 | if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) | |
429 | sh_num = 0xffffffff; | |
430 | ||
0d2edd37 | 431 | regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); |
d38ceaf9 AD |
432 | if (!regs) |
433 | return -ENOMEM; | |
0d2edd37 | 434 | alloc_size = info->read_mmr_reg.count * sizeof(*regs); |
d38ceaf9 AD |
435 | |
436 | for (i = 0; i < info->read_mmr_reg.count; i++) | |
437 | if (amdgpu_asic_read_register(adev, se_num, sh_num, | |
438 | info->read_mmr_reg.dword_offset + i, | |
439 | ®s[i])) { | |
440 | DRM_DEBUG_KMS("unallowed offset %#x\n", | |
441 | info->read_mmr_reg.dword_offset + i); | |
442 | kfree(regs); | |
443 | return -EFAULT; | |
444 | } | |
445 | n = copy_to_user(out, regs, min(size, alloc_size)); | |
446 | kfree(regs); | |
447 | return n ? -EFAULT : 0; | |
448 | } | |
449 | case AMDGPU_INFO_DEV_INFO: { | |
c193fa91 | 450 | struct drm_amdgpu_info_device dev_info = {}; |
d38ceaf9 AD |
451 | |
452 | dev_info.device_id = dev->pdev->device; | |
453 | dev_info.chip_rev = adev->rev_id; | |
454 | dev_info.external_rev = adev->external_rev_id; | |
455 | dev_info.pci_rev = dev->pdev->revision; | |
456 | dev_info.family = adev->family; | |
457 | dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; | |
458 | dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
459 | /* return all clocks in KHz */ | |
460 | dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; | |
32bf7106 | 461 | if (adev->pm.dpm_enabled) { |
d38ceaf9 AD |
462 | dev_info.max_engine_clock = |
463 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; | |
32bf7106 KW |
464 | dev_info.max_memory_clock = |
465 | adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; | |
466 | } else { | |
d38ceaf9 | 467 | dev_info.max_engine_clock = adev->pm.default_sclk * 10; |
32bf7106 KW |
468 | dev_info.max_memory_clock = adev->pm.default_mclk * 10; |
469 | } | |
d38ceaf9 | 470 | dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; |
0b10029d AD |
471 | dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * |
472 | adev->gfx.config.max_shader_engines; | |
d38ceaf9 AD |
473 | dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; |
474 | dev_info._pad = 0; | |
475 | dev_info.ids_flags = 0; | |
2f7d10b3 | 476 | if (adev->flags & AMD_IS_APU) |
d38ceaf9 AD |
477 | dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; |
478 | dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; | |
02b70c8c | 479 | dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; |
c548b345 | 480 | dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); |
d38ceaf9 AD |
481 | dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * |
482 | AMDGPU_GPU_PAGE_SIZE; | |
483 | dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; | |
484 | ||
7dae69a2 AD |
485 | dev_info.cu_active_number = adev->gfx.cu_info.number; |
486 | dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; | |
a101a899 | 487 | dev_info.ce_ram_size = adev->gfx.ce_ram_size; |
7dae69a2 AD |
488 | memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], |
489 | sizeof(adev->gfx.cu_info.bitmap)); | |
81c59f54 KW |
490 | dev_info.vram_type = adev->mc.vram_type; |
491 | dev_info.vram_bit_width = adev->mc.vram_width; | |
fa92754e | 492 | dev_info.vce_harvest_config = adev->vce.harvest_config; |
d38ceaf9 AD |
493 | |
494 | return copy_to_user(out, &dev_info, | |
495 | min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; | |
496 | } | |
497 | default: | |
498 | DRM_DEBUG_KMS("Invalid request %d\n", info->query); | |
499 | return -EINVAL; | |
500 | } | |
501 | return 0; | |
502 | } | |
503 | ||
504 | ||
505 | /* | |
506 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
507 | */ | |
508 | /** | |
8b7530b1 | 509 | * amdgpu_driver_lastclose_kms - drm callback for last close |
d38ceaf9 AD |
510 | * |
511 | * @dev: drm dev pointer | |
512 | * | |
1694467b | 513 | * Switch vga_switcheroo state after last close (all asics). |
d38ceaf9 AD |
514 | */ |
515 | void amdgpu_driver_lastclose_kms(struct drm_device *dev) | |
516 | { | |
8b7530b1 AD |
517 | struct amdgpu_device *adev = dev->dev_private; |
518 | ||
519 | amdgpu_fbdev_restore_mode(adev); | |
d38ceaf9 AD |
520 | vga_switcheroo_process_delayed_switch(); |
521 | } | |
522 | ||
523 | /** | |
524 | * amdgpu_driver_open_kms - drm callback for open | |
525 | * | |
526 | * @dev: drm dev pointer | |
527 | * @file_priv: drm file | |
528 | * | |
529 | * On device open, init vm on cayman+ (all asics). | |
530 | * Returns 0 on success, error on failure. | |
531 | */ | |
532 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
533 | { | |
534 | struct amdgpu_device *adev = dev->dev_private; | |
535 | struct amdgpu_fpriv *fpriv; | |
536 | int r; | |
537 | ||
538 | file_priv->driver_priv = NULL; | |
539 | ||
540 | r = pm_runtime_get_sync(dev->dev); | |
541 | if (r < 0) | |
542 | return r; | |
543 | ||
544 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
545 | if (unlikely(!fpriv)) | |
546 | return -ENOMEM; | |
547 | ||
548 | r = amdgpu_vm_init(adev, &fpriv->vm); | |
549 | if (r) | |
550 | goto error_free; | |
551 | ||
552 | mutex_init(&fpriv->bo_list_lock); | |
553 | idr_init(&fpriv->bo_list_handles); | |
554 | ||
efd4ccb5 | 555 | amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); |
d38ceaf9 AD |
556 | |
557 | file_priv->driver_priv = fpriv; | |
558 | ||
559 | pm_runtime_mark_last_busy(dev->dev); | |
560 | pm_runtime_put_autosuspend(dev->dev); | |
561 | return 0; | |
562 | ||
563 | error_free: | |
564 | kfree(fpriv); | |
565 | ||
566 | return r; | |
567 | } | |
568 | ||
569 | /** | |
570 | * amdgpu_driver_postclose_kms - drm callback for post close | |
571 | * | |
572 | * @dev: drm dev pointer | |
573 | * @file_priv: drm file | |
574 | * | |
575 | * On device post close, tear down vm on cayman+ (all asics). | |
576 | */ | |
577 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
578 | struct drm_file *file_priv) | |
579 | { | |
580 | struct amdgpu_device *adev = dev->dev_private; | |
581 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
582 | struct amdgpu_bo_list *list; | |
583 | int handle; | |
584 | ||
585 | if (!fpriv) | |
586 | return; | |
587 | ||
02537d63 CK |
588 | amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); |
589 | ||
cd437e37 LL |
590 | amdgpu_uvd_free_handles(adev, file_priv); |
591 | amdgpu_vce_free_handles(adev, file_priv); | |
592 | ||
d38ceaf9 AD |
593 | amdgpu_vm_fini(adev, &fpriv->vm); |
594 | ||
595 | idr_for_each_entry(&fpriv->bo_list_handles, list, handle) | |
596 | amdgpu_bo_list_free(list); | |
597 | ||
598 | idr_destroy(&fpriv->bo_list_handles); | |
599 | mutex_destroy(&fpriv->bo_list_lock); | |
600 | ||
d38ceaf9 AD |
601 | kfree(fpriv); |
602 | file_priv->driver_priv = NULL; | |
603 | } | |
604 | ||
605 | /** | |
606 | * amdgpu_driver_preclose_kms - drm callback for pre close | |
607 | * | |
608 | * @dev: drm dev pointer | |
609 | * @file_priv: drm file | |
610 | * | |
611 | * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx | |
612 | * (all asics). | |
613 | */ | |
614 | void amdgpu_driver_preclose_kms(struct drm_device *dev, | |
615 | struct drm_file *file_priv) | |
616 | { | |
d38ceaf9 AD |
617 | } |
618 | ||
619 | /* | |
620 | * VBlank related functions. | |
621 | */ | |
622 | /** | |
623 | * amdgpu_get_vblank_counter_kms - get frame count | |
624 | * | |
625 | * @dev: drm dev pointer | |
88e72717 | 626 | * @pipe: crtc to get the frame count from |
d38ceaf9 AD |
627 | * |
628 | * Gets the frame count on the requested crtc (all asics). | |
629 | * Returns frame count on success, -EINVAL on failure. | |
630 | */ | |
88e72717 | 631 | u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
632 | { |
633 | struct amdgpu_device *adev = dev->dev_private; | |
8e36f9d3 AD |
634 | int vpos, hpos, stat; |
635 | u32 count; | |
d38ceaf9 | 636 | |
88e72717 TR |
637 | if (pipe >= adev->mode_info.num_crtc) { |
638 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
d38ceaf9 AD |
639 | return -EINVAL; |
640 | } | |
641 | ||
8e36f9d3 AD |
642 | /* The hw increments its frame counter at start of vsync, not at start |
643 | * of vblank, as is required by DRM core vblank counter handling. | |
644 | * Cook the hw count here to make it appear to the caller as if it | |
645 | * incremented at start of vblank. We measure distance to start of | |
646 | * vblank in vpos. vpos therefore will be >= 0 between start of vblank | |
647 | * and start of vsync, so vpos >= 0 means to bump the hw frame counter | |
648 | * result by 1 to give the proper appearance to caller. | |
649 | */ | |
650 | if (adev->mode_info.crtcs[pipe]) { | |
651 | /* Repeat readout if needed to provide stable result if | |
652 | * we cross start of vsync during the queries. | |
653 | */ | |
654 | do { | |
655 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
656 | /* Ask amdgpu_get_crtc_scanoutpos to return vpos as | |
657 | * distance to start of vblank, instead of regular | |
658 | * vertical scanout pos. | |
659 | */ | |
660 | stat = amdgpu_get_crtc_scanoutpos( | |
661 | dev, pipe, GET_DISTANCE_TO_VBLANKSTART, | |
662 | &vpos, &hpos, NULL, NULL, | |
663 | &adev->mode_info.crtcs[pipe]->base.hwmode); | |
664 | } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); | |
665 | ||
666 | if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != | |
667 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { | |
668 | DRM_DEBUG_VBL("Query failed! stat %d\n", stat); | |
669 | } else { | |
670 | DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", | |
671 | pipe, vpos); | |
672 | ||
673 | /* Bump counter if we are at >= leading edge of vblank, | |
674 | * but before vsync where vpos would turn negative and | |
675 | * the hw counter really increments. | |
676 | */ | |
677 | if (vpos >= 0) | |
678 | count++; | |
679 | } | |
680 | } else { | |
681 | /* Fallback to use value as is. */ | |
682 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
683 | DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); | |
684 | } | |
685 | ||
686 | return count; | |
d38ceaf9 AD |
687 | } |
688 | ||
689 | /** | |
690 | * amdgpu_enable_vblank_kms - enable vblank interrupt | |
691 | * | |
692 | * @dev: drm dev pointer | |
88e72717 | 693 | * @pipe: crtc to enable vblank interrupt for |
d38ceaf9 AD |
694 | * |
695 | * Enable the interrupt on the requested crtc (all asics). | |
696 | * Returns 0 on success, -EINVAL on failure. | |
697 | */ | |
88e72717 | 698 | int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
699 | { |
700 | struct amdgpu_device *adev = dev->dev_private; | |
88e72717 | 701 | int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
702 | |
703 | return amdgpu_irq_get(adev, &adev->crtc_irq, idx); | |
704 | } | |
705 | ||
706 | /** | |
707 | * amdgpu_disable_vblank_kms - disable vblank interrupt | |
708 | * | |
709 | * @dev: drm dev pointer | |
88e72717 | 710 | * @pipe: crtc to disable vblank interrupt for |
d38ceaf9 AD |
711 | * |
712 | * Disable the interrupt on the requested crtc (all asics). | |
713 | */ | |
88e72717 | 714 | void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) |
d38ceaf9 AD |
715 | { |
716 | struct amdgpu_device *adev = dev->dev_private; | |
88e72717 | 717 | int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
718 | |
719 | amdgpu_irq_put(adev, &adev->crtc_irq, idx); | |
720 | } | |
721 | ||
722 | /** | |
723 | * amdgpu_get_vblank_timestamp_kms - get vblank timestamp | |
724 | * | |
725 | * @dev: drm dev pointer | |
726 | * @crtc: crtc to get the timestamp for | |
727 | * @max_error: max error | |
728 | * @vblank_time: time value | |
729 | * @flags: flags passed to the driver | |
730 | * | |
731 | * Gets the timestamp on the requested crtc based on the | |
732 | * scanout position. (all asics). | |
733 | * Returns postive status flags on success, negative error on failure. | |
734 | */ | |
88e72717 | 735 | int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, |
d38ceaf9 AD |
736 | int *max_error, |
737 | struct timeval *vblank_time, | |
738 | unsigned flags) | |
739 | { | |
88e72717 | 740 | struct drm_crtc *crtc; |
d38ceaf9 AD |
741 | struct amdgpu_device *adev = dev->dev_private; |
742 | ||
88e72717 TR |
743 | if (pipe >= dev->num_crtcs) { |
744 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
d38ceaf9 AD |
745 | return -EINVAL; |
746 | } | |
747 | ||
748 | /* Get associated drm_crtc: */ | |
88e72717 | 749 | crtc = &adev->mode_info.crtcs[pipe]->base; |
9ddf940f HW |
750 | if (!crtc) { |
751 | /* This can occur on driver load if some component fails to | |
752 | * initialize completely and driver is unloaded */ | |
753 | DRM_ERROR("Uninitialized crtc %d\n", pipe); | |
754 | return -EINVAL; | |
755 | } | |
d38ceaf9 AD |
756 | |
757 | /* Helper routine in DRM core does all the work: */ | |
88e72717 | 758 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
d38ceaf9 | 759 | vblank_time, flags, |
88e72717 | 760 | &crtc->hwmode); |
d38ceaf9 AD |
761 | } |
762 | ||
763 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { | |
f8c47144 DV |
764 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
765 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
766 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
d38ceaf9 | 767 | /* KMS */ |
f8c47144 DV |
768 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), |
769 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
770 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
771 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
772 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
773 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
774 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
775 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
776 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), | |
d38ceaf9 | 777 | }; |
f498d9ed | 778 | const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); |
50ab2533 HR |
779 | |
780 | /* | |
781 | * Debugfs info | |
782 | */ | |
783 | #if defined(CONFIG_DEBUG_FS) | |
784 | ||
785 | static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) | |
786 | { | |
787 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
788 | struct drm_device *dev = node->minor->dev; | |
789 | struct amdgpu_device *adev = dev->dev_private; | |
790 | struct drm_amdgpu_info_firmware fw_info; | |
791 | struct drm_amdgpu_query_fw query_fw; | |
792 | int ret, i; | |
793 | ||
794 | /* VCE */ | |
795 | query_fw.fw_type = AMDGPU_INFO_FW_VCE; | |
796 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
797 | if (ret) | |
798 | return ret; | |
799 | seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", | |
800 | fw_info.feature, fw_info.ver); | |
801 | ||
802 | /* UVD */ | |
803 | query_fw.fw_type = AMDGPU_INFO_FW_UVD; | |
804 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
805 | if (ret) | |
806 | return ret; | |
807 | seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", | |
808 | fw_info.feature, fw_info.ver); | |
809 | ||
810 | /* GMC */ | |
811 | query_fw.fw_type = AMDGPU_INFO_FW_GMC; | |
812 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
813 | if (ret) | |
814 | return ret; | |
815 | seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", | |
816 | fw_info.feature, fw_info.ver); | |
817 | ||
818 | /* ME */ | |
819 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; | |
820 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
821 | if (ret) | |
822 | return ret; | |
823 | seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", | |
824 | fw_info.feature, fw_info.ver); | |
825 | ||
826 | /* PFP */ | |
827 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; | |
828 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
829 | if (ret) | |
830 | return ret; | |
831 | seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", | |
832 | fw_info.feature, fw_info.ver); | |
833 | ||
834 | /* CE */ | |
835 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; | |
836 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
837 | if (ret) | |
838 | return ret; | |
839 | seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", | |
840 | fw_info.feature, fw_info.ver); | |
841 | ||
842 | /* RLC */ | |
843 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; | |
844 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
845 | if (ret) | |
846 | return ret; | |
847 | seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", | |
848 | fw_info.feature, fw_info.ver); | |
849 | ||
850 | /* MEC */ | |
851 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; | |
852 | query_fw.index = 0; | |
853 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
854 | if (ret) | |
855 | return ret; | |
856 | seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", | |
857 | fw_info.feature, fw_info.ver); | |
858 | ||
859 | /* MEC2 */ | |
860 | if (adev->asic_type == CHIP_KAVERI || | |
861 | (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { | |
862 | query_fw.index = 1; | |
863 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
864 | if (ret) | |
865 | return ret; | |
866 | seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", | |
867 | fw_info.feature, fw_info.ver); | |
868 | } | |
869 | ||
870 | /* SMC */ | |
871 | query_fw.fw_type = AMDGPU_INFO_FW_SMC; | |
872 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
873 | if (ret) | |
874 | return ret; | |
875 | seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", | |
876 | fw_info.feature, fw_info.ver); | |
877 | ||
878 | /* SDMA */ | |
879 | query_fw.fw_type = AMDGPU_INFO_FW_SDMA; | |
880 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
881 | query_fw.index = i; | |
882 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
883 | if (ret) | |
884 | return ret; | |
885 | seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", | |
886 | i, fw_info.feature, fw_info.ver); | |
887 | } | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | static const struct drm_info_list amdgpu_firmware_info_list[] = { | |
893 | {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, | |
894 | }; | |
895 | #endif | |
896 | ||
897 | int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) | |
898 | { | |
899 | #if defined(CONFIG_DEBUG_FS) | |
900 | return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, | |
901 | ARRAY_SIZE(amdgpu_firmware_info_list)); | |
902 | #else | |
903 | return 0; | |
904 | #endif | |
905 | } |