[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_mode.h

/*
 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
 *                VA Linux Systems Inc., Fremont, California.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Original Authors:
 *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
 *
 * Kernel port Author: Dave Airlie
 */

#ifndef AMDGPU_MODE_H
#define AMDGPU_MODE_H

#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_fixed.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_plane_helper.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/hrtimer.h>
#include "amdgpu_irq.h"

struct amdgpu_bo;
struct amdgpu_device;
struct amdgpu_encoder;
struct amdgpu_router;
struct amdgpu_hpd;

#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)

#define AMDGPU_MAX_HPD_PINS 6
#define AMDGPU_MAX_CRTCS 6
#define AMDGPU_MAX_AFMT_BLOCKS 9

enum amdgpu_rmx_type {
	RMX_OFF,
	RMX_FULL,
	RMX_CENTER,
	RMX_ASPECT
};

enum amdgpu_underscan_type {
	UNDERSCAN_OFF,
	UNDERSCAN_ON,
	UNDERSCAN_AUTO,
};

#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10

enum amdgpu_hpd_id {
	AMDGPU_HPD_1 = 0,
	AMDGPU_HPD_2,
	AMDGPU_HPD_3,
	AMDGPU_HPD_4,
	AMDGPU_HPD_5,
	AMDGPU_HPD_6,
	AMDGPU_HPD_LAST,
	AMDGPU_HPD_NONE = 0xff,
};

enum amdgpu_crtc_irq {
	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	AMDGPU_CRTC_IRQ_VBLANK2,
	AMDGPU_CRTC_IRQ_VBLANK3,
	AMDGPU_CRTC_IRQ_VBLANK4,
	AMDGPU_CRTC_IRQ_VBLANK5,
	AMDGPU_CRTC_IRQ_VBLANK6,
	AMDGPU_CRTC_IRQ_VLINE1,
	AMDGPU_CRTC_IRQ_VLINE2,
	AMDGPU_CRTC_IRQ_VLINE3,
	AMDGPU_CRTC_IRQ_VLINE4,
	AMDGPU_CRTC_IRQ_VLINE5,
	AMDGPU_CRTC_IRQ_VLINE6,
	AMDGPU_CRTC_IRQ_LAST,
	AMDGPU_CRTC_IRQ_NONE = 0xff
};

enum amdgpu_pageflip_irq {
	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	AMDGPU_PAGEFLIP_IRQ_D2,
	AMDGPU_PAGEFLIP_IRQ_D3,
	AMDGPU_PAGEFLIP_IRQ_D4,
	AMDGPU_PAGEFLIP_IRQ_D5,
	AMDGPU_PAGEFLIP_IRQ_D6,
	AMDGPU_PAGEFLIP_IRQ_LAST,
	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
};

enum amdgpu_flip_status {
	AMDGPU_FLIP_NONE,
	AMDGPU_FLIP_PENDING,
	AMDGPU_FLIP_SUBMITTED
};

#define AMDGPU_MAX_I2C_BUS 16

/* amdgpu gpio-based i2c
 * 1. "mask" reg and bits
 *    grabs the gpio pins for software use
 *    0=not held  1=held
 * 2. "a" reg and bits
 *    output pin value
 *    0=low 1=high
 * 3. "en" reg and bits
 *    sets the pin direction
 *    0=input 1=output
 * 4. "y" reg and bits
 *    input pin value
 *    0=low 1=high
 */
struct amdgpu_i2c_bus_rec {
	bool valid;
	/* id used by atom */
	uint8_t i2c_id;
	/* id used by atom */
	enum amdgpu_hpd_id hpd;
	/* can be used with hw i2c engine */
	bool hw_capable;
	/* uses multi-media i2c engine */
	bool mm_i2c;
	/* regs and bits */
	uint32_t mask_clk_reg;
	uint32_t mask_data_reg;
	uint32_t a_clk_reg;
	uint32_t a_data_reg;
	uint32_t en_clk_reg;
	uint32_t en_data_reg;
	uint32_t y_clk_reg;
	uint32_t y_data_reg;
	uint32_t mask_clk_mask;
	uint32_t mask_data_mask;
	uint32_t a_clk_mask;
	uint32_t a_data_mask;
	uint32_t en_clk_mask;
	uint32_t en_data_mask;
	uint32_t y_clk_mask;
	uint32_t y_data_mask;
};

#define AMDGPU_MAX_BIOS_CONNECTOR 16

/* pll flags */
#define AMDGPU_PLL_USE_BIOS_DIVS        (1 << 0)
#define AMDGPU_PLL_NO_ODD_POST_DIV      (1 << 1)
#define AMDGPU_PLL_USE_REF_DIV          (1 << 2)
#define AMDGPU_PLL_LEGACY               (1 << 3)
#define AMDGPU_PLL_PREFER_LOW_REF_DIV   (1 << 4)
#define AMDGPU_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
#define AMDGPU_PLL_PREFER_LOW_FB_DIV    (1 << 6)
#define AMDGPU_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
#define AMDGPU_PLL_PREFER_LOW_POST_DIV  (1 << 8)
#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
#define AMDGPU_PLL_USE_FRAC_FB_DIV      (1 << 10)
#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
#define AMDGPU_PLL_USE_POST_DIV         (1 << 12)
#define AMDGPU_PLL_IS_LCD               (1 << 13)
#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)

struct amdgpu_pll {
	/* reference frequency */
	uint32_t reference_freq;

	/* fixed dividers */
	uint32_t reference_div;
	uint32_t post_div;

	/* pll in/out limits */
	uint32_t pll_in_min;
	uint32_t pll_in_max;
	uint32_t pll_out_min;
	uint32_t pll_out_max;
	uint32_t lcd_pll_out_min;
	uint32_t lcd_pll_out_max;
	uint32_t best_vco;

	/* divider limits */
	uint32_t min_ref_div;
	uint32_t max_ref_div;
	uint32_t min_post_div;
	uint32_t max_post_div;
	uint32_t min_feedback_div;
	uint32_t max_feedback_div;
	uint32_t min_frac_feedback_div;
	uint32_t max_frac_feedback_div;

	/* flags for the current clock */
	uint32_t flags;

	/* pll id */
	uint32_t id;
};

struct amdgpu_i2c_chan {
	struct i2c_adapter adapter;
	struct drm_device *dev;
	struct i2c_algo_bit_data bit;
	struct amdgpu_i2c_bus_rec rec;
	struct drm_dp_aux aux;
	bool has_aux;
	struct mutex mutex;
};

struct amdgpu_fbdev;

struct amdgpu_afmt {
	bool enabled;
	int offset;
	bool last_buffer_filled_status;
	int id;
	struct amdgpu_audio_pin *pin;
};

/*
 * Audio
 */
struct amdgpu_audio_pin {
	int			channels;
	int			rate;
	int			bits_per_sample;
	u8			status_bits;
	u8			category_code;
	u32			offset;
	bool			connected;
	u32			id;
};

struct amdgpu_audio {
	bool enabled;
	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
	int num_pins;
};

struct amdgpu_mode_mc_save {
	u32 vga_render_control;
	u32 vga_hdp_control;
	bool crtc_enabled[AMDGPU_MAX_CRTCS];
};

struct amdgpu_display_funcs {
	/* vga render */
	void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
	/* display watermarks */
	void (*bandwidth_update)(struct amdgpu_device *adev);
	/* get frame count */
	u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
	/* wait for vblank */
	void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
	/* is dce hung */
	bool (*is_display_hung)(struct amdgpu_device *adev);
	/* set backlight level */
	void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
				    u8 level);
	/* get backlight level */
	u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
	/* hotplug detect */
	bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
	void (*hpd_set_polarity)(struct amdgpu_device *adev,
				 enum amdgpu_hpd_id hpd);
	u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
	/* pageflipping */
	void (*page_flip)(struct amdgpu_device *adev,
			  int crtc_id, u64 crtc_base, bool async);
	int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
					u32 *vbl, u32 *position);
	/* display topology setup */
	void (*add_encoder)(struct amdgpu_device *adev,
			    uint32_t encoder_enum,
			    uint32_t supported_device,
			    u16 caps);
	void (*add_connector)(struct amdgpu_device *adev,
			      uint32_t connector_id,
			      uint32_t supported_device,
			      int connector_type,
			      struct amdgpu_i2c_bus_rec *i2c_bus,
			      uint16_t connector_object_id,
			      struct amdgpu_hpd *hpd,
			      struct amdgpu_router *router);
	void (*stop_mc_access)(struct amdgpu_device *adev,
			       struct amdgpu_mode_mc_save *save);
	void (*resume_mc_access)(struct amdgpu_device *adev,
				 struct amdgpu_mode_mc_save *save);
};

struct amdgpu_mode_info {
	struct atom_context *atom_context;
	struct card_info *atom_card_info;
	bool mode_config_initialized;
	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
	/* DVI-I properties */
	struct drm_property *coherent_mode_property;
	/* DAC enable load detect */
	struct drm_property *load_detect_property;
	/* underscan */
	struct drm_property *underscan_property;
	struct drm_property *underscan_hborder_property;
	struct drm_property *underscan_vborder_property;
	/* audio */
	struct drm_property *audio_property;
	/* FMT dithering */
	struct drm_property *dither_property;
	/* hardcoded DFP edid from BIOS */
	struct edid *bios_hardcoded_edid;
	int bios_hardcoded_edid_size;

	/* pointer to fbdev info structure */
	struct amdgpu_fbdev *rfbdev;
	/* firmware flags */
	u16 firmware_flags;
	/* pointer to backlight encoder */
	struct amdgpu_encoder *bl_encoder;
	struct amdgpu_audio	audio; /* audio stuff */
	int			num_crtc; /* number of crtcs */
	int			num_hpd; /* number of hpd pins */
	int			num_dig; /* number of dig blocks */
	int			disp_priority;
	const struct amdgpu_display_funcs *funcs;
	struct hrtimer vblank_timer;
	enum amdgpu_interrupt_state vsync_timer_enabled;
};

#define AMDGPU_MAX_BL_LEVEL 0xFF

#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

struct amdgpu_backlight_privdata {
	struct amdgpu_encoder *encoder;
	uint8_t negative;
};

#endif

struct amdgpu_atom_ss {
	uint16_t percentage;
	uint16_t percentage_divider;
	uint8_t type;
	uint16_t step;
	uint8_t delay;
	uint8_t range;
	uint8_t refdiv;
	/* asic_ss */
	uint16_t rate;
	uint16_t amount;
};

struct amdgpu_crtc {
	struct drm_crtc base;
	int crtc_id;
	u16 lut_r[256], lut_g[256], lut_b[256];
	bool enabled;
	bool can_tile;
	uint32_t crtc_offset;
	struct drm_gem_object *cursor_bo;
	uint64_t cursor_addr;
	int cursor_x;
	int cursor_y;
	int cursor_hot_x;
	int cursor_hot_y;
	int cursor_width;
	int cursor_height;
	int max_cursor_width;
	int max_cursor_height;
	enum amdgpu_rmx_type rmx_type;
	u8 h_border;
	u8 v_border;
	fixed20_12 vsc;
	fixed20_12 hsc;
	struct drm_display_mode native_mode;
	u32 pll_id;
	/* page flipping */
	struct amdgpu_flip_work *pflip_works;
	enum amdgpu_flip_status pflip_status;
	int deferred_flip_completion;
	/* pll sharing */
	struct amdgpu_atom_ss ss;
	bool ss_enabled;
	u32 adjusted_clock;
	int bpc;
	u32 pll_reference_div;
	u32 pll_post_div;
	u32 pll_flags;
	struct drm_encoder *encoder;
	struct drm_connector *connector;
	/* for dpm */
	u32 line_time;
	u32 wm_low;
	u32 wm_high;
	u32 lb_vblank_lead_lines;
	struct drm_display_mode hw_mode;
};

struct amdgpu_encoder_atom_dig {
	bool linkb;
	/* atom dig */
	bool coherent_mode;
	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	/* atom lvds/edp */
	uint32_t lcd_misc;
	uint16_t panel_pwr_delay;
	uint32_t lcd_ss_id;
	/* panel mode */
	struct drm_display_mode native_mode;
	struct backlight_device *bl_dev;
	int dpms_mode;
	uint8_t backlight_level;
	int panel_mode;
	struct amdgpu_afmt *afmt;
};

struct amdgpu_encoder {
	struct drm_encoder base;
	uint32_t encoder_enum;
	uint32_t encoder_id;
	uint32_t devices;
	uint32_t active_device;
	uint32_t flags;
	uint32_t pixel_clock;
	enum amdgpu_rmx_type rmx_type;
	enum amdgpu_underscan_type underscan_type;
	uint32_t underscan_hborder;
	uint32_t underscan_vborder;
	struct drm_display_mode native_mode;
	void *enc_priv;
	int audio_polling_active;
	bool is_ext_encoder;
	u16 caps;
};

struct amdgpu_connector_atom_dig {
	/* displayport */
	u8 dpcd[DP_RECEIVER_CAP_SIZE];
	u8 dp_sink_type;
	int dp_clock;
	int dp_lane_count;
	bool edp_on;
};

struct amdgpu_gpio_rec {
	bool valid;
	u8 id;
	u32 reg;
	u32 mask;
	u32 shift;
};

struct amdgpu_hpd {
	enum amdgpu_hpd_id hpd;
	u8 plugged_state;
	struct amdgpu_gpio_rec gpio;
};

struct amdgpu_router {
	u32 router_id;
	struct amdgpu_i2c_bus_rec i2c_info;
	u8 i2c_addr;
	/* i2c mux */
	bool ddc_valid;
	u8 ddc_mux_type;
	u8 ddc_mux_control_pin;
	u8 ddc_mux_state;
	/* clock/data mux */
	bool cd_valid;
	u8 cd_mux_type;
	u8 cd_mux_control_pin;
	u8 cd_mux_state;
};

enum amdgpu_connector_audio {
	AMDGPU_AUDIO_DISABLE = 0,
	AMDGPU_AUDIO_ENABLE = 1,
	AMDGPU_AUDIO_AUTO = 2
};

enum amdgpu_connector_dither {
	AMDGPU_FMT_DITHER_DISABLE = 0,
	AMDGPU_FMT_DITHER_ENABLE = 1,
};

struct amdgpu_connector {
	struct drm_connector base;
	uint32_t connector_id;
	uint32_t devices;
	struct amdgpu_i2c_chan *ddc_bus;
	/* some systems have an hdmi and vga port with a shared ddc line */
	bool shared_ddc;
	bool use_digital;
	/* we need to mind the EDID between detect
	   and get modes due to analog/digital/tvencoder */
	struct edid *edid;
	void *con_priv;
	bool dac_load_detect;
	bool detected_by_load; /* if the connection status was determined by load */
	uint16_t connector_object_id;
	struct amdgpu_hpd hpd;
	struct amdgpu_router router;
	struct amdgpu_i2c_chan *router_bus;
	enum amdgpu_connector_audio audio;
	enum amdgpu_connector_dither dither;
	unsigned pixelclock_for_modeset;
};

struct amdgpu_framebuffer {
	struct drm_framebuffer base;
	struct drm_gem_object *obj;
};

#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
				((em) == ATOM_ENCODER_MODE_DP_MST))

/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
#define USE_REAL_VBLANKSTART		(1 << 30)
#define GET_DISTANCE_TO_VBLANKSTART	(1 << 31)

void amdgpu_link_encoder_connector(struct drm_device *dev);

struct drm_connector *
amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
struct drm_connector *
amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
				    u32 pixel_clock);

u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);

bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);

void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);

int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
			       unsigned int flags, int *vpos, int *hpos,
			       ktime_t *stime, ktime_t *etime,
			       const struct drm_display_mode *mode);

int amdgpu_framebuffer_init(struct drm_device *dev,
			     struct amdgpu_framebuffer *rfb,
			     const struct drm_mode_fb_cmd2 *mode_cmd,
			     struct drm_gem_object *obj);

int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);

void amdgpu_enc_destroy(struct drm_encoder *encoder);
void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
					const struct drm_display_mode *mode,
					struct drm_display_mode *adjusted_mode);
void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
			     struct drm_display_mode *adjusted_mode);
int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);

/* fbdev layer */
int amdgpu_fbdev_init(struct amdgpu_device *adev);
void amdgpu_fbdev_fini(struct amdgpu_device *adev);
void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);

void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);


int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);

/* amdgpu_display.c */
void amdgpu_print_display_setup(struct drm_device *dev);
int amdgpu_modeset_create_props(struct amdgpu_device *adev);
int amdgpu_crtc_set_config(struct drm_mode_set *set);
int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 struct drm_pending_vblank_event *event,
				 uint32_t page_flip_flags, uint32_t target);
extern const struct drm_mode_config_funcs amdgpu_mode_funcs;

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
	3	* VA Linux Systems Inc., Fremont, California.
	4	* Copyright 2008 Red Hat Inc.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Original Authors:
	25	* Kevin E. Martin, Rickard E. Faith, Alan Hourihane
	26	*
	27	* Kernel port Author: Dave Airlie
	28	*/
	29
	30	#ifndef AMDGPU_MODE_H
	31	#define AMDGPU_MODE_H
	32
	33	#include <drm/drm_crtc.h>
	34	#include <drm/drm_edid.h>
	35	#include <drm/drm_dp_helper.h>
	36	#include <drm/drm_fixed.h>
	37	#include <drm/drm_crtc_helper.h>
b516a9ef	38	#include <drm/drm_fb_helper.h>
d38ceaf9 AD	39	#include <drm/drm_plane_helper.h>
	40	#include <linux/i2c.h>
	41	#include <linux/i2c-algo-bit.h>
46ac3622 ED	42	#include <linux/hrtimer.h>
46ac3622 ED	43	#include "amdgpu_irq.h"
d38ceaf9 AD	44
	45	struct amdgpu_bo;
	46	struct amdgpu_device;
	47	struct amdgpu_encoder;
	48	struct amdgpu_router;
	49	struct amdgpu_hpd;
	50
	51	#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
	52	#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
	53	#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
	54	#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
	55
	56	#define AMDGPU_MAX_HPD_PINS 6
	57	#define AMDGPU_MAX_CRTCS 6
22384459	58	#define AMDGPU_MAX_AFMT_BLOCKS 9
d38ceaf9 AD	59
	60	enum amdgpu_rmx_type {
	61	RMX_OFF,
	62	RMX_FULL,
	63	RMX_CENTER,
	64	RMX_ASPECT
	65	};
	66
	67	enum amdgpu_underscan_type {
	68	UNDERSCAN_OFF,
	69	UNDERSCAN_ON,
	70	UNDERSCAN_AUTO,
	71	};
	72
	73	#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
	74	#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
	75
	76	enum amdgpu_hpd_id {
	77	AMDGPU_HPD_1 = 0,
	78	AMDGPU_HPD_2,
	79	AMDGPU_HPD_3,
	80	AMDGPU_HPD_4,
	81	AMDGPU_HPD_5,
	82	AMDGPU_HPD_6,
	83	AMDGPU_HPD_LAST,
	84	AMDGPU_HPD_NONE = 0xff,
	85	};
	86
	87	enum amdgpu_crtc_irq {
	88	AMDGPU_CRTC_IRQ_VBLANK1 = 0,
	89	AMDGPU_CRTC_IRQ_VBLANK2,
	90	AMDGPU_CRTC_IRQ_VBLANK3,
	91	AMDGPU_CRTC_IRQ_VBLANK4,
	92	AMDGPU_CRTC_IRQ_VBLANK5,
	93	AMDGPU_CRTC_IRQ_VBLANK6,
	94	AMDGPU_CRTC_IRQ_VLINE1,
	95	AMDGPU_CRTC_IRQ_VLINE2,
	96	AMDGPU_CRTC_IRQ_VLINE3,
	97	AMDGPU_CRTC_IRQ_VLINE4,
	98	AMDGPU_CRTC_IRQ_VLINE5,
	99	AMDGPU_CRTC_IRQ_VLINE6,
	100	AMDGPU_CRTC_IRQ_LAST,
	101	AMDGPU_CRTC_IRQ_NONE = 0xff
	102	};
	103
	104	enum amdgpu_pageflip_irq {
	105	AMDGPU_PAGEFLIP_IRQ_D1 = 0,
	106	AMDGPU_PAGEFLIP_IRQ_D2,
	107	AMDGPU_PAGEFLIP_IRQ_D3,
	108	AMDGPU_PAGEFLIP_IRQ_D4,
	109	AMDGPU_PAGEFLIP_IRQ_D5,
	110	AMDGPU_PAGEFLIP_IRQ_D6,
	111	AMDGPU_PAGEFLIP_IRQ_LAST,
	112	AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
	113	};
	114
	115	enum amdgpu_flip_status {
	116	AMDGPU_FLIP_NONE,
	117	AMDGPU_FLIP_PENDING,
	118	AMDGPU_FLIP_SUBMITTED
	119	};
	120
	121	#define AMDGPU_MAX_I2C_BUS 16
	122
123	/* amdgpu gpio-based i2c
124	* 1. "mask" reg and bits
125	* grabs the gpio pins for software use
126	* 0=not held 1=held
127	* 2. "a" reg and bits
128	* output pin value
129	* 0=low 1=high
130	* 3. "en" reg and bits
131	* sets the pin direction
132	* 0=input 1=output
133	* 4. "y" reg and bits
134	* input pin value
135	* 0=low 1=high
136	*/
137	struct amdgpu_i2c_bus_rec {
138	bool valid;
139	/* id used by atom */
140	uint8_t i2c_id;
141	/* id used by atom */
142	enum amdgpu_hpd_id hpd;
143	/* can be used with hw i2c engine */
144	bool hw_capable;
145	/* uses multi-media i2c engine */
146	bool mm_i2c;
147	/* regs and bits */
148	uint32_t mask_clk_reg;
149	uint32_t mask_data_reg;
150	uint32_t a_clk_reg;
151	uint32_t a_data_reg;
152	uint32_t en_clk_reg;
153	uint32_t en_data_reg;
154	uint32_t y_clk_reg;
155	uint32_t y_data_reg;
156	uint32_t mask_clk_mask;
157	uint32_t mask_data_mask;
158	uint32_t a_clk_mask;
159	uint32_t a_data_mask;
160	uint32_t en_clk_mask;
161	uint32_t en_data_mask;
162	uint32_t y_clk_mask;
163	uint32_t y_data_mask;
164	};
165
166	#define AMDGPU_MAX_BIOS_CONNECTOR 16
167
168	/* pll flags */
169	#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
170	#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
171	#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
172	#define AMDGPU_PLL_LEGACY (1 << 3)
173	#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
174	#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
175	#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
176	#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
177	#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
178	#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
179	#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
180	#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
181	#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
182	#define AMDGPU_PLL_IS_LCD (1 << 13)
183	#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
184
185	struct amdgpu_pll {
186	/* reference frequency */
187	uint32_t reference_freq;
188
189	/* fixed dividers */
190	uint32_t reference_div;
191	uint32_t post_div;
192
193	/* pll in/out limits */
194	uint32_t pll_in_min;
195	uint32_t pll_in_max;
196	uint32_t pll_out_min;
197	uint32_t pll_out_max;
198	uint32_t lcd_pll_out_min;
199	uint32_t lcd_pll_out_max;
200	uint32_t best_vco;
201
202	/* divider limits */
203	uint32_t min_ref_div;
204	uint32_t max_ref_div;
205	uint32_t min_post_div;
206	uint32_t max_post_div;
207	uint32_t min_feedback_div;
208	uint32_t max_feedback_div;
209	uint32_t min_frac_feedback_div;
210	uint32_t max_frac_feedback_div;
211
212	/* flags for the current clock */
213	uint32_t flags;
214
215	/* pll id */
216	uint32_t id;
217	};
218
219	struct amdgpu_i2c_chan {
220	struct i2c_adapter adapter;
221	struct drm_device *dev;
222	struct i2c_algo_bit_data bit;
223	struct amdgpu_i2c_bus_rec rec;
224	struct drm_dp_aux aux;
225	bool has_aux;
226	struct mutex mutex;
227	};
228
229	struct amdgpu_fbdev;
230
231	struct amdgpu_afmt {
232	bool enabled;
233	int offset;
234	bool last_buffer_filled_status;
235	int id;
236	struct amdgpu_audio_pin *pin;
237	};
238
239	/*
240	* Audio
241	*/
242	struct amdgpu_audio_pin {
243	int channels;
244	int rate;
245	int bits_per_sample;
246	u8 status_bits;
247	u8 category_code;
248	u32 offset;
249	bool connected;
250	u32 id;
251	};
252
253	struct amdgpu_audio {
254	bool enabled;
255	struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
256	int num_pins;
257	};
258
259	struct amdgpu_mode_mc_save {
260	u32 vga_render_control;
261	u32 vga_hdp_control;
262	bool crtc_enabled[AMDGPU_MAX_CRTCS];
263	};
264
265	struct amdgpu_display_funcs {
266	/* vga render */
267	void (set_vga_render_state)(struct amdgpu_device adev, bool render);
268	/* display watermarks */
269	void (bandwidth_update)(struct amdgpu_device adev);
270	/* get frame count */
271	u32 (vblank_get_counter)(struct amdgpu_device adev, int crtc);
272	/* wait for vblank */
273	void (vblank_wait)(struct amdgpu_device adev, int crtc);
274	/* is dce hung */
275	bool (is_display_hung)(struct amdgpu_device adev);
276	/* set backlight level */
277	void (backlight_set_level)(struct amdgpu_encoder amdgpu_encoder,
278	u8 level);
279	/* get backlight level */
280	u8 (backlight_get_level)(struct amdgpu_encoder amdgpu_encoder);
281	/* hotplug detect */
282	bool (hpd_sense)(struct amdgpu_device adev, enum amdgpu_hpd_id hpd);
283	void (hpd_set_polarity)(struct amdgpu_device adev,
284	enum amdgpu_hpd_id hpd);
285	u32 (hpd_get_gpio_reg)(struct amdgpu_device adev);
286	/* pageflipping */
287	void (page_flip)(struct amdgpu_device adev,
cb9e59d7	288	int crtc_id, u64 crtc_base, bool async);
d38ceaf9 AD	289	int (page_flip_get_scanoutpos)(struct amdgpu_device adev, int crtc,
	290	u32 vbl, u32 position);
	291	/* display topology setup */
	292	void (add_encoder)(struct amdgpu_device adev,
	293	uint32_t encoder_enum,
	294	uint32_t supported_device,
	295	u16 caps);
	296	void (add_connector)(struct amdgpu_device adev,
	297	uint32_t connector_id,
	298	uint32_t supported_device,
	299	int connector_type,
	300	struct amdgpu_i2c_bus_rec *i2c_bus,
	301	uint16_t connector_object_id,
	302	struct amdgpu_hpd *hpd,
	303	struct amdgpu_router *router);
	304	void (stop_mc_access)(struct amdgpu_device adev,
	305	struct amdgpu_mode_mc_save *save);
	306	void (resume_mc_access)(struct amdgpu_device adev,
	307	struct amdgpu_mode_mc_save *save);
	308	};
	309
	310	struct amdgpu_mode_info {
	311	struct atom_context *atom_context;
	312	struct card_info *atom_card_info;
	313	bool mode_config_initialized;
f195038c AD	314	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
f195038c AD	315	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
d38ceaf9 AD	316	/* DVI-I properties */
	317	struct drm_property *coherent_mode_property;
	318	/* DAC enable load detect */
	319	struct drm_property *load_detect_property;
	320	/* underscan */
	321	struct drm_property *underscan_property;
	322	struct drm_property *underscan_hborder_property;
	323	struct drm_property *underscan_vborder_property;
	324	/* audio */
	325	struct drm_property *audio_property;
	326	/* FMT dithering */
	327	struct drm_property *dither_property;
	328	/* hardcoded DFP edid from BIOS */
	329	struct edid *bios_hardcoded_edid;
	330	int bios_hardcoded_edid_size;
	331
	332	/* pointer to fbdev info structure */
	333	struct amdgpu_fbdev *rfbdev;
	334	/* firmware flags */
	335	u16 firmware_flags;
	336	/* pointer to backlight encoder */
	337	struct amdgpu_encoder *bl_encoder;
	338	struct amdgpu_audio audio; /* audio stuff */
	339	int num_crtc; /* number of crtcs */
	340	int num_hpd; /* number of hpd pins */
	341	int num_dig; /* number of dig blocks */
	342	int disp_priority;
	343	const struct amdgpu_display_funcs *funcs;
46ac3622 ED	344	struct hrtimer vblank_timer;
46ac3622 ED	345	enum amdgpu_interrupt_state vsync_timer_enabled;
d38ceaf9 AD	346	};
	347
	348	#define AMDGPU_MAX_BL_LEVEL 0xFF
	349
	350	#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) \|\| defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
	351
	352	struct amdgpu_backlight_privdata {
	353	struct amdgpu_encoder *encoder;
	354	uint8_t negative;
	355	};
	356
	357	#endif
	358
	359	struct amdgpu_atom_ss {
	360	uint16_t percentage;
	361	uint16_t percentage_divider;
	362	uint8_t type;
	363	uint16_t step;
	364	uint8_t delay;
	365	uint8_t range;
	366	uint8_t refdiv;
	367	/* asic_ss */
	368	uint16_t rate;
	369	uint16_t amount;
	370	};
	371
	372	struct amdgpu_crtc {
	373	struct drm_crtc base;
	374	int crtc_id;
	375	u16 lut_r[256], lut_g[256], lut_b[256];
	376	bool enabled;
	377	bool can_tile;
	378	uint32_t crtc_offset;
	379	struct drm_gem_object *cursor_bo;
	380	uint64_t cursor_addr;
29275a9b AD	381	int cursor_x;
	382	int cursor_y;
	383	int cursor_hot_x;
	384	int cursor_hot_y;
d38ceaf9 AD	385	int cursor_width;
	386	int cursor_height;
	387	int max_cursor_width;
	388	int max_cursor_height;
	389	enum amdgpu_rmx_type rmx_type;
	390	u8 h_border;
	391	u8 v_border;
	392	fixed20_12 vsc;
	393	fixed20_12 hsc;
	394	struct drm_display_mode native_mode;
	395	u32 pll_id;
	396	/* page flipping */
d38ceaf9 AD	397	struct amdgpu_flip_work *pflip_works;
	398	enum amdgpu_flip_status pflip_status;
	399	int deferred_flip_completion;
	400	/* pll sharing */
	401	struct amdgpu_atom_ss ss;
	402	bool ss_enabled;
	403	u32 adjusted_clock;
	404	int bpc;
	405	u32 pll_reference_div;
	406	u32 pll_post_div;
	407	u32 pll_flags;
	408	struct drm_encoder *encoder;
	409	struct drm_connector *connector;
	410	/* for dpm */
	411	u32 line_time;
	412	u32 wm_low;
	413	u32 wm_high;
8e36f9d3	414	u32 lb_vblank_lead_lines;
d38ceaf9 AD	415	struct drm_display_mode hw_mode;
	416	};
	417
	418	struct amdgpu_encoder_atom_dig {
	419	bool linkb;
	420	/* atom dig */
	421	bool coherent_mode;
	422	int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
	423	/* atom lvds/edp */
	424	uint32_t lcd_misc;
	425	uint16_t panel_pwr_delay;
	426	uint32_t lcd_ss_id;
	427	/* panel mode */
	428	struct drm_display_mode native_mode;
	429	struct backlight_device *bl_dev;
	430	int dpms_mode;
	431	uint8_t backlight_level;
	432	int panel_mode;
	433	struct amdgpu_afmt *afmt;
	434	};
	435
	436	struct amdgpu_encoder {
	437	struct drm_encoder base;
	438	uint32_t encoder_enum;
	439	uint32_t encoder_id;
	440	uint32_t devices;
	441	uint32_t active_device;
	442	uint32_t flags;
	443	uint32_t pixel_clock;
	444	enum amdgpu_rmx_type rmx_type;
	445	enum amdgpu_underscan_type underscan_type;
	446	uint32_t underscan_hborder;
	447	uint32_t underscan_vborder;
	448	struct drm_display_mode native_mode;
	449	void *enc_priv;
	450	int audio_polling_active;
	451	bool is_ext_encoder;
	452	u16 caps;
	453	};
	454
	455	struct amdgpu_connector_atom_dig {
	456	/* displayport */
	457	u8 dpcd[DP_RECEIVER_CAP_SIZE];
	458	u8 dp_sink_type;
	459	int dp_clock;
	460	int dp_lane_count;
	461	bool edp_on;
	462	};
	463
	464	struct amdgpu_gpio_rec {
	465	bool valid;
	466	u8 id;
	467	u32 reg;
	468	u32 mask;
	469	u32 shift;
	470	};
	471
	472	struct amdgpu_hpd {
	473	enum amdgpu_hpd_id hpd;
	474	u8 plugged_state;
	475	struct amdgpu_gpio_rec gpio;
	476	};
	477
	478	struct amdgpu_router {
479	u32 router_id;
480	struct amdgpu_i2c_bus_rec i2c_info;
481	u8 i2c_addr;
482	/* i2c mux */
483	bool ddc_valid;
484	u8 ddc_mux_type;
485	u8 ddc_mux_control_pin;
486	u8 ddc_mux_state;
487	/* clock/data mux */
488	bool cd_valid;
489	u8 cd_mux_type;
490	u8 cd_mux_control_pin;
491	u8 cd_mux_state;
492	};
493
494	enum amdgpu_connector_audio {
495	AMDGPU_AUDIO_DISABLE = 0,
496	AMDGPU_AUDIO_ENABLE = 1,
497	AMDGPU_AUDIO_AUTO = 2
498	};
499
500	enum amdgpu_connector_dither {
501	AMDGPU_FMT_DITHER_DISABLE = 0,
502	AMDGPU_FMT_DITHER_ENABLE = 1,
503	};
504
505	struct amdgpu_connector {
506	struct drm_connector base;
507	uint32_t connector_id;
508	uint32_t devices;
509	struct amdgpu_i2c_chan *ddc_bus;
510	/* some systems have an hdmi and vga port with a shared ddc line */
511	bool shared_ddc;
512	bool use_digital;
513	/* we need to mind the EDID between detect
514	and get modes due to analog/digital/tvencoder */
515	struct edid *edid;
516	void *con_priv;
517	bool dac_load_detect;
518	bool detected_by_load; /* if the connection status was determined by load */
519	uint16_t connector_object_id;
520	struct amdgpu_hpd hpd;
521	struct amdgpu_router router;
522	struct amdgpu_i2c_chan *router_bus;
523	enum amdgpu_connector_audio audio;
524	enum amdgpu_connector_dither dither;
525	unsigned pixelclock_for_modeset;
526	};
527
528	struct amdgpu_framebuffer {
529	struct drm_framebuffer base;
530	struct drm_gem_object *obj;
531	};
532
533	#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) \|\| \
534	((em) == ATOM_ENCODER_MODE_DP_MST))
535
8e36f9d3	536	/* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */
edf600da	537	#define USE_REAL_VBLANKSTART (1 << 30)
8e36f9d3 AD	538	#define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
8e36f9d3 AD	539
d38ceaf9 AD	540	void amdgpu_link_encoder_connector(struct drm_device *dev);
	541
	542	struct drm_connector *
	543	amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
	544	struct drm_connector *
	545	amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
	546	bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
	547	u32 pixel_clock);
	548
	549	u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
	550	struct drm_encoder amdgpu_get_external_encoder(struct drm_encoder encoder);
	551
	552	bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
	553
	554	void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
	555
88e72717 TR	556	int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
	557	unsigned int flags, int vpos, int hpos,
	558	ktime_t stime, ktime_t etime,
	559	const struct drm_display_mode *mode);
d38ceaf9 AD	560
	561	int amdgpu_framebuffer_init(struct drm_device *dev,
	562	struct amdgpu_framebuffer *rfb,
1eb83451	563	const struct drm_mode_fb_cmd2 *mode_cmd,
d38ceaf9 AD	564	struct drm_gem_object *obj);
	565
	566	int amdgpufb_remove(struct drm_device dev, struct drm_framebuffer fb);
	567
	568	void amdgpu_enc_destroy(struct drm_encoder *encoder);
	569	void amdgpu_copy_fb(struct drm_device dev, struct drm_gem_object dst_obj);
	570	bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
	571	const struct drm_display_mode *mode,
	572	struct drm_display_mode *adjusted_mode);
	573	void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
	574	struct drm_display_mode *adjusted_mode);
	575	int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
	576
	577	/* fbdev layer */
	578	int amdgpu_fbdev_init(struct amdgpu_device *adev);
	579	void amdgpu_fbdev_fini(struct amdgpu_device *adev);
	580	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
	581	int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
	582	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj);
8b7530b1	583	void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev);
d38ceaf9 AD	584
	585	void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
	586
	587
	588	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
	589
	590	/* amdgpu_display.c */
	591	void amdgpu_print_display_setup(struct drm_device *dev);
	592	int amdgpu_modeset_create_props(struct amdgpu_device *adev);
	593	int amdgpu_crtc_set_config(struct drm_mode_set *set);
325cbba1 MD	594	int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
	595	struct drm_framebuffer *fb,
	596	struct drm_pending_vblank_event *event,
	597	uint32_t page_flip_flags, uint32_t target);
d38ceaf9 AD	598	extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
	599
	600	#endif