[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_object.c

/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include <drm/drm_cache.h>
#include "amdgpu.h"
#include "amdgpu_trace.h"


int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);

static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
						struct ttm_mem_reg *mem)
{
	u64 ret = 0;
	if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
		ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
			   adev->mc.visible_vram_size ?
			   adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
			   mem->size;
	}
	return ret;
}

static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
		       struct ttm_mem_reg *old_mem,
		       struct ttm_mem_reg *new_mem)
{
	u64 vis_size;
	if (!adev)
		return;

	if (new_mem) {
		switch (new_mem->mem_type) {
		case TTM_PL_TT:
			atomic64_add(new_mem->size, &adev->gtt_usage);
			break;
		case TTM_PL_VRAM:
			atomic64_add(new_mem->size, &adev->vram_usage);
			vis_size = amdgpu_get_vis_part_size(adev, new_mem);
			atomic64_add(vis_size, &adev->vram_vis_usage);
			break;
		}
	}

	if (old_mem) {
		switch (old_mem->mem_type) {
		case TTM_PL_TT:
			atomic64_sub(old_mem->size, &adev->gtt_usage);
			break;
		case TTM_PL_VRAM:
			atomic64_sub(old_mem->size, &adev->vram_usage);
			vis_size = amdgpu_get_vis_part_size(adev, old_mem);
			atomic64_sub(vis_size, &adev->vram_vis_usage);
			break;
		}
	}
}

static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
	struct amdgpu_bo *bo;

	bo = container_of(tbo, struct amdgpu_bo, tbo);

	amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);

	drm_gem_object_release(&bo->gem_base);
	amdgpu_bo_unref(&bo->parent);
	kfree(bo->metadata);
	kfree(bo);
}

bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &amdgpu_ttm_bo_destroy)
		return true;
	return false;
}

static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
				      struct ttm_placement *placement,
				      struct ttm_place *placements,
				      u32 domain, u64 flags)
{
	u32 c = 0, i;

	placement->placement = placements;
	placement->busy_placement = placements;

	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
		if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
			adev->mc.visible_vram_size < adev->mc.real_vram_size) {
			placements[c].fpfn =
				adev->mc.visible_vram_size >> PAGE_SHIFT;
			placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
				TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN;
		}
		placements[c].fpfn = 0;
		placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
			TTM_PL_FLAG_VRAM;
		if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
			placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;
	}

	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
			placements[c].fpfn = 0;
			placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
				TTM_PL_FLAG_UNCACHED;
		} else {
			placements[c].fpfn = 0;
			placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
		}
	}

	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
			placements[c].fpfn = 0;
			placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
				TTM_PL_FLAG_UNCACHED;
		} else {
			placements[c].fpfn = 0;
			placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
		}
	}

	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
		placements[c].fpfn = 0;
		placements[c++].flags = TTM_PL_FLAG_UNCACHED |
			AMDGPU_PL_FLAG_GDS;
	}
	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
		placements[c].fpfn = 0;
		placements[c++].flags = TTM_PL_FLAG_UNCACHED |
			AMDGPU_PL_FLAG_GWS;
	}
	if (domain & AMDGPU_GEM_DOMAIN_OA) {
		placements[c].fpfn = 0;
		placements[c++].flags = TTM_PL_FLAG_UNCACHED |
			AMDGPU_PL_FLAG_OA;
	}

	if (!c) {
		placements[c].fpfn = 0;
		placements[c++].flags = TTM_PL_MASK_CACHING |
			TTM_PL_FLAG_SYSTEM;
	}
	placement->num_placement = c;
	placement->num_busy_placement = c;

	for (i = 0; i < c; i++) {
		if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
			(placements[i].flags & TTM_PL_FLAG_VRAM) &&
			!placements[i].fpfn)
			placements[i].lpfn =
				adev->mc.visible_vram_size >> PAGE_SHIFT;
		else
			placements[i].lpfn = 0;
	}
}

void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
{
	amdgpu_ttm_placement_init(rbo->adev, &rbo->placement,
				  rbo->placements, domain, rbo->flags);
}

static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
					struct ttm_placement *placement)
{
	BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));

	memcpy(bo->placements, placement->placement,
	       placement->num_placement * sizeof(struct ttm_place));
	bo->placement.num_placement = placement->num_placement;
	bo->placement.num_busy_placement = placement->num_busy_placement;
	bo->placement.placement = bo->placements;
	bo->placement.busy_placement = bo->placements;
}

int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
				unsigned long size, int byte_align,
				bool kernel, u32 domain, u64 flags,
				struct sg_table *sg,
				struct ttm_placement *placement,
				struct reservation_object *resv,
				struct amdgpu_bo **bo_ptr)
{
	struct amdgpu_bo *bo;
	enum ttm_bo_type type;
	unsigned long page_align;
	size_t acc_size;
	int r;

	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
	size = ALIGN(size, PAGE_SIZE);

	if (kernel) {
		type = ttm_bo_type_kernel;
	} else if (sg) {
		type = ttm_bo_type_sg;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;

	acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
				       sizeof(struct amdgpu_bo));

	bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
	if (unlikely(r)) {
		kfree(bo);
		return r;
	}
	bo->adev = adev;
	INIT_LIST_HEAD(&bo->list);
	INIT_LIST_HEAD(&bo->va);
	bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
					 AMDGPU_GEM_DOMAIN_GTT |
					 AMDGPU_GEM_DOMAIN_CPU |
					 AMDGPU_GEM_DOMAIN_GDS |
					 AMDGPU_GEM_DOMAIN_GWS |
					 AMDGPU_GEM_DOMAIN_OA);
	bo->allowed_domains = bo->prefered_domains;
	if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;

	bo->flags = flags;

	/* For architectures that don't support WC memory,
	 * mask out the WC flag from the BO
	 */
	if (!drm_arch_can_wc_memory())
		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;

	amdgpu_fill_placement_to_bo(bo, placement);
	/* Kernel allocation are uninterruptible */
	r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
			&bo->placement, page_align, !kernel, NULL,
			acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
	if (unlikely(r != 0)) {
		return r;
	}
	*bo_ptr = bo;

	trace_amdgpu_bo_create(bo);

	return 0;
}

int amdgpu_bo_create(struct amdgpu_device *adev,
		     unsigned long size, int byte_align,
		     bool kernel, u32 domain, u64 flags,
		     struct sg_table *sg,
		     struct reservation_object *resv,
		     struct amdgpu_bo **bo_ptr)
{
	struct ttm_placement placement = {0};
	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];

	memset(&placements, 0,
	       (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));

	amdgpu_ttm_placement_init(adev, &placement,
				  placements, domain, flags);

	return amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
					   domain, flags, sg, &placement,
					   resv, bo_ptr);
}

int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
{
	bool is_iomem;
	long r;

	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
		return -EPERM;

	if (bo->kptr) {
		if (ptr) {
			*ptr = bo->kptr;
		}
		return 0;
	}

	r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
						MAX_SCHEDULE_TIMEOUT);
	if (r < 0)
		return r;

	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
	if (r)
		return r;

	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
	if (ptr)
		*ptr = bo->kptr;

	return 0;
}

void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
{
	if (bo->kptr == NULL)
		return;
	bo->kptr = NULL;
	ttm_bo_kunmap(&bo->kmap);
}

struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
{
	if (bo == NULL)
		return NULL;

	ttm_bo_reference(&bo->tbo);
	return bo;
}

void amdgpu_bo_unref(struct amdgpu_bo **bo)
{
	struct ttm_buffer_object *tbo;

	if ((*bo) == NULL)
		return;

	tbo = &((*bo)->tbo);
	ttm_bo_unref(&tbo);
	if (tbo == NULL)
		*bo = NULL;
}

int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
			     u64 min_offset, u64 max_offset,
			     u64 *gpu_addr)
{
	int r, i;
	unsigned fpfn, lpfn;

	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
		return -EPERM;

	if (WARN_ON_ONCE(min_offset > max_offset))
		return -EINVAL;

	if (bo->pin_count) {
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = amdgpu_bo_gpu_offset(bo);

		if (max_offset != 0) {
			u64 domain_start;
			if (domain == AMDGPU_GEM_DOMAIN_VRAM)
				domain_start = bo->adev->mc.vram_start;
			else
				domain_start = bo->adev->mc.gtt_start;
			WARN_ON_ONCE(max_offset <
				     (amdgpu_bo_gpu_offset(bo) - domain_start));
		}

		return 0;
	}
	amdgpu_ttm_placement_from_domain(bo, domain);
	for (i = 0; i < bo->placement.num_placement; i++) {
		/* force to pin into visible video ram */
		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
		    !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
		    (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) {
			if (WARN_ON_ONCE(min_offset >
					 bo->adev->mc.visible_vram_size))
				return -EINVAL;
			fpfn = min_offset >> PAGE_SHIFT;
			lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
		} else {
			fpfn = min_offset >> PAGE_SHIFT;
			lpfn = max_offset >> PAGE_SHIFT;
		}
		if (fpfn > bo->placements[i].fpfn)
			bo->placements[i].fpfn = fpfn;
		if (!bo->placements[i].lpfn ||
		    (lpfn && lpfn < bo->placements[i].lpfn))
			bo->placements[i].lpfn = lpfn;
		bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
	}

	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	if (likely(r == 0)) {
		bo->pin_count = 1;
		if (gpu_addr != NULL)
			*gpu_addr = amdgpu_bo_gpu_offset(bo);
		if (domain == AMDGPU_GEM_DOMAIN_VRAM)
			bo->adev->vram_pin_size += amdgpu_bo_size(bo);
		else
			bo->adev->gart_pin_size += amdgpu_bo_size(bo);
	} else {
		dev_err(bo->adev->dev, "%p pin failed\n", bo);
	}
	return r;
}

int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
{
	return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
}

int amdgpu_bo_unpin(struct amdgpu_bo *bo)
{
	int r, i;

	if (!bo->pin_count) {
		dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++) {
		bo->placements[i].lpfn = 0;
		bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
	}
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	if (likely(r == 0)) {
		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
			bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
		else
			bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
	} else {
		dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
	}
	return r;
}

int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
	if (0 && (adev->flags & AMD_IS_APU)) {
		/* Useless to evict on IGP chips */
		return 0;
	}
	return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
}

static const char *amdgpu_vram_names[] = {
	"UNKNOWN",
	"GDDR1",
	"DDR2",
	"GDDR3",
	"GDDR4",
	"GDDR5",
	"HBM",
	"DDR3"
};

int amdgpu_bo_init(struct amdgpu_device *adev)
{
	/* Add an MTRR for the VRAM */
	adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
					      adev->mc.aper_size);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		adev->mc.mc_vram_size >> 20,
		(unsigned long long)adev->mc.aper_size >> 20);
	DRM_INFO("RAM width %dbits %s\n",
		 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
	return amdgpu_ttm_init(adev);
}

void amdgpu_bo_fini(struct amdgpu_device *adev)
{
	amdgpu_ttm_fini(adev);
	arch_phys_wc_del(adev->mc.vram_mtrr);
}

int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
{
	if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
		return -EINVAL;

	bo->tiling_flags = tiling_flags;
	return 0;
}

void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
{
	lockdep_assert_held(&bo->tbo.resv->lock.base);

	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
}

int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
			    uint32_t metadata_size, uint64_t flags)
{
	void *buffer;

	if (!metadata_size) {
		if (bo->metadata_size) {
			kfree(bo->metadata);
			bo->metadata_size = 0;
		}
		return 0;
	}

	if (metadata == NULL)
		return -EINVAL;

	buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
	if (buffer == NULL)
		return -ENOMEM;

	kfree(bo->metadata);
	bo->metadata_flags = flags;
	bo->metadata = buffer;
	bo->metadata_size = metadata_size;

	return 0;
}

int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
			   size_t buffer_size, uint32_t *metadata_size,
			   uint64_t *flags)
{
	if (!buffer && !metadata_size)
		return -EINVAL;

	if (buffer) {
		if (buffer_size < bo->metadata_size)
			return -EINVAL;

		if (bo->metadata_size)
			memcpy(buffer, bo->metadata, bo->metadata_size);
	}

	if (metadata_size)
		*metadata_size = bo->metadata_size;
	if (flags)
		*flags = bo->metadata_flags;

	return 0;
}

void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
			   struct ttm_mem_reg *new_mem)
{
	struct amdgpu_bo *rbo;

	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
		return;

	rbo = container_of(bo, struct amdgpu_bo, tbo);
	amdgpu_vm_bo_invalidate(rbo->adev, rbo);

	/* update statistics */
	if (!new_mem)
		return;

	/* move_notify is called before move happens */
	amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
}

int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
	struct amdgpu_device *adev;
	struct amdgpu_bo *abo;
	unsigned long offset, size, lpfn;
	int i, r;

	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
		return 0;

	abo = container_of(bo, struct amdgpu_bo, tbo);
	adev = abo->adev;
	if (bo->mem.mem_type != TTM_PL_VRAM)
		return 0;

	size = bo->mem.num_pages << PAGE_SHIFT;
	offset = bo->mem.start << PAGE_SHIFT;
	if ((offset + size) <= adev->mc.visible_vram_size)
		return 0;

	/* Can't move a pinned BO to visible VRAM */
	if (abo->pin_count > 0)
		return -EINVAL;

	/* hurrah the memory is not visible ! */
	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
	lpfn =	adev->mc.visible_vram_size >> PAGE_SHIFT;
	for (i = 0; i < abo->placement.num_placement; i++) {
		/* Force into visible VRAM */
		if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
		    (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn))
			abo->placements[i].lpfn = lpfn;
	}
	r = ttm_bo_validate(bo, &abo->placement, false, false);
	if (unlikely(r == -ENOMEM)) {
		amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
		return ttm_bo_validate(bo, &abo->placement, false, false);
	} else if (unlikely(r != 0)) {
		return r;
	}

	offset = bo->mem.start << PAGE_SHIFT;
	/* this should never happen */
	if ((offset + size) > adev->mc.visible_vram_size)
		return -EINVAL;

	return 0;
}

/**
 * amdgpu_bo_fence - add fence to buffer object
 *
 * @bo: buffer object in question
 * @fence: fence to add
 * @shared: true if fence should be added shared
 *
 */
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
		     bool shared)
{
	struct reservation_object *resv = bo->tbo.resv;

	if (shared)
		reservation_object_add_shared_fence(resv, fence);
	else
		reservation_object_add_excl_fence(resv, fence);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
	30	* Dave Airlie
	31	*/
	32	#include <linux/list.h>
	33	#include <linux/slab.h>
	34	#include <drm/drmP.h>
	35	#include <drm/amdgpu_drm.h>
a187f17f	36	#include <drm/drm_cache.h>
d38ceaf9 AD	37	#include "amdgpu.h"
	38	#include "amdgpu_trace.h"
	39
	40
	41	int amdgpu_ttm_init(struct amdgpu_device *adev);
	42	void amdgpu_ttm_fini(struct amdgpu_device *adev);
	43
	44	static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
7e5a547f	45	struct ttm_mem_reg *mem)
d38ceaf9 AD	46	{
	47	u64 ret = 0;
	48	if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
	49	ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
	50	adev->mc.visible_vram_size ?
7e5a547f	51	adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
d38ceaf9 AD	52	mem->size;
	53	}
	54	return ret;
	55	}
	56
	57	static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
	58	struct ttm_mem_reg *old_mem,
	59	struct ttm_mem_reg *new_mem)
	60	{
	61	u64 vis_size;
	62	if (!adev)
	63	return;
	64
	65	if (new_mem) {
	66	switch (new_mem->mem_type) {
	67	case TTM_PL_TT:
	68	atomic64_add(new_mem->size, &adev->gtt_usage);
	69	break;
	70	case TTM_PL_VRAM:
	71	atomic64_add(new_mem->size, &adev->vram_usage);
	72	vis_size = amdgpu_get_vis_part_size(adev, new_mem);
	73	atomic64_add(vis_size, &adev->vram_vis_usage);
	74	break;
	75	}
	76	}
	77
	78	if (old_mem) {
	79	switch (old_mem->mem_type) {
	80	case TTM_PL_TT:
	81	atomic64_sub(old_mem->size, &adev->gtt_usage);
	82	break;
	83	case TTM_PL_VRAM:
	84	atomic64_sub(old_mem->size, &adev->vram_usage);
	85	vis_size = amdgpu_get_vis_part_size(adev, old_mem);
	86	atomic64_sub(vis_size, &adev->vram_vis_usage);
	87	break;
	88	}
	89	}
	90	}
	91
	92	static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
	93	{
	94	struct amdgpu_bo *bo;
	95
	96	bo = container_of(tbo, struct amdgpu_bo, tbo);
	97
	98	amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
d38ceaf9	99
d38ceaf9	100	drm_gem_object_release(&bo->gem_base);
82b9c55b	101	amdgpu_bo_unref(&bo->parent);
d38ceaf9 AD	102	kfree(bo->metadata);
	103	kfree(bo);
	104	}
	105
	106	bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
	107	{
	108	if (bo->destroy == &amdgpu_ttm_bo_destroy)
	109	return true;
	110	return false;
	111	}
	112
7e5a547f CZ	113	static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
	114	struct ttm_placement *placement,
	115	struct ttm_place *placements,
	116	u32 domain, u64 flags)
d38ceaf9 AD	117	{
d38ceaf9 AD	118	u32 c = 0, i;
7e5a547f CZ	119
	120	placement->placement = placements;
	121	placement->busy_placement = placements;
d38ceaf9 AD	122
d38ceaf9 AD	123	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
7e5a547f CZ	124	if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
	125	adev->mc.visible_vram_size < adev->mc.real_vram_size) {
	126	placements[c].fpfn =
	127	adev->mc.visible_vram_size >> PAGE_SHIFT;
	128	placements[c++].flags = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
cace5dce	129	TTM_PL_FLAG_VRAM \| TTM_PL_FLAG_TOPDOWN;
d38ceaf9	130	}
7e5a547f CZ	131	placements[c].fpfn = 0;
	132	placements[c++].flags = TTM_PL_FLAG_WC \| TTM_PL_FLAG_UNCACHED \|
	133	TTM_PL_FLAG_VRAM;
95d79183 CZ	134	if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
95d79183 CZ	135	placements[c - 1].flags \|= TTM_PL_FLAG_TOPDOWN;
d38ceaf9 AD	136	}
	137
	138	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
7e5a547f CZ	139	if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
	140	placements[c].fpfn = 0;
	141	placements[c++].flags = TTM_PL_FLAG_WC \| TTM_PL_FLAG_TT \|
	142	TTM_PL_FLAG_UNCACHED;
d38ceaf9	143	} else {
7e5a547f CZ	144	placements[c].fpfn = 0;
7e5a547f CZ	145	placements[c++].flags = TTM_PL_FLAG_CACHED \| TTM_PL_FLAG_TT;
d38ceaf9 AD	146	}
	147	}
	148
	149	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
7e5a547f CZ	150	if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
	151	placements[c].fpfn = 0;
	152	placements[c++].flags = TTM_PL_FLAG_WC \| TTM_PL_FLAG_SYSTEM \|
	153	TTM_PL_FLAG_UNCACHED;
d38ceaf9	154	} else {
7e5a547f CZ	155	placements[c].fpfn = 0;
7e5a547f CZ	156	placements[c++].flags = TTM_PL_FLAG_CACHED \| TTM_PL_FLAG_SYSTEM;
d38ceaf9 AD	157	}
	158	}
	159
	160	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
7e5a547f CZ	161	placements[c].fpfn = 0;
	162	placements[c++].flags = TTM_PL_FLAG_UNCACHED \|
	163	AMDGPU_PL_FLAG_GDS;
d38ceaf9 AD	164	}
d38ceaf9 AD	165	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
7e5a547f CZ	166	placements[c].fpfn = 0;
	167	placements[c++].flags = TTM_PL_FLAG_UNCACHED \|
	168	AMDGPU_PL_FLAG_GWS;
d38ceaf9 AD	169	}
d38ceaf9 AD	170	if (domain & AMDGPU_GEM_DOMAIN_OA) {
7e5a547f CZ	171	placements[c].fpfn = 0;
	172	placements[c++].flags = TTM_PL_FLAG_UNCACHED \|
	173	AMDGPU_PL_FLAG_OA;
d38ceaf9 AD	174	}
	175
	176	if (!c) {
7e5a547f CZ	177	placements[c].fpfn = 0;
	178	placements[c++].flags = TTM_PL_MASK_CACHING \|
	179	TTM_PL_FLAG_SYSTEM;
d38ceaf9	180	}
7e5a547f CZ	181	placement->num_placement = c;
7e5a547f CZ	182	placement->num_busy_placement = c;
d38ceaf9 AD	183
d38ceaf9 AD	184	for (i = 0; i < c; i++) {
7e5a547f CZ	185	if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
	186	(placements[i].flags & TTM_PL_FLAG_VRAM) &&
	187	!placements[i].fpfn)
	188	placements[i].lpfn =
	189	adev->mc.visible_vram_size >> PAGE_SHIFT;
d38ceaf9	190	else
7e5a547f	191	placements[i].lpfn = 0;
d38ceaf9	192	}
d38ceaf9 AD	193	}
d38ceaf9 AD	194
7e5a547f CZ	195	void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
	196	{
	197	amdgpu_ttm_placement_init(rbo->adev, &rbo->placement,
	198	rbo->placements, domain, rbo->flags);
	199	}
	200
	201	static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
	202	struct ttm_placement *placement)
	203	{
	204	BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
	205
	206	memcpy(bo->placements, placement->placement,
	207	placement->num_placement * sizeof(struct ttm_place));
	208	bo->placement.num_placement = placement->num_placement;
	209	bo->placement.num_busy_placement = placement->num_busy_placement;
	210	bo->placement.placement = bo->placements;
	211	bo->placement.busy_placement = bo->placements;
	212	}
	213
	214	int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
	215	unsigned long size, int byte_align,
	216	bool kernel, u32 domain, u64 flags,
	217	struct sg_table *sg,
	218	struct ttm_placement *placement,
72d7668b	219	struct reservation_object *resv,
7e5a547f	220	struct amdgpu_bo **bo_ptr)
d38ceaf9 AD	221	{
	222	struct amdgpu_bo *bo;
	223	enum ttm_bo_type type;
	224	unsigned long page_align;
	225	size_t acc_size;
	226	int r;
	227
d38ceaf9 AD	228	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
	229	size = ALIGN(size, PAGE_SIZE);
	230
	231	if (kernel) {
	232	type = ttm_bo_type_kernel;
	233	} else if (sg) {
	234	type = ttm_bo_type_sg;
	235	} else {
	236	type = ttm_bo_type_device;
	237	}
	238	*bo_ptr = NULL;
	239
	240	acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
	241	sizeof(struct amdgpu_bo));
	242
	243	bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
	244	if (bo == NULL)
	245	return -ENOMEM;
	246	r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
	247	if (unlikely(r)) {
	248	kfree(bo);
	249	return r;
	250	}
	251	bo->adev = adev;
	252	INIT_LIST_HEAD(&bo->list);
	253	INIT_LIST_HEAD(&bo->va);
1ea863fd CK	254	bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM \|
	255	AMDGPU_GEM_DOMAIN_GTT \|
	256	AMDGPU_GEM_DOMAIN_CPU \|
	257	AMDGPU_GEM_DOMAIN_GDS \|
	258	AMDGPU_GEM_DOMAIN_GWS \|
	259	AMDGPU_GEM_DOMAIN_OA);
	260	bo->allowed_domains = bo->prefered_domains;
	261	if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
	262	bo->allowed_domains \|= AMDGPU_GEM_DOMAIN_GTT;
d38ceaf9 AD	263
d38ceaf9 AD	264	bo->flags = flags;
a187f17f OG	265
	266	/* For architectures that don't support WC memory,
	267	* mask out the WC flag from the BO
	268	*/
	269	if (!drm_arch_can_wc_memory())
	270	bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
	271
7e5a547f	272	amdgpu_fill_placement_to_bo(bo, placement);
d38ceaf9	273	/* Kernel allocation are uninterruptible */
d38ceaf9 AD	274	r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
d38ceaf9 AD	275	&bo->placement, page_align, !kernel, NULL,
72d7668b	276	acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
d38ceaf9 AD	277	if (unlikely(r != 0)) {
	278	return r;
	279	}
	280	*bo_ptr = bo;
	281
	282	trace_amdgpu_bo_create(bo);
	283
	284	return 0;
	285	}
	286
7e5a547f CZ	287	int amdgpu_bo_create(struct amdgpu_device *adev,
	288	unsigned long size, int byte_align,
	289	bool kernel, u32 domain, u64 flags,
72d7668b CK	290	struct sg_table *sg,
	291	struct reservation_object *resv,
	292	struct amdgpu_bo **bo_ptr)
7e5a547f CZ	293	{
	294	struct ttm_placement placement = {0};
	295	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
	296
	297	memset(&placements, 0,
	298	(AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
	299
	300	amdgpu_ttm_placement_init(adev, &placement,
	301	placements, domain, flags);
	302
72d7668b CK	303	return amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
	304	domain, flags, sg, &placement,
	305	resv, bo_ptr);
7e5a547f CZ	306	}
7e5a547f CZ	307
d38ceaf9 AD	308	int amdgpu_bo_kmap(struct amdgpu_bo bo, void *ptr)
	309	{
	310	bool is_iomem;
587f3c70	311	long r;
d38ceaf9	312
271c8125 CK	313	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
	314	return -EPERM;
	315
d38ceaf9 AD	316	if (bo->kptr) {
	317	if (ptr) {
	318	*ptr = bo->kptr;
	319	}
	320	return 0;
	321	}
587f3c70 CK	322
	323	r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
	324	MAX_SCHEDULE_TIMEOUT);
	325	if (r < 0)
	326	return r;
	327
d38ceaf9	328	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
587f3c70	329	if (r)
d38ceaf9	330	return r;
587f3c70	331
d38ceaf9	332	bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
587f3c70	333	if (ptr)
d38ceaf9	334	*ptr = bo->kptr;
587f3c70	335
d38ceaf9 AD	336	return 0;
	337	}
	338
	339	void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
	340	{
	341	if (bo->kptr == NULL)
	342	return;
	343	bo->kptr = NULL;
	344	ttm_bo_kunmap(&bo->kmap);
	345	}
	346
	347	struct amdgpu_bo amdgpu_bo_ref(struct amdgpu_bo bo)
	348	{
	349	if (bo == NULL)
	350	return NULL;
	351
	352	ttm_bo_reference(&bo->tbo);
	353	return bo;
	354	}
	355
	356	void amdgpu_bo_unref(struct amdgpu_bo **bo)
	357	{
	358	struct ttm_buffer_object *tbo;
	359
	360	if ((*bo) == NULL)
	361	return;
	362
	363	tbo = &((*bo)->tbo);
	364	ttm_bo_unref(&tbo);
	365	if (tbo == NULL)
	366	*bo = NULL;
	367	}
	368
7e5a547f CZ	369	int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
7e5a547f CZ	370	u64 min_offset, u64 max_offset,
d38ceaf9 AD	371	u64 *gpu_addr)
	372	{
	373	int r, i;
7e5a547f	374	unsigned fpfn, lpfn;
d38ceaf9	375
cc325d19	376	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
d38ceaf9 AD	377	return -EPERM;
d38ceaf9 AD	378
7e5a547f CZ	379	if (WARN_ON_ONCE(min_offset > max_offset))
	380	return -EINVAL;
	381
d38ceaf9 AD	382	if (bo->pin_count) {
	383	bo->pin_count++;
	384	if (gpu_addr)
	385	*gpu_addr = amdgpu_bo_gpu_offset(bo);
	386
	387	if (max_offset != 0) {
	388	u64 domain_start;
d38ceaf9 AD	389	if (domain == AMDGPU_GEM_DOMAIN_VRAM)
	390	domain_start = bo->adev->mc.vram_start;
	391	else
	392	domain_start = bo->adev->mc.gtt_start;
	393	WARN_ON_ONCE(max_offset <
	394	(amdgpu_bo_gpu_offset(bo) - domain_start));
	395	}
	396
	397	return 0;
	398	}
	399	amdgpu_ttm_placement_from_domain(bo, domain);
	400	for (i = 0; i < bo->placement.num_placement; i++) {
	401	/* force to pin into visible video ram */
	402	if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
7e5a547f CZ	403	!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
	404	(!max_offset \|\| max_offset > bo->adev->mc.visible_vram_size)) {
	405	if (WARN_ON_ONCE(min_offset >
	406	bo->adev->mc.visible_vram_size))
	407	return -EINVAL;
	408	fpfn = min_offset >> PAGE_SHIFT;
	409	lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
	410	} else {
	411	fpfn = min_offset >> PAGE_SHIFT;
	412	lpfn = max_offset >> PAGE_SHIFT;
	413	}
	414	if (fpfn > bo->placements[i].fpfn)
	415	bo->placements[i].fpfn = fpfn;
78d0e182 CK	416	if (!bo->placements[i].lpfn \|\|
78d0e182 CK	417	(lpfn && lpfn < bo->placements[i].lpfn))
7e5a547f	418	bo->placements[i].lpfn = lpfn;
d38ceaf9 AD	419	bo->placements[i].flags \|= TTM_PL_FLAG_NO_EVICT;
	420	}
	421
	422	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	423	if (likely(r == 0)) {
	424	bo->pin_count = 1;
	425	if (gpu_addr != NULL)
	426	*gpu_addr = amdgpu_bo_gpu_offset(bo);
	427	if (domain == AMDGPU_GEM_DOMAIN_VRAM)
	428	bo->adev->vram_pin_size += amdgpu_bo_size(bo);
	429	else
	430	bo->adev->gart_pin_size += amdgpu_bo_size(bo);
	431	} else {
	432	dev_err(bo->adev->dev, "%p pin failed\n", bo);
	433	}
	434	return r;
	435	}
	436
	437	int amdgpu_bo_pin(struct amdgpu_bo bo, u32 domain, u64 gpu_addr)
	438	{
7e5a547f	439	return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
d38ceaf9 AD	440	}
	441
	442	int amdgpu_bo_unpin(struct amdgpu_bo *bo)
	443	{
	444	int r, i;
	445
	446	if (!bo->pin_count) {
	447	dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
	448	return 0;
	449	}
	450	bo->pin_count--;
	451	if (bo->pin_count)
	452	return 0;
	453	for (i = 0; i < bo->placement.num_placement; i++) {
	454	bo->placements[i].lpfn = 0;
	455	bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
	456	}
	457	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	458	if (likely(r == 0)) {
	459	if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
	460	bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
	461	else
	462	bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
	463	} else {
	464	dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
	465	}
	466	return r;
	467	}
	468
	469	int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
	470	{
	471	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
2f7d10b3	472	if (0 && (adev->flags & AMD_IS_APU)) {
d38ceaf9 AD	473	/* Useless to evict on IGP chips */
	474	return 0;
	475	}
	476	return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
	477	}
	478
1f8628c7 AD	479	static const char *amdgpu_vram_names[] = {
	480	"UNKNOWN",
	481	"GDDR1",
	482	"DDR2",
	483	"GDDR3",
	484	"GDDR4",
	485	"GDDR5",
	486	"HBM",
	487	"DDR3"
	488	};
	489
d38ceaf9 AD	490	int amdgpu_bo_init(struct amdgpu_device *adev)
	491	{
	492	/* Add an MTRR for the VRAM */
	493	adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
	494	adev->mc.aper_size);
	495	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
	496	adev->mc.mc_vram_size >> 20,
	497	(unsigned long long)adev->mc.aper_size >> 20);
1f8628c7 AD	498	DRM_INFO("RAM width %dbits %s\n",
1f8628c7 AD	499	adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
d38ceaf9 AD	500	return amdgpu_ttm_init(adev);
	501	}
	502
	503	void amdgpu_bo_fini(struct amdgpu_device *adev)
	504	{
	505	amdgpu_ttm_fini(adev);
	506	arch_phys_wc_del(adev->mc.vram_mtrr);
	507	}
	508
	509	int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
	510	struct vm_area_struct *vma)
	511	{
	512	return ttm_fbdev_mmap(vma, &bo->tbo);
	513	}
	514
	515	int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
	516	{
fbd76d59	517	if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
d38ceaf9	518	return -EINVAL;
d38ceaf9 AD	519
	520	bo->tiling_flags = tiling_flags;
	521	return 0;
	522	}
	523
	524	void amdgpu_bo_get_tiling_flags(struct amdgpu_bo bo, u64 tiling_flags)
	525	{
	526	lockdep_assert_held(&bo->tbo.resv->lock.base);
	527
	528	if (tiling_flags)
	529	*tiling_flags = bo->tiling_flags;
	530	}
	531
	532	int amdgpu_bo_set_metadata (struct amdgpu_bo bo, void metadata,
	533	uint32_t metadata_size, uint64_t flags)
	534	{
	535	void *buffer;
	536
	537	if (!metadata_size) {
	538	if (bo->metadata_size) {
	539	kfree(bo->metadata);
	540	bo->metadata_size = 0;
	541	}
	542	return 0;
	543	}
	544
	545	if (metadata == NULL)
	546	return -EINVAL;
	547
71affda5	548	buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
d38ceaf9 AD	549	if (buffer == NULL)
	550	return -ENOMEM;
	551
d38ceaf9 AD	552	kfree(bo->metadata);
	553	bo->metadata_flags = flags;
	554	bo->metadata = buffer;
	555	bo->metadata_size = metadata_size;
	556
	557	return 0;
	558	}
	559
	560	int amdgpu_bo_get_metadata(struct amdgpu_bo bo, void buffer,
	561	size_t buffer_size, uint32_t *metadata_size,
	562	uint64_t *flags)
	563	{
	564	if (!buffer && !metadata_size)
	565	return -EINVAL;
	566
	567	if (buffer) {
	568	if (buffer_size < bo->metadata_size)
	569	return -EINVAL;
	570
	571	if (bo->metadata_size)
	572	memcpy(buffer, bo->metadata, bo->metadata_size);
	573	}
	574
	575	if (metadata_size)
	576	*metadata_size = bo->metadata_size;
	577	if (flags)
	578	*flags = bo->metadata_flags;
	579
	580	return 0;
	581	}
	582
	583	void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
	584	struct ttm_mem_reg *new_mem)
	585	{
	586	struct amdgpu_bo *rbo;
	587
	588	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
	589	return;
	590
	591	rbo = container_of(bo, struct amdgpu_bo, tbo);
	592	amdgpu_vm_bo_invalidate(rbo->adev, rbo);
	593
	594	/* update statistics */
	595	if (!new_mem)
	596	return;
	597
	598	/* move_notify is called before move happens */
	599	amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
	600	}
	601
	602	int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
	603	{
	604	struct amdgpu_device *adev;
5fb1941d CK	605	struct amdgpu_bo *abo;
	606	unsigned long offset, size, lpfn;
	607	int i, r;
d38ceaf9 AD	608
	609	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
	610	return 0;
5fb1941d CK	611
	612	abo = container_of(bo, struct amdgpu_bo, tbo);
	613	adev = abo->adev;
	614	if (bo->mem.mem_type != TTM_PL_VRAM)
	615	return 0;
	616
	617	size = bo->mem.num_pages << PAGE_SHIFT;
	618	offset = bo->mem.start << PAGE_SHIFT;
	619	if ((offset + size) <= adev->mc.visible_vram_size)
	620	return 0;
	621
104ece97 MD	622	/* Can't move a pinned BO to visible VRAM */
	623	if (abo->pin_count > 0)
	624	return -EINVAL;
	625
5fb1941d CK	626	/* hurrah the memory is not visible ! */
	627	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
	628	lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
	629	for (i = 0; i < abo->placement.num_placement; i++) {
	630	/* Force into visible VRAM */
	631	if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
	632	(!abo->placements[i].lpfn \|\| abo->placements[i].lpfn > lpfn))
	633	abo->placements[i].lpfn = lpfn;
	634	}
	635	r = ttm_bo_validate(bo, &abo->placement, false, false);
	636	if (unlikely(r == -ENOMEM)) {
	637	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
	638	return ttm_bo_validate(bo, &abo->placement, false, false);
	639	} else if (unlikely(r != 0)) {
	640	return r;
d38ceaf9	641	}
5fb1941d CK	642
	643	offset = bo->mem.start << PAGE_SHIFT;
	644	/* this should never happen */
	645	if ((offset + size) > adev->mc.visible_vram_size)
	646	return -EINVAL;
	647
d38ceaf9 AD	648	return 0;
	649	}
	650
	651	/**
	652	* amdgpu_bo_fence - add fence to buffer object
	653	*
	654	* @bo: buffer object in question
	655	* @fence: fence to add
	656	* @shared: true if fence should be added shared
	657	*
	658	*/
e40a3115	659	void amdgpu_bo_fence(struct amdgpu_bo bo, struct fence fence,
d38ceaf9 AD	660	bool shared)
	661	{
	662	struct reservation_object *resv = bo->tbo.resv;
	663
	664	if (shared)
e40a3115	665	reservation_object_add_shared_fence(resv, fence);
d38ceaf9	666	else
e40a3115	667	reservation_object_add_excl_fence(resv, fence);
d38ceaf9	668	}