[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_object.h

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __AMDGPU_OBJECT_H__
#define __AMDGPU_OBJECT_H__

#include <drm/amdgpu_drm.h>
#include "amdgpu.h"

/**
 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
 * @mem_type:	ttm memory type
 *
 * Returns corresponding domain of the ttm mem_type
 */
static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
{
	switch (mem_type) {
	case TTM_PL_VRAM:
		return AMDGPU_GEM_DOMAIN_VRAM;
	case TTM_PL_TT:
		return AMDGPU_GEM_DOMAIN_GTT;
	case TTM_PL_SYSTEM:
		return AMDGPU_GEM_DOMAIN_CPU;
	case AMDGPU_PL_GDS:
		return AMDGPU_GEM_DOMAIN_GDS;
	case AMDGPU_PL_GWS:
		return AMDGPU_GEM_DOMAIN_GWS;
	case AMDGPU_PL_OA:
		return AMDGPU_GEM_DOMAIN_OA;
	default:
		break;
	}
	return 0;
}

/**
 * amdgpu_bo_reserve - reserve bo
 * @bo:		bo structure
 * @no_intr:	don't return -ERESTARTSYS on pending signal
 *
 * Returns:
 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 * a signal. Release all buffer reservations and return to user-space.
 */
static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
{
	int r;

	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
	if (unlikely(r != 0)) {
		if (r != -ERESTARTSYS)
			dev_err(bo->adev->dev, "%p reserve failed\n", bo);
		return r;
	}
	return 0;
}

static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
{
	ttm_bo_unreserve(&bo->tbo);
}

/**
 * amdgpu_bo_gpu_offset - return GPU offset of bo
 * @bo:	amdgpu object for which we query the offset
 *
 * Returns current GPU offset of the object.
 *
 * Note: object should either be pinned or reserved when calling this
 * function, it might be useful to add check for this for debugging.
 */
static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
{
	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
	return bo->tbo.offset;
}

static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
{
	return bo->tbo.num_pages << PAGE_SHIFT;
}

static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
{
	return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
}

static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
{
	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
}

/**
 * amdgpu_bo_mmap_offset - return mmap offset of bo
 * @bo:	amdgpu object for which we query the offset
 *
 * Returns mmap offset of the object.
 */
static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
{
	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
}

int amdgpu_bo_create(struct amdgpu_device *adev,
			    unsigned long size, int byte_align,
			    bool kernel, u32 domain, u64 flags,
			    struct sg_table *sg,
			    struct reservation_object *resv,
			    struct amdgpu_bo **bo_ptr);
int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
				unsigned long size, int byte_align,
				bool kernel, u32 domain, u64 flags,
				struct sg_table *sg,
				struct ttm_placement *placement,
			        struct reservation_object *resv,
				struct amdgpu_bo **bo_ptr);
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
void amdgpu_bo_unref(struct amdgpu_bo **bo);
int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
			     u64 min_offset, u64 max_offset,
			     u64 *gpu_addr);
int amdgpu_bo_unpin(struct amdgpu_bo *bo);
int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
int amdgpu_bo_init(struct amdgpu_device *adev);
void amdgpu_bo_fini(struct amdgpu_device *adev);
int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
				struct vm_area_struct *vma);
int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
			    uint32_t metadata_size, uint64_t flags);
int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
			   size_t buffer_size, uint32_t *metadata_size,
			   uint64_t *flags);
void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
				  struct ttm_mem_reg *new_mem);
int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
		     bool shared);

/*
 * sub allocation
 */

static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
{
	return sa_bo->manager->gpu_addr + sa_bo->soffset;
}

static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
{
	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
}

int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
				     struct amdgpu_sa_manager *sa_manager,
				     unsigned size, u32 align, u32 domain);
void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
				      struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
				      struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
					struct amdgpu_sa_manager *sa_manager);
int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
		     struct amdgpu_sa_bo **sa_bo,
		     unsigned size, unsigned align);
void amdgpu_sa_bo_free(struct amdgpu_device *adev,
			      struct amdgpu_sa_bo **sa_bo,
			      struct fence *fence);
#if defined(CONFIG_DEBUG_FS)
void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
					 struct seq_file *m);
#endif


#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#ifndef __AMDGPU_OBJECT_H__
	29	#define __AMDGPU_OBJECT_H__
	30
	31	#include <drm/amdgpu_drm.h>
	32	#include "amdgpu.h"
	33
	34	/**
	35	* amdgpu_mem_type_to_domain - return domain corresponding to mem_type
	36	* @mem_type: ttm memory type
	37	*
	38	* Returns corresponding domain of the ttm mem_type
	39	*/
	40	static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
	41	{
	42	switch (mem_type) {
	43	case TTM_PL_VRAM:
	44	return AMDGPU_GEM_DOMAIN_VRAM;
	45	case TTM_PL_TT:
	46	return AMDGPU_GEM_DOMAIN_GTT;
	47	case TTM_PL_SYSTEM:
	48	return AMDGPU_GEM_DOMAIN_CPU;
	49	case AMDGPU_PL_GDS:
	50	return AMDGPU_GEM_DOMAIN_GDS;
	51	case AMDGPU_PL_GWS:
	52	return AMDGPU_GEM_DOMAIN_GWS;
	53	case AMDGPU_PL_OA:
	54	return AMDGPU_GEM_DOMAIN_OA;
	55	default:
	56	break;
	57	}
	58	return 0;
	59	}
	60
	61	/**
	62	* amdgpu_bo_reserve - reserve bo
	63	* @bo: bo structure
	64	* @no_intr: don't return -ERESTARTSYS on pending signal
65	*
66	* Returns:
67	* -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
68	* a signal. Release all buffer reservations and return to user-space.
69	*/
70	static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
71	{
72	int r;
73
74	r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
75	if (unlikely(r != 0)) {
76	if (r != -ERESTARTSYS)
77	dev_err(bo->adev->dev, "%p reserve failed\n", bo);
78	return r;
79	}
80	return 0;
81	}
82
83	static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
84	{
85	ttm_bo_unreserve(&bo->tbo);
86	}
87
88	/**
89	* amdgpu_bo_gpu_offset - return GPU offset of bo
90	* @bo: amdgpu object for which we query the offset
91	*
92	* Returns current GPU offset of the object.
93	*
94	* Note: object should either be pinned or reserved when calling this
95	* function, it might be useful to add check for this for debugging.
96	*/
97	static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
98	{
191caba6	99	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
d38ceaf9 AD	100	return bo->tbo.offset;
	101	}
	102
	103	static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
	104	{
	105	return bo->tbo.num_pages << PAGE_SHIFT;
	106	}
	107
	108	static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
	109	{
	110	return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
	111	}
	112
	113	static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
	114	{
	115	return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
	116	}
	117
	118	/**
	119	* amdgpu_bo_mmap_offset - return mmap offset of bo
	120	* @bo: amdgpu object for which we query the offset
	121	*
	122	* Returns mmap offset of the object.
	123	*/
	124	static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
	125	{
	126	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
	127	}
	128
	129	int amdgpu_bo_create(struct amdgpu_device *adev,
	130	unsigned long size, int byte_align,
	131	bool kernel, u32 domain, u64 flags,
	132	struct sg_table *sg,
72d7668b	133	struct reservation_object *resv,
d38ceaf9	134	struct amdgpu_bo **bo_ptr);
7e5a547f CZ	135	int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
	136	unsigned long size, int byte_align,
	137	bool kernel, u32 domain, u64 flags,
	138	struct sg_table *sg,
	139	struct ttm_placement *placement,
72d7668b	140	struct reservation_object *resv,
7e5a547f	141	struct amdgpu_bo **bo_ptr);
d38ceaf9 AD	142	int amdgpu_bo_kmap(struct amdgpu_bo bo, void *ptr);
	143	void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
	144	struct amdgpu_bo amdgpu_bo_ref(struct amdgpu_bo bo);
	145	void amdgpu_bo_unref(struct amdgpu_bo **bo);
	146	int amdgpu_bo_pin(struct amdgpu_bo bo, u32 domain, u64 gpu_addr);
	147	int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
7e5a547f CZ	148	u64 min_offset, u64 max_offset,
7e5a547f CZ	149	u64 *gpu_addr);
d38ceaf9 AD	150	int amdgpu_bo_unpin(struct amdgpu_bo *bo);
d38ceaf9 AD	151	int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
d38ceaf9 AD	152	int amdgpu_bo_init(struct amdgpu_device *adev);
	153	void amdgpu_bo_fini(struct amdgpu_device *adev);
	154	int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
	155	struct vm_area_struct *vma);
	156	int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
	157	void amdgpu_bo_get_tiling_flags(struct amdgpu_bo bo, u64 tiling_flags);
	158	int amdgpu_bo_set_metadata (struct amdgpu_bo bo, void metadata,
	159	uint32_t metadata_size, uint64_t flags);
	160	int amdgpu_bo_get_metadata(struct amdgpu_bo bo, void buffer,
	161	size_t buffer_size, uint32_t *metadata_size,
	162	uint64_t *flags);
	163	void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
	164	struct ttm_mem_reg *new_mem);
	165	int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
e40a3115	166	void amdgpu_bo_fence(struct amdgpu_bo bo, struct fence fence,
d38ceaf9 AD	167	bool shared);
	168
	169	/*
	170	* sub allocation
	171	*/
	172
	173	static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
	174	{
	175	return sa_bo->manager->gpu_addr + sa_bo->soffset;
	176	}
	177
	178	static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
	179	{
	180	return sa_bo->manager->cpu_ptr + sa_bo->soffset;
	181	}
	182
	183	int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
	184	struct amdgpu_sa_manager *sa_manager,
	185	unsigned size, u32 align, u32 domain);
	186	void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
	187	struct amdgpu_sa_manager *sa_manager);
	188	int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
	189	struct amdgpu_sa_manager *sa_manager);
	190	int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
	191	struct amdgpu_sa_manager *sa_manager);
bbf0b345 JZ	192	int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
	193	struct amdgpu_sa_bo **sa_bo,
	194	unsigned size, unsigned align);
d38ceaf9 AD	195	void amdgpu_sa_bo_free(struct amdgpu_device *adev,
d38ceaf9 AD	196	struct amdgpu_sa_bo **sa_bo,
4ce9891e	197	struct fence *fence);
d38ceaf9 AD	198	#if defined(CONFIG_DEBUG_FS)
	199	void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
	200	struct seq_file *m);
	201	#endif
	202
	203
	204	#endif