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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pm.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23#include <drm/drmP.h>
24#include "amdgpu.h"
25#include "amdgpu_drv.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "atom.h"
29#include <linux/power_supply.h>
30#include <linux/hwmon.h>
31#include <linux/hwmon-sysfs.h>
32
1b5708ff
RZ		 33#include "amd_powerplay.h"
34
d38ceaf9
AD		 35static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
36
37void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
38{
e61710c5 39 if (adev->pp_enabled)
1b5708ff
RZ		 40 /* TODO */
41 return;
42
d38ceaf9
AD		 43 if (adev->pm.dpm_enabled) {
44 mutex_lock(&adev->pm.mutex);
45 if (power_supply_is_system_supplied() > 0)
46 adev->pm.dpm.ac_power = true;
47 else
48 adev->pm.dpm.ac_power = false;
49 if (adev->pm.funcs->enable_bapm)
50 amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
51 mutex_unlock(&adev->pm.mutex);
52 }
53}
54
55static ssize_t amdgpu_get_dpm_state(struct device *dev,
56 struct device_attribute *attr,
57 char *buf)
58{
59 struct drm_device *ddev = dev_get_drvdata(dev);
60 struct amdgpu_device *adev = ddev->dev_private;
1b5708ff
RZ		 61 enum amd_pm_state_type pm;
62
e61710c5 63 if (adev->pp_enabled) {
1b5708ff
RZ		 64 pm = amdgpu_dpm_get_current_power_state(adev);
65 } else
66 pm = adev->pm.dpm.user_state;
d38ceaf9
AD		 67
68 return snprintf(buf, PAGE_SIZE, "%s\n",
69 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
70 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
71}
72
73static ssize_t amdgpu_set_dpm_state(struct device *dev,
74 struct device_attribute *attr,
75 const char *buf,
76 size_t count)
77{
78 struct drm_device *ddev = dev_get_drvdata(dev);
79 struct amdgpu_device *adev = ddev->dev_private;
1b5708ff 80 enum amd_pm_state_type state;
d38ceaf9 81
d38ceaf9 82 if (strncmp("battery", buf, strlen("battery")) == 0)
1b5708ff 83 state = POWER_STATE_TYPE_BATTERY;
d38ceaf9 84 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
1b5708ff 85 state = POWER_STATE_TYPE_BALANCED;
d38ceaf9 86 else if (strncmp("performance", buf, strlen("performance")) == 0)
1b5708ff 87 state = POWER_STATE_TYPE_PERFORMANCE;
d38ceaf9 88 else {
d38ceaf9
AD		 89 count = -EINVAL;
90 goto fail;
91 }
d38ceaf9 92
e61710c5 93 if (adev->pp_enabled) {
1b5708ff
RZ		 94 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
95 } else {
96 mutex_lock(&adev->pm.mutex);
97 adev->pm.dpm.user_state = state;
98 mutex_unlock(&adev->pm.mutex);
99
100 /* Can't set dpm state when the card is off */
101 if (!(adev->flags & AMD_IS_PX) ||
102 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
103 amdgpu_pm_compute_clocks(adev);
104 }
d38ceaf9
AD		 105fail:
106 return count;
107}
108
109static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
1b5708ff
RZ		 110 struct device_attribute *attr,
111 char *buf)
d38ceaf9
AD		 112{
113 struct drm_device *ddev = dev_get_drvdata(dev);
114 struct amdgpu_device *adev = ddev->dev_private;
d38ceaf9 115
0c67df48
AD		 116 if ((adev->flags & AMD_IS_PX) &&
117 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
118 return snprintf(buf, PAGE_SIZE, "off\n");
119
e61710c5 120 if (adev->pp_enabled) {
1b5708ff
RZ		 121 enum amd_dpm_forced_level level;
122
123 level = amdgpu_dpm_get_performance_level(adev);
124 return snprintf(buf, PAGE_SIZE, "%s\n",
125 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
f3898ea1
EH		 126 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
127 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
128 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : "unknown");
1b5708ff
RZ		 129 } else {
130 enum amdgpu_dpm_forced_level level;
131
132 level = adev->pm.dpm.forced_level;
133 return snprintf(buf, PAGE_SIZE, "%s\n",
134 (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
135 (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
136 }
d38ceaf9
AD		 137}
138
139static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
140 struct device_attribute *attr,
141 const char *buf,
142 size_t count)
143{
144 struct drm_device *ddev = dev_get_drvdata(dev);
145 struct amdgpu_device *adev = ddev->dev_private;
146 enum amdgpu_dpm_forced_level level;
147 int ret = 0;
148
0c67df48
AD		 149 /* Can't force performance level when the card is off */
150 if ((adev->flags & AMD_IS_PX) &&
151 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
152 return -EINVAL;
153
d38ceaf9
AD		 154 if (strncmp("low", buf, strlen("low")) == 0) {
155 level = AMDGPU_DPM_FORCED_LEVEL_LOW;
156 } else if (strncmp("high", buf, strlen("high")) == 0) {
157 level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
158 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
159 level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
f3898ea1
EH		 160 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
161 level = AMDGPU_DPM_FORCED_LEVEL_MANUAL;
d38ceaf9
AD		 162 } else {
163 count = -EINVAL;
164 goto fail;
165 }
1b5708ff 166
e61710c5 167 if (adev->pp_enabled)
1b5708ff
RZ		 168 amdgpu_dpm_force_performance_level(adev, level);
169 else {
170 mutex_lock(&adev->pm.mutex);
d38ceaf9
AD		 171 if (adev->pm.dpm.thermal_active) {
172 count = -EINVAL;
10f950f6 173 mutex_unlock(&adev->pm.mutex);
d38ceaf9
AD		 174 goto fail;
175 }
176 ret = amdgpu_dpm_force_performance_level(adev, level);
177 if (ret)
178 count = -EINVAL;
1b5708ff
RZ		 179 else
180 adev->pm.dpm.forced_level = level;
181 mutex_unlock(&adev->pm.mutex);
d38ceaf9
AD		 182 }
183fail:
d38ceaf9
AD		 184 return count;
185}
186
f3898ea1
EH		 187static ssize_t amdgpu_get_pp_num_states(struct device *dev,
188 struct device_attribute *attr,
189 char *buf)
190{
191 struct drm_device *ddev = dev_get_drvdata(dev);
192 struct amdgpu_device *adev = ddev->dev_private;
193 struct pp_states_info data;
194 int i, buf_len;
195
196 if (adev->pp_enabled)
197 amdgpu_dpm_get_pp_num_states(adev, &data);
198
199 buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
200 for (i = 0; i < data.nums; i++)
201 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
202 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
203 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
204 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
205 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
206
207 return buf_len;
208}
209
210static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
211 struct device_attribute *attr,
212 char *buf)
213{
214 struct drm_device *ddev = dev_get_drvdata(dev);
215 struct amdgpu_device *adev = ddev->dev_private;
216 struct pp_states_info data;
217 enum amd_pm_state_type pm = 0;
218 int i = 0;
219
220 if (adev->pp_enabled) {
221
222 pm = amdgpu_dpm_get_current_power_state(adev);
223 amdgpu_dpm_get_pp_num_states(adev, &data);
224
225 for (i = 0; i < data.nums; i++) {
226 if (pm == data.states[i])
227 break;
228 }
229
230 if (i == data.nums)
231 i = -EINVAL;
232 }
233
234 return snprintf(buf, PAGE_SIZE, "%d\n", i);
235}
236
237static ssize_t amdgpu_get_pp_force_state(struct device *dev,
238 struct device_attribute *attr,
239 char *buf)
240{
241 struct drm_device *ddev = dev_get_drvdata(dev);
242 struct amdgpu_device *adev = ddev->dev_private;
243 struct pp_states_info data;
244 enum amd_pm_state_type pm = 0;
245 int i;
246
247 if (adev->pp_force_state_enabled && adev->pp_enabled) {
248 pm = amdgpu_dpm_get_current_power_state(adev);
249 amdgpu_dpm_get_pp_num_states(adev, &data);
250
251 for (i = 0; i < data.nums; i++) {
252 if (pm == data.states[i])
253 break;
254 }
255
256 if (i == data.nums)
257 i = -EINVAL;
258
259 return snprintf(buf, PAGE_SIZE, "%d\n", i);
260
261 } else
262 return snprintf(buf, PAGE_SIZE, "\n");
263}
264
265static ssize_t amdgpu_set_pp_force_state(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf,
268 size_t count)
269{
270 struct drm_device *ddev = dev_get_drvdata(dev);
271 struct amdgpu_device *adev = ddev->dev_private;
272 enum amd_pm_state_type state = 0;
041bf022 273 unsigned long idx;
f3898ea1
EH		 274 int ret;
275
276 if (strlen(buf) == 1)
277 adev->pp_force_state_enabled = false;
041bf022
DC		 278 else if (adev->pp_enabled) {
279 struct pp_states_info data;
f3898ea1 280
041bf022
DC		 281 ret = kstrtoul(buf, 0, &idx);
282 if (ret || idx >= ARRAY_SIZE(data.states)) {
f3898ea1
EH		 283 count = -EINVAL;
284 goto fail;
285 }
286
041bf022
DC		 287 amdgpu_dpm_get_pp_num_states(adev, &data);
288 state = data.states[idx];
289 /* only set user selected power states */
290 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
291 state != POWER_STATE_TYPE_DEFAULT) {
292 amdgpu_dpm_dispatch_task(adev,
293 AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
294 adev->pp_force_state_enabled = true;
f3898ea1
EH		 295 }
296 }
297fail:
298 return count;
299}
300
301static ssize_t amdgpu_get_pp_table(struct device *dev,
302 struct device_attribute *attr,
303 char *buf)
304{
305 struct drm_device *ddev = dev_get_drvdata(dev);
306 struct amdgpu_device *adev = ddev->dev_private;
307 char *table = NULL;
4f7ec157 308 int size;
f3898ea1
EH		 309
310 if (adev->pp_enabled)
311 size = amdgpu_dpm_get_pp_table(adev, &table);
312 else
313 return 0;
314
315 if (size >= PAGE_SIZE)
316 size = PAGE_SIZE - 1;
317
4f7ec157 318 memcpy(buf, table, size);
f3898ea1
EH		 319
320 return size;
321}
322
323static ssize_t amdgpu_set_pp_table(struct device *dev,
324 struct device_attribute *attr,
325 const char *buf,
326 size_t count)
327{
328 struct drm_device *ddev = dev_get_drvdata(dev);
329 struct amdgpu_device *adev = ddev->dev_private;
330
331 if (adev->pp_enabled)
332 amdgpu_dpm_set_pp_table(adev, buf, count);
333
334 return count;
335}
336
337static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
338 struct device_attribute *attr,
339 char *buf)
340{
341 struct drm_device *ddev = dev_get_drvdata(dev);
342 struct amdgpu_device *adev = ddev->dev_private;
343 ssize_t size = 0;
344
345 if (adev->pp_enabled)
346 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
c85e299f
EH		 347 else if (adev->pm.funcs->print_clock_levels)
348 size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
f3898ea1
EH		 349
350 return size;
351}
352
353static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
354 struct device_attribute *attr,
355 const char *buf,
356 size_t count)
357{
358 struct drm_device *ddev = dev_get_drvdata(dev);
359 struct amdgpu_device *adev = ddev->dev_private;
360 int ret;
361 long level;
5632708f
EH		 362 uint32_t i, mask = 0;
363 char sub_str[2];
f3898ea1 364
14b33074
EH		 365 for (i = 0; i < strlen(buf); i++) {
366 if (*(buf + i) == '\n')
367 continue;
5632708f
EH		 368 sub_str[0] = *(buf + i);
369 sub_str[1] = '\0';
370 ret = kstrtol(sub_str, 0, &level);
f3898ea1 371
5632708f
EH		 372 if (ret) {
373 count = -EINVAL;
374 goto fail;
375 }
376 mask |= 1 << level;
f3898ea1
EH		 377 }
378
379 if (adev->pp_enabled)
5632708f 380 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
c85e299f
EH		 381 else if (adev->pm.funcs->force_clock_level)
382 adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
f3898ea1
EH		 383fail:
384 return count;
385}
386
387static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
388 struct device_attribute *attr,
389 char *buf)
390{
391 struct drm_device *ddev = dev_get_drvdata(dev);
392 struct amdgpu_device *adev = ddev->dev_private;
393 ssize_t size = 0;
394
395 if (adev->pp_enabled)
396 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
c85e299f
EH		 397 else if (adev->pm.funcs->print_clock_levels)
398 size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
f3898ea1
EH		 399
400 return size;
401}
402
403static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
404 struct device_attribute *attr,
405 const char *buf,
406 size_t count)
407{
408 struct drm_device *ddev = dev_get_drvdata(dev);
409 struct amdgpu_device *adev = ddev->dev_private;
410 int ret;
411 long level;
5632708f
EH		 412 uint32_t i, mask = 0;
413 char sub_str[2];
f3898ea1 414
14b33074
EH		 415 for (i = 0; i < strlen(buf); i++) {
416 if (*(buf + i) == '\n')
417 continue;
5632708f
EH		 418 sub_str[0] = *(buf + i);
419 sub_str[1] = '\0';
420 ret = kstrtol(sub_str, 0, &level);
f3898ea1 421
5632708f
EH		 422 if (ret) {
423 count = -EINVAL;
424 goto fail;
425 }
426 mask |= 1 << level;
f3898ea1
EH		 427 }
428
429 if (adev->pp_enabled)
5632708f 430 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
c85e299f
EH		 431 else if (adev->pm.funcs->force_clock_level)
432 adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
f3898ea1
EH		 433fail:
434 return count;
435}
436
437static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
438 struct device_attribute *attr,
439 char *buf)
440{
441 struct drm_device *ddev = dev_get_drvdata(dev);
442 struct amdgpu_device *adev = ddev->dev_private;
443 ssize_t size = 0;
444
445 if (adev->pp_enabled)
446 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
c85e299f
EH		 447 else if (adev->pm.funcs->print_clock_levels)
448 size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
f3898ea1
EH		 449
450 return size;
451}
452
453static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
454 struct device_attribute *attr,
455 const char *buf,
456 size_t count)
457{
458 struct drm_device *ddev = dev_get_drvdata(dev);
459 struct amdgpu_device *adev = ddev->dev_private;
460 int ret;
461 long level;
5632708f
EH		 462 uint32_t i, mask = 0;
463 char sub_str[2];
f3898ea1 464
14b33074
EH		 465 for (i = 0; i < strlen(buf); i++) {
466 if (*(buf + i) == '\n')
467 continue;
5632708f
EH		 468 sub_str[0] = *(buf + i);
469 sub_str[1] = '\0';
470 ret = kstrtol(sub_str, 0, &level);
f3898ea1 471
5632708f
EH		 472 if (ret) {
473 count = -EINVAL;
474 goto fail;
475 }
476 mask |= 1 << level;
f3898ea1
EH		 477 }
478
479 if (adev->pp_enabled)
5632708f 480 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
c85e299f
EH		 481 else if (adev->pm.funcs->force_clock_level)
482 adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
f3898ea1
EH		 483fail:
484 return count;
485}
486
428bafa8
EH		 487static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
488 struct device_attribute *attr,
489 char *buf)
490{
491 struct drm_device *ddev = dev_get_drvdata(dev);
492 struct amdgpu_device *adev = ddev->dev_private;
493 uint32_t value = 0;
494
495 if (adev->pp_enabled)
496 value = amdgpu_dpm_get_sclk_od(adev);
8b2e574d
EH		 497 else if (adev->pm.funcs->get_sclk_od)
498 value = adev->pm.funcs->get_sclk_od(adev);
428bafa8
EH		 499
500 return snprintf(buf, PAGE_SIZE, "%d\n", value);
501}
502
503static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
504 struct device_attribute *attr,
505 const char *buf,
506 size_t count)
507{
508 struct drm_device *ddev = dev_get_drvdata(dev);
509 struct amdgpu_device *adev = ddev->dev_private;
510 int ret;
511 long int value;
512
513 ret = kstrtol(buf, 0, &value);
514
515 if (ret) {
516 count = -EINVAL;
517 goto fail;
518 }
519
8b2e574d 520 if (adev->pp_enabled) {
428bafa8 521 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
8b2e574d
EH		 522 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
523 } else if (adev->pm.funcs->set_sclk_od) {
524 adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
525 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
526 amdgpu_pm_compute_clocks(adev);
527 }
428bafa8
EH		 528
529fail:
530 return count;
531}
532
f2bdc05f
EH		 533static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
534 struct device_attribute *attr,
535 char *buf)
536{
537 struct drm_device *ddev = dev_get_drvdata(dev);
538 struct amdgpu_device *adev = ddev->dev_private;
539 uint32_t value = 0;
540
541 if (adev->pp_enabled)
542 value = amdgpu_dpm_get_mclk_od(adev);
543 else if (adev->pm.funcs->get_mclk_od)
544 value = adev->pm.funcs->get_mclk_od(adev);
545
546 return snprintf(buf, PAGE_SIZE, "%d\n", value);
547}
548
549static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
550 struct device_attribute *attr,
551 const char *buf,
552 size_t count)
553{
554 struct drm_device *ddev = dev_get_drvdata(dev);
555 struct amdgpu_device *adev = ddev->dev_private;
556 int ret;
557 long int value;
558
559 ret = kstrtol(buf, 0, &value);
560
561 if (ret) {
562 count = -EINVAL;
563 goto fail;
564 }
565
566 if (adev->pp_enabled) {
567 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
568 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
569 } else if (adev->pm.funcs->set_mclk_od) {
570 adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
571 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
572 amdgpu_pm_compute_clocks(adev);
573 }
574
575fail:
576 return count;
577}
578
d38ceaf9
AD		 579static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
580static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
581 amdgpu_get_dpm_forced_performance_level,
582 amdgpu_set_dpm_forced_performance_level);
f3898ea1
EH		 583static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
584static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
585static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
586 amdgpu_get_pp_force_state,
587 amdgpu_set_pp_force_state);
588static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
589 amdgpu_get_pp_table,
590 amdgpu_set_pp_table);
591static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
592 amdgpu_get_pp_dpm_sclk,
593 amdgpu_set_pp_dpm_sclk);
594static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
595 amdgpu_get_pp_dpm_mclk,
596 amdgpu_set_pp_dpm_mclk);
597static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
598 amdgpu_get_pp_dpm_pcie,
599 amdgpu_set_pp_dpm_pcie);
428bafa8
EH		 600static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
601 amdgpu_get_pp_sclk_od,
602 amdgpu_set_pp_sclk_od);
f2bdc05f
EH		 603static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
604 amdgpu_get_pp_mclk_od,
605 amdgpu_set_pp_mclk_od);
d38ceaf9
AD		 606
607static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
608 struct device_attribute *attr,
609 char *buf)
610{
611 struct amdgpu_device *adev = dev_get_drvdata(dev);
0c67df48 612 struct drm_device *ddev = adev->ddev;
d38ceaf9
AD		 613 int temp;
614
0c67df48
AD		 615 /* Can't get temperature when the card is off */
616 if ((adev->flags & AMD_IS_PX) &&
617 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
618 return -EINVAL;
619
e61710c5 620 if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
d38ceaf9 621 temp = 0;
8804b8d5
RZ		 622 else
623 temp = amdgpu_dpm_get_temperature(adev);
d38ceaf9
AD		 624
625 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
626}
627
628static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
629 struct device_attribute *attr,
630 char *buf)
631{
632 struct amdgpu_device *adev = dev_get_drvdata(dev);
633 int hyst = to_sensor_dev_attr(attr)->index;
634 int temp;
635
636 if (hyst)
637 temp = adev->pm.dpm.thermal.min_temp;
638 else
639 temp = adev->pm.dpm.thermal.max_temp;
640
641 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
642}
643
644static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
645 struct device_attribute *attr,
646 char *buf)
647{
648 struct amdgpu_device *adev = dev_get_drvdata(dev);
649 u32 pwm_mode = 0;
650
e61710c5 651 if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
8804b8d5
RZ		 652 return -EINVAL;
653
654 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
d38ceaf9
AD		 655
656 /* never 0 (full-speed), fuse or smc-controlled always */
657 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
658}
659
660static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
661 struct device_attribute *attr,
662 const char *buf,
663 size_t count)
664{
665 struct amdgpu_device *adev = dev_get_drvdata(dev);
666 int err;
667 int value;
668
e61710c5 669 if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
d38ceaf9
AD		 670 return -EINVAL;
671
672 err = kstrtoint(buf, 10, &value);
673 if (err)
674 return err;
675
676 switch (value) {
677 case 1: /* manual, percent-based */
678 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
679 break;
680 default: /* disable */
681 amdgpu_dpm_set_fan_control_mode(adev, 0);
682 break;
683 }
684
685 return count;
686}
687
688static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
689 struct device_attribute *attr,
690 char *buf)
691{
692 return sprintf(buf, "%i\n", 0);
693}
694
695static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
696 struct device_attribute *attr,
697 char *buf)
698{
699 return sprintf(buf, "%i\n", 255);
700}
701
702static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
703 struct device_attribute *attr,
704 const char *buf, size_t count)
705{
706 struct amdgpu_device *adev = dev_get_drvdata(dev);
707 int err;
708 u32 value;
709
710 err = kstrtou32(buf, 10, &value);
711 if (err)
712 return err;
713
714 value = (value * 100) / 255;
715
716 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
717 if (err)
718 return err;
719
720 return count;
721}
722
723static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
724 struct device_attribute *attr,
725 char *buf)
726{
727 struct amdgpu_device *adev = dev_get_drvdata(dev);
728 int err;
729 u32 speed;
730
731 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
732 if (err)
733 return err;
734
735 speed = (speed * 255) / 100;
736
737 return sprintf(buf, "%i\n", speed);
738}
739
740static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
741static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
742static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
743static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
744static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
745static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
746static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
747
748static struct attribute *hwmon_attributes[] = {
749 &sensor_dev_attr_temp1_input.dev_attr.attr,
750 &sensor_dev_attr_temp1_crit.dev_attr.attr,
751 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
752 &sensor_dev_attr_pwm1.dev_attr.attr,
753 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
754 &sensor_dev_attr_pwm1_min.dev_attr.attr,
755 &sensor_dev_attr_pwm1_max.dev_attr.attr,
756 NULL
757};
758
759static umode_t hwmon_attributes_visible(struct kobject *kobj,
760 struct attribute *attr, int index)
761{
cc29ec87 762 struct device *dev = kobj_to_dev(kobj);
d38ceaf9
AD		 763 struct amdgpu_device *adev = dev_get_drvdata(dev);
764 umode_t effective_mode = attr->mode;
765
1b5708ff 766 /* Skip limit attributes if DPM is not enabled */
d38ceaf9
AD		 767 if (!adev->pm.dpm_enabled &&
768 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
27100735
AD		 769 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
770 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
771 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
772 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
773 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
d38ceaf9
AD		 774 return 0;
775
e61710c5 776 if (adev->pp_enabled)
8804b8d5
RZ		 777 return effective_mode;
778
d38ceaf9
AD		 779 /* Skip fan attributes if fan is not present */
780 if (adev->pm.no_fan &&
781 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
782 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
783 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
784 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
785 return 0;
786
787 /* mask fan attributes if we have no bindings for this asic to expose */
788 if ((!adev->pm.funcs->get_fan_speed_percent &&
789 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
790 (!adev->pm.funcs->get_fan_control_mode &&
791 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
792 effective_mode &= ~S_IRUGO;
793
794 if ((!adev->pm.funcs->set_fan_speed_percent &&
795 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
796 (!adev->pm.funcs->set_fan_control_mode &&
797 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
798 effective_mode &= ~S_IWUSR;
799
800 /* hide max/min values if we can't both query and manage the fan */
801 if ((!adev->pm.funcs->set_fan_speed_percent &&
802 !adev->pm.funcs->get_fan_speed_percent) &&
803 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
804 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
805 return 0;
806
807 return effective_mode;
808}
809
810static const struct attribute_group hwmon_attrgroup = {
811 .attrs = hwmon_attributes,
812 .is_visible = hwmon_attributes_visible,
813};
814
815static const struct attribute_group *hwmon_groups[] = {
816 &hwmon_attrgroup,
817 NULL
818};
819
820void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
821{
822 struct amdgpu_device *adev =
823 container_of(work, struct amdgpu_device,
824 pm.dpm.thermal.work);
825 /* switch to the thermal state */
3a2c788d 826 enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
d38ceaf9
AD		 827
828 if (!adev->pm.dpm_enabled)
829 return;
830
831 if (adev->pm.funcs->get_temperature) {
832 int temp = amdgpu_dpm_get_temperature(adev);
833
834 if (temp < adev->pm.dpm.thermal.min_temp)
835 /* switch back the user state */
836 dpm_state = adev->pm.dpm.user_state;
837 } else {
838 if (adev->pm.dpm.thermal.high_to_low)
839 /* switch back the user state */
840 dpm_state = adev->pm.dpm.user_state;
841 }
842 mutex_lock(&adev->pm.mutex);
843 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
844 adev->pm.dpm.thermal_active = true;
845 else
846 adev->pm.dpm.thermal_active = false;
847 adev->pm.dpm.state = dpm_state;
848 mutex_unlock(&adev->pm.mutex);
849
850 amdgpu_pm_compute_clocks(adev);
851}
852
853static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
3a2c788d 854 enum amd_pm_state_type dpm_state)
d38ceaf9
AD		 855{
856 int i;
857 struct amdgpu_ps *ps;
858 u32 ui_class;
859 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
860 true : false;
861
862 /* check if the vblank period is too short to adjust the mclk */
863 if (single_display && adev->pm.funcs->vblank_too_short) {
864 if (amdgpu_dpm_vblank_too_short(adev))
865 single_display = false;
866 }
867
868 /* certain older asics have a separare 3D performance state,
869 * so try that first if the user selected performance
870 */
871 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
872 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
873 /* balanced states don't exist at the moment */
874 if (dpm_state == POWER_STATE_TYPE_BALANCED)
875 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
876
877restart_search:
878 /* Pick the best power state based on current conditions */
879 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
880 ps = &adev->pm.dpm.ps[i];
881 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
882 switch (dpm_state) {
883 /* user states */
884 case POWER_STATE_TYPE_BATTERY:
885 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
886 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
887 if (single_display)
888 return ps;
889 } else
890 return ps;
891 }
892 break;
893 case POWER_STATE_TYPE_BALANCED:
894 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
895 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
896 if (single_display)
897 return ps;
898 } else
899 return ps;
900 }
901 break;
902 case POWER_STATE_TYPE_PERFORMANCE:
903 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
904 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
905 if (single_display)
906 return ps;
907 } else
908 return ps;
909 }
910 break;
911 /* internal states */
912 case POWER_STATE_TYPE_INTERNAL_UVD:
913 if (adev->pm.dpm.uvd_ps)
914 return adev->pm.dpm.uvd_ps;
915 else
916 break;
917 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
918 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
919 return ps;
920 break;
921 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
922 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
923 return ps;
924 break;
925 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
926 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
927 return ps;
928 break;
929 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
930 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
931 return ps;
932 break;
933 case POWER_STATE_TYPE_INTERNAL_BOOT:
934 return adev->pm.dpm.boot_ps;
935 case POWER_STATE_TYPE_INTERNAL_THERMAL:
936 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
937 return ps;
938 break;
939 case POWER_STATE_TYPE_INTERNAL_ACPI:
940 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
941 return ps;
942 break;
943 case POWER_STATE_TYPE_INTERNAL_ULV:
944 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
945 return ps;
946 break;
947 case POWER_STATE_TYPE_INTERNAL_3DPERF:
948 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
949 return ps;
950 break;
951 default:
952 break;
953 }
954 }
955 /* use a fallback state if we didn't match */
956 switch (dpm_state) {
957 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
958 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
959 goto restart_search;
960 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
961 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
962 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
963 if (adev->pm.dpm.uvd_ps) {
964 return adev->pm.dpm.uvd_ps;
965 } else {
966 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
967 goto restart_search;
968 }
969 case POWER_STATE_TYPE_INTERNAL_THERMAL:
970 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
971 goto restart_search;
972 case POWER_STATE_TYPE_INTERNAL_ACPI:
973 dpm_state = POWER_STATE_TYPE_BATTERY;
974 goto restart_search;
975 case POWER_STATE_TYPE_BATTERY:
976 case POWER_STATE_TYPE_BALANCED:
977 case POWER_STATE_TYPE_INTERNAL_3DPERF:
978 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
979 goto restart_search;
980 default:
981 break;
982 }
983
984 return NULL;
985}
986
987static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
988{
989 int i;
990 struct amdgpu_ps *ps;
3a2c788d 991 enum amd_pm_state_type dpm_state;
d38ceaf9
AD		 992 int ret;
993
994 /* if dpm init failed */
995 if (!adev->pm.dpm_enabled)
996 return;
997
998 if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
999 /* add other state override checks here */
1000 if ((!adev->pm.dpm.thermal_active) &&
1001 (!adev->pm.dpm.uvd_active))
1002 adev->pm.dpm.state = adev->pm.dpm.user_state;
1003 }
1004 dpm_state = adev->pm.dpm.state;
1005
1006 ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1007 if (ps)
1008 adev->pm.dpm.requested_ps = ps;
1009 else
1010 return;
1011
1012 /* no need to reprogram if nothing changed unless we are on BTC+ */
1013 if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) {
1014 /* vce just modifies an existing state so force a change */
1015 if (ps->vce_active != adev->pm.dpm.vce_active)
1016 goto force;
2f7d10b3 1017 if (adev->flags & AMD_IS_APU) {
d38ceaf9
AD		 1018 /* for APUs if the num crtcs changed but state is the same,
1019 * all we need to do is update the display configuration.
1020 */
1021 if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) {
1022 /* update display watermarks based on new power state */
1023 amdgpu_display_bandwidth_update(adev);
1024 /* update displays */
1025 amdgpu_dpm_display_configuration_changed(adev);
1026 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1027 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1028 }
1029 return;
1030 } else {
1031 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1032 * nothing to do, if the num crtcs is > 1 and state is the same,
1033 * update display configuration.
1034 */
1035 if (adev->pm.dpm.new_active_crtcs ==
1036 adev->pm.dpm.current_active_crtcs) {
1037 return;
1038 } else if ((adev->pm.dpm.current_active_crtc_count > 1) &&
1039 (adev->pm.dpm.new_active_crtc_count > 1)) {
1040 /* update display watermarks based on new power state */
1041 amdgpu_display_bandwidth_update(adev);
1042 /* update displays */
1043 amdgpu_dpm_display_configuration_changed(adev);
1044 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1045 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1046 return;
1047 }
1048 }
1049 }
1050
1051force:
1052 if (amdgpu_dpm == 1) {
1053 printk("switching from power state:\n");
1054 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1055 printk("switching to power state:\n");
1056 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1057 }
1058
d38ceaf9
AD		 1059 /* update whether vce is active */
1060 ps->vce_active = adev->pm.dpm.vce_active;
1061
1062 ret = amdgpu_dpm_pre_set_power_state(adev);
1063 if (ret)
a27de35c 1064 return;
d38ceaf9
AD		 1065
1066 /* update display watermarks based on new power state */
1067 amdgpu_display_bandwidth_update(adev);
d38ceaf9
AD		 1068
1069 /* wait for the rings to drain */
1070 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1071 struct amdgpu_ring *ring = adev->rings[i];
1072 if (ring && ring->ready)
1073 amdgpu_fence_wait_empty(ring);
1074 }
1075
1076 /* program the new power state */
1077 amdgpu_dpm_set_power_state(adev);
1078
1079 /* update current power state */
1080 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps;
1081
1082 amdgpu_dpm_post_set_power_state(adev);
1083
8e7cedc6
AD		 1084 /* update displays */
1085 amdgpu_dpm_display_configuration_changed(adev);
1086
eda1d1cf
AD		 1087 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1088 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1089
d38ceaf9
AD		 1090 if (adev->pm.funcs->force_performance_level) {
1091 if (adev->pm.dpm.thermal_active) {
1092 enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
1093 /* force low perf level for thermal */
1094 amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW);
1095 /* save the user's level */
1096 adev->pm.dpm.forced_level = level;
1097 } else {
1098 /* otherwise, user selected level */
1099 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1100 }
1101 }
d38ceaf9
AD		 1102}
1103
1104void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1105{
e61710c5 1106 if (adev->pp_enabled)
d38ceaf9 1107 amdgpu_dpm_powergate_uvd(adev, !enable);
1b5708ff
RZ		 1108 else {
1109 if (adev->pm.funcs->powergate_uvd) {
d38ceaf9 1110 mutex_lock(&adev->pm.mutex);
1b5708ff
RZ		 1111 /* enable/disable UVD */
1112 amdgpu_dpm_powergate_uvd(adev, !enable);
d38ceaf9
AD		 1113 mutex_unlock(&adev->pm.mutex);
1114 } else {
1b5708ff
RZ		 1115 if (enable) {
1116 mutex_lock(&adev->pm.mutex);
1117 adev->pm.dpm.uvd_active = true;
1118 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1119 mutex_unlock(&adev->pm.mutex);
1120 } else {
1121 mutex_lock(&adev->pm.mutex);
1122 adev->pm.dpm.uvd_active = false;
1123 mutex_unlock(&adev->pm.mutex);
1124 }
1125 amdgpu_pm_compute_clocks(adev);
d38ceaf9
AD		 1126 }
1127
d38ceaf9
AD		 1128 }
1129}
1130
1131void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1132{
e61710c5 1133 if (adev->pp_enabled)
b7a07769 1134 amdgpu_dpm_powergate_vce(adev, !enable);
1b5708ff
RZ		 1135 else {
1136 if (adev->pm.funcs->powergate_vce) {
b7a07769 1137 mutex_lock(&adev->pm.mutex);
1b5708ff 1138 amdgpu_dpm_powergate_vce(adev, !enable);
b7a07769
SJ		 1139 mutex_unlock(&adev->pm.mutex);
1140 } else {
1b5708ff
RZ		 1141 if (enable) {
1142 mutex_lock(&adev->pm.mutex);
1143 adev->pm.dpm.vce_active = true;
1144 /* XXX select vce level based on ring/task */
1145 adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
1146 mutex_unlock(&adev->pm.mutex);
1147 } else {
1148 mutex_lock(&adev->pm.mutex);
1149 adev->pm.dpm.vce_active = false;
1150 mutex_unlock(&adev->pm.mutex);
1151 }
1152 amdgpu_pm_compute_clocks(adev);
b7a07769 1153 }
b7a07769 1154 }
d38ceaf9
AD		 1155}
1156
1157void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1158{
1159 int i;
1160
e61710c5 1161 if (adev->pp_enabled)
1b5708ff
RZ		 1162 /* TO DO */
1163 return;
1164
1165 for (i = 0; i < adev->pm.dpm.num_ps; i++)
d38ceaf9 1166 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1b5708ff 1167
d38ceaf9
AD		 1168}
1169
1170int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1171{
1172 int ret;
1173
c86f5ebf
AD		 1174 if (adev->pm.sysfs_initialized)
1175 return 0;
1176
e61710c5 1177 if (!adev->pp_enabled) {
1b5708ff
RZ		 1178 if (adev->pm.funcs->get_temperature == NULL)
1179 return 0;
1180 }
1181
d38ceaf9
AD		 1182 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1183 DRIVER_NAME, adev,
1184 hwmon_groups);
1185 if (IS_ERR(adev->pm.int_hwmon_dev)) {
1186 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1187 dev_err(adev->dev,
1188 "Unable to register hwmon device: %d\n", ret);
1189 return ret;
1190 }
1191
1192 ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1193 if (ret) {
1194 DRM_ERROR("failed to create device file for dpm state\n");
1195 return ret;
1196 }
1197 ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1198 if (ret) {
1199 DRM_ERROR("failed to create device file for dpm state\n");
1200 return ret;
1201 }
f3898ea1
EH		 1202
1203 if (adev->pp_enabled) {
1204 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1205 if (ret) {
1206 DRM_ERROR("failed to create device file pp_num_states\n");
1207 return ret;
1208 }
1209 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1210 if (ret) {
1211 DRM_ERROR("failed to create device file pp_cur_state\n");
1212 return ret;
1213 }
1214 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1215 if (ret) {
1216 DRM_ERROR("failed to create device file pp_force_state\n");
1217 return ret;
1218 }
1219 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1220 if (ret) {
1221 DRM_ERROR("failed to create device file pp_table\n");
1222 return ret;
1223 }
f3898ea1 1224 }
c85e299f
EH		 1225
1226 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1227 if (ret) {
1228 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1229 return ret;
1230 }
1231 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1232 if (ret) {
1233 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1234 return ret;
1235 }
1236 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1237 if (ret) {
1238 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1239 return ret;
1240 }
8b2e574d
EH		 1241 ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1242 if (ret) {
1243 DRM_ERROR("failed to create device file pp_sclk_od\n");
1244 return ret;
1245 }
f2bdc05f
EH		 1246 ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1247 if (ret) {
1248 DRM_ERROR("failed to create device file pp_mclk_od\n");
1249 return ret;
1250 }
c85e299f 1251
d38ceaf9
AD		 1252 ret = amdgpu_debugfs_pm_init(adev);
1253 if (ret) {
1254 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1255 return ret;
1256 }
1257
c86f5ebf
AD		 1258 adev->pm.sysfs_initialized = true;
1259
d38ceaf9
AD		 1260 return 0;
1261}
1262
1263void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1264{
1265 if (adev->pm.int_hwmon_dev)
1266 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1267 device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1268 device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
f3898ea1
EH		 1269 if (adev->pp_enabled) {
1270 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1271 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1272 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1273 device_remove_file(adev->dev, &dev_attr_pp_table);
f3898ea1 1274 }
c85e299f
EH		 1275 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1276 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1277 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
8b2e574d 1278 device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
f2bdc05f 1279 device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
d38ceaf9
AD		 1280}
1281
1282void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1283{
1284 struct drm_device *ddev = adev->ddev;
1285 struct drm_crtc *crtc;
1286 struct amdgpu_crtc *amdgpu_crtc;
1287
1288 if (!adev->pm.dpm_enabled)
1289 return;
1290
e61710c5 1291 if (adev->pp_enabled) {
1b5708ff
RZ		 1292 int i = 0;
1293
1294 amdgpu_display_bandwidth_update(adev);
a27de35c
CK		 1295 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1296 struct amdgpu_ring *ring = adev->rings[i];
1297 if (ring && ring->ready)
1298 amdgpu_fence_wait_empty(ring);
1299 }
d38ceaf9 1300
1b5708ff
RZ		 1301 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1302 } else {
1303 mutex_lock(&adev->pm.mutex);
1304 adev->pm.dpm.new_active_crtcs = 0;
1305 adev->pm.dpm.new_active_crtc_count = 0;
1306 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1307 list_for_each_entry(crtc,
1308 &ddev->mode_config.crtc_list, head) {
1309 amdgpu_crtc = to_amdgpu_crtc(crtc);
1310 if (crtc->enabled) {
1311 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1312 adev->pm.dpm.new_active_crtc_count++;
1313 }
d38ceaf9
AD		 1314 }
1315 }
1b5708ff
RZ		 1316 /* update battery/ac status */
1317 if (power_supply_is_system_supplied() > 0)
1318 adev->pm.dpm.ac_power = true;
1319 else
1320 adev->pm.dpm.ac_power = false;
d38ceaf9 1321
1b5708ff 1322 amdgpu_dpm_change_power_state_locked(adev);
d38ceaf9 1323
1b5708ff
RZ		 1324 mutex_unlock(&adev->pm.mutex);
1325 }
d38ceaf9
AD		 1326}
1327
1328/*
1329 * Debugfs info
1330 */
1331#if defined(CONFIG_DEBUG_FS)
1332
1333static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1334{
1335 struct drm_info_node *node = (struct drm_info_node *) m->private;
1336 struct drm_device *dev = node->minor->dev;
1337 struct amdgpu_device *adev = dev->dev_private;
0c67df48 1338 struct drm_device *ddev = adev->ddev;
d38ceaf9 1339
1b5708ff
RZ		 1340 if (!adev->pm.dpm_enabled) {
1341 seq_printf(m, "dpm not enabled\n");
1342 return 0;
1343 }
0c67df48
AD		 1344 if ((adev->flags & AMD_IS_PX) &&
1345 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1346 seq_printf(m, "PX asic powered off\n");
1347 } else if (adev->pp_enabled) {
1b5708ff
RZ		 1348 amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1349 } else {
d38ceaf9
AD		 1350 mutex_lock(&adev->pm.mutex);
1351 if (adev->pm.funcs->debugfs_print_current_performance_level)
1352 amdgpu_dpm_debugfs_print_current_performance_level(adev, m);
1353 else
1354 seq_printf(m, "Debugfs support not implemented for this asic\n");
1355 mutex_unlock(&adev->pm.mutex);
1356 }
1357
1358 return 0;
1359}
1360
06ab6832 1361static const struct drm_info_list amdgpu_pm_info_list[] = {
d38ceaf9
AD		 1362 {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1363};
1364#endif
1365
1366static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1367{
1368#if defined(CONFIG_DEBUG_FS)
1369 return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1370#else
1371 return 0;
1372#endif
1373}
Linux kernel - Deliverables
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