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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | * Christian König | |
28 | */ | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/slab.h> | |
4f4824b5 | 31 | #include <linux/debugfs.h> |
d38ceaf9 AD |
32 | #include <drm/drmP.h> |
33 | #include <drm/amdgpu_drm.h> | |
34 | #include "amdgpu.h" | |
35 | #include "atom.h" | |
36 | ||
37 | /* | |
38 | * Rings | |
39 | * Most engines on the GPU are fed via ring buffers. Ring | |
40 | * buffers are areas of GPU accessible memory that the host | |
41 | * writes commands into and the GPU reads commands out of. | |
42 | * There is a rptr (read pointer) that determines where the | |
43 | * GPU is currently reading, and a wptr (write pointer) | |
44 | * which determines where the host has written. When the | |
45 | * pointers are equal, the ring is idle. When the host | |
46 | * writes commands to the ring buffer, it increments the | |
47 | * wptr. The GPU then starts fetching commands and executes | |
48 | * them until the pointers are equal again. | |
49 | */ | |
eb430969 CK |
50 | static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, |
51 | struct amdgpu_ring *ring); | |
a909c6bd | 52 | static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring); |
d38ceaf9 | 53 | |
d38ceaf9 AD |
54 | /** |
55 | * amdgpu_ring_alloc - allocate space on the ring buffer | |
56 | * | |
57 | * @adev: amdgpu_device pointer | |
58 | * @ring: amdgpu_ring structure holding ring information | |
59 | * @ndw: number of dwords to allocate in the ring buffer | |
60 | * | |
61 | * Allocate @ndw dwords in the ring buffer (all asics). | |
62 | * Returns 0 on success, error on failure. | |
63 | */ | |
64 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) | |
65 | { | |
d38ceaf9 AD |
66 | /* Align requested size with padding so unlock_commit can |
67 | * pad safely */ | |
d38ceaf9 | 68 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
c7e6be23 CK |
69 | |
70 | /* Make sure we aren't trying to allocate more space | |
71 | * than the maximum for one submission | |
72 | */ | |
73 | if (WARN_ON_ONCE(ndw > ring->max_dw)) | |
74 | return -ENOMEM; | |
75 | ||
d38ceaf9 AD |
76 | ring->count_dw = ndw; |
77 | ring->wptr_old = ring->wptr; | |
f06505b8 CK |
78 | |
79 | if (ring->funcs->begin_use) | |
80 | ring->funcs->begin_use(ring); | |
81 | ||
d38ceaf9 AD |
82 | return 0; |
83 | } | |
84 | ||
edff0e28 JZ |
85 | /** amdgpu_ring_insert_nop - insert NOP packets |
86 | * | |
87 | * @ring: amdgpu_ring structure holding ring information | |
88 | * @count: the number of NOP packets to insert | |
89 | * | |
90 | * This is the generic insert_nop function for rings except SDMA | |
91 | */ | |
92 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) | |
93 | { | |
94 | int i; | |
95 | ||
96 | for (i = 0; i < count; i++) | |
97 | amdgpu_ring_write(ring, ring->nop); | |
98 | } | |
99 | ||
9e5d5309 CK |
100 | /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets |
101 | * | |
102 | * @ring: amdgpu_ring structure holding ring information | |
103 | * @ib: IB to add NOP packets to | |
104 | * | |
105 | * This is the generic pad_ib function for rings except SDMA | |
106 | */ | |
107 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) | |
108 | { | |
109 | while (ib->length_dw & ring->align_mask) | |
110 | ib->ptr[ib->length_dw++] = ring->nop; | |
111 | } | |
112 | ||
d38ceaf9 AD |
113 | /** |
114 | * amdgpu_ring_commit - tell the GPU to execute the new | |
115 | * commands on the ring buffer | |
116 | * | |
117 | * @adev: amdgpu_device pointer | |
118 | * @ring: amdgpu_ring structure holding ring information | |
119 | * | |
120 | * Update the wptr (write pointer) to tell the GPU to | |
121 | * execute new commands on the ring buffer (all asics). | |
122 | */ | |
123 | void amdgpu_ring_commit(struct amdgpu_ring *ring) | |
124 | { | |
edff0e28 JZ |
125 | uint32_t count; |
126 | ||
d38ceaf9 | 127 | /* We pad to match fetch size */ |
edff0e28 JZ |
128 | count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); |
129 | count %= ring->align_mask + 1; | |
130 | ring->funcs->insert_nop(ring, count); | |
131 | ||
d38ceaf9 AD |
132 | mb(); |
133 | amdgpu_ring_set_wptr(ring); | |
f06505b8 CK |
134 | |
135 | if (ring->funcs->end_use) | |
136 | ring->funcs->end_use(ring); | |
d38ceaf9 AD |
137 | } |
138 | ||
d38ceaf9 AD |
139 | /** |
140 | * amdgpu_ring_undo - reset the wptr | |
141 | * | |
142 | * @ring: amdgpu_ring structure holding ring information | |
143 | * | |
144 | * Reset the driver's copy of the wptr (all asics). | |
145 | */ | |
146 | void amdgpu_ring_undo(struct amdgpu_ring *ring) | |
147 | { | |
148 | ring->wptr = ring->wptr_old; | |
f06505b8 CK |
149 | |
150 | if (ring->funcs->end_use) | |
151 | ring->funcs->end_use(ring); | |
d38ceaf9 AD |
152 | } |
153 | ||
d38ceaf9 AD |
154 | /** |
155 | * amdgpu_ring_init - init driver ring struct. | |
156 | * | |
157 | * @adev: amdgpu_device pointer | |
158 | * @ring: amdgpu_ring structure holding ring information | |
a3f1cf35 | 159 | * @max_ndw: maximum number of dw for ring alloc |
d38ceaf9 AD |
160 | * @nop: nop packet for this ring |
161 | * | |
162 | * Initialize the driver information for the selected ring (all asics). | |
163 | * Returns 0 on success, error on failure. | |
164 | */ | |
165 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
a3f1cf35 | 166 | unsigned max_dw, u32 nop, u32 align_mask, |
d38ceaf9 AD |
167 | struct amdgpu_irq_src *irq_src, unsigned irq_type, |
168 | enum amdgpu_ring_type ring_type) | |
169 | { | |
d38ceaf9 AD |
170 | int r; |
171 | ||
172 | if (ring->adev == NULL) { | |
173 | if (adev->num_rings >= AMDGPU_MAX_RINGS) | |
174 | return -EINVAL; | |
175 | ||
176 | ring->adev = adev; | |
177 | ring->idx = adev->num_rings++; | |
178 | adev->rings[ring->idx] = ring; | |
e6151a08 CK |
179 | r = amdgpu_fence_driver_init_ring(ring, |
180 | amdgpu_sched_hw_submission); | |
4f839a24 CK |
181 | if (r) |
182 | return r; | |
d38ceaf9 AD |
183 | } |
184 | ||
185 | r = amdgpu_wb_get(adev, &ring->rptr_offs); | |
186 | if (r) { | |
187 | dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); | |
188 | return r; | |
189 | } | |
190 | ||
191 | r = amdgpu_wb_get(adev, &ring->wptr_offs); | |
192 | if (r) { | |
193 | dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); | |
194 | return r; | |
195 | } | |
196 | ||
197 | r = amdgpu_wb_get(adev, &ring->fence_offs); | |
198 | if (r) { | |
199 | dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); | |
200 | return r; | |
201 | } | |
202 | ||
128cff1a ML |
203 | r = amdgpu_wb_get(adev, &ring->cond_exe_offs); |
204 | if (r) { | |
205 | dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); | |
206 | return r; | |
207 | } | |
208 | ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4); | |
209 | ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs]; | |
210 | ||
d38ceaf9 AD |
211 | r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); |
212 | if (r) { | |
213 | dev_err(adev->dev, "failed initializing fences (%d).\n", r); | |
214 | return r; | |
215 | } | |
216 | ||
a3f1cf35 CK |
217 | ring->ring_size = roundup_pow_of_two(max_dw * 4 * |
218 | amdgpu_sched_hw_submission); | |
d38ceaf9 AD |
219 | ring->align_mask = align_mask; |
220 | ring->nop = nop; | |
221 | ring->type = ring_type; | |
222 | ||
223 | /* Allocate ring buffer */ | |
224 | if (ring->ring_obj == NULL) { | |
37ac235b CK |
225 | r = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, |
226 | AMDGPU_GEM_DOMAIN_GTT, | |
227 | &ring->ring_obj, | |
228 | &ring->gpu_addr, | |
229 | (void **)&ring->ring); | |
d38ceaf9 AD |
230 | if (r) { |
231 | dev_err(adev->dev, "(%d) ring create failed\n", r); | |
232 | return r; | |
233 | } | |
cc7d8c79 | 234 | memset((void *)ring->ring, 0, ring->ring_size); |
d38ceaf9 AD |
235 | } |
236 | ring->ptr_mask = (ring->ring_size / 4) - 1; | |
a3f1cf35 | 237 | ring->max_dw = max_dw; |
d38ceaf9 AD |
238 | |
239 | if (amdgpu_debugfs_ring_init(adev, ring)) { | |
240 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
241 | } | |
d38ceaf9 AD |
242 | return 0; |
243 | } | |
244 | ||
245 | /** | |
246 | * amdgpu_ring_fini - tear down the driver ring struct. | |
247 | * | |
248 | * @adev: amdgpu_device pointer | |
249 | * @ring: amdgpu_ring structure holding ring information | |
250 | * | |
251 | * Tear down the driver information for the selected ring (all asics). | |
252 | */ | |
253 | void amdgpu_ring_fini(struct amdgpu_ring *ring) | |
254 | { | |
255 | int r; | |
256 | struct amdgpu_bo *ring_obj; | |
257 | ||
d38ceaf9 AD |
258 | ring_obj = ring->ring_obj; |
259 | ring->ready = false; | |
260 | ring->ring = NULL; | |
261 | ring->ring_obj = NULL; | |
d38ceaf9 | 262 | |
67a6a504 | 263 | amdgpu_wb_free(ring->adev, ring->cond_exe_offs); |
d38ceaf9 AD |
264 | amdgpu_wb_free(ring->adev, ring->fence_offs); |
265 | amdgpu_wb_free(ring->adev, ring->rptr_offs); | |
266 | amdgpu_wb_free(ring->adev, ring->wptr_offs); | |
d38ceaf9 AD |
267 | |
268 | if (ring_obj) { | |
269 | r = amdgpu_bo_reserve(ring_obj, false); | |
270 | if (likely(r == 0)) { | |
271 | amdgpu_bo_kunmap(ring_obj); | |
272 | amdgpu_bo_unpin(ring_obj); | |
273 | amdgpu_bo_unreserve(ring_obj); | |
274 | } | |
275 | amdgpu_bo_unref(&ring_obj); | |
276 | } | |
a909c6bd | 277 | amdgpu_debugfs_ring_fini(ring); |
d38ceaf9 AD |
278 | } |
279 | ||
280 | /* | |
281 | * Debugfs info | |
282 | */ | |
283 | #if defined(CONFIG_DEBUG_FS) | |
284 | ||
4f4824b5 TSD |
285 | /* Layout of file is 12 bytes consisting of |
286 | * - rptr | |
287 | * - wptr | |
288 | * - driver's copy of wptr | |
289 | * | |
290 | * followed by n-words of ring data | |
291 | */ | |
292 | static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, | |
293 | size_t size, loff_t *pos) | |
d38ceaf9 | 294 | { |
4f4824b5 TSD |
295 | struct amdgpu_ring *ring = (struct amdgpu_ring*)f->f_inode->i_private; |
296 | int r, i; | |
297 | uint32_t value, result, early[3]; | |
298 | ||
c71dbd93 | 299 | if (*pos & 3 || size & 3) |
4f4824b5 TSD |
300 | return -EINVAL; |
301 | ||
302 | result = 0; | |
303 | ||
304 | if (*pos < 12) { | |
305 | early[0] = amdgpu_ring_get_rptr(ring); | |
306 | early[1] = amdgpu_ring_get_wptr(ring); | |
307 | early[2] = ring->wptr; | |
308 | for (i = *pos / 4; i < 3 && size; i++) { | |
309 | r = put_user(early[i], (uint32_t *)buf); | |
310 | if (r) | |
311 | return r; | |
312 | buf += 4; | |
313 | result += 4; | |
314 | size -= 4; | |
315 | *pos += 4; | |
316 | } | |
c7e6be23 | 317 | } |
4f4824b5 TSD |
318 | |
319 | while (size) { | |
320 | if (*pos >= (ring->ring_size + 12)) | |
321 | return result; | |
322 | ||
323 | value = ring->ring[(*pos - 12)/4]; | |
324 | r = put_user(value, (uint32_t*)buf); | |
325 | if (r) | |
326 | return r; | |
327 | buf += 4; | |
328 | result += 4; | |
329 | size -= 4; | |
330 | *pos += 4; | |
d38ceaf9 | 331 | } |
4f4824b5 TSD |
332 | |
333 | return result; | |
d38ceaf9 AD |
334 | } |
335 | ||
4f4824b5 TSD |
336 | static const struct file_operations amdgpu_debugfs_ring_fops = { |
337 | .owner = THIS_MODULE, | |
338 | .read = amdgpu_debugfs_ring_read, | |
339 | .llseek = default_llseek | |
340 | }; | |
d38ceaf9 AD |
341 | |
342 | #endif | |
343 | ||
771c8ec1 CK |
344 | static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, |
345 | struct amdgpu_ring *ring) | |
d38ceaf9 AD |
346 | { |
347 | #if defined(CONFIG_DEBUG_FS) | |
4f4824b5 TSD |
348 | struct drm_minor *minor = adev->ddev->primary; |
349 | struct dentry *ent, *root = minor->debugfs_root; | |
350 | char name[32]; | |
d38ceaf9 | 351 | |
771c8ec1 | 352 | sprintf(name, "amdgpu_ring_%s", ring->name); |
771c8ec1 | 353 | |
4f4824b5 TSD |
354 | ent = debugfs_create_file(name, |
355 | S_IFREG | S_IRUGO, root, | |
356 | ring, &amdgpu_debugfs_ring_fops); | |
357 | if (IS_ERR(ent)) | |
358 | return PTR_ERR(ent); | |
359 | ||
360 | i_size_write(ent->d_inode, ring->ring_size + 12); | |
a909c6bd | 361 | ring->ent = ent; |
d38ceaf9 AD |
362 | #endif |
363 | return 0; | |
364 | } | |
a909c6bd ML |
365 | |
366 | static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring) | |
367 | { | |
368 | #if defined(CONFIG_DEBUG_FS) | |
369 | debugfs_remove(ring->ent); | |
370 | #endif | |
371 | } |