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Merge tag 'drm-intel-next-2016-02-14' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_uvd.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <deathsimple@vodafone.de>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35
36#include "amdgpu.h"
37#include "amdgpu_pm.h"
38#include "amdgpu_uvd.h"
39#include "cikd.h"
40#include "uvd/uvd_4_2_d.h"
41
42/* 1 second timeout */
43#define UVD_IDLE_TIMEOUT_MS 1000
44
45/* Firmware Names */
46#ifdef CONFIG_DRM_AMDGPU_CIK
47#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
48#define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
49#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
50#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
51#define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
52#endif
c65444fe
JZ		 53#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
54#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
974ee3db 55#define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin"
a39c8cea 56#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin"
d38ceaf9
AD		 57
58/**
59 * amdgpu_uvd_cs_ctx - Command submission parser context
60 *
61 * Used for emulating virtual memory support on UVD 4.2.
62 */
63struct amdgpu_uvd_cs_ctx {
64 struct amdgpu_cs_parser *parser;
65 unsigned reg, count;
66 unsigned data0, data1;
67 unsigned idx;
68 unsigned ib_idx;
69
70 /* does the IB has a msg command */
71 bool has_msg_cmd;
72
73 /* minimum buffer sizes */
74 unsigned *buf_sizes;
75};
76
77#ifdef CONFIG_DRM_AMDGPU_CIK
78MODULE_FIRMWARE(FIRMWARE_BONAIRE);
79MODULE_FIRMWARE(FIRMWARE_KABINI);
80MODULE_FIRMWARE(FIRMWARE_KAVERI);
81MODULE_FIRMWARE(FIRMWARE_HAWAII);
82MODULE_FIRMWARE(FIRMWARE_MULLINS);
83#endif
84MODULE_FIRMWARE(FIRMWARE_TONGA);
85MODULE_FIRMWARE(FIRMWARE_CARRIZO);
974ee3db 86MODULE_FIRMWARE(FIRMWARE_FIJI);
a39c8cea 87MODULE_FIRMWARE(FIRMWARE_STONEY);
d38ceaf9
AD		 88
89static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
90static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
91
92int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
93{
ead833ec
CK		 94 struct amdgpu_ring *ring;
95 struct amd_sched_rq *rq;
d38ceaf9
AD		 96 unsigned long bo_size;
97 const char *fw_name;
98 const struct common_firmware_header *hdr;
99 unsigned version_major, version_minor, family_id;
100 int i, r;
101
102 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
103
104 switch (adev->asic_type) {
105#ifdef CONFIG_DRM_AMDGPU_CIK
106 case CHIP_BONAIRE:
107 fw_name = FIRMWARE_BONAIRE;
108 break;
109 case CHIP_KABINI:
110 fw_name = FIRMWARE_KABINI;
111 break;
112 case CHIP_KAVERI:
113 fw_name = FIRMWARE_KAVERI;
114 break;
115 case CHIP_HAWAII:
116 fw_name = FIRMWARE_HAWAII;
117 break;
118 case CHIP_MULLINS:
119 fw_name = FIRMWARE_MULLINS;
120 break;
121#endif
122 case CHIP_TONGA:
123 fw_name = FIRMWARE_TONGA;
124 break;
974ee3db
DZ		 125 case CHIP_FIJI:
126 fw_name = FIRMWARE_FIJI;
127 break;
d38ceaf9
AD		 128 case CHIP_CARRIZO:
129 fw_name = FIRMWARE_CARRIZO;
130 break;
a39c8cea
SL		 131 case CHIP_STONEY:
132 fw_name = FIRMWARE_STONEY;
133 break;
d38ceaf9
AD		 134 default:
135 return -EINVAL;
136 }
137
138 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
139 if (r) {
140 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n",
141 fw_name);
142 return r;
143 }
144
145 r = amdgpu_ucode_validate(adev->uvd.fw);
146 if (r) {
147 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n",
148 fw_name);
149 release_firmware(adev->uvd.fw);
150 adev->uvd.fw = NULL;
151 return r;
152 }
153
154 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
155 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
156 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
157 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
158 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
159 version_major, version_minor, family_id);
160
161 bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
162 + AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
163 r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
857d913d
AD		 164 AMDGPU_GEM_DOMAIN_VRAM,
165 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 166 NULL, NULL, &adev->uvd.vcpu_bo);
d38ceaf9
AD		 167 if (r) {
168 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
169 return r;
170 }
171
172 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
173 if (r) {
174 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
175 dev_err(adev->dev, "(%d) failed to reserve UVD bo\n", r);
176 return r;
177 }
178
179 r = amdgpu_bo_pin(adev->uvd.vcpu_bo, AMDGPU_GEM_DOMAIN_VRAM,
180 &adev->uvd.gpu_addr);
181 if (r) {
182 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
183 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
184 dev_err(adev->dev, "(%d) UVD bo pin failed\n", r);
185 return r;
186 }
187
188 r = amdgpu_bo_kmap(adev->uvd.vcpu_bo, &adev->uvd.cpu_addr);
189 if (r) {
190 dev_err(adev->dev, "(%d) UVD map failed\n", r);
191 return r;
192 }
193
194 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
195
ead833ec
CK		 196 ring = &adev->uvd.ring;
197 rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_NORMAL];
198 r = amd_sched_entity_init(&ring->sched, &adev->uvd.entity,
199 rq, amdgpu_sched_jobs);
200 if (r != 0) {
201 DRM_ERROR("Failed setting up UVD run queue.\n");
202 return r;
203 }
204
d38ceaf9
AD		 205 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
206 atomic_set(&adev->uvd.handles[i], 0);
207 adev->uvd.filp[i] = NULL;
208 }
209
210 /* from uvd v5.0 HW addressing capacity increased to 64 bits */
5fc3aeeb 211 if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
d38ceaf9
AD		 212 adev->uvd.address_64_bit = true;
213
214 return 0;
215}
216
217int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
218{
219 int r;
220
221 if (adev->uvd.vcpu_bo == NULL)
222 return 0;
223
ead833ec
CK		 224 amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
225
d38ceaf9
AD		 226 r = amdgpu_bo_reserve(adev->uvd.vcpu_bo, false);
227 if (!r) {
228 amdgpu_bo_kunmap(adev->uvd.vcpu_bo);
229 amdgpu_bo_unpin(adev->uvd.vcpu_bo);
230 amdgpu_bo_unreserve(adev->uvd.vcpu_bo);
231 }
232
233 amdgpu_bo_unref(&adev->uvd.vcpu_bo);
234
235 amdgpu_ring_fini(&adev->uvd.ring);
236
237 release_firmware(adev->uvd.fw);
238
239 return 0;
240}
241
242int amdgpu_uvd_suspend(struct amdgpu_device *adev)
243{
8f8202f7
CK		 244 struct amdgpu_ring *ring = &adev->uvd.ring;
245 int i, r;
d38ceaf9
AD		 246
247 if (adev->uvd.vcpu_bo == NULL)
248 return 0;
249
8f8202f7
CK		 250 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
251 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
252 if (handle != 0) {
253 struct fence *fence;
d38ceaf9 254
8f8202f7 255 amdgpu_uvd_note_usage(adev);
d38ceaf9 256
d7af97db 257 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence);
8f8202f7
CK		 258 if (r) {
259 DRM_ERROR("Error destroying UVD (%d)!\n", r);
260 continue;
261 }
d38ceaf9 262
8f8202f7
CK		 263 fence_wait(fence, false);
264 fence_put(fence);
d38ceaf9 265
8f8202f7
CK		 266 adev->uvd.filp[i] = NULL;
267 atomic_set(&adev->uvd.handles[i], 0);
268 }
269 }
d38ceaf9
AD		 270
271 return 0;
272}
273
274int amdgpu_uvd_resume(struct amdgpu_device *adev)
275{
276 unsigned size;
277 void *ptr;
278 const struct common_firmware_header *hdr;
279 unsigned offset;
280
281 if (adev->uvd.vcpu_bo == NULL)
282 return -EINVAL;
283
284 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
285 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
286 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
287 (adev->uvd.fw->size) - offset);
288
289 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
290 size -= le32_to_cpu(hdr->ucode_size_bytes);
291 ptr = adev->uvd.cpu_addr;
292 ptr += le32_to_cpu(hdr->ucode_size_bytes);
293
8f8202f7 294 memset(ptr, 0, size);
d38ceaf9
AD		 295
296 return 0;
297}
298
299void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
300{
301 struct amdgpu_ring *ring = &adev->uvd.ring;
302 int i, r;
303
304 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
305 uint32_t handle = atomic_read(&adev->uvd.handles[i]);
306 if (handle != 0 && adev->uvd.filp[i] == filp) {
0e3f154a 307 struct fence *fence;
d38ceaf9
AD		 308
309 amdgpu_uvd_note_usage(adev);
310
d7af97db
CK		 311 r = amdgpu_uvd_get_destroy_msg(ring, handle,
312 false, &fence);
d38ceaf9
AD		 313 if (r) {
314 DRM_ERROR("Error destroying UVD (%d)!\n", r);
315 continue;
316 }
317
0e3f154a
CZ		 318 fence_wait(fence, false);
319 fence_put(fence);
d38ceaf9
AD		 320
321 adev->uvd.filp[i] = NULL;
322 atomic_set(&adev->uvd.handles[i], 0);
323 }
324 }
325}
326
327static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *rbo)
328{
329 int i;
330 for (i = 0; i < rbo->placement.num_placement; ++i) {
331 rbo->placements[i].fpfn = 0 >> PAGE_SHIFT;
332 rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
333 }
334}
335
336/**
337 * amdgpu_uvd_cs_pass1 - first parsing round
338 *
339 * @ctx: UVD parser context
340 *
341 * Make sure UVD message and feedback buffers are in VRAM and
342 * nobody is violating an 256MB boundary.
343 */
344static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
345{
346 struct amdgpu_bo_va_mapping *mapping;
347 struct amdgpu_bo *bo;
348 uint32_t cmd, lo, hi;
349 uint64_t addr;
350 int r = 0;
351
352 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
353 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
354 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
355
356 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
357 if (mapping == NULL) {
358 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
359 return -EINVAL;
360 }
361
362 if (!ctx->parser->adev->uvd.address_64_bit) {
363 /* check if it's a message or feedback command */
364 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
365 if (cmd == 0x0 || cmd == 0x3) {
366 /* yes, force it into VRAM */
367 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
368 amdgpu_ttm_placement_from_domain(bo, domain);
369 }
370 amdgpu_uvd_force_into_uvd_segment(bo);
371
372 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
373 }
374
375 return r;
376}
377
378/**
379 * amdgpu_uvd_cs_msg_decode - handle UVD decode message
380 *
381 * @msg: pointer to message structure
382 * @buf_sizes: returned buffer sizes
383 *
384 * Peek into the decode message and calculate the necessary buffer sizes.
385 */
386static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
387{
388 unsigned stream_type = msg[4];
389 unsigned width = msg[6];
390 unsigned height = msg[7];
391 unsigned dpb_size = msg[9];
392 unsigned pitch = msg[28];
393 unsigned level = msg[57];
394
395 unsigned width_in_mb = width / 16;
396 unsigned height_in_mb = ALIGN(height / 16, 2);
397 unsigned fs_in_mb = width_in_mb * height_in_mb;
398
21df89a5
JZ		 399 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
400 unsigned min_ctx_size = 0;
d38ceaf9
AD		 401
402 image_size = width * height;
403 image_size += image_size / 2;
404 image_size = ALIGN(image_size, 1024);
405
406 switch (stream_type) {
407 case 0: /* H264 */
408 case 7: /* H264 Perf */
409 switch(level) {
410 case 30:
411 num_dpb_buffer = 8100 / fs_in_mb;
412 break;
413 case 31:
414 num_dpb_buffer = 18000 / fs_in_mb;
415 break;
416 case 32:
417 num_dpb_buffer = 20480 / fs_in_mb;
418 break;
419 case 41:
420 num_dpb_buffer = 32768 / fs_in_mb;
421 break;
422 case 42:
423 num_dpb_buffer = 34816 / fs_in_mb;
424 break;
425 case 50:
426 num_dpb_buffer = 110400 / fs_in_mb;
427 break;
428 case 51:
429 num_dpb_buffer = 184320 / fs_in_mb;
430 break;
431 default:
432 num_dpb_buffer = 184320 / fs_in_mb;
433 break;
434 }
435 num_dpb_buffer++;
436 if (num_dpb_buffer > 17)
437 num_dpb_buffer = 17;
438
439 /* reference picture buffer */
440 min_dpb_size = image_size * num_dpb_buffer;
441
442 /* macroblock context buffer */
443 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192;
444
445 /* IT surface buffer */
446 min_dpb_size += width_in_mb * height_in_mb * 32;
447 break;
448
449 case 1: /* VC1 */
450
451 /* reference picture buffer */
452 min_dpb_size = image_size * 3;
453
454 /* CONTEXT_BUFFER */
455 min_dpb_size += width_in_mb * height_in_mb * 128;
456
457 /* IT surface buffer */
458 min_dpb_size += width_in_mb * 64;
459
460 /* DB surface buffer */
461 min_dpb_size += width_in_mb * 128;
462
463 /* BP */
464 tmp = max(width_in_mb, height_in_mb);
465 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
466 break;
467
468 case 3: /* MPEG2 */
469
470 /* reference picture buffer */
471 min_dpb_size = image_size * 3;
472 break;
473
474 case 4: /* MPEG4 */
475
476 /* reference picture buffer */
477 min_dpb_size = image_size * 3;
478
479 /* CM */
480 min_dpb_size += width_in_mb * height_in_mb * 64;
481
482 /* IT surface buffer */
483 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
484 break;
485
86fa0bdc
CK		 486 case 16: /* H265 */
487 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2;
488 image_size = ALIGN(image_size, 256);
489
490 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
491 min_dpb_size = image_size * num_dpb_buffer;
8c8bac59
BZ		 492 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
493 * 16 * num_dpb_buffer + 52 * 1024;
86fa0bdc
CK		 494 break;
495
d38ceaf9
AD		 496 default:
497 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
498 return -EINVAL;
499 }
500
501 if (width > pitch) {
502 DRM_ERROR("Invalid UVD decoding target pitch!\n");
503 return -EINVAL;
504 }
505
506 if (dpb_size < min_dpb_size) {
507 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
508 dpb_size, min_dpb_size);
509 return -EINVAL;
510 }
511
512 buf_sizes[0x1] = dpb_size;
513 buf_sizes[0x2] = image_size;
8c8bac59 514 buf_sizes[0x4] = min_ctx_size;
d38ceaf9
AD		 515 return 0;
516}
517
518/**
519 * amdgpu_uvd_cs_msg - handle UVD message
520 *
521 * @ctx: UVD parser context
522 * @bo: buffer object containing the message
523 * @offset: offset into the buffer object
524 *
525 * Peek into the UVD message and extract the session id.
526 * Make sure that we don't open up to many sessions.
527 */
528static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx,
529 struct amdgpu_bo *bo, unsigned offset)
530{
531 struct amdgpu_device *adev = ctx->parser->adev;
532 int32_t *msg, msg_type, handle;
d38ceaf9 533 void *ptr;
4127a59e
CK		 534 long r;
535 int i;
d38ceaf9
AD		 536
537 if (offset & 0x3F) {
538 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
539 return -EINVAL;
540 }
541
713293b8
CK		 542 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
543 MAX_SCHEDULE_TIMEOUT);
4127a59e
CK		 544 if (r < 0) {
545 DRM_ERROR("Failed waiting for UVD message (%ld)!\n", r);
713293b8 546 return r;
d38ceaf9
AD		 547 }
548
549 r = amdgpu_bo_kmap(bo, &ptr);
550 if (r) {
4127a59e 551 DRM_ERROR("Failed mapping the UVD message (%ld)!\n", r);
d38ceaf9
AD		 552 return r;
553 }
554
555 msg = ptr + offset;
556
557 msg_type = msg[1];
558 handle = msg[2];
559
560 if (handle == 0) {
561 DRM_ERROR("Invalid UVD handle!\n");
562 return -EINVAL;
563 }
564
5146419e
LL		 565 switch (msg_type) {
566 case 0:
567 /* it's a create msg, calc image size (width * height) */
568 amdgpu_bo_kunmap(bo);
569
570 /* try to alloc a new handle */
571 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
572 if (atomic_read(&adev->uvd.handles[i]) == handle) {
573 DRM_ERROR("Handle 0x%x already in use!\n", handle);
574 return -EINVAL;
575 }
576
577 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) {
578 adev->uvd.filp[i] = ctx->parser->filp;
579 return 0;
580 }
581 }
582
583 DRM_ERROR("No more free UVD handles!\n");
584 return -EINVAL;
585
586 case 1:
d38ceaf9
AD		 587 /* it's a decode msg, calc buffer sizes */
588 r = amdgpu_uvd_cs_msg_decode(msg, ctx->buf_sizes);
589 amdgpu_bo_kunmap(bo);
590 if (r)
591 return r;
592
5146419e
LL		 593 /* validate the handle */
594 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) {
595 if (atomic_read(&adev->uvd.handles[i]) == handle) {
596 if (adev->uvd.filp[i] != ctx->parser->filp) {
597 DRM_ERROR("UVD handle collision detected!\n");
598 return -EINVAL;
599 }
600 return 0;
601 }
602 }
603
604 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle);
605 return -ENOENT;
606
607 case 2:
d38ceaf9
AD		 608 /* it's a destroy msg, free the handle */
609 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
610 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0);
611 amdgpu_bo_kunmap(bo);
612 return 0;
d38ceaf9 613
5146419e
LL		 614 default:
615 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
616 return -EINVAL;
d38ceaf9 617 }
5146419e 618 BUG();
d38ceaf9
AD		 619 return -EINVAL;
620}
621
622/**
623 * amdgpu_uvd_cs_pass2 - second parsing round
624 *
625 * @ctx: UVD parser context
626 *
627 * Patch buffer addresses, make sure buffer sizes are correct.
628 */
629static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
630{
631 struct amdgpu_bo_va_mapping *mapping;
632 struct amdgpu_bo *bo;
d38ceaf9
AD		 633 uint32_t cmd, lo, hi;
634 uint64_t start, end;
635 uint64_t addr;
636 int r;
637
638 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0);
639 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1);
640 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32);
641
642 mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
643 if (mapping == NULL)
644 return -EINVAL;
645
646 start = amdgpu_bo_gpu_offset(bo);
647
648 end = (mapping->it.last + 1 - mapping->it.start);
649 end = end * AMDGPU_GPU_PAGE_SIZE + start;
650
651 addr -= ((uint64_t)mapping->it.start) * AMDGPU_GPU_PAGE_SIZE;
652 start += addr;
653
7270f839
CK		 654 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0,
655 lower_32_bits(start));
656 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1,
657 upper_32_bits(start));
d38ceaf9
AD		 658
659 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
660 if (cmd < 0x4) {
661 if ((end - start) < ctx->buf_sizes[cmd]) {
662 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
663 (unsigned)(end - start),
664 ctx->buf_sizes[cmd]);
665 return -EINVAL;
666 }
667
8c8bac59
BZ		 668 } else if (cmd == 0x206) {
669 if ((end - start) < ctx->buf_sizes[4]) {
670 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
671 (unsigned)(end - start),
672 ctx->buf_sizes[4]);
673 return -EINVAL;
674 }
d38ceaf9
AD		 675 } else if ((cmd != 0x100) && (cmd != 0x204)) {
676 DRM_ERROR("invalid UVD command %X!\n", cmd);
677 return -EINVAL;
678 }
679
680 if (!ctx->parser->adev->uvd.address_64_bit) {
681 if ((start >> 28) != ((end - 1) >> 28)) {
682 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
683 start, end);
684 return -EINVAL;
685 }
686
687 if ((cmd == 0 || cmd == 0x3) &&
688 (start >> 28) != (ctx->parser->adev->uvd.gpu_addr >> 28)) {
689 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
690 start, end);
691 return -EINVAL;
692 }
693 }
694
695 if (cmd == 0) {
696 ctx->has_msg_cmd = true;
697 r = amdgpu_uvd_cs_msg(ctx, bo, addr);
698 if (r)
699 return r;
700 } else if (!ctx->has_msg_cmd) {
701 DRM_ERROR("Message needed before other commands are send!\n");
702 return -EINVAL;
703 }
704
705 return 0;
706}
707
708/**
709 * amdgpu_uvd_cs_reg - parse register writes
710 *
711 * @ctx: UVD parser context
712 * @cb: callback function
713 *
714 * Parse the register writes, call cb on each complete command.
715 */
716static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx,
717 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
718{
50838c8c 719 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
d38ceaf9
AD		 720 int i, r;
721
722 ctx->idx++;
723 for (i = 0; i <= ctx->count; ++i) {
724 unsigned reg = ctx->reg + i;
725
726 if (ctx->idx >= ib->length_dw) {
727 DRM_ERROR("Register command after end of CS!\n");
728 return -EINVAL;
729 }
730
731 switch (reg) {
732 case mmUVD_GPCOM_VCPU_DATA0:
733 ctx->data0 = ctx->idx;
734 break;
735 case mmUVD_GPCOM_VCPU_DATA1:
736 ctx->data1 = ctx->idx;
737 break;
738 case mmUVD_GPCOM_VCPU_CMD:
739 r = cb(ctx);
740 if (r)
741 return r;
742 break;
743 case mmUVD_ENGINE_CNTL:
744 break;
745 default:
746 DRM_ERROR("Invalid reg 0x%X!\n", reg);
747 return -EINVAL;
748 }
749 ctx->idx++;
750 }
751 return 0;
752}
753
754/**
755 * amdgpu_uvd_cs_packets - parse UVD packets
756 *
757 * @ctx: UVD parser context
758 * @cb: callback function
759 *
760 * Parse the command stream packets.
761 */
762static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx,
763 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx))
764{
50838c8c 765 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx];
d38ceaf9
AD		 766 int r;
767
768 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) {
769 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx);
770 unsigned type = CP_PACKET_GET_TYPE(cmd);
771 switch (type) {
772 case PACKET_TYPE0:
773 ctx->reg = CP_PACKET0_GET_REG(cmd);
774 ctx->count = CP_PACKET_GET_COUNT(cmd);
775 r = amdgpu_uvd_cs_reg(ctx, cb);
776 if (r)
777 return r;
778 break;
779 case PACKET_TYPE2:
780 ++ctx->idx;
781 break;
782 default:
783 DRM_ERROR("Unknown packet type %d !\n", type);
784 return -EINVAL;
785 }
786 }
787 return 0;
788}
789
790/**
791 * amdgpu_uvd_ring_parse_cs - UVD command submission parser
792 *
793 * @parser: Command submission parser context
794 *
795 * Parse the command stream, patch in addresses as necessary.
796 */
797int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
798{
799 struct amdgpu_uvd_cs_ctx ctx = {};
800 unsigned buf_sizes[] = {
801 [0x00000000] = 2048,
8c8bac59
BZ		 802 [0x00000001] = 0xFFFFFFFF,
803 [0x00000002] = 0xFFFFFFFF,
d38ceaf9 804 [0x00000003] = 2048,
8c8bac59 805 [0x00000004] = 0xFFFFFFFF,
d38ceaf9 806 };
50838c8c 807 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx];
d38ceaf9
AD		 808 int r;
809
810 if (ib->length_dw % 16) {
811 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
812 ib->length_dw);
813 return -EINVAL;
814 }
815
816 ctx.parser = parser;
817 ctx.buf_sizes = buf_sizes;
818 ctx.ib_idx = ib_idx;
819
820 /* first round, make sure the buffers are actually in the UVD segment */
821 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1);
822 if (r)
823 return r;
824
825 /* second round, patch buffer addresses into the command stream */
826 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2);
827 if (r)
828 return r;
829
830 if (!ctx.has_msg_cmd) {
831 DRM_ERROR("UVD-IBs need a msg command!\n");
832 return -EINVAL;
833 }
834
835 amdgpu_uvd_note_usage(ctx.parser->adev);
836
837 return 0;
838}
839
d7af97db
CK		 840static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
841 bool direct, struct fence **fence)
d38ceaf9
AD		 842{
843 struct ttm_validate_buffer tv;
844 struct ww_acquire_ctx ticket;
845 struct list_head head;
d71518b5
CK		 846 struct amdgpu_job *job;
847 struct amdgpu_ib *ib;
1763552e 848 struct fence *f = NULL;
7b5ec431 849 struct amdgpu_device *adev = ring->adev;
d38ceaf9
AD		 850 uint64_t addr;
851 int i, r;
852
853 memset(&tv, 0, sizeof(tv));
854 tv.bo = &bo->tbo;
855
856 INIT_LIST_HEAD(&head);
857 list_add(&tv.head, &head);
858
859 r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
860 if (r)
861 return r;
862
863 if (!bo->adev->uvd.address_64_bit) {
864 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
865 amdgpu_uvd_force_into_uvd_segment(bo);
866 }
867
868 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
869 if (r)
870 goto err;
d71518b5
CK		 871
872 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
7b5ec431 873 if (r)
d71518b5 874 goto err;
d38ceaf9 875
d71518b5 876 ib = &job->ibs[0];
d38ceaf9 877 addr = amdgpu_bo_gpu_offset(bo);
7b5ec431
CZ		 878 ib->ptr[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
879 ib->ptr[1] = addr;
880 ib->ptr[2] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
881 ib->ptr[3] = addr >> 32;
882 ib->ptr[4] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
883 ib->ptr[5] = 0;
d38ceaf9 884 for (i = 6; i < 16; ++i)
7b5ec431
CZ		 885 ib->ptr[i] = PACKET2(0);
886 ib->length_dw = 16;
d38ceaf9 887
d7af97db
CK		 888 if (direct) {
889 r = amdgpu_ib_schedule(ring, 1, ib,
e86f9cee 890 AMDGPU_FENCE_OWNER_UNDEFINED, NULL, &f);
d7af97db
CK		 891 if (r)
892 goto err_free;
893
894 amdgpu_job_free(job);
895 } else {
ead833ec 896 r = amdgpu_job_submit(job, ring, &adev->uvd.entity,
d7af97db
CK		 897 AMDGPU_FENCE_OWNER_UNDEFINED, &f);
898 if (r)
899 goto err_free;
900 }
d38ceaf9 901
1763552e 902 ttm_eu_fence_buffer_objects(&ticket, &head, f);
d38ceaf9 903
7b5ec431 904 if (fence)
1763552e 905 *fence = fence_get(f);
d38ceaf9 906 amdgpu_bo_unref(&bo);
281b4223 907 fence_put(f);
7b5ec431 908
7b5ec431 909 return 0;
d71518b5
CK		 910
911err_free:
912 amdgpu_job_free(job);
913
d38ceaf9
AD		 914err:
915 ttm_eu_backoff_reservation(&ticket, &head);
916 return r;
917}
918
919/* multiple fence commands without any stream commands in between can
920 crash the vcpu so just try to emmit a dummy create/destroy msg to
921 avoid this */
922int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
0e3f154a 923 struct fence **fence)
d38ceaf9
AD		 924{
925 struct amdgpu_device *adev = ring->adev;
926 struct amdgpu_bo *bo;
927 uint32_t *msg;
928 int r, i;
929
930 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
857d913d
AD		 931 AMDGPU_GEM_DOMAIN_VRAM,
932 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 933 NULL, NULL, &bo);
d38ceaf9
AD		 934 if (r)
935 return r;
936
937 r = amdgpu_bo_reserve(bo, false);
938 if (r) {
939 amdgpu_bo_unref(&bo);
940 return r;
941 }
942
943 r = amdgpu_bo_kmap(bo, (void **)&msg);
944 if (r) {
945 amdgpu_bo_unreserve(bo);
946 amdgpu_bo_unref(&bo);
947 return r;
948 }
949
950 /* stitch together an UVD create msg */
951 msg[0] = cpu_to_le32(0x00000de4);
952 msg[1] = cpu_to_le32(0x00000000);
953 msg[2] = cpu_to_le32(handle);
954 msg[3] = cpu_to_le32(0x00000000);
955 msg[4] = cpu_to_le32(0x00000000);
956 msg[5] = cpu_to_le32(0x00000000);
957 msg[6] = cpu_to_le32(0x00000000);
958 msg[7] = cpu_to_le32(0x00000780);
959 msg[8] = cpu_to_le32(0x00000440);
960 msg[9] = cpu_to_le32(0x00000000);
961 msg[10] = cpu_to_le32(0x01b37000);
962 for (i = 11; i < 1024; ++i)
963 msg[i] = cpu_to_le32(0x0);
964
965 amdgpu_bo_kunmap(bo);
966 amdgpu_bo_unreserve(bo);
967
d7af97db 968 return amdgpu_uvd_send_msg(ring, bo, true, fence);
d38ceaf9
AD		 969}
970
971int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
d7af97db 972 bool direct, struct fence **fence)
d38ceaf9
AD		 973{
974 struct amdgpu_device *adev = ring->adev;
975 struct amdgpu_bo *bo;
976 uint32_t *msg;
977 int r, i;
978
979 r = amdgpu_bo_create(adev, 1024, PAGE_SIZE, true,
857d913d
AD		 980 AMDGPU_GEM_DOMAIN_VRAM,
981 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b 982 NULL, NULL, &bo);
d38ceaf9
AD		 983 if (r)
984 return r;
985
986 r = amdgpu_bo_reserve(bo, false);
987 if (r) {
988 amdgpu_bo_unref(&bo);
989 return r;
990 }
991
992 r = amdgpu_bo_kmap(bo, (void **)&msg);
993 if (r) {
994 amdgpu_bo_unreserve(bo);
995 amdgpu_bo_unref(&bo);
996 return r;
997 }
998
999 /* stitch together an UVD destroy msg */
1000 msg[0] = cpu_to_le32(0x00000de4);
1001 msg[1] = cpu_to_le32(0x00000002);
1002 msg[2] = cpu_to_le32(handle);
1003 msg[3] = cpu_to_le32(0x00000000);
1004 for (i = 4; i < 1024; ++i)
1005 msg[i] = cpu_to_le32(0x0);
1006
1007 amdgpu_bo_kunmap(bo);
1008 amdgpu_bo_unreserve(bo);
1009
d7af97db 1010 return amdgpu_uvd_send_msg(ring, bo, direct, fence);
d38ceaf9
AD		 1011}
1012
1013static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
1014{
1015 struct amdgpu_device *adev =
1016 container_of(work, struct amdgpu_device, uvd.idle_work.work);
1017 unsigned i, fences, handles = 0;
1018
1019 fences = amdgpu_fence_count_emitted(&adev->uvd.ring);
1020
1021 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
1022 if (atomic_read(&adev->uvd.handles[i]))
1023 ++handles;
1024
1025 if (fences == 0 && handles == 0) {
1026 if (adev->pm.dpm_enabled) {
1027 amdgpu_dpm_enable_uvd(adev, false);
1028 } else {
1029 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
1030 }
1031 } else {
1032 schedule_delayed_work(&adev->uvd.idle_work,
1033 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1034 }
1035}
1036
1037static void amdgpu_uvd_note_usage(struct amdgpu_device *adev)
1038{
1039 bool set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work);
1040 set_clocks &= schedule_delayed_work(&adev->uvd.idle_work,
1041 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
1042
1043 if (set_clocks) {
1044 if (adev->pm.dpm_enabled) {
1045 amdgpu_dpm_enable_uvd(adev, true);
1046 } else {
1047 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
1048 }
1049 }
1050}
Linux kernel - Deliverables
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