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Merge tag 'drm-intel-next-2016-02-14' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / dce_v10_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34
35#include "dce/dce_10_0_d.h"
36#include "dce/dce_10_0_sh_mask.h"
37#include "dce/dce_10_0_enum.h"
38#include "oss/oss_3_0_d.h"
39#include "oss/oss_3_0_sh_mask.h"
40#include "gmc/gmc_8_1_d.h"
41#include "gmc/gmc_8_1_sh_mask.h"
42
43static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
44static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
45
46static const u32 crtc_offsets[] =
47{
48 CRTC0_REGISTER_OFFSET,
49 CRTC1_REGISTER_OFFSET,
50 CRTC2_REGISTER_OFFSET,
51 CRTC3_REGISTER_OFFSET,
52 CRTC4_REGISTER_OFFSET,
53 CRTC5_REGISTER_OFFSET,
54 CRTC6_REGISTER_OFFSET
55};
56
57static const u32 hpd_offsets[] =
58{
59 HPD0_REGISTER_OFFSET,
60 HPD1_REGISTER_OFFSET,
61 HPD2_REGISTER_OFFSET,
62 HPD3_REGISTER_OFFSET,
63 HPD4_REGISTER_OFFSET,
64 HPD5_REGISTER_OFFSET
65};
66
67static const uint32_t dig_offsets[] = {
68 DIG0_REGISTER_OFFSET,
69 DIG1_REGISTER_OFFSET,
70 DIG2_REGISTER_OFFSET,
71 DIG3_REGISTER_OFFSET,
72 DIG4_REGISTER_OFFSET,
73 DIG5_REGISTER_OFFSET,
74 DIG6_REGISTER_OFFSET
75};
76
77static const struct {
78 uint32_t reg;
79 uint32_t vblank;
80 uint32_t vline;
81 uint32_t hpd;
82
83} interrupt_status_offsets[] = { {
84 .reg = mmDISP_INTERRUPT_STATUS,
85 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
86 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
87 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
88}, {
89 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
90 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
91 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
92 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
93}, {
94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
96 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
98}, {
99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
101 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
103}, {
104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
108}, {
109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
113} };
114
115static const u32 golden_settings_tonga_a11[] =
116{
117 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
118 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
119 mmFBC_MISC, 0x1f311fff, 0x12300000,
120 mmHDMI_CONTROL, 0x31000111, 0x00000011,
121};
122
5732a94f
AD		 123static const u32 tonga_mgcg_cgcg_init[] =
124{
125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
127};
128
84390860
DZ		 129static const u32 golden_settings_fiji_a10[] =
130{
131 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
132 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
133 mmFBC_MISC, 0x1f311fff, 0x12300000,
134 mmHDMI_CONTROL, 0x31000111, 0x00000011,
135};
136
137static const u32 fiji_mgcg_cgcg_init[] =
138{
139 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
140 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
141};
142
aaa36a97
AD		 143static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
144{
145 switch (adev->asic_type) {
84390860
DZ		 146 case CHIP_FIJI:
147 amdgpu_program_register_sequence(adev,
148 fiji_mgcg_cgcg_init,
149 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
150 amdgpu_program_register_sequence(adev,
151 golden_settings_fiji_a10,
152 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
153 break;
aaa36a97 154 case CHIP_TONGA:
5732a94f
AD		 155 amdgpu_program_register_sequence(adev,
156 tonga_mgcg_cgcg_init,
157 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
aaa36a97
AD		 158 amdgpu_program_register_sequence(adev,
159 golden_settings_tonga_a11,
160 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
161 break;
162 default:
163 break;
164 }
165}
166
167static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
168 u32 block_offset, u32 reg)
169{
170 unsigned long flags;
171 u32 r;
172
173 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
174 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
175 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
176 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
177
178 return r;
179}
180
181static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
182 u32 block_offset, u32 reg, u32 v)
183{
184 unsigned long flags;
185
186 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
187 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
189 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
190}
191
192static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
193{
194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
195 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
196 return true;
197 else
198 return false;
199}
200
201static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
202{
203 u32 pos1, pos2;
204
205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
207
208 if (pos1 != pos2)
209 return true;
210 else
211 return false;
212}
213
214/**
215 * dce_v10_0_vblank_wait - vblank wait asic callback.
216 *
217 * @adev: amdgpu_device pointer
218 * @crtc: crtc to wait for vblank on
219 *
220 * Wait for vblank on the requested crtc (evergreen+).
221 */
222static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
223{
224 unsigned i = 0;
225
226 if (crtc >= adev->mode_info.num_crtc)
227 return;
228
229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
230 return;
231
232 /* depending on when we hit vblank, we may be close to active; if so,
233 * wait for another frame.
234 */
235 while (dce_v10_0_is_in_vblank(adev, crtc)) {
236 if (i++ % 100 == 0) {
237 if (!dce_v10_0_is_counter_moving(adev, crtc))
238 break;
239 }
240 }
241
242 while (!dce_v10_0_is_in_vblank(adev, crtc)) {
243 if (i++ % 100 == 0) {
244 if (!dce_v10_0_is_counter_moving(adev, crtc))
245 break;
246 }
247 }
248}
249
250static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
251{
252 if (crtc >= adev->mode_info.num_crtc)
253 return 0;
254 else
255 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
256}
257
f6c7aba4
MD		 258static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
259{
260 unsigned i;
261
262 /* Enable pflip interrupts */
263 for (i = 0; i < adev->mode_info.num_crtc; i++)
264 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
265}
266
267static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
268{
269 unsigned i;
270
271 /* Disable pflip interrupts */
272 for (i = 0; i < adev->mode_info.num_crtc; i++)
273 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
274}
275
aaa36a97
AD		 276/**
277 * dce_v10_0_page_flip - pageflip callback.
278 *
279 * @adev: amdgpu_device pointer
280 * @crtc_id: crtc to cleanup pageflip on
281 * @crtc_base: new address of the crtc (GPU MC address)
282 *
0eaaacab
AD		 283 * Triggers the actual pageflip by updating the primary
284 * surface base address.
aaa36a97
AD		 285 */
286static void dce_v10_0_page_flip(struct amdgpu_device *adev,
287 int crtc_id, u64 crtc_base)
288{
289 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
aaa36a97 290
0eaaacab 291 /* update the primary scanout address */
aaa36a97
AD		 292 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
293 upper_32_bits(crtc_base));
0eaaacab 294 /* writing to the low address triggers the update */
aaa36a97
AD		 295 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
296 lower_32_bits(crtc_base));
0eaaacab
AD		 297 /* post the write */
298 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
aaa36a97
AD		 299}
300
301static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
302 u32 *vbl, u32 *position)
303{
304 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
305 return -EINVAL;
306
307 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
308 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
309
310 return 0;
311}
312
313/**
314 * dce_v10_0_hpd_sense - hpd sense callback.
315 *
316 * @adev: amdgpu_device pointer
317 * @hpd: hpd (hotplug detect) pin
318 *
319 * Checks if a digital monitor is connected (evergreen+).
320 * Returns true if connected, false if not connected.
321 */
322static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
323 enum amdgpu_hpd_id hpd)
324{
325 int idx;
326 bool connected = false;
327
328 switch (hpd) {
329 case AMDGPU_HPD_1:
330 idx = 0;
331 break;
332 case AMDGPU_HPD_2:
333 idx = 1;
334 break;
335 case AMDGPU_HPD_3:
336 idx = 2;
337 break;
338 case AMDGPU_HPD_4:
339 idx = 3;
340 break;
341 case AMDGPU_HPD_5:
342 idx = 4;
343 break;
344 case AMDGPU_HPD_6:
345 idx = 5;
346 break;
347 default:
348 return connected;
349 }
350
351 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
352 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
353 connected = true;
354
355 return connected;
356}
357
358/**
359 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
360 *
361 * @adev: amdgpu_device pointer
362 * @hpd: hpd (hotplug detect) pin
363 *
364 * Set the polarity of the hpd pin (evergreen+).
365 */
366static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
367 enum amdgpu_hpd_id hpd)
368{
369 u32 tmp;
370 bool connected = dce_v10_0_hpd_sense(adev, hpd);
371 int idx;
372
373 switch (hpd) {
374 case AMDGPU_HPD_1:
375 idx = 0;
376 break;
377 case AMDGPU_HPD_2:
378 idx = 1;
379 break;
380 case AMDGPU_HPD_3:
381 idx = 2;
382 break;
383 case AMDGPU_HPD_4:
384 idx = 3;
385 break;
386 case AMDGPU_HPD_5:
387 idx = 4;
388 break;
389 case AMDGPU_HPD_6:
390 idx = 5;
391 break;
392 default:
393 return;
394 }
395
396 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
397 if (connected)
398 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
399 else
400 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
401 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
402}
403
404/**
405 * dce_v10_0_hpd_init - hpd setup callback.
406 *
407 * @adev: amdgpu_device pointer
408 *
409 * Setup the hpd pins used by the card (evergreen+).
410 * Enable the pin, set the polarity, and enable the hpd interrupts.
411 */
412static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
413{
414 struct drm_device *dev = adev->ddev;
415 struct drm_connector *connector;
416 u32 tmp;
417 int idx;
418
419 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
420 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
421
422 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
423 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
424 /* don't try to enable hpd on eDP or LVDS avoid breaking the
425 * aux dp channel on imac and help (but not completely fix)
426 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
427 * also avoid interrupt storms during dpms.
428 */
429 continue;
430 }
431
432 switch (amdgpu_connector->hpd.hpd) {
433 case AMDGPU_HPD_1:
434 idx = 0;
435 break;
436 case AMDGPU_HPD_2:
437 idx = 1;
438 break;
439 case AMDGPU_HPD_3:
440 idx = 2;
441 break;
442 case AMDGPU_HPD_4:
443 idx = 3;
444 break;
445 case AMDGPU_HPD_5:
446 idx = 4;
447 break;
448 case AMDGPU_HPD_6:
449 idx = 5;
450 break;
451 default:
452 continue;
453 }
454
455 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
456 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
457 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
458
459 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
460 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
461 DC_HPD_CONNECT_INT_DELAY,
462 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
463 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
464 DC_HPD_DISCONNECT_INT_DELAY,
465 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
466 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
467
468 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
469 amdgpu_irq_get(adev, &adev->hpd_irq,
470 amdgpu_connector->hpd.hpd);
471 }
472}
473
474/**
475 * dce_v10_0_hpd_fini - hpd tear down callback.
476 *
477 * @adev: amdgpu_device pointer
478 *
479 * Tear down the hpd pins used by the card (evergreen+).
480 * Disable the hpd interrupts.
481 */
482static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
483{
484 struct drm_device *dev = adev->ddev;
485 struct drm_connector *connector;
486 u32 tmp;
487 int idx;
488
489 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
490 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
491
492 switch (amdgpu_connector->hpd.hpd) {
493 case AMDGPU_HPD_1:
494 idx = 0;
495 break;
496 case AMDGPU_HPD_2:
497 idx = 1;
498 break;
499 case AMDGPU_HPD_3:
500 idx = 2;
501 break;
502 case AMDGPU_HPD_4:
503 idx = 3;
504 break;
505 case AMDGPU_HPD_5:
506 idx = 4;
507 break;
508 case AMDGPU_HPD_6:
509 idx = 5;
510 break;
511 default:
512 continue;
513 }
514
515 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
516 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
517 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
518
519 amdgpu_irq_put(adev, &adev->hpd_irq,
520 amdgpu_connector->hpd.hpd);
521 }
522}
523
524static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
525{
526 return mmDC_GPIO_HPD_A;
527}
528
529static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
530{
531 u32 crtc_hung = 0;
532 u32 crtc_status[6];
533 u32 i, j, tmp;
534
535 for (i = 0; i < adev->mode_info.num_crtc; i++) {
536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
537 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
538 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
539 crtc_hung |= (1 << i);
540 }
541 }
542
543 for (j = 0; j < 10; j++) {
544 for (i = 0; i < adev->mode_info.num_crtc; i++) {
545 if (crtc_hung & (1 << i)) {
546 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
547 if (tmp != crtc_status[i])
548 crtc_hung &= ~(1 << i);
549 }
550 }
551 if (crtc_hung == 0)
552 return false;
553 udelay(100);
554 }
555
556 return true;
557}
558
559static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
560 struct amdgpu_mode_mc_save *save)
561{
562 u32 crtc_enabled, tmp;
563 int i;
564
565 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
566 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
567
568 /* disable VGA render */
569 tmp = RREG32(mmVGA_RENDER_CONTROL);
570 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
571 WREG32(mmVGA_RENDER_CONTROL, tmp);
572
573 /* blank the display controllers */
574 for (i = 0; i < adev->mode_info.num_crtc; i++) {
575 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
576 CRTC_CONTROL, CRTC_MASTER_EN);
577 if (crtc_enabled) {
578#if 0
579 u32 frame_count;
580 int j;
581
582 save->crtc_enabled[i] = true;
583 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
584 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
585 amdgpu_display_vblank_wait(adev, i);
586 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
587 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
588 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
589 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
590 }
591 /* wait for the next frame */
592 frame_count = amdgpu_display_vblank_get_counter(adev, i);
593 for (j = 0; j < adev->usec_timeout; j++) {
594 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
595 break;
596 udelay(1);
597 }
598 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
599 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
600 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
601 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
602 }
603 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
604 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
605 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
606 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
607 }
608#else
609 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
610 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
611 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
612 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
613 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
614 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
615 save->crtc_enabled[i] = false;
616 /* ***** */
617#endif
618 } else {
619 save->crtc_enabled[i] = false;
620 }
621 }
622}
623
624static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
625 struct amdgpu_mode_mc_save *save)
626{
627 u32 tmp, frame_count;
628 int i, j;
629
630 /* update crtc base addresses */
631 for (i = 0; i < adev->mode_info.num_crtc; i++) {
632 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
633 upper_32_bits(adev->mc.vram_start));
634 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
635 upper_32_bits(adev->mc.vram_start));
636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
637 (u32)adev->mc.vram_start);
638 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
639 (u32)adev->mc.vram_start);
640
641 if (save->crtc_enabled[i]) {
642 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
643 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
644 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
645 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
646 }
647 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
648 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
649 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
650 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
651 }
652 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
653 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
654 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
655 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
656 }
657 for (j = 0; j < adev->usec_timeout; j++) {
658 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
659 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
660 break;
661 udelay(1);
662 }
663 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
664 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
665 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
666 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
667 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
668 /* wait for the next frame */
669 frame_count = amdgpu_display_vblank_get_counter(adev, i);
670 for (j = 0; j < adev->usec_timeout; j++) {
671 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
672 break;
673 udelay(1);
674 }
675 }
676 }
677
678 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
679 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
680
681 /* Unlock vga access */
682 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
683 mdelay(1);
684 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
685}
686
687static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
688 bool render)
689{
690 u32 tmp;
691
692 /* Lockout access through VGA aperture*/
693 tmp = RREG32(mmVGA_HDP_CONTROL);
694 if (render)
695 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
696 else
697 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
698 WREG32(mmVGA_HDP_CONTROL, tmp);
699
700 /* disable VGA render */
701 tmp = RREG32(mmVGA_RENDER_CONTROL);
702 if (render)
703 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
704 else
705 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
706 WREG32(mmVGA_RENDER_CONTROL, tmp);
707}
708
709static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
710{
711 struct drm_device *dev = encoder->dev;
712 struct amdgpu_device *adev = dev->dev_private;
713 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
714 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
715 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
716 int bpc = 0;
717 u32 tmp = 0;
718 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
719
720 if (connector) {
721 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
722 bpc = amdgpu_connector_get_monitor_bpc(connector);
723 dither = amdgpu_connector->dither;
724 }
725
726 /* LVDS/eDP FMT is set up by atom */
727 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
728 return;
729
730 /* not needed for analog */
731 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
732 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
733 return;
734
735 if (bpc == 0)
736 return;
737
738 switch (bpc) {
739 case 6:
740 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
741 /* XXX sort out optimal dither settings */
742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
746 } else {
747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
749 }
750 break;
751 case 8:
752 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
753 /* XXX sort out optimal dither settings */
754 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
755 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
759 } else {
760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
762 }
763 break;
764 case 10:
765 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
766 /* XXX sort out optimal dither settings */
767 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
768 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
769 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
770 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
772 } else {
773 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
775 }
776 break;
777 default:
778 /* not needed */
779 break;
780 }
781
782 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
783}
784
785
786/* display watermark setup */
787/**
788 * dce_v10_0_line_buffer_adjust - Set up the line buffer
789 *
790 * @adev: amdgpu_device pointer
791 * @amdgpu_crtc: the selected display controller
792 * @mode: the current display mode on the selected display
793 * controller
794 *
795 * Setup up the line buffer allocation for
796 * the selected display controller (CIK).
797 * Returns the line buffer size in pixels.
798 */
799static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
800 struct amdgpu_crtc *amdgpu_crtc,
801 struct drm_display_mode *mode)
802{
803 u32 tmp, buffer_alloc, i, mem_cfg;
804 u32 pipe_offset = amdgpu_crtc->crtc_id;
805 /*
806 * Line Buffer Setup
807 * There are 6 line buffers, one for each display controllers.
808 * There are 3 partitions per LB. Select the number of partitions
809 * to enable based on the display width. For display widths larger
810 * than 4096, you need use to use 2 display controllers and combine
811 * them using the stereo blender.
812 */
813 if (amdgpu_crtc->base.enabled && mode) {
814 if (mode->crtc_hdisplay < 1920) {
815 mem_cfg = 1;
816 buffer_alloc = 2;
817 } else if (mode->crtc_hdisplay < 2560) {
818 mem_cfg = 2;
819 buffer_alloc = 2;
820 } else if (mode->crtc_hdisplay < 4096) {
821 mem_cfg = 0;
2f7d10b3 822 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 823 } else {
824 DRM_DEBUG_KMS("Mode too big for LB!\n");
825 mem_cfg = 0;
2f7d10b3 826 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
aaa36a97
AD		 827 }
828 } else {
829 mem_cfg = 1;
830 buffer_alloc = 0;
831 }
832
833 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
834 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
835 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
836
837 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
838 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
839 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
840
841 for (i = 0; i < adev->usec_timeout; i++) {
842 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
843 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
844 break;
845 udelay(1);
846 }
847
848 if (amdgpu_crtc->base.enabled && mode) {
849 switch (mem_cfg) {
850 case 0:
851 default:
852 return 4096 * 2;
853 case 1:
854 return 1920 * 2;
855 case 2:
856 return 2560 * 2;
857 }
858 }
859
860 /* controller not enabled, so no lb used */
861 return 0;
862}
863
864/**
865 * cik_get_number_of_dram_channels - get the number of dram channels
866 *
867 * @adev: amdgpu_device pointer
868 *
869 * Look up the number of video ram channels (CIK).
870 * Used for display watermark bandwidth calculations
871 * Returns the number of dram channels
872 */
873static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
874{
875 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
876
877 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
878 case 0:
879 default:
880 return 1;
881 case 1:
882 return 2;
883 case 2:
884 return 4;
885 case 3:
886 return 8;
887 case 4:
888 return 3;
889 case 5:
890 return 6;
891 case 6:
892 return 10;
893 case 7:
894 return 12;
895 case 8:
896 return 16;
897 }
898}
899
900struct dce10_wm_params {
901 u32 dram_channels; /* number of dram channels */
902 u32 yclk; /* bandwidth per dram data pin in kHz */
903 u32 sclk; /* engine clock in kHz */
904 u32 disp_clk; /* display clock in kHz */
905 u32 src_width; /* viewport width */
906 u32 active_time; /* active display time in ns */
907 u32 blank_time; /* blank time in ns */
908 bool interlaced; /* mode is interlaced */
909 fixed20_12 vsc; /* vertical scale ratio */
910 u32 num_heads; /* number of active crtcs */
911 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
912 u32 lb_size; /* line buffer allocated to pipe */
913 u32 vtaps; /* vertical scaler taps */
914};
915
916/**
917 * dce_v10_0_dram_bandwidth - get the dram bandwidth
918 *
919 * @wm: watermark calculation data
920 *
921 * Calculate the raw dram bandwidth (CIK).
922 * Used for display watermark bandwidth calculations
923 * Returns the dram bandwidth in MBytes/s
924 */
925static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
926{
927 /* Calculate raw DRAM Bandwidth */
928 fixed20_12 dram_efficiency; /* 0.7 */
929 fixed20_12 yclk, dram_channels, bandwidth;
930 fixed20_12 a;
931
932 a.full = dfixed_const(1000);
933 yclk.full = dfixed_const(wm->yclk);
934 yclk.full = dfixed_div(yclk, a);
935 dram_channels.full = dfixed_const(wm->dram_channels * 4);
936 a.full = dfixed_const(10);
937 dram_efficiency.full = dfixed_const(7);
938 dram_efficiency.full = dfixed_div(dram_efficiency, a);
939 bandwidth.full = dfixed_mul(dram_channels, yclk);
940 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
941
942 return dfixed_trunc(bandwidth);
943}
944
945/**
946 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
947 *
948 * @wm: watermark calculation data
949 *
950 * Calculate the dram bandwidth used for display (CIK).
951 * Used for display watermark bandwidth calculations
952 * Returns the dram bandwidth for display in MBytes/s
953 */
954static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
955{
956 /* Calculate DRAM Bandwidth and the part allocated to display. */
957 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
958 fixed20_12 yclk, dram_channels, bandwidth;
959 fixed20_12 a;
960
961 a.full = dfixed_const(1000);
962 yclk.full = dfixed_const(wm->yclk);
963 yclk.full = dfixed_div(yclk, a);
964 dram_channels.full = dfixed_const(wm->dram_channels * 4);
965 a.full = dfixed_const(10);
966 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
967 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
968 bandwidth.full = dfixed_mul(dram_channels, yclk);
969 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
970
971 return dfixed_trunc(bandwidth);
972}
973
974/**
975 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
976 *
977 * @wm: watermark calculation data
978 *
979 * Calculate the data return bandwidth used for display (CIK).
980 * Used for display watermark bandwidth calculations
981 * Returns the data return bandwidth in MBytes/s
982 */
983static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
984{
985 /* Calculate the display Data return Bandwidth */
986 fixed20_12 return_efficiency; /* 0.8 */
987 fixed20_12 sclk, bandwidth;
988 fixed20_12 a;
989
990 a.full = dfixed_const(1000);
991 sclk.full = dfixed_const(wm->sclk);
992 sclk.full = dfixed_div(sclk, a);
993 a.full = dfixed_const(10);
994 return_efficiency.full = dfixed_const(8);
995 return_efficiency.full = dfixed_div(return_efficiency, a);
996 a.full = dfixed_const(32);
997 bandwidth.full = dfixed_mul(a, sclk);
998 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
999
1000 return dfixed_trunc(bandwidth);
1001}
1002
1003/**
1004 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
1005 *
1006 * @wm: watermark calculation data
1007 *
1008 * Calculate the dmif bandwidth used for display (CIK).
1009 * Used for display watermark bandwidth calculations
1010 * Returns the dmif bandwidth in MBytes/s
1011 */
1012static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1013{
1014 /* Calculate the DMIF Request Bandwidth */
1015 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1016 fixed20_12 disp_clk, bandwidth;
1017 fixed20_12 a, b;
1018
1019 a.full = dfixed_const(1000);
1020 disp_clk.full = dfixed_const(wm->disp_clk);
1021 disp_clk.full = dfixed_div(disp_clk, a);
1022 a.full = dfixed_const(32);
1023 b.full = dfixed_mul(a, disp_clk);
1024
1025 a.full = dfixed_const(10);
1026 disp_clk_request_efficiency.full = dfixed_const(8);
1027 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1028
1029 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1030
1031 return dfixed_trunc(bandwidth);
1032}
1033
1034/**
1035 * dce_v10_0_available_bandwidth - get the min available bandwidth
1036 *
1037 * @wm: watermark calculation data
1038 *
1039 * Calculate the min available bandwidth used for display (CIK).
1040 * Used for display watermark bandwidth calculations
1041 * Returns the min available bandwidth in MBytes/s
1042 */
1043static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
1044{
1045 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1046 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
1047 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
1048 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
1049
1050 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1051}
1052
1053/**
1054 * dce_v10_0_average_bandwidth - get the average available bandwidth
1055 *
1056 * @wm: watermark calculation data
1057 *
1058 * Calculate the average available bandwidth used for display (CIK).
1059 * Used for display watermark bandwidth calculations
1060 * Returns the average available bandwidth in MBytes/s
1061 */
1062static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
1063{
1064 /* Calculate the display mode Average Bandwidth
1065 * DisplayMode should contain the source and destination dimensions,
1066 * timing, etc.
1067 */
1068 fixed20_12 bpp;
1069 fixed20_12 line_time;
1070 fixed20_12 src_width;
1071 fixed20_12 bandwidth;
1072 fixed20_12 a;
1073
1074 a.full = dfixed_const(1000);
1075 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1076 line_time.full = dfixed_div(line_time, a);
1077 bpp.full = dfixed_const(wm->bytes_per_pixel);
1078 src_width.full = dfixed_const(wm->src_width);
1079 bandwidth.full = dfixed_mul(src_width, bpp);
1080 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1081 bandwidth.full = dfixed_div(bandwidth, line_time);
1082
1083 return dfixed_trunc(bandwidth);
1084}
1085
1086/**
1087 * dce_v10_0_latency_watermark - get the latency watermark
1088 *
1089 * @wm: watermark calculation data
1090 *
1091 * Calculate the latency watermark (CIK).
1092 * Used for display watermark bandwidth calculations
1093 * Returns the latency watermark in ns
1094 */
1095static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
1096{
1097 /* First calculate the latency in ns */
1098 u32 mc_latency = 2000; /* 2000 ns. */
1099 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
1100 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1101 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1102 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1103 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1104 (wm->num_heads * cursor_line_pair_return_time);
1105 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1106 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1107 u32 tmp, dmif_size = 12288;
1108 fixed20_12 a, b, c;
1109
1110 if (wm->num_heads == 0)
1111 return 0;
1112
1113 a.full = dfixed_const(2);
1114 b.full = dfixed_const(1);
1115 if ((wm->vsc.full > a.full) ||
1116 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1117 (wm->vtaps >= 5) ||
1118 ((wm->vsc.full >= a.full) && wm->interlaced))
1119 max_src_lines_per_dst_line = 4;
1120 else
1121 max_src_lines_per_dst_line = 2;
1122
1123 a.full = dfixed_const(available_bandwidth);
1124 b.full = dfixed_const(wm->num_heads);
1125 a.full = dfixed_div(a, b);
1126
1127 b.full = dfixed_const(mc_latency + 512);
1128 c.full = dfixed_const(wm->disp_clk);
1129 b.full = dfixed_div(b, c);
1130
1131 c.full = dfixed_const(dmif_size);
1132 b.full = dfixed_div(c, b);
1133
1134 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1135
1136 b.full = dfixed_const(1000);
1137 c.full = dfixed_const(wm->disp_clk);
1138 b.full = dfixed_div(c, b);
1139 c.full = dfixed_const(wm->bytes_per_pixel);
1140 b.full = dfixed_mul(b, c);
1141
1142 lb_fill_bw = min(tmp, dfixed_trunc(b));
1143
1144 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1145 b.full = dfixed_const(1000);
1146 c.full = dfixed_const(lb_fill_bw);
1147 b.full = dfixed_div(c, b);
1148 a.full = dfixed_div(a, b);
1149 line_fill_time = dfixed_trunc(a);
1150
1151 if (line_fill_time < wm->active_time)
1152 return latency;
1153 else
1154 return latency + (line_fill_time - wm->active_time);
1155
1156}
1157
1158/**
1159 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1160 * average and available dram bandwidth
1161 *
1162 * @wm: watermark calculation data
1163 *
1164 * Check if the display average bandwidth fits in the display
1165 * dram bandwidth (CIK).
1166 * Used for display watermark bandwidth calculations
1167 * Returns true if the display fits, false if not.
1168 */
1169static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1170{
1171 if (dce_v10_0_average_bandwidth(wm) <=
1172 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1173 return true;
1174 else
1175 return false;
1176}
1177
1178/**
1179 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1180 * average and available bandwidth
1181 *
1182 * @wm: watermark calculation data
1183 *
1184 * Check if the display average bandwidth fits in the display
1185 * available bandwidth (CIK).
1186 * Used for display watermark bandwidth calculations
1187 * Returns true if the display fits, false if not.
1188 */
1189static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1190{
1191 if (dce_v10_0_average_bandwidth(wm) <=
1192 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
1193 return true;
1194 else
1195 return false;
1196}
1197
1198/**
1199 * dce_v10_0_check_latency_hiding - check latency hiding
1200 *
1201 * @wm: watermark calculation data
1202 *
1203 * Check latency hiding (CIK).
1204 * Used for display watermark bandwidth calculations
1205 * Returns true if the display fits, false if not.
1206 */
1207static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
1208{
1209 u32 lb_partitions = wm->lb_size / wm->src_width;
1210 u32 line_time = wm->active_time + wm->blank_time;
1211 u32 latency_tolerant_lines;
1212 u32 latency_hiding;
1213 fixed20_12 a;
1214
1215 a.full = dfixed_const(1);
1216 if (wm->vsc.full > a.full)
1217 latency_tolerant_lines = 1;
1218 else {
1219 if (lb_partitions <= (wm->vtaps + 1))
1220 latency_tolerant_lines = 1;
1221 else
1222 latency_tolerant_lines = 2;
1223 }
1224
1225 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1226
1227 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1228 return true;
1229 else
1230 return false;
1231}
1232
1233/**
1234 * dce_v10_0_program_watermarks - program display watermarks
1235 *
1236 * @adev: amdgpu_device pointer
1237 * @amdgpu_crtc: the selected display controller
1238 * @lb_size: line buffer size
1239 * @num_heads: number of display controllers in use
1240 *
1241 * Calculate and program the display watermarks for the
1242 * selected display controller (CIK).
1243 */
1244static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1245 struct amdgpu_crtc *amdgpu_crtc,
1246 u32 lb_size, u32 num_heads)
1247{
1248 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1249 struct dce10_wm_params wm_low, wm_high;
1250 u32 pixel_period;
1251 u32 line_time = 0;
1252 u32 latency_watermark_a = 0, latency_watermark_b = 0;
8e36f9d3 1253 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
aaa36a97
AD		 1254
1255 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1256 pixel_period = 1000000 / (u32)mode->clock;
1257 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1258
1259 /* watermark for high clocks */
1260 if (adev->pm.dpm_enabled) {
1261 wm_high.yclk =
1262 amdgpu_dpm_get_mclk(adev, false) * 10;
1263 wm_high.sclk =
1264 amdgpu_dpm_get_sclk(adev, false) * 10;
1265 } else {
1266 wm_high.yclk = adev->pm.current_mclk * 10;
1267 wm_high.sclk = adev->pm.current_sclk * 10;
1268 }
1269
1270 wm_high.disp_clk = mode->clock;
1271 wm_high.src_width = mode->crtc_hdisplay;
1272 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1273 wm_high.blank_time = line_time - wm_high.active_time;
1274 wm_high.interlaced = false;
1275 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1276 wm_high.interlaced = true;
1277 wm_high.vsc = amdgpu_crtc->vsc;
1278 wm_high.vtaps = 1;
1279 if (amdgpu_crtc->rmx_type != RMX_OFF)
1280 wm_high.vtaps = 2;
1281 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1282 wm_high.lb_size = lb_size;
1283 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1284 wm_high.num_heads = num_heads;
1285
1286 /* set for high clocks */
1287 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1288
1289 /* possibly force display priority to high */
1290 /* should really do this at mode validation time... */
1291 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1292 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1293 !dce_v10_0_check_latency_hiding(&wm_high) ||
1294 (adev->mode_info.disp_priority == 2)) {
1295 DRM_DEBUG_KMS("force priority to high\n");
1296 }
1297
1298 /* watermark for low clocks */
1299 if (adev->pm.dpm_enabled) {
1300 wm_low.yclk =
1301 amdgpu_dpm_get_mclk(adev, true) * 10;
1302 wm_low.sclk =
1303 amdgpu_dpm_get_sclk(adev, true) * 10;
1304 } else {
1305 wm_low.yclk = adev->pm.current_mclk * 10;
1306 wm_low.sclk = adev->pm.current_sclk * 10;
1307 }
1308
1309 wm_low.disp_clk = mode->clock;
1310 wm_low.src_width = mode->crtc_hdisplay;
1311 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1312 wm_low.blank_time = line_time - wm_low.active_time;
1313 wm_low.interlaced = false;
1314 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1315 wm_low.interlaced = true;
1316 wm_low.vsc = amdgpu_crtc->vsc;
1317 wm_low.vtaps = 1;
1318 if (amdgpu_crtc->rmx_type != RMX_OFF)
1319 wm_low.vtaps = 2;
1320 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1321 wm_low.lb_size = lb_size;
1322 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1323 wm_low.num_heads = num_heads;
1324
1325 /* set for low clocks */
1326 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1327
1328 /* possibly force display priority to high */
1329 /* should really do this at mode validation time... */
1330 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1331 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1332 !dce_v10_0_check_latency_hiding(&wm_low) ||
1333 (adev->mode_info.disp_priority == 2)) {
1334 DRM_DEBUG_KMS("force priority to high\n");
1335 }
8e36f9d3 1336 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
aaa36a97
AD		 1337 }
1338
1339 /* select wm A */
1340 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1341 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1342 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1343 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1344 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1345 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1346 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1347 /* select wm B */
1348 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1349 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1350 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
be9fd2e9 1351 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
aaa36a97
AD		 1352 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1353 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1354 /* restore original selection */
1355 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1356
1357 /* save values for DPM */
1358 amdgpu_crtc->line_time = line_time;
1359 amdgpu_crtc->wm_high = latency_watermark_a;
1360 amdgpu_crtc->wm_low = latency_watermark_b;
8e36f9d3
AD		 1361 /* Save number of lines the linebuffer leads before the scanout */
1362 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
aaa36a97
AD		 1363}
1364
1365/**
1366 * dce_v10_0_bandwidth_update - program display watermarks
1367 *
1368 * @adev: amdgpu_device pointer
1369 *
1370 * Calculate and program the display watermarks and line
1371 * buffer allocation (CIK).
1372 */
1373static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1374{
1375 struct drm_display_mode *mode = NULL;
1376 u32 num_heads = 0, lb_size;
1377 int i;
1378
1379 amdgpu_update_display_priority(adev);
1380
1381 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1382 if (adev->mode_info.crtcs[i]->base.enabled)
1383 num_heads++;
1384 }
1385 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1386 mode = &adev->mode_info.crtcs[i]->base.mode;
1387 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1388 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1389 lb_size, num_heads);
1390 }
1391}
1392
1393static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1394{
1395 int i;
1396 u32 offset, tmp;
1397
1398 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1399 offset = adev->mode_info.audio.pin[i].offset;
1400 tmp = RREG32_AUDIO_ENDPT(offset,
1401 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1402 if (((tmp &
1403 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1404 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1405 adev->mode_info.audio.pin[i].connected = false;
1406 else
1407 adev->mode_info.audio.pin[i].connected = true;
1408 }
1409}
1410
1411static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1412{
1413 int i;
1414
1415 dce_v10_0_audio_get_connected_pins(adev);
1416
1417 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1418 if (adev->mode_info.audio.pin[i].connected)
1419 return &adev->mode_info.audio.pin[i];
1420 }
1421 DRM_ERROR("No connected audio pins found!\n");
1422 return NULL;
1423}
1424
1425static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1426{
1427 struct amdgpu_device *adev = encoder->dev->dev_private;
1428 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1429 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1430 u32 tmp;
1431
1432 if (!dig || !dig->afmt || !dig->afmt->pin)
1433 return;
1434
1435 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1436 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1437 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1438}
1439
1440static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1441 struct drm_display_mode *mode)
1442{
1443 struct amdgpu_device *adev = encoder->dev->dev_private;
1444 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1445 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1446 struct drm_connector *connector;
1447 struct amdgpu_connector *amdgpu_connector = NULL;
1448 u32 tmp;
1449 int interlace = 0;
1450
1451 if (!dig || !dig->afmt || !dig->afmt->pin)
1452 return;
1453
1454 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1455 if (connector->encoder == encoder) {
1456 amdgpu_connector = to_amdgpu_connector(connector);
1457 break;
1458 }
1459 }
1460
1461 if (!amdgpu_connector) {
1462 DRM_ERROR("Couldn't find encoder's connector\n");
1463 return;
1464 }
1465
1466 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1467 interlace = 1;
1468 if (connector->latency_present[interlace]) {
1469 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1470 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1471 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1472 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1473 } else {
1474 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1475 VIDEO_LIPSYNC, 0);
1476 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1477 AUDIO_LIPSYNC, 0);
1478 }
1479 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1480 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1481}
1482
1483static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1484{
1485 struct amdgpu_device *adev = encoder->dev->dev_private;
1486 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1487 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1488 struct drm_connector *connector;
1489 struct amdgpu_connector *amdgpu_connector = NULL;
1490 u32 tmp;
1491 u8 *sadb = NULL;
1492 int sad_count;
1493
1494 if (!dig || !dig->afmt || !dig->afmt->pin)
1495 return;
1496
1497 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1498 if (connector->encoder == encoder) {
1499 amdgpu_connector = to_amdgpu_connector(connector);
1500 break;
1501 }
1502 }
1503
1504 if (!amdgpu_connector) {
1505 DRM_ERROR("Couldn't find encoder's connector\n");
1506 return;
1507 }
1508
1509 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1510 if (sad_count < 0) {
1511 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1512 sad_count = 0;
1513 }
1514
1515 /* program the speaker allocation */
1516 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1517 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1518 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1519 DP_CONNECTION, 0);
1520 /* set HDMI mode */
1521 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1522 HDMI_CONNECTION, 1);
1523 if (sad_count)
1524 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1525 SPEAKER_ALLOCATION, sadb[0]);
1526 else
1527 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1528 SPEAKER_ALLOCATION, 5); /* stereo */
1529 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1530 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1531
1532 kfree(sadb);
1533}
1534
1535static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1536{
1537 struct amdgpu_device *adev = encoder->dev->dev_private;
1538 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1539 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1540 struct drm_connector *connector;
1541 struct amdgpu_connector *amdgpu_connector = NULL;
1542 struct cea_sad *sads;
1543 int i, sad_count;
1544
1545 static const u16 eld_reg_to_type[][2] = {
1546 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1547 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1548 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1549 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1550 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1551 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1552 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1553 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1554 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1555 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1556 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1557 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1558 };
1559
1560 if (!dig || !dig->afmt || !dig->afmt->pin)
1561 return;
1562
1563 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1564 if (connector->encoder == encoder) {
1565 amdgpu_connector = to_amdgpu_connector(connector);
1566 break;
1567 }
1568 }
1569
1570 if (!amdgpu_connector) {
1571 DRM_ERROR("Couldn't find encoder's connector\n");
1572 return;
1573 }
1574
1575 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1576 if (sad_count <= 0) {
1577 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1578 return;
1579 }
1580 BUG_ON(!sads);
1581
1582 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1583 u32 tmp = 0;
1584 u8 stereo_freqs = 0;
1585 int max_channels = -1;
1586 int j;
1587
1588 for (j = 0; j < sad_count; j++) {
1589 struct cea_sad *sad = &sads[j];
1590
1591 if (sad->format == eld_reg_to_type[i][1]) {
1592 if (sad->channels > max_channels) {
1593 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1594 MAX_CHANNELS, sad->channels);
1595 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1596 DESCRIPTOR_BYTE_2, sad->byte2);
1597 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1598 SUPPORTED_FREQUENCIES, sad->freq);
1599 max_channels = sad->channels;
1600 }
1601
1602 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1603 stereo_freqs |= sad->freq;
1604 else
1605 break;
1606 }
1607 }
1608
1609 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1610 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1611 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1612 }
1613
1614 kfree(sads);
1615}
1616
1617static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1618 struct amdgpu_audio_pin *pin,
1619 bool enable)
1620{
1621 if (!pin)
1622 return;
1623
1624 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1625 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1626}
1627
1628static const u32 pin_offsets[] =
1629{
1630 AUD0_REGISTER_OFFSET,
1631 AUD1_REGISTER_OFFSET,
1632 AUD2_REGISTER_OFFSET,
1633 AUD3_REGISTER_OFFSET,
1634 AUD4_REGISTER_OFFSET,
1635 AUD5_REGISTER_OFFSET,
1636 AUD6_REGISTER_OFFSET,
1637};
1638
1639static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1640{
1641 int i;
1642
1643 if (!amdgpu_audio)
1644 return 0;
1645
1646 adev->mode_info.audio.enabled = true;
1647
1648 adev->mode_info.audio.num_pins = 7;
1649
1650 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1651 adev->mode_info.audio.pin[i].channels = -1;
1652 adev->mode_info.audio.pin[i].rate = -1;
1653 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1654 adev->mode_info.audio.pin[i].status_bits = 0;
1655 adev->mode_info.audio.pin[i].category_code = 0;
1656 adev->mode_info.audio.pin[i].connected = false;
1657 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1658 adev->mode_info.audio.pin[i].id = i;
1659 /* disable audio. it will be set up later */
1660 /* XXX remove once we switch to ip funcs */
1661 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1662 }
1663
1664 return 0;
1665}
1666
1667static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1668{
1669 int i;
1670
1671 if (!adev->mode_info.audio.enabled)
1672 return;
1673
1674 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1675 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1676
1677 adev->mode_info.audio.enabled = false;
1678}
1679
1680/*
1681 * update the N and CTS parameters for a given pixel clock rate
1682 */
1683static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1684{
1685 struct drm_device *dev = encoder->dev;
1686 struct amdgpu_device *adev = dev->dev_private;
1687 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1688 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1689 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1690 u32 tmp;
1691
1692 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1694 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1695 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1696 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1697 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1698
1699 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1700 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1701 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1702 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1703 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1704 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1705
1706 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1707 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1708 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1709 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1710 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1711 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1712
1713}
1714
1715/*
1716 * build a HDMI Video Info Frame
1717 */
1718static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1719 void *buffer, size_t size)
1720{
1721 struct drm_device *dev = encoder->dev;
1722 struct amdgpu_device *adev = dev->dev_private;
1723 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1724 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1725 uint8_t *frame = buffer + 3;
1726 uint8_t *header = buffer;
1727
1728 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1729 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1730 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1731 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1732 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1733 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1734 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1735 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1736}
1737
1738static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1739{
1740 struct drm_device *dev = encoder->dev;
1741 struct amdgpu_device *adev = dev->dev_private;
1742 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1743 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1744 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1745 u32 dto_phase = 24 * 1000;
1746 u32 dto_modulo = clock;
1747 u32 tmp;
1748
1749 if (!dig || !dig->afmt)
1750 return;
1751
1752 /* XXX two dtos; generally use dto0 for hdmi */
1753 /* Express [24MHz / target pixel clock] as an exact rational
1754 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1755 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1756 */
1757 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1758 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1759 amdgpu_crtc->crtc_id);
1760 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1761 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1762 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1763}
1764
1765/*
1766 * update the info frames with the data from the current display mode
1767 */
1768static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1769 struct drm_display_mode *mode)
1770{
1771 struct drm_device *dev = encoder->dev;
1772 struct amdgpu_device *adev = dev->dev_private;
1773 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1774 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1775 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1776 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1777 struct hdmi_avi_infoframe frame;
1778 ssize_t err;
1779 u32 tmp;
1780 int bpc = 8;
1781
1782 if (!dig || !dig->afmt)
1783 return;
1784
1785 /* Silent, r600_hdmi_enable will raise WARN for us */
1786 if (!dig->afmt->enabled)
1787 return;
1788
1789 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1790 if (encoder->crtc) {
1791 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1792 bpc = amdgpu_crtc->bpc;
1793 }
1794
1795 /* disable audio prior to setting up hw */
1796 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1797 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1798
1799 dce_v10_0_audio_set_dto(encoder, mode->clock);
1800
1801 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1802 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1803 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1804
1805 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1806
1807 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1808 switch (bpc) {
1809 case 0:
1810 case 6:
1811 case 8:
1812 case 16:
1813 default:
1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1815 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1816 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1817 connector->name, bpc);
1818 break;
1819 case 10:
1820 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1821 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1822 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1823 connector->name);
1824 break;
1825 case 12:
1826 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1827 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1828 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1829 connector->name);
1830 break;
1831 }
1832 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1833
1834 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1835 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1836 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1837 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1838 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1839
1840 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1841 /* enable audio info frames (frames won't be set until audio is enabled) */
1842 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1843 /* required for audio info values to be updated */
1844 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1845 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1846
1847 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1848 /* required for audio info values to be updated */
1849 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1850 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1851
1852 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1853 /* anything other than 0 */
1854 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1855 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1856
1857 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1858
1859 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1860 /* set the default audio delay */
1861 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1862 /* should be suffient for all audio modes and small enough for all hblanks */
1863 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1864 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1865
1866 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1867 /* allow 60958 channel status fields to be updated */
1868 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1869 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1870
1871 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1872 if (bpc > 8)
1873 /* clear SW CTS value */
1874 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1875 else
1876 /* select SW CTS value */
1877 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1878 /* allow hw to sent ACR packets when required */
1879 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1880 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1881
1882 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1883
1884 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1885 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1886 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1887
1888 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1889 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1890 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1891
1892 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1893 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1894 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1895 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1896 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1897 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1898 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1899 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1900
1901 dce_v10_0_audio_write_speaker_allocation(encoder);
1902
1903 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1904 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1905
1906 dce_v10_0_afmt_audio_select_pin(encoder);
1907 dce_v10_0_audio_write_sad_regs(encoder);
1908 dce_v10_0_audio_write_latency_fields(encoder, mode);
1909
1910 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1911 if (err < 0) {
1912 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1913 return;
1914 }
1915
1916 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1917 if (err < 0) {
1918 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1919 return;
1920 }
1921
1922 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1923
1924 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1925 /* enable AVI info frames */
1926 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1927 /* required for audio info values to be updated */
1928 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1929 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1930
1931 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1932 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1933 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1934
1935 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1936 /* send audio packets */
1937 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1938 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1939
1940 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1941 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1942 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1943 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1944
1945 /* enable audio after to setting up hw */
1946 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1947}
1948
1949static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1950{
1951 struct drm_device *dev = encoder->dev;
1952 struct amdgpu_device *adev = dev->dev_private;
1953 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1954 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1955
1956 if (!dig || !dig->afmt)
1957 return;
1958
1959 /* Silent, r600_hdmi_enable will raise WARN for us */
1960 if (enable && dig->afmt->enabled)
1961 return;
1962 if (!enable && !dig->afmt->enabled)
1963 return;
1964
1965 if (!enable && dig->afmt->pin) {
1966 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1967 dig->afmt->pin = NULL;
1968 }
1969
1970 dig->afmt->enabled = enable;
1971
1972 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1973 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1974}
1975
1976static void dce_v10_0_afmt_init(struct amdgpu_device *adev)
1977{
1978 int i;
1979
1980 for (i = 0; i < adev->mode_info.num_dig; i++)
1981 adev->mode_info.afmt[i] = NULL;
1982
1983 /* DCE10 has audio blocks tied to DIG encoders */
1984 for (i = 0; i < adev->mode_info.num_dig; i++) {
1985 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1986 if (adev->mode_info.afmt[i]) {
1987 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1988 adev->mode_info.afmt[i]->id = i;
1989 }
1990 }
1991}
1992
1993static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1994{
1995 int i;
1996
1997 for (i = 0; i < adev->mode_info.num_dig; i++) {
1998 kfree(adev->mode_info.afmt[i]);
1999 adev->mode_info.afmt[i] = NULL;
2000 }
2001}
2002
2003static const u32 vga_control_regs[6] =
2004{
2005 mmD1VGA_CONTROL,
2006 mmD2VGA_CONTROL,
2007 mmD3VGA_CONTROL,
2008 mmD4VGA_CONTROL,
2009 mmD5VGA_CONTROL,
2010 mmD6VGA_CONTROL,
2011};
2012
2013static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
2014{
2015 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2016 struct drm_device *dev = crtc->dev;
2017 struct amdgpu_device *adev = dev->dev_private;
2018 u32 vga_control;
2019
2020 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2021 if (enable)
2022 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2023 else
2024 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2025}
2026
2027static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
2028{
2029 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2030 struct drm_device *dev = crtc->dev;
2031 struct amdgpu_device *adev = dev->dev_private;
2032
2033 if (enable)
2034 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2035 else
2036 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2037}
2038
aaa36a97
AD		 2039static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
2040 struct drm_framebuffer *fb,
2041 int x, int y, int atomic)
2042{
2043 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2044 struct drm_device *dev = crtc->dev;
2045 struct amdgpu_device *adev = dev->dev_private;
2046 struct amdgpu_framebuffer *amdgpu_fb;
2047 struct drm_framebuffer *target_fb;
2048 struct drm_gem_object *obj;
2049 struct amdgpu_bo *rbo;
2050 uint64_t fb_location, tiling_flags;
2051 uint32_t fb_format, fb_pitch_pixels;
aaa36a97 2052 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
fbd76d59 2053 u32 pipe_config;
aaa36a97
AD		 2054 u32 tmp, viewport_w, viewport_h;
2055 int r;
2056 bool bypass_lut = false;
2057
2058 /* no fb bound */
2059 if (!atomic && !crtc->primary->fb) {
2060 DRM_DEBUG_KMS("No FB bound\n");
2061 return 0;
2062 }
2063
2064 if (atomic) {
2065 amdgpu_fb = to_amdgpu_framebuffer(fb);
2066 target_fb = fb;
2067 }
2068 else {
2069 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2070 target_fb = crtc->primary->fb;
2071 }
2072
2073 /* If atomic, assume fb object is pinned & idle & fenced and
2074 * just update base pointers
2075 */
2076 obj = amdgpu_fb->obj;
2077 rbo = gem_to_amdgpu_bo(obj);
2078 r = amdgpu_bo_reserve(rbo, false);
2079 if (unlikely(r != 0))
2080 return r;
2081
2082 if (atomic)
2083 fb_location = amdgpu_bo_gpu_offset(rbo);
2084 else {
2085 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2086 if (unlikely(r != 0)) {
2087 amdgpu_bo_unreserve(rbo);
2088 return -EINVAL;
2089 }
2090 }
2091
2092 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2093 amdgpu_bo_unreserve(rbo);
2094
fbd76d59
MO		 2095 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2096
aaa36a97
AD		 2097 switch (target_fb->pixel_format) {
2098 case DRM_FORMAT_C8:
2099 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2100 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2101 break;
2102 case DRM_FORMAT_XRGB4444:
2103 case DRM_FORMAT_ARGB4444:
2104 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2105 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2106#ifdef __BIG_ENDIAN
2107 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2108 ENDIAN_8IN16);
2109#endif
2110 break;
2111 case DRM_FORMAT_XRGB1555:
2112 case DRM_FORMAT_ARGB1555:
2113 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2114 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2115#ifdef __BIG_ENDIAN
2116 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2117 ENDIAN_8IN16);
2118#endif
2119 break;
2120 case DRM_FORMAT_BGRX5551:
2121 case DRM_FORMAT_BGRA5551:
2122 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2123 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2124#ifdef __BIG_ENDIAN
2125 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2126 ENDIAN_8IN16);
2127#endif
2128 break;
2129 case DRM_FORMAT_RGB565:
2130 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2131 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2132#ifdef __BIG_ENDIAN
2133 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2134 ENDIAN_8IN16);
2135#endif
2136 break;
2137 case DRM_FORMAT_XRGB8888:
2138 case DRM_FORMAT_ARGB8888:
2139 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2140 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2141#ifdef __BIG_ENDIAN
2142 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2143 ENDIAN_8IN32);
2144#endif
2145 break;
2146 case DRM_FORMAT_XRGB2101010:
2147 case DRM_FORMAT_ARGB2101010:
2148 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2149 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2150#ifdef __BIG_ENDIAN
2151 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2152 ENDIAN_8IN32);
2153#endif
2154 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2155 bypass_lut = true;
2156 break;
2157 case DRM_FORMAT_BGRX1010102:
2158 case DRM_FORMAT_BGRA1010102:
2159 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2160 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2161#ifdef __BIG_ENDIAN
2162 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2163 ENDIAN_8IN32);
2164#endif
2165 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2166 bypass_lut = true;
2167 break;
2168 default:
2169 DRM_ERROR("Unsupported screen format %s\n",
2170 drm_get_format_name(target_fb->pixel_format));
2171 return -EINVAL;
2172 }
2173
fbd76d59
MO		 2174 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2175 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
aaa36a97 2176
fbd76d59
MO		 2177 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2178 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2179 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2180 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2181 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
aaa36a97 2182
aaa36a97
AD		 2183 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2184 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2185 ARRAY_2D_TILED_THIN1);
2186 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2187 tile_split);
2188 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2189 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2190 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2191 mtaspect);
2192 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2193 ADDR_SURF_MICRO_TILING_DISPLAY);
fbd76d59 2194 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
aaa36a97
AD		 2195 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2196 ARRAY_1D_TILED_THIN1);
2197 }
2198
aaa36a97
AD		 2199 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2200 pipe_config);
2201
2202 dce_v10_0_vga_enable(crtc, false);
2203
2204 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2205 upper_32_bits(fb_location));
2206 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2207 upper_32_bits(fb_location));
2208 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2209 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2210 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2211 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2212 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2213 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2214
2215 /*
2216 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2217 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2218 * retain the full precision throughout the pipeline.
2219 */
2220 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2221 if (bypass_lut)
2222 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2223 else
2224 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2225 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2226
2227 if (bypass_lut)
2228 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2229
2230 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2231 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2232 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2233 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2234 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2235 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2236
2237 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2238 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2239
2240 dce_v10_0_grph_enable(crtc, true);
2241
2242 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2243 target_fb->height);
2244
2245 x &= ~3;
2246 y &= ~1;
2247 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2248 (x << 16) | y);
2249 viewport_w = crtc->mode.hdisplay;
2250 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2251 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2252 (viewport_w << 16) | viewport_h);
2253
2254 /* pageflip setup */
2255 /* make sure flip is at vb rather than hb */
2256 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2257 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2258 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2259 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2260
2261 /* set pageflip to happen only at start of vblank interval (front porch) */
2262 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2263
2264 if (!atomic && fb && fb != crtc->primary->fb) {
2265 amdgpu_fb = to_amdgpu_framebuffer(fb);
2266 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2267 r = amdgpu_bo_reserve(rbo, false);
2268 if (unlikely(r != 0))
2269 return r;
2270 amdgpu_bo_unpin(rbo);
2271 amdgpu_bo_unreserve(rbo);
2272 }
2273
2274 /* Bytes per pixel may have changed */
2275 dce_v10_0_bandwidth_update(adev);
2276
2277 return 0;
2278}
2279
2280static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2281 struct drm_display_mode *mode)
2282{
2283 struct drm_device *dev = crtc->dev;
2284 struct amdgpu_device *adev = dev->dev_private;
2285 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2286 u32 tmp;
2287
2288 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2289 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2290 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2291 else
2292 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2293 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2294}
2295
2296static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2297{
2298 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2299 struct drm_device *dev = crtc->dev;
2300 struct amdgpu_device *adev = dev->dev_private;
2301 int i;
2302 u32 tmp;
2303
2304 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2305
2306 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2307 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2308 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2309 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2310
2311 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2312 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2313 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2314
2315 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2316 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2317 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2318
2319 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2320 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2321 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2322 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2323
2324 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2325
2326 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2327 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2328 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2329
2330 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2331 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2332 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2333
2334 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2335 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2336
2337 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2338 for (i = 0; i < 256; i++) {
2339 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2340 (amdgpu_crtc->lut_r[i] << 20) |
2341 (amdgpu_crtc->lut_g[i] << 10) |
2342 (amdgpu_crtc->lut_b[i] << 0));
2343 }
2344
2345 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2346 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2347 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2348 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2349 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2350
2351 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2352 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2353 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2354 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2355
2356 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2357 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2358 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2359 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2360
2361 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2362 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2363 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2364 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2365
2366 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2367 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2368 /* XXX this only needs to be programmed once per crtc at startup,
2369 * not sure where the best place for it is
2370 */
2371 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2372 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2373 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2374}
2375
2376static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2377{
2378 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2379 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2380
2381 switch (amdgpu_encoder->encoder_id) {
2382 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2383 if (dig->linkb)
2384 return 1;
2385 else
2386 return 0;
2387 break;
2388 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2389 if (dig->linkb)
2390 return 3;
2391 else
2392 return 2;
2393 break;
2394 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2395 if (dig->linkb)
2396 return 5;
2397 else
2398 return 4;
2399 break;
2400 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2401 return 6;
2402 break;
2403 default:
2404 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2405 return 0;
2406 }
2407}
2408
2409/**
2410 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2411 *
2412 * @crtc: drm crtc
2413 *
2414 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2415 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2416 * monitors a dedicated PPLL must be used. If a particular board has
2417 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2418 * as there is no need to program the PLL itself. If we are not able to
2419 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2420 * avoid messing up an existing monitor.
2421 *
2422 * Asic specific PLL information
2423 *
2424 * DCE 10.x
2425 * Tonga
2426 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2427 * CI
2428 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2429 *
2430 */
2431static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2432{
2433 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2434 struct drm_device *dev = crtc->dev;
2435 struct amdgpu_device *adev = dev->dev_private;
2436 u32 pll_in_use;
2437 int pll;
2438
2439 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2440 if (adev->clock.dp_extclk)
2441 /* skip PPLL programming if using ext clock */
2442 return ATOM_PPLL_INVALID;
2443 else {
2444 /* use the same PPLL for all DP monitors */
2445 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2446 if (pll != ATOM_PPLL_INVALID)
2447 return pll;
2448 }
2449 } else {
2450 /* use the same PPLL for all monitors with the same clock */
2451 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2452 if (pll != ATOM_PPLL_INVALID)
2453 return pll;
2454 }
2455
2456 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2457 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2458 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2459 return ATOM_PPLL2;
2460 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2461 return ATOM_PPLL1;
2462 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2463 return ATOM_PPLL0;
2464 DRM_ERROR("unable to allocate a PPLL\n");
2465 return ATOM_PPLL_INVALID;
2466}
2467
2468static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2469{
2470 struct amdgpu_device *adev = crtc->dev->dev_private;
2471 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2472 uint32_t cur_lock;
2473
2474 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2475 if (lock)
2476 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2477 else
2478 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2479 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2480}
2481
2482static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2483{
2484 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2485 struct amdgpu_device *adev = crtc->dev->dev_private;
2486 u32 tmp;
2487
2488 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2489 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2490 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2491}
2492
2493static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2494{
2495 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2496 struct amdgpu_device *adev = crtc->dev->dev_private;
2497 u32 tmp;
2498
3c681718
AD		 2499 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2500 upper_32_bits(amdgpu_crtc->cursor_addr));
2501 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2502 lower_32_bits(amdgpu_crtc->cursor_addr));
2503
aaa36a97
AD		 2504 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2505 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2506 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2507 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2508}
2509
29275a9b
AD		 2510static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2511 int x, int y)
aaa36a97
AD		 2512{
2513 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2514 struct amdgpu_device *adev = crtc->dev->dev_private;
2515 int xorigin = 0, yorigin = 0;
2516
2517 /* avivo cursor are offset into the total surface */
2518 x += crtc->x;
2519 y += crtc->y;
2520 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2521
2522 if (x < 0) {
2523 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2524 x = 0;
2525 }
2526 if (y < 0) {
2527 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2528 y = 0;
2529 }
2530
aaa36a97
AD		 2531 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2532 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2533 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2534 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
29275a9b
AD		 2535
2536 amdgpu_crtc->cursor_x = x;
2537 amdgpu_crtc->cursor_y = y;
aaa36a97
AD		 2538
2539 return 0;
2540}
2541
29275a9b
AD		 2542static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2543 int x, int y)
2544{
2545 int ret;
2546
2547 dce_v10_0_lock_cursor(crtc, true);
2548 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2549 dce_v10_0_lock_cursor(crtc, false);
2550
2551 return ret;
2552}
2553
2554static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2555 struct drm_file *file_priv,
2556 uint32_t handle,
2557 uint32_t width,
2558 uint32_t height,
2559 int32_t hot_x,
2560 int32_t hot_y)
aaa36a97
AD		 2561{
2562 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2563 struct drm_gem_object *obj;
f9242d1b 2564 struct amdgpu_bo *aobj;
aaa36a97
AD		 2565 int ret;
2566
2567 if (!handle) {
2568 /* turn off cursor */
2569 dce_v10_0_hide_cursor(crtc);
2570 obj = NULL;
2571 goto unpin;
2572 }
2573
2574 if ((width > amdgpu_crtc->max_cursor_width) ||
2575 (height > amdgpu_crtc->max_cursor_height)) {
2576 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2577 return -EINVAL;
2578 }
2579
2580 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2581 if (!obj) {
2582 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2583 return -ENOENT;
2584 }
2585
f9242d1b
AD		 2586 aobj = gem_to_amdgpu_bo(obj);
2587 ret = amdgpu_bo_reserve(aobj, false);
2588 if (ret != 0) {
2589 drm_gem_object_unreference_unlocked(obj);
2590 return ret;
2591 }
2592
2593 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2594 amdgpu_bo_unreserve(aobj);
2595 if (ret) {
2596 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2597 drm_gem_object_unreference_unlocked(obj);
2598 return ret;
2599 }
aaa36a97
AD		 2600
2601 amdgpu_crtc->cursor_width = width;
2602 amdgpu_crtc->cursor_height = height;
2603
2604 dce_v10_0_lock_cursor(crtc, true);
ef67e38c
AD		 2605
2606 if (hot_x != amdgpu_crtc->cursor_hot_x ||
2607 hot_y != amdgpu_crtc->cursor_hot_y) {
2608 int x, y;
2609
2610 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2611 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2612
2613 dce_v10_0_cursor_move_locked(crtc, x, y);
2614
2615 amdgpu_crtc->cursor_hot_x = hot_x;
2616 amdgpu_crtc->cursor_hot_y = hot_y;
2617 }
2618
aaa36a97
AD		 2619 dce_v10_0_show_cursor(crtc);
2620 dce_v10_0_lock_cursor(crtc, false);
2621
2622unpin:
2623 if (amdgpu_crtc->cursor_bo) {
dd0b5d2f
AD		 2624 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2625 ret = amdgpu_bo_reserve(aobj, false);
aaa36a97 2626 if (likely(ret == 0)) {
dd0b5d2f
AD		 2627 amdgpu_bo_unpin(aobj);
2628 amdgpu_bo_unreserve(aobj);
aaa36a97
AD		 2629 }
2630 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2631 }
2632
2633 amdgpu_crtc->cursor_bo = obj;
2634 return 0;
dd0b5d2f 2635}
aaa36a97 2636
dd0b5d2f
AD		 2637static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2638{
2639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
dd0b5d2f
AD		 2640
2641 if (amdgpu_crtc->cursor_bo) {
2642 dce_v10_0_lock_cursor(crtc, true);
2643
2644 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2645 amdgpu_crtc->cursor_y);
2646
f9242d1b 2647 dce_v10_0_show_cursor(crtc);
dd0b5d2f
AD		 2648
2649 dce_v10_0_lock_cursor(crtc, false);
2650 }
aaa36a97
AD		 2651}
2652
2653static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2654 u16 *blue, uint32_t start, uint32_t size)
2655{
2656 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2657 int end = (start + size > 256) ? 256 : start + size, i;
2658
2659 /* userspace palettes are always correct as is */
2660 for (i = start; i < end; i++) {
2661 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2662 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2663 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2664 }
2665 dce_v10_0_crtc_load_lut(crtc);
2666}
2667
2668static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2669{
2670 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2671
2672 drm_crtc_cleanup(crtc);
aaa36a97
AD		 2673 kfree(amdgpu_crtc);
2674}
2675
2676static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
29275a9b 2677 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
aaa36a97
AD		 2678 .cursor_move = dce_v10_0_crtc_cursor_move,
2679 .gamma_set = dce_v10_0_crtc_gamma_set,
2680 .set_config = amdgpu_crtc_set_config,
2681 .destroy = dce_v10_0_crtc_destroy,
2682 .page_flip = amdgpu_crtc_page_flip,
2683};
2684
2685static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2686{
2687 struct drm_device *dev = crtc->dev;
2688 struct amdgpu_device *adev = dev->dev_private;
2689 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
5e6775ab 2690 unsigned type;
aaa36a97
AD		 2691
2692 switch (mode) {
2693 case DRM_MODE_DPMS_ON:
2694 amdgpu_crtc->enabled = true;
2695 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2696 dce_v10_0_vga_enable(crtc, true);
2697 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2698 dce_v10_0_vga_enable(crtc, false);
f6c7aba4 2699 /* Make sure VBLANK and PFLIP interrupts are still enabled */
5e6775ab
MD		 2700 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2701 amdgpu_irq_update(adev, &adev->crtc_irq, type);
f6c7aba4 2702 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
aaa36a97
AD		 2703 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2704 dce_v10_0_crtc_load_lut(crtc);
2705 break;
2706 case DRM_MODE_DPMS_STANDBY:
2707 case DRM_MODE_DPMS_SUSPEND:
2708 case DRM_MODE_DPMS_OFF:
2709 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2710 if (amdgpu_crtc->enabled) {
2711 dce_v10_0_vga_enable(crtc, true);
2712 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2713 dce_v10_0_vga_enable(crtc, false);
2714 }
2715 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2716 amdgpu_crtc->enabled = false;
2717 break;
2718 }
2719 /* adjust pm to dpms */
2720 amdgpu_pm_compute_clocks(adev);
2721}
2722
2723static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2724{
2725 /* disable crtc pair power gating before programming */
2726 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2727 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2728 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2729}
2730
2731static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2732{
2733 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2734 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2735}
2736
2737static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2738{
2739 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2740 struct drm_device *dev = crtc->dev;
2741 struct amdgpu_device *adev = dev->dev_private;
2742 struct amdgpu_atom_ss ss;
2743 int i;
2744
2745 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2746 if (crtc->primary->fb) {
2747 int r;
2748 struct amdgpu_framebuffer *amdgpu_fb;
2749 struct amdgpu_bo *rbo;
2750
2751 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2752 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2753 r = amdgpu_bo_reserve(rbo, false);
2754 if (unlikely(r))
2755 DRM_ERROR("failed to reserve rbo before unpin\n");
2756 else {
2757 amdgpu_bo_unpin(rbo);
2758 amdgpu_bo_unreserve(rbo);
2759 }
2760 }
2761 /* disable the GRPH */
2762 dce_v10_0_grph_enable(crtc, false);
2763
2764 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2765
2766 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2767 if (adev->mode_info.crtcs[i] &&
2768 adev->mode_info.crtcs[i]->enabled &&
2769 i != amdgpu_crtc->crtc_id &&
2770 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2771 /* one other crtc is using this pll don't turn
2772 * off the pll
2773 */
2774 goto done;
2775 }
2776 }
2777
2778 switch (amdgpu_crtc->pll_id) {
2779 case ATOM_PPLL0:
2780 case ATOM_PPLL1:
2781 case ATOM_PPLL2:
2782 /* disable the ppll */
2783 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2784 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2785 break;
2786 default:
2787 break;
2788 }
2789done:
2790 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2791 amdgpu_crtc->adjusted_clock = 0;
2792 amdgpu_crtc->encoder = NULL;
2793 amdgpu_crtc->connector = NULL;
2794}
2795
2796static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2797 struct drm_display_mode *mode,
2798 struct drm_display_mode *adjusted_mode,
2799 int x, int y, struct drm_framebuffer *old_fb)
2800{
2801 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2802
2803 if (!amdgpu_crtc->adjusted_clock)
2804 return -EINVAL;
2805
2806 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2807 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2808 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2809 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2810 amdgpu_atombios_crtc_scaler_setup(crtc);
dd0b5d2f 2811 dce_v10_0_cursor_reset(crtc);
aaa36a97
AD		 2812 /* update the hw version fpr dpm */
2813 amdgpu_crtc->hw_mode = *adjusted_mode;
2814
2815 return 0;
2816}
2817
2818static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2819 const struct drm_display_mode *mode,
2820 struct drm_display_mode *adjusted_mode)
2821{
2822 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2823 struct drm_device *dev = crtc->dev;
2824 struct drm_encoder *encoder;
2825
2826 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2827 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2828 if (encoder->crtc == crtc) {
2829 amdgpu_crtc->encoder = encoder;
2830 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2831 break;
2832 }
2833 }
2834 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2835 amdgpu_crtc->encoder = NULL;
2836 amdgpu_crtc->connector = NULL;
2837 return false;
2838 }
2839 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2840 return false;
2841 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2842 return false;
2843 /* pick pll */
2844 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2845 /* if we can't get a PPLL for a non-DP encoder, fail */
2846 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2847 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2848 return false;
2849
2850 return true;
2851}
2852
2853static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2854 struct drm_framebuffer *old_fb)
2855{
2856 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2857}
2858
2859static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2860 struct drm_framebuffer *fb,
2861 int x, int y, enum mode_set_atomic state)
2862{
2863 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2864}
2865
2866static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2867 .dpms = dce_v10_0_crtc_dpms,
2868 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2869 .mode_set = dce_v10_0_crtc_mode_set,
2870 .mode_set_base = dce_v10_0_crtc_set_base,
2871 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2872 .prepare = dce_v10_0_crtc_prepare,
2873 .commit = dce_v10_0_crtc_commit,
2874 .load_lut = dce_v10_0_crtc_load_lut,
2875 .disable = dce_v10_0_crtc_disable,
2876};
2877
2878static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2879{
2880 struct amdgpu_crtc *amdgpu_crtc;
2881 int i;
2882
2883 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2884 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2885 if (amdgpu_crtc == NULL)
2886 return -ENOMEM;
2887
2888 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2889
2890 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2891 amdgpu_crtc->crtc_id = index;
aaa36a97
AD		 2892 adev->mode_info.crtcs[index] = amdgpu_crtc;
2893
2894 amdgpu_crtc->max_cursor_width = 128;
2895 amdgpu_crtc->max_cursor_height = 128;
2896 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2897 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2898
2899 for (i = 0; i < 256; i++) {
2900 amdgpu_crtc->lut_r[i] = i << 2;
2901 amdgpu_crtc->lut_g[i] = i << 2;
2902 amdgpu_crtc->lut_b[i] = i << 2;
2903 }
2904
2905 switch (amdgpu_crtc->crtc_id) {
2906 case 0:
2907 default:
2908 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2909 break;
2910 case 1:
2911 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2912 break;
2913 case 2:
2914 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2915 break;
2916 case 3:
2917 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2918 break;
2919 case 4:
2920 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2921 break;
2922 case 5:
2923 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2924 break;
2925 }
2926
2927 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2928 amdgpu_crtc->adjusted_clock = 0;
2929 amdgpu_crtc->encoder = NULL;
2930 amdgpu_crtc->connector = NULL;
2931 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2932
2933 return 0;
2934}
2935
5fc3aeeb 2936static int dce_v10_0_early_init(void *handle)
aaa36a97 2937{
5fc3aeeb 2938 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2939
aaa36a97
AD		 2940 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2941 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2942
2943 dce_v10_0_set_display_funcs(adev);
2944 dce_v10_0_set_irq_funcs(adev);
2945
2946 switch (adev->asic_type) {
84390860 2947 case CHIP_FIJI:
aaa36a97
AD		 2948 case CHIP_TONGA:
2949 adev->mode_info.num_crtc = 6; /* XXX 7??? */
2950 adev->mode_info.num_hpd = 6;
2951 adev->mode_info.num_dig = 7;
2952 break;
2953 default:
2954 /* FIXME: not supported yet */
2955 return -EINVAL;
2956 }
2957
2958 return 0;
2959}
2960
5fc3aeeb 2961static int dce_v10_0_sw_init(void *handle)
aaa36a97
AD		 2962{
2963 int r, i;
5fc3aeeb 2964 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 2965
2966 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2967 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2968 if (r)
2969 return r;
2970 }
2971
2972 for (i = 8; i < 20; i += 2) {
2973 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2974 if (r)
2975 return r;
2976 }
2977
2978 /* HPD hotplug */
2979 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2980 if (r)
2981 return r;
2982
2983 adev->mode_info.mode_config_initialized = true;
2984
2985 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2986
2987 adev->ddev->mode_config.max_width = 16384;
2988 adev->ddev->mode_config.max_height = 16384;
2989
2990 adev->ddev->mode_config.preferred_depth = 24;
2991 adev->ddev->mode_config.prefer_shadow = 1;
2992
2993 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2994
2995 r = amdgpu_modeset_create_props(adev);
2996 if (r)
2997 return r;
2998
2999 adev->ddev->mode_config.max_width = 16384;
3000 adev->ddev->mode_config.max_height = 16384;
3001
3002 /* allocate crtcs */
3003 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3004 r = dce_v10_0_crtc_init(adev, i);
3005 if (r)
3006 return r;
3007 }
3008
3009 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3010 amdgpu_print_display_setup(adev->ddev);
3011 else
3012 return -EINVAL;
3013
3014 /* setup afmt */
3015 dce_v10_0_afmt_init(adev);
3016
3017 r = dce_v10_0_audio_init(adev);
3018 if (r)
3019 return r;
3020
3021 drm_kms_helper_poll_init(adev->ddev);
3022
3023 return r;
3024}
3025
5fc3aeeb 3026static int dce_v10_0_sw_fini(void *handle)
aaa36a97 3027{
5fc3aeeb 3028 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3029
aaa36a97
AD		 3030 kfree(adev->mode_info.bios_hardcoded_edid);
3031
3032 drm_kms_helper_poll_fini(adev->ddev);
3033
3034 dce_v10_0_audio_fini(adev);
3035
3036 dce_v10_0_afmt_fini(adev);
3037
3038 drm_mode_config_cleanup(adev->ddev);
3039 adev->mode_info.mode_config_initialized = false;
3040
3041 return 0;
3042}
3043
5fc3aeeb 3044static int dce_v10_0_hw_init(void *handle)
aaa36a97
AD		 3045{
3046 int i;
5fc3aeeb 3047 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3048
3049 dce_v10_0_init_golden_registers(adev);
3050
3051 /* init dig PHYs, disp eng pll */
3052 amdgpu_atombios_encoder_init_dig(adev);
3053 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3054
3055 /* initialize hpd */
3056 dce_v10_0_hpd_init(adev);
3057
3058 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3059 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3060 }
3061
f6c7aba4
MD		 3062 dce_v10_0_pageflip_interrupt_init(adev);
3063
aaa36a97
AD		 3064 return 0;
3065}
3066
5fc3aeeb 3067static int dce_v10_0_hw_fini(void *handle)
aaa36a97
AD		 3068{
3069 int i;
5fc3aeeb 3070 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3071
3072 dce_v10_0_hpd_fini(adev);
3073
3074 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3075 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3076 }
3077
f6c7aba4
MD		 3078 dce_v10_0_pageflip_interrupt_fini(adev);
3079
aaa36a97
AD		 3080 return 0;
3081}
3082
5fc3aeeb 3083static int dce_v10_0_suspend(void *handle)
aaa36a97 3084{
5fc3aeeb 3085 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 3086
aaa36a97
AD		 3087 amdgpu_atombios_scratch_regs_save(adev);
3088
f9fff064 3089 return dce_v10_0_hw_fini(handle);
aaa36a97
AD		 3090}
3091
5fc3aeeb 3092static int dce_v10_0_resume(void *handle)
aaa36a97 3093{
5fc3aeeb 3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
f9fff064 3095 int ret;
aaa36a97 3096
f9fff064 3097 ret = dce_v10_0_hw_init(handle);
aaa36a97
AD		 3098
3099 amdgpu_atombios_scratch_regs_restore(adev);
3100
aaa36a97
AD		 3101 /* turn on the BL */
3102 if (adev->mode_info.bl_encoder) {
3103 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3104 adev->mode_info.bl_encoder);
3105 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3106 bl_level);
3107 }
3108
f9fff064 3109 return ret;
aaa36a97
AD		 3110}
3111
5fc3aeeb 3112static bool dce_v10_0_is_idle(void *handle)
aaa36a97 3113{
aaa36a97
AD		 3114 return true;
3115}
3116
5fc3aeeb 3117static int dce_v10_0_wait_for_idle(void *handle)
aaa36a97 3118{
aaa36a97
AD		 3119 return 0;
3120}
3121
5fc3aeeb 3122static void dce_v10_0_print_status(void *handle)
aaa36a97 3123{
5fc3aeeb 3124 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3125
aaa36a97
AD		 3126 dev_info(adev->dev, "DCE 10.x registers\n");
3127 /* XXX todo */
3128}
3129
5fc3aeeb 3130static int dce_v10_0_soft_reset(void *handle)
aaa36a97
AD		 3131{
3132 u32 srbm_soft_reset = 0, tmp;
5fc3aeeb 3133 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3134
3135 if (dce_v10_0_is_display_hung(adev))
3136 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3137
3138 if (srbm_soft_reset) {
5fc3aeeb 3139 dce_v10_0_print_status((void *)adev);
aaa36a97
AD		 3140
3141 tmp = RREG32(mmSRBM_SOFT_RESET);
3142 tmp |= srbm_soft_reset;
3143 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3144 WREG32(mmSRBM_SOFT_RESET, tmp);
3145 tmp = RREG32(mmSRBM_SOFT_RESET);
3146
3147 udelay(50);
3148
3149 tmp &= ~srbm_soft_reset;
3150 WREG32(mmSRBM_SOFT_RESET, tmp);
3151 tmp = RREG32(mmSRBM_SOFT_RESET);
3152
3153 /* Wait a little for things to settle down */
3154 udelay(50);
5fc3aeeb 3155 dce_v10_0_print_status((void *)adev);
aaa36a97
AD		 3156 }
3157 return 0;
3158}
3159
3160static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3161 int crtc,
3162 enum amdgpu_interrupt_state state)
3163{
3164 u32 lb_interrupt_mask;
3165
3166 if (crtc >= adev->mode_info.num_crtc) {
3167 DRM_DEBUG("invalid crtc %d\n", crtc);
3168 return;
3169 }
3170
3171 switch (state) {
3172 case AMDGPU_IRQ_STATE_DISABLE:
3173 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3174 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3175 VBLANK_INTERRUPT_MASK, 0);
3176 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3177 break;
3178 case AMDGPU_IRQ_STATE_ENABLE:
3179 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3180 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3181 VBLANK_INTERRUPT_MASK, 1);
3182 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3183 break;
3184 default:
3185 break;
3186 }
3187}
3188
3189static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3190 int crtc,
3191 enum amdgpu_interrupt_state state)
3192{
3193 u32 lb_interrupt_mask;
3194
3195 if (crtc >= adev->mode_info.num_crtc) {
3196 DRM_DEBUG("invalid crtc %d\n", crtc);
3197 return;
3198 }
3199
3200 switch (state) {
3201 case AMDGPU_IRQ_STATE_DISABLE:
3202 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3203 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3204 VLINE_INTERRUPT_MASK, 0);
3205 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3206 break;
3207 case AMDGPU_IRQ_STATE_ENABLE:
3208 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3209 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3210 VLINE_INTERRUPT_MASK, 1);
3211 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3212 break;
3213 default:
3214 break;
3215 }
3216}
3217
3218static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3219 struct amdgpu_irq_src *source,
3220 unsigned hpd,
3221 enum amdgpu_interrupt_state state)
3222{
3223 u32 tmp;
3224
3225 if (hpd >= adev->mode_info.num_hpd) {
3226 DRM_DEBUG("invalid hdp %d\n", hpd);
3227 return 0;
3228 }
3229
3230 switch (state) {
3231 case AMDGPU_IRQ_STATE_DISABLE:
3232 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3233 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3234 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3235 break;
3236 case AMDGPU_IRQ_STATE_ENABLE:
3237 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3238 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3239 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3240 break;
3241 default:
3242 break;
3243 }
3244
3245 return 0;
3246}
3247
3248static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3249 struct amdgpu_irq_src *source,
3250 unsigned type,
3251 enum amdgpu_interrupt_state state)
3252{
3253 switch (type) {
3254 case AMDGPU_CRTC_IRQ_VBLANK1:
3255 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3256 break;
3257 case AMDGPU_CRTC_IRQ_VBLANK2:
3258 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3259 break;
3260 case AMDGPU_CRTC_IRQ_VBLANK3:
3261 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3262 break;
3263 case AMDGPU_CRTC_IRQ_VBLANK4:
3264 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3265 break;
3266 case AMDGPU_CRTC_IRQ_VBLANK5:
3267 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3268 break;
3269 case AMDGPU_CRTC_IRQ_VBLANK6:
3270 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3271 break;
3272 case AMDGPU_CRTC_IRQ_VLINE1:
3273 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3274 break;
3275 case AMDGPU_CRTC_IRQ_VLINE2:
3276 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3277 break;
3278 case AMDGPU_CRTC_IRQ_VLINE3:
3279 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3280 break;
3281 case AMDGPU_CRTC_IRQ_VLINE4:
3282 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3283 break;
3284 case AMDGPU_CRTC_IRQ_VLINE5:
3285 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3286 break;
3287 case AMDGPU_CRTC_IRQ_VLINE6:
3288 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3289 break;
3290 default:
3291 break;
3292 }
3293 return 0;
3294}
3295
3296static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3297 struct amdgpu_irq_src *src,
3298 unsigned type,
3299 enum amdgpu_interrupt_state state)
3300{
7dfac896
AD		 3301 u32 reg;
3302
3303 if (type >= adev->mode_info.num_crtc) {
3304 DRM_ERROR("invalid pageflip crtc %d\n", type);
3305 return -EINVAL;
aaa36a97
AD		 3306 }
3307
7dfac896 3308 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
aaa36a97 3309 if (state == AMDGPU_IRQ_STATE_DISABLE)
7dfac896
AD		 3310 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3311 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97 3312 else
7dfac896
AD		 3313 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3314 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
aaa36a97
AD		 3315
3316 return 0;
3317}
3318
3319static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3320 struct amdgpu_irq_src *source,
3321 struct amdgpu_iv_entry *entry)
3322{
aaa36a97
AD		 3323 unsigned long flags;
3324 unsigned crtc_id;
3325 struct amdgpu_crtc *amdgpu_crtc;
3326 struct amdgpu_flip_work *works;
3327
3328 crtc_id = (entry->src_id - 8) >> 1;
3329 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3330
7dfac896
AD		 3331 if (crtc_id >= adev->mode_info.num_crtc) {
3332 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3333 return -EINVAL;
aaa36a97
AD		 3334 }
3335
7dfac896
AD		 3336 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3337 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3338 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3339 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
aaa36a97
AD		 3340
3341 /* IRQ could occur when in initial stage */
3342 if (amdgpu_crtc == NULL)
3343 return 0;
3344
3345 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3346 works = amdgpu_crtc->pflip_works;
3347 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3348 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3349 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3350 amdgpu_crtc->pflip_status,
3351 AMDGPU_FLIP_SUBMITTED);
3352 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3353 return 0;
3354 }
3355
3356 /* page flip completed. clean up */
3357 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3358 amdgpu_crtc->pflip_works = NULL;
3359
3360 /* wakeup usersapce */
3361 if (works->event)
3362 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3363
3364 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3365
3366 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
87d58c11 3367 schedule_work(&works->unpin_work);
aaa36a97
AD		 3368
3369 return 0;
3370}
3371
3372static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3373 int hpd)
3374{
3375 u32 tmp;
3376
3377 if (hpd >= adev->mode_info.num_hpd) {
3378 DRM_DEBUG("invalid hdp %d\n", hpd);
3379 return;
3380 }
3381
3382 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3383 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3384 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3385}
3386
3387static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3388 int crtc)
3389{
3390 u32 tmp;
3391
3392 if (crtc >= adev->mode_info.num_crtc) {
3393 DRM_DEBUG("invalid crtc %d\n", crtc);
3394 return;
3395 }
3396
3397 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3398 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3399 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3400}
3401
3402static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3403 int crtc)
3404{
3405 u32 tmp;
3406
3407 if (crtc >= adev->mode_info.num_crtc) {
3408 DRM_DEBUG("invalid crtc %d\n", crtc);
3409 return;
3410 }
3411
3412 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3413 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3414 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3415}
3416
3417static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3418 struct amdgpu_irq_src *source,
3419 struct amdgpu_iv_entry *entry)
3420{
3421 unsigned crtc = entry->src_id - 1;
3422 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3423 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3424
3425 switch (entry->src_data) {
3426 case 0: /* vblank */
bd833144 3427 if (disp_int & interrupt_status_offsets[crtc].vblank)
aaa36a97 3428 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
bd833144
MK		 3429 else
3430 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3431
3432 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3433 drm_handle_vblank(adev->ddev, crtc);
aaa36a97 3434 }
bd833144
MK		 3435 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3436
aaa36a97
AD		 3437 break;
3438 case 1: /* vline */
bd833144 3439 if (disp_int & interrupt_status_offsets[crtc].vline)
aaa36a97 3440 dce_v10_0_crtc_vline_int_ack(adev, crtc);
bd833144
MK		 3441 else
3442 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3443
3444 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3445
aaa36a97
AD		 3446 break;
3447 default:
3448 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3449 break;
3450 }
3451
3452 return 0;
3453}
3454
3455static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3456 struct amdgpu_irq_src *source,
3457 struct amdgpu_iv_entry *entry)
3458{
3459 uint32_t disp_int, mask;
3460 unsigned hpd;
3461
3462 if (entry->src_data >= adev->mode_info.num_hpd) {
3463 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3464 return 0;
3465 }
3466
3467 hpd = entry->src_data;
3468 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3469 mask = interrupt_status_offsets[hpd].hpd;
3470
3471 if (disp_int & mask) {
3472 dce_v10_0_hpd_int_ack(adev, hpd);
3473 schedule_work(&adev->hotplug_work);
3474 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3475 }
3476
3477 return 0;
3478}
3479
5fc3aeeb 3480static int dce_v10_0_set_clockgating_state(void *handle,
3481 enum amd_clockgating_state state)
aaa36a97
AD		 3482{
3483 return 0;
3484}
3485
5fc3aeeb 3486static int dce_v10_0_set_powergating_state(void *handle,
3487 enum amd_powergating_state state)
aaa36a97
AD		 3488{
3489 return 0;
3490}
3491
5fc3aeeb 3492const struct amd_ip_funcs dce_v10_0_ip_funcs = {
aaa36a97
AD		 3493 .early_init = dce_v10_0_early_init,
3494 .late_init = NULL,
3495 .sw_init = dce_v10_0_sw_init,
3496 .sw_fini = dce_v10_0_sw_fini,
3497 .hw_init = dce_v10_0_hw_init,
3498 .hw_fini = dce_v10_0_hw_fini,
3499 .suspend = dce_v10_0_suspend,
3500 .resume = dce_v10_0_resume,
3501 .is_idle = dce_v10_0_is_idle,
3502 .wait_for_idle = dce_v10_0_wait_for_idle,
3503 .soft_reset = dce_v10_0_soft_reset,
3504 .print_status = dce_v10_0_print_status,
3505 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3506 .set_powergating_state = dce_v10_0_set_powergating_state,
3507};
3508
3509static void
3510dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3511 struct drm_display_mode *mode,
3512 struct drm_display_mode *adjusted_mode)
3513{
3514 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3515
3516 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3517
3518 /* need to call this here rather than in prepare() since we need some crtc info */
3519 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3520
3521 /* set scaler clears this on some chips */
3522 dce_v10_0_set_interleave(encoder->crtc, mode);
3523
3524 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3525 dce_v10_0_afmt_enable(encoder, true);
3526 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3527 }
3528}
3529
3530static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3531{
3532 struct amdgpu_device *adev = encoder->dev->dev_private;
3533 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3534 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3535
3536 if ((amdgpu_encoder->active_device &
3537 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3538 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3539 ENCODER_OBJECT_ID_NONE)) {
3540 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3541 if (dig) {
3542 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3543 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3544 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3545 }
3546 }
3547
3548 amdgpu_atombios_scratch_regs_lock(adev, true);
3549
3550 if (connector) {
3551 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3552
3553 /* select the clock/data port if it uses a router */
3554 if (amdgpu_connector->router.cd_valid)
3555 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3556
3557 /* turn eDP panel on for mode set */
3558 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3559 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3560 ATOM_TRANSMITTER_ACTION_POWER_ON);
3561 }
3562
3563 /* this is needed for the pll/ss setup to work correctly in some cases */
3564 amdgpu_atombios_encoder_set_crtc_source(encoder);
3565 /* set up the FMT blocks */
3566 dce_v10_0_program_fmt(encoder);
3567}
3568
3569static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3570{
3571 struct drm_device *dev = encoder->dev;
3572 struct amdgpu_device *adev = dev->dev_private;
3573
3574 /* need to call this here as we need the crtc set up */
3575 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3576 amdgpu_atombios_scratch_regs_lock(adev, false);
3577}
3578
3579static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3580{
3581 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3582 struct amdgpu_encoder_atom_dig *dig;
3583
3584 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3585
3586 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3587 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3588 dce_v10_0_afmt_enable(encoder, false);
3589 dig = amdgpu_encoder->enc_priv;
3590 dig->dig_encoder = -1;
3591 }
3592 amdgpu_encoder->active_device = 0;
3593}
3594
3595/* these are handled by the primary encoders */
3596static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3597{
3598
3599}
3600
3601static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3602{
3603
3604}
3605
3606static void
3607dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3608 struct drm_display_mode *mode,
3609 struct drm_display_mode *adjusted_mode)
3610{
3611
3612}
3613
3614static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3615{
3616
3617}
3618
3619static void
3620dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3621{
3622
3623}
3624
aaa36a97
AD		 3625static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3626 .dpms = dce_v10_0_ext_dpms,
aaa36a97
AD		 3627 .prepare = dce_v10_0_ext_prepare,
3628 .mode_set = dce_v10_0_ext_mode_set,
3629 .commit = dce_v10_0_ext_commit,
3630 .disable = dce_v10_0_ext_disable,
3631 /* no detect for TMDS/LVDS yet */
3632};
3633
3634static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3635 .dpms = amdgpu_atombios_encoder_dpms,
3636 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3637 .prepare = dce_v10_0_encoder_prepare,
3638 .mode_set = dce_v10_0_encoder_mode_set,
3639 .commit = dce_v10_0_encoder_commit,
3640 .disable = dce_v10_0_encoder_disable,
3641 .detect = amdgpu_atombios_encoder_dig_detect,
3642};
3643
3644static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3645 .dpms = amdgpu_atombios_encoder_dpms,
3646 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3647 .prepare = dce_v10_0_encoder_prepare,
3648 .mode_set = dce_v10_0_encoder_mode_set,
3649 .commit = dce_v10_0_encoder_commit,
3650 .detect = amdgpu_atombios_encoder_dac_detect,
3651};
3652
3653static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3654{
3655 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3656 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3657 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3658 kfree(amdgpu_encoder->enc_priv);
3659 drm_encoder_cleanup(encoder);
3660 kfree(amdgpu_encoder);
3661}
3662
3663static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3664 .destroy = dce_v10_0_encoder_destroy,
3665};
3666
3667static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3668 uint32_t encoder_enum,
3669 uint32_t supported_device,
3670 u16 caps)
3671{
3672 struct drm_device *dev = adev->ddev;
3673 struct drm_encoder *encoder;
3674 struct amdgpu_encoder *amdgpu_encoder;
3675
3676 /* see if we already added it */
3677 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3678 amdgpu_encoder = to_amdgpu_encoder(encoder);
3679 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3680 amdgpu_encoder->devices |= supported_device;
3681 return;
3682 }
3683
3684 }
3685
3686 /* add a new one */
3687 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3688 if (!amdgpu_encoder)
3689 return;
3690
3691 encoder = &amdgpu_encoder->base;
3692 switch (adev->mode_info.num_crtc) {
3693 case 1:
3694 encoder->possible_crtcs = 0x1;
3695 break;
3696 case 2:
3697 default:
3698 encoder->possible_crtcs = 0x3;
3699 break;
3700 case 4:
3701 encoder->possible_crtcs = 0xf;
3702 break;
3703 case 6:
3704 encoder->possible_crtcs = 0x3f;
3705 break;
3706 }
3707
3708 amdgpu_encoder->enc_priv = NULL;
3709
3710 amdgpu_encoder->encoder_enum = encoder_enum;
3711 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3712 amdgpu_encoder->devices = supported_device;
3713 amdgpu_encoder->rmx_type = RMX_OFF;
3714 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3715 amdgpu_encoder->is_ext_encoder = false;
3716 amdgpu_encoder->caps = caps;
3717
3718 switch (amdgpu_encoder->encoder_id) {
3719 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3720 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3721 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3722 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3723 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3724 break;
3725 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3726 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3727 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3728 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3729 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3730 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3731 amdgpu_encoder->rmx_type = RMX_FULL;
3732 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3733 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3734 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3735 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3736 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3737 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3738 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3739 } else {
3740 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3741 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3742 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3743 }
3744 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3745 break;
3746 case ENCODER_OBJECT_ID_SI170B:
3747 case ENCODER_OBJECT_ID_CH7303:
3748 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3749 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3750 case ENCODER_OBJECT_ID_TITFP513:
3751 case ENCODER_OBJECT_ID_VT1623:
3752 case ENCODER_OBJECT_ID_HDMI_SI1930:
3753 case ENCODER_OBJECT_ID_TRAVIS:
3754 case ENCODER_OBJECT_ID_NUTMEG:
3755 /* these are handled by the primary encoders */
3756 amdgpu_encoder->is_ext_encoder = true;
3757 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3758 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3759 DRM_MODE_ENCODER_LVDS, NULL);
aaa36a97
AD		 3760 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3761 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3762 DRM_MODE_ENCODER_DAC, NULL);
aaa36a97
AD		 3763 else
3764 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
13a3d91f 3765 DRM_MODE_ENCODER_TMDS, NULL);
aaa36a97
AD		 3766 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3767 break;
3768 }
3769}
3770
3771static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3772 .set_vga_render_state = &dce_v10_0_set_vga_render_state,
3773 .bandwidth_update = &dce_v10_0_bandwidth_update,
3774 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3775 .vblank_wait = &dce_v10_0_vblank_wait,
3776 .is_display_hung = &dce_v10_0_is_display_hung,
3777 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3778 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3779 .hpd_sense = &dce_v10_0_hpd_sense,
3780 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3781 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3782 .page_flip = &dce_v10_0_page_flip,
3783 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3784 .add_encoder = &dce_v10_0_encoder_add,
3785 .add_connector = &amdgpu_connector_add,
3786 .stop_mc_access = &dce_v10_0_stop_mc_access,
3787 .resume_mc_access = &dce_v10_0_resume_mc_access,
3788};
3789
3790static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3791{
3792 if (adev->mode_info.funcs == NULL)
3793 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3794}
3795
3796static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3797 .set = dce_v10_0_set_crtc_irq_state,
3798 .process = dce_v10_0_crtc_irq,
3799};
3800
3801static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3802 .set = dce_v10_0_set_pageflip_irq_state,
3803 .process = dce_v10_0_pageflip_irq,
3804};
3805
3806static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3807 .set = dce_v10_0_set_hpd_irq_state,
3808 .process = dce_v10_0_hpd_irq,
3809};
3810
3811static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3812{
3813 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3814 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3815
3816 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3817 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3818
3819 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3820 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3821}
Linux kernel - Deliverables
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