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Merge tag 'drm-vc4-next-2016-02-17' of github.com:anholt/linux into drm-next
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / gfx_v7_0.c
CommitLineData
a2e73f56
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_ih.h"
27#include "amdgpu_gfx.h"
28#include "cikd.h"
29#include "cik.h"
30#include "atom.h"
31#include "amdgpu_ucode.h"
32#include "clearstate_ci.h"
33
a2e73f56
AD		 34#include "dce/dce_8_0_d.h"
35#include "dce/dce_8_0_sh_mask.h"
36
37#include "bif/bif_4_1_d.h"
38#include "bif/bif_4_1_sh_mask.h"
39
40#include "gca/gfx_7_0_d.h"
41#include "gca/gfx_7_2_enum.h"
42#include "gca/gfx_7_2_sh_mask.h"
43
44#include "gmc/gmc_7_0_d.h"
45#include "gmc/gmc_7_0_sh_mask.h"
46
47#include "oss/oss_2_0_d.h"
48#include "oss/oss_2_0_sh_mask.h"
49
50#define GFX7_NUM_GFX_RINGS 1
51#define GFX7_NUM_COMPUTE_RINGS 8
52
53static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
56int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);
57
58MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
59MODULE_FIRMWARE("radeon/bonaire_me.bin");
60MODULE_FIRMWARE("radeon/bonaire_ce.bin");
61MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
62MODULE_FIRMWARE("radeon/bonaire_mec.bin");
63
64MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
65MODULE_FIRMWARE("radeon/hawaii_me.bin");
66MODULE_FIRMWARE("radeon/hawaii_ce.bin");
67MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
68MODULE_FIRMWARE("radeon/hawaii_mec.bin");
69
70MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
71MODULE_FIRMWARE("radeon/kaveri_me.bin");
72MODULE_FIRMWARE("radeon/kaveri_ce.bin");
73MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
74MODULE_FIRMWARE("radeon/kaveri_mec.bin");
75MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
76
77MODULE_FIRMWARE("radeon/kabini_pfp.bin");
78MODULE_FIRMWARE("radeon/kabini_me.bin");
79MODULE_FIRMWARE("radeon/kabini_ce.bin");
80MODULE_FIRMWARE("radeon/kabini_rlc.bin");
81MODULE_FIRMWARE("radeon/kabini_mec.bin");
82
83MODULE_FIRMWARE("radeon/mullins_pfp.bin");
84MODULE_FIRMWARE("radeon/mullins_me.bin");
85MODULE_FIRMWARE("radeon/mullins_ce.bin");
86MODULE_FIRMWARE("radeon/mullins_rlc.bin");
87MODULE_FIRMWARE("radeon/mullins_mec.bin");
88
89static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
90{
91 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
92 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
93 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
94 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
95 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
96 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
97 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
98 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
99 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
100 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
101 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
102 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
103 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
104 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
105 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
106 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
107};
108
109static const u32 spectre_rlc_save_restore_register_list[] =
110{
111 (0x0e00 << 16) | (0xc12c >> 2),
112 0x00000000,
113 (0x0e00 << 16) | (0xc140 >> 2),
114 0x00000000,
115 (0x0e00 << 16) | (0xc150 >> 2),
116 0x00000000,
117 (0x0e00 << 16) | (0xc15c >> 2),
118 0x00000000,
119 (0x0e00 << 16) | (0xc168 >> 2),
120 0x00000000,
121 (0x0e00 << 16) | (0xc170 >> 2),
122 0x00000000,
123 (0x0e00 << 16) | (0xc178 >> 2),
124 0x00000000,
125 (0x0e00 << 16) | (0xc204 >> 2),
126 0x00000000,
127 (0x0e00 << 16) | (0xc2b4 >> 2),
128 0x00000000,
129 (0x0e00 << 16) | (0xc2b8 >> 2),
130 0x00000000,
131 (0x0e00 << 16) | (0xc2bc >> 2),
132 0x00000000,
133 (0x0e00 << 16) | (0xc2c0 >> 2),
134 0x00000000,
135 (0x0e00 << 16) | (0x8228 >> 2),
136 0x00000000,
137 (0x0e00 << 16) | (0x829c >> 2),
138 0x00000000,
139 (0x0e00 << 16) | (0x869c >> 2),
140 0x00000000,
141 (0x0600 << 16) | (0x98f4 >> 2),
142 0x00000000,
143 (0x0e00 << 16) | (0x98f8 >> 2),
144 0x00000000,
145 (0x0e00 << 16) | (0x9900 >> 2),
146 0x00000000,
147 (0x0e00 << 16) | (0xc260 >> 2),
148 0x00000000,
149 (0x0e00 << 16) | (0x90e8 >> 2),
150 0x00000000,
151 (0x0e00 << 16) | (0x3c000 >> 2),
152 0x00000000,
153 (0x0e00 << 16) | (0x3c00c >> 2),
154 0x00000000,
155 (0x0e00 << 16) | (0x8c1c >> 2),
156 0x00000000,
157 (0x0e00 << 16) | (0x9700 >> 2),
158 0x00000000,
159 (0x0e00 << 16) | (0xcd20 >> 2),
160 0x00000000,
161 (0x4e00 << 16) | (0xcd20 >> 2),
162 0x00000000,
163 (0x5e00 << 16) | (0xcd20 >> 2),
164 0x00000000,
165 (0x6e00 << 16) | (0xcd20 >> 2),
166 0x00000000,
167 (0x7e00 << 16) | (0xcd20 >> 2),
168 0x00000000,
169 (0x8e00 << 16) | (0xcd20 >> 2),
170 0x00000000,
171 (0x9e00 << 16) | (0xcd20 >> 2),
172 0x00000000,
173 (0xae00 << 16) | (0xcd20 >> 2),
174 0x00000000,
175 (0xbe00 << 16) | (0xcd20 >> 2),
176 0x00000000,
177 (0x0e00 << 16) | (0x89bc >> 2),
178 0x00000000,
179 (0x0e00 << 16) | (0x8900 >> 2),
180 0x00000000,
181 0x3,
182 (0x0e00 << 16) | (0xc130 >> 2),
183 0x00000000,
184 (0x0e00 << 16) | (0xc134 >> 2),
185 0x00000000,
186 (0x0e00 << 16) | (0xc1fc >> 2),
187 0x00000000,
188 (0x0e00 << 16) | (0xc208 >> 2),
189 0x00000000,
190 (0x0e00 << 16) | (0xc264 >> 2),
191 0x00000000,
192 (0x0e00 << 16) | (0xc268 >> 2),
193 0x00000000,
194 (0x0e00 << 16) | (0xc26c >> 2),
195 0x00000000,
196 (0x0e00 << 16) | (0xc270 >> 2),
197 0x00000000,
198 (0x0e00 << 16) | (0xc274 >> 2),
199 0x00000000,
200 (0x0e00 << 16) | (0xc278 >> 2),
201 0x00000000,
202 (0x0e00 << 16) | (0xc27c >> 2),
203 0x00000000,
204 (0x0e00 << 16) | (0xc280 >> 2),
205 0x00000000,
206 (0x0e00 << 16) | (0xc284 >> 2),
207 0x00000000,
208 (0x0e00 << 16) | (0xc288 >> 2),
209 0x00000000,
210 (0x0e00 << 16) | (0xc28c >> 2),
211 0x00000000,
212 (0x0e00 << 16) | (0xc290 >> 2),
213 0x00000000,
214 (0x0e00 << 16) | (0xc294 >> 2),
215 0x00000000,
216 (0x0e00 << 16) | (0xc298 >> 2),
217 0x00000000,
218 (0x0e00 << 16) | (0xc29c >> 2),
219 0x00000000,
220 (0x0e00 << 16) | (0xc2a0 >> 2),
221 0x00000000,
222 (0x0e00 << 16) | (0xc2a4 >> 2),
223 0x00000000,
224 (0x0e00 << 16) | (0xc2a8 >> 2),
225 0x00000000,
226 (0x0e00 << 16) | (0xc2ac >> 2),
227 0x00000000,
228 (0x0e00 << 16) | (0xc2b0 >> 2),
229 0x00000000,
230 (0x0e00 << 16) | (0x301d0 >> 2),
231 0x00000000,
232 (0x0e00 << 16) | (0x30238 >> 2),
233 0x00000000,
234 (0x0e00 << 16) | (0x30250 >> 2),
235 0x00000000,
236 (0x0e00 << 16) | (0x30254 >> 2),
237 0x00000000,
238 (0x0e00 << 16) | (0x30258 >> 2),
239 0x00000000,
240 (0x0e00 << 16) | (0x3025c >> 2),
241 0x00000000,
242 (0x4e00 << 16) | (0xc900 >> 2),
243 0x00000000,
244 (0x5e00 << 16) | (0xc900 >> 2),
245 0x00000000,
246 (0x6e00 << 16) | (0xc900 >> 2),
247 0x00000000,
248 (0x7e00 << 16) | (0xc900 >> 2),
249 0x00000000,
250 (0x8e00 << 16) | (0xc900 >> 2),
251 0x00000000,
252 (0x9e00 << 16) | (0xc900 >> 2),
253 0x00000000,
254 (0xae00 << 16) | (0xc900 >> 2),
255 0x00000000,
256 (0xbe00 << 16) | (0xc900 >> 2),
257 0x00000000,
258 (0x4e00 << 16) | (0xc904 >> 2),
259 0x00000000,
260 (0x5e00 << 16) | (0xc904 >> 2),
261 0x00000000,
262 (0x6e00 << 16) | (0xc904 >> 2),
263 0x00000000,
264 (0x7e00 << 16) | (0xc904 >> 2),
265 0x00000000,
266 (0x8e00 << 16) | (0xc904 >> 2),
267 0x00000000,
268 (0x9e00 << 16) | (0xc904 >> 2),
269 0x00000000,
270 (0xae00 << 16) | (0xc904 >> 2),
271 0x00000000,
272 (0xbe00 << 16) | (0xc904 >> 2),
273 0x00000000,
274 (0x4e00 << 16) | (0xc908 >> 2),
275 0x00000000,
276 (0x5e00 << 16) | (0xc908 >> 2),
277 0x00000000,
278 (0x6e00 << 16) | (0xc908 >> 2),
279 0x00000000,
280 (0x7e00 << 16) | (0xc908 >> 2),
281 0x00000000,
282 (0x8e00 << 16) | (0xc908 >> 2),
283 0x00000000,
284 (0x9e00 << 16) | (0xc908 >> 2),
285 0x00000000,
286 (0xae00 << 16) | (0xc908 >> 2),
287 0x00000000,
288 (0xbe00 << 16) | (0xc908 >> 2),
289 0x00000000,
290 (0x4e00 << 16) | (0xc90c >> 2),
291 0x00000000,
292 (0x5e00 << 16) | (0xc90c >> 2),
293 0x00000000,
294 (0x6e00 << 16) | (0xc90c >> 2),
295 0x00000000,
296 (0x7e00 << 16) | (0xc90c >> 2),
297 0x00000000,
298 (0x8e00 << 16) | (0xc90c >> 2),
299 0x00000000,
300 (0x9e00 << 16) | (0xc90c >> 2),
301 0x00000000,
302 (0xae00 << 16) | (0xc90c >> 2),
303 0x00000000,
304 (0xbe00 << 16) | (0xc90c >> 2),
305 0x00000000,
306 (0x4e00 << 16) | (0xc910 >> 2),
307 0x00000000,
308 (0x5e00 << 16) | (0xc910 >> 2),
309 0x00000000,
310 (0x6e00 << 16) | (0xc910 >> 2),
311 0x00000000,
312 (0x7e00 << 16) | (0xc910 >> 2),
313 0x00000000,
314 (0x8e00 << 16) | (0xc910 >> 2),
315 0x00000000,
316 (0x9e00 << 16) | (0xc910 >> 2),
317 0x00000000,
318 (0xae00 << 16) | (0xc910 >> 2),
319 0x00000000,
320 (0xbe00 << 16) | (0xc910 >> 2),
321 0x00000000,
322 (0x0e00 << 16) | (0xc99c >> 2),
323 0x00000000,
324 (0x0e00 << 16) | (0x9834 >> 2),
325 0x00000000,
326 (0x0000 << 16) | (0x30f00 >> 2),
327 0x00000000,
328 (0x0001 << 16) | (0x30f00 >> 2),
329 0x00000000,
330 (0x0000 << 16) | (0x30f04 >> 2),
331 0x00000000,
332 (0x0001 << 16) | (0x30f04 >> 2),
333 0x00000000,
334 (0x0000 << 16) | (0x30f08 >> 2),
335 0x00000000,
336 (0x0001 << 16) | (0x30f08 >> 2),
337 0x00000000,
338 (0x0000 << 16) | (0x30f0c >> 2),
339 0x00000000,
340 (0x0001 << 16) | (0x30f0c >> 2),
341 0x00000000,
342 (0x0600 << 16) | (0x9b7c >> 2),
343 0x00000000,
344 (0x0e00 << 16) | (0x8a14 >> 2),
345 0x00000000,
346 (0x0e00 << 16) | (0x8a18 >> 2),
347 0x00000000,
348 (0x0600 << 16) | (0x30a00 >> 2),
349 0x00000000,
350 (0x0e00 << 16) | (0x8bf0 >> 2),
351 0x00000000,
352 (0x0e00 << 16) | (0x8bcc >> 2),
353 0x00000000,
354 (0x0e00 << 16) | (0x8b24 >> 2),
355 0x00000000,
356 (0x0e00 << 16) | (0x30a04 >> 2),
357 0x00000000,
358 (0x0600 << 16) | (0x30a10 >> 2),
359 0x00000000,
360 (0x0600 << 16) | (0x30a14 >> 2),
361 0x00000000,
362 (0x0600 << 16) | (0x30a18 >> 2),
363 0x00000000,
364 (0x0600 << 16) | (0x30a2c >> 2),
365 0x00000000,
366 (0x0e00 << 16) | (0xc700 >> 2),
367 0x00000000,
368 (0x0e00 << 16) | (0xc704 >> 2),
369 0x00000000,
370 (0x0e00 << 16) | (0xc708 >> 2),
371 0x00000000,
372 (0x0e00 << 16) | (0xc768 >> 2),
373 0x00000000,
374 (0x0400 << 16) | (0xc770 >> 2),
375 0x00000000,
376 (0x0400 << 16) | (0xc774 >> 2),
377 0x00000000,
378 (0x0400 << 16) | (0xc778 >> 2),
379 0x00000000,
380 (0x0400 << 16) | (0xc77c >> 2),
381 0x00000000,
382 (0x0400 << 16) | (0xc780 >> 2),
383 0x00000000,
384 (0x0400 << 16) | (0xc784 >> 2),
385 0x00000000,
386 (0x0400 << 16) | (0xc788 >> 2),
387 0x00000000,
388 (0x0400 << 16) | (0xc78c >> 2),
389 0x00000000,
390 (0x0400 << 16) | (0xc798 >> 2),
391 0x00000000,
392 (0x0400 << 16) | (0xc79c >> 2),
393 0x00000000,
394 (0x0400 << 16) | (0xc7a0 >> 2),
395 0x00000000,
396 (0x0400 << 16) | (0xc7a4 >> 2),
397 0x00000000,
398 (0x0400 << 16) | (0xc7a8 >> 2),
399 0x00000000,
400 (0x0400 << 16) | (0xc7ac >> 2),
401 0x00000000,
402 (0x0400 << 16) | (0xc7b0 >> 2),
403 0x00000000,
404 (0x0400 << 16) | (0xc7b4 >> 2),
405 0x00000000,
406 (0x0e00 << 16) | (0x9100 >> 2),
407 0x00000000,
408 (0x0e00 << 16) | (0x3c010 >> 2),
409 0x00000000,
410 (0x0e00 << 16) | (0x92a8 >> 2),
411 0x00000000,
412 (0x0e00 << 16) | (0x92ac >> 2),
413 0x00000000,
414 (0x0e00 << 16) | (0x92b4 >> 2),
415 0x00000000,
416 (0x0e00 << 16) | (0x92b8 >> 2),
417 0x00000000,
418 (0x0e00 << 16) | (0x92bc >> 2),
419 0x00000000,
420 (0x0e00 << 16) | (0x92c0 >> 2),
421 0x00000000,
422 (0x0e00 << 16) | (0x92c4 >> 2),
423 0x00000000,
424 (0x0e00 << 16) | (0x92c8 >> 2),
425 0x00000000,
426 (0x0e00 << 16) | (0x92cc >> 2),
427 0x00000000,
428 (0x0e00 << 16) | (0x92d0 >> 2),
429 0x00000000,
430 (0x0e00 << 16) | (0x8c00 >> 2),
431 0x00000000,
432 (0x0e00 << 16) | (0x8c04 >> 2),
433 0x00000000,
434 (0x0e00 << 16) | (0x8c20 >> 2),
435 0x00000000,
436 (0x0e00 << 16) | (0x8c38 >> 2),
437 0x00000000,
438 (0x0e00 << 16) | (0x8c3c >> 2),
439 0x00000000,
440 (0x0e00 << 16) | (0xae00 >> 2),
441 0x00000000,
442 (0x0e00 << 16) | (0x9604 >> 2),
443 0x00000000,
444 (0x0e00 << 16) | (0xac08 >> 2),
445 0x00000000,
446 (0x0e00 << 16) | (0xac0c >> 2),
447 0x00000000,
448 (0x0e00 << 16) | (0xac10 >> 2),
449 0x00000000,
450 (0x0e00 << 16) | (0xac14 >> 2),
451 0x00000000,
452 (0x0e00 << 16) | (0xac58 >> 2),
453 0x00000000,
454 (0x0e00 << 16) | (0xac68 >> 2),
455 0x00000000,
456 (0x0e00 << 16) | (0xac6c >> 2),
457 0x00000000,
458 (0x0e00 << 16) | (0xac70 >> 2),
459 0x00000000,
460 (0x0e00 << 16) | (0xac74 >> 2),
461 0x00000000,
462 (0x0e00 << 16) | (0xac78 >> 2),
463 0x00000000,
464 (0x0e00 << 16) | (0xac7c >> 2),
465 0x00000000,
466 (0x0e00 << 16) | (0xac80 >> 2),
467 0x00000000,
468 (0x0e00 << 16) | (0xac84 >> 2),
469 0x00000000,
470 (0x0e00 << 16) | (0xac88 >> 2),
471 0x00000000,
472 (0x0e00 << 16) | (0xac8c >> 2),
473 0x00000000,
474 (0x0e00 << 16) | (0x970c >> 2),
475 0x00000000,
476 (0x0e00 << 16) | (0x9714 >> 2),
477 0x00000000,
478 (0x0e00 << 16) | (0x9718 >> 2),
479 0x00000000,
480 (0x0e00 << 16) | (0x971c >> 2),
481 0x00000000,
482 (0x0e00 << 16) | (0x31068 >> 2),
483 0x00000000,
484 (0x4e00 << 16) | (0x31068 >> 2),
485 0x00000000,
486 (0x5e00 << 16) | (0x31068 >> 2),
487 0x00000000,
488 (0x6e00 << 16) | (0x31068 >> 2),
489 0x00000000,
490 (0x7e00 << 16) | (0x31068 >> 2),
491 0x00000000,
492 (0x8e00 << 16) | (0x31068 >> 2),
493 0x00000000,
494 (0x9e00 << 16) | (0x31068 >> 2),
495 0x00000000,
496 (0xae00 << 16) | (0x31068 >> 2),
497 0x00000000,
498 (0xbe00 << 16) | (0x31068 >> 2),
499 0x00000000,
500 (0x0e00 << 16) | (0xcd10 >> 2),
501 0x00000000,
502 (0x0e00 << 16) | (0xcd14 >> 2),
503 0x00000000,
504 (0x0e00 << 16) | (0x88b0 >> 2),
505 0x00000000,
506 (0x0e00 << 16) | (0x88b4 >> 2),
507 0x00000000,
508 (0x0e00 << 16) | (0x88b8 >> 2),
509 0x00000000,
510 (0x0e00 << 16) | (0x88bc >> 2),
511 0x00000000,
512 (0x0400 << 16) | (0x89c0 >> 2),
513 0x00000000,
514 (0x0e00 << 16) | (0x88c4 >> 2),
515 0x00000000,
516 (0x0e00 << 16) | (0x88c8 >> 2),
517 0x00000000,
518 (0x0e00 << 16) | (0x88d0 >> 2),
519 0x00000000,
520 (0x0e00 << 16) | (0x88d4 >> 2),
521 0x00000000,
522 (0x0e00 << 16) | (0x88d8 >> 2),
523 0x00000000,
524 (0x0e00 << 16) | (0x8980 >> 2),
525 0x00000000,
526 (0x0e00 << 16) | (0x30938 >> 2),
527 0x00000000,
528 (0x0e00 << 16) | (0x3093c >> 2),
529 0x00000000,
530 (0x0e00 << 16) | (0x30940 >> 2),
531 0x00000000,
532 (0x0e00 << 16) | (0x89a0 >> 2),
533 0x00000000,
534 (0x0e00 << 16) | (0x30900 >> 2),
535 0x00000000,
536 (0x0e00 << 16) | (0x30904 >> 2),
537 0x00000000,
538 (0x0e00 << 16) | (0x89b4 >> 2),
539 0x00000000,
540 (0x0e00 << 16) | (0x3c210 >> 2),
541 0x00000000,
542 (0x0e00 << 16) | (0x3c214 >> 2),
543 0x00000000,
544 (0x0e00 << 16) | (0x3c218 >> 2),
545 0x00000000,
546 (0x0e00 << 16) | (0x8904 >> 2),
547 0x00000000,
548 0x5,
549 (0x0e00 << 16) | (0x8c28 >> 2),
550 (0x0e00 << 16) | (0x8c2c >> 2),
551 (0x0e00 << 16) | (0x8c30 >> 2),
552 (0x0e00 << 16) | (0x8c34 >> 2),
553 (0x0e00 << 16) | (0x9600 >> 2),
554};
555
556static const u32 kalindi_rlc_save_restore_register_list[] =
557{
558 (0x0e00 << 16) | (0xc12c >> 2),
559 0x00000000,
560 (0x0e00 << 16) | (0xc140 >> 2),
561 0x00000000,
562 (0x0e00 << 16) | (0xc150 >> 2),
563 0x00000000,
564 (0x0e00 << 16) | (0xc15c >> 2),
565 0x00000000,
566 (0x0e00 << 16) | (0xc168 >> 2),
567 0x00000000,
568 (0x0e00 << 16) | (0xc170 >> 2),
569 0x00000000,
570 (0x0e00 << 16) | (0xc204 >> 2),
571 0x00000000,
572 (0x0e00 << 16) | (0xc2b4 >> 2),
573 0x00000000,
574 (0x0e00 << 16) | (0xc2b8 >> 2),
575 0x00000000,
576 (0x0e00 << 16) | (0xc2bc >> 2),
577 0x00000000,
578 (0x0e00 << 16) | (0xc2c0 >> 2),
579 0x00000000,
580 (0x0e00 << 16) | (0x8228 >> 2),
581 0x00000000,
582 (0x0e00 << 16) | (0x829c >> 2),
583 0x00000000,
584 (0x0e00 << 16) | (0x869c >> 2),
585 0x00000000,
586 (0x0600 << 16) | (0x98f4 >> 2),
587 0x00000000,
588 (0x0e00 << 16) | (0x98f8 >> 2),
589 0x00000000,
590 (0x0e00 << 16) | (0x9900 >> 2),
591 0x00000000,
592 (0x0e00 << 16) | (0xc260 >> 2),
593 0x00000000,
594 (0x0e00 << 16) | (0x90e8 >> 2),
595 0x00000000,
596 (0x0e00 << 16) | (0x3c000 >> 2),
597 0x00000000,
598 (0x0e00 << 16) | (0x3c00c >> 2),
599 0x00000000,
600 (0x0e00 << 16) | (0x8c1c >> 2),
601 0x00000000,
602 (0x0e00 << 16) | (0x9700 >> 2),
603 0x00000000,
604 (0x0e00 << 16) | (0xcd20 >> 2),
605 0x00000000,
606 (0x4e00 << 16) | (0xcd20 >> 2),
607 0x00000000,
608 (0x5e00 << 16) | (0xcd20 >> 2),
609 0x00000000,
610 (0x6e00 << 16) | (0xcd20 >> 2),
611 0x00000000,
612 (0x7e00 << 16) | (0xcd20 >> 2),
613 0x00000000,
614 (0x0e00 << 16) | (0x89bc >> 2),
615 0x00000000,
616 (0x0e00 << 16) | (0x8900 >> 2),
617 0x00000000,
618 0x3,
619 (0x0e00 << 16) | (0xc130 >> 2),
620 0x00000000,
621 (0x0e00 << 16) | (0xc134 >> 2),
622 0x00000000,
623 (0x0e00 << 16) | (0xc1fc >> 2),
624 0x00000000,
625 (0x0e00 << 16) | (0xc208 >> 2),
626 0x00000000,
627 (0x0e00 << 16) | (0xc264 >> 2),
628 0x00000000,
629 (0x0e00 << 16) | (0xc268 >> 2),
630 0x00000000,
631 (0x0e00 << 16) | (0xc26c >> 2),
632 0x00000000,
633 (0x0e00 << 16) | (0xc270 >> 2),
634 0x00000000,
635 (0x0e00 << 16) | (0xc274 >> 2),
636 0x00000000,
637 (0x0e00 << 16) | (0xc28c >> 2),
638 0x00000000,
639 (0x0e00 << 16) | (0xc290 >> 2),
640 0x00000000,
641 (0x0e00 << 16) | (0xc294 >> 2),
642 0x00000000,
643 (0x0e00 << 16) | (0xc298 >> 2),
644 0x00000000,
645 (0x0e00 << 16) | (0xc2a0 >> 2),
646 0x00000000,
647 (0x0e00 << 16) | (0xc2a4 >> 2),
648 0x00000000,
649 (0x0e00 << 16) | (0xc2a8 >> 2),
650 0x00000000,
651 (0x0e00 << 16) | (0xc2ac >> 2),
652 0x00000000,
653 (0x0e00 << 16) | (0x301d0 >> 2),
654 0x00000000,
655 (0x0e00 << 16) | (0x30238 >> 2),
656 0x00000000,
657 (0x0e00 << 16) | (0x30250 >> 2),
658 0x00000000,
659 (0x0e00 << 16) | (0x30254 >> 2),
660 0x00000000,
661 (0x0e00 << 16) | (0x30258 >> 2),
662 0x00000000,
663 (0x0e00 << 16) | (0x3025c >> 2),
664 0x00000000,
665 (0x4e00 << 16) | (0xc900 >> 2),
666 0x00000000,
667 (0x5e00 << 16) | (0xc900 >> 2),
668 0x00000000,
669 (0x6e00 << 16) | (0xc900 >> 2),
670 0x00000000,
671 (0x7e00 << 16) | (0xc900 >> 2),
672 0x00000000,
673 (0x4e00 << 16) | (0xc904 >> 2),
674 0x00000000,
675 (0x5e00 << 16) | (0xc904 >> 2),
676 0x00000000,
677 (0x6e00 << 16) | (0xc904 >> 2),
678 0x00000000,
679 (0x7e00 << 16) | (0xc904 >> 2),
680 0x00000000,
681 (0x4e00 << 16) | (0xc908 >> 2),
682 0x00000000,
683 (0x5e00 << 16) | (0xc908 >> 2),
684 0x00000000,
685 (0x6e00 << 16) | (0xc908 >> 2),
686 0x00000000,
687 (0x7e00 << 16) | (0xc908 >> 2),
688 0x00000000,
689 (0x4e00 << 16) | (0xc90c >> 2),
690 0x00000000,
691 (0x5e00 << 16) | (0xc90c >> 2),
692 0x00000000,
693 (0x6e00 << 16) | (0xc90c >> 2),
694 0x00000000,
695 (0x7e00 << 16) | (0xc90c >> 2),
696 0x00000000,
697 (0x4e00 << 16) | (0xc910 >> 2),
698 0x00000000,
699 (0x5e00 << 16) | (0xc910 >> 2),
700 0x00000000,
701 (0x6e00 << 16) | (0xc910 >> 2),
702 0x00000000,
703 (0x7e00 << 16) | (0xc910 >> 2),
704 0x00000000,
705 (0x0e00 << 16) | (0xc99c >> 2),
706 0x00000000,
707 (0x0e00 << 16) | (0x9834 >> 2),
708 0x00000000,
709 (0x0000 << 16) | (0x30f00 >> 2),
710 0x00000000,
711 (0x0000 << 16) | (0x30f04 >> 2),
712 0x00000000,
713 (0x0000 << 16) | (0x30f08 >> 2),
714 0x00000000,
715 (0x0000 << 16) | (0x30f0c >> 2),
716 0x00000000,
717 (0x0600 << 16) | (0x9b7c >> 2),
718 0x00000000,
719 (0x0e00 << 16) | (0x8a14 >> 2),
720 0x00000000,
721 (0x0e00 << 16) | (0x8a18 >> 2),
722 0x00000000,
723 (0x0600 << 16) | (0x30a00 >> 2),
724 0x00000000,
725 (0x0e00 << 16) | (0x8bf0 >> 2),
726 0x00000000,
727 (0x0e00 << 16) | (0x8bcc >> 2),
728 0x00000000,
729 (0x0e00 << 16) | (0x8b24 >> 2),
730 0x00000000,
731 (0x0e00 << 16) | (0x30a04 >> 2),
732 0x00000000,
733 (0x0600 << 16) | (0x30a10 >> 2),
734 0x00000000,
735 (0x0600 << 16) | (0x30a14 >> 2),
736 0x00000000,
737 (0x0600 << 16) | (0x30a18 >> 2),
738 0x00000000,
739 (0x0600 << 16) | (0x30a2c >> 2),
740 0x00000000,
741 (0x0e00 << 16) | (0xc700 >> 2),
742 0x00000000,
743 (0x0e00 << 16) | (0xc704 >> 2),
744 0x00000000,
745 (0x0e00 << 16) | (0xc708 >> 2),
746 0x00000000,
747 (0x0e00 << 16) | (0xc768 >> 2),
748 0x00000000,
749 (0x0400 << 16) | (0xc770 >> 2),
750 0x00000000,
751 (0x0400 << 16) | (0xc774 >> 2),
752 0x00000000,
753 (0x0400 << 16) | (0xc798 >> 2),
754 0x00000000,
755 (0x0400 << 16) | (0xc79c >> 2),
756 0x00000000,
757 (0x0e00 << 16) | (0x9100 >> 2),
758 0x00000000,
759 (0x0e00 << 16) | (0x3c010 >> 2),
760 0x00000000,
761 (0x0e00 << 16) | (0x8c00 >> 2),
762 0x00000000,
763 (0x0e00 << 16) | (0x8c04 >> 2),
764 0x00000000,
765 (0x0e00 << 16) | (0x8c20 >> 2),
766 0x00000000,
767 (0x0e00 << 16) | (0x8c38 >> 2),
768 0x00000000,
769 (0x0e00 << 16) | (0x8c3c >> 2),
770 0x00000000,
771 (0x0e00 << 16) | (0xae00 >> 2),
772 0x00000000,
773 (0x0e00 << 16) | (0x9604 >> 2),
774 0x00000000,
775 (0x0e00 << 16) | (0xac08 >> 2),
776 0x00000000,
777 (0x0e00 << 16) | (0xac0c >> 2),
778 0x00000000,
779 (0x0e00 << 16) | (0xac10 >> 2),
780 0x00000000,
781 (0x0e00 << 16) | (0xac14 >> 2),
782 0x00000000,
783 (0x0e00 << 16) | (0xac58 >> 2),
784 0x00000000,
785 (0x0e00 << 16) | (0xac68 >> 2),
786 0x00000000,
787 (0x0e00 << 16) | (0xac6c >> 2),
788 0x00000000,
789 (0x0e00 << 16) | (0xac70 >> 2),
790 0x00000000,
791 (0x0e00 << 16) | (0xac74 >> 2),
792 0x00000000,
793 (0x0e00 << 16) | (0xac78 >> 2),
794 0x00000000,
795 (0x0e00 << 16) | (0xac7c >> 2),
796 0x00000000,
797 (0x0e00 << 16) | (0xac80 >> 2),
798 0x00000000,
799 (0x0e00 << 16) | (0xac84 >> 2),
800 0x00000000,
801 (0x0e00 << 16) | (0xac88 >> 2),
802 0x00000000,
803 (0x0e00 << 16) | (0xac8c >> 2),
804 0x00000000,
805 (0x0e00 << 16) | (0x970c >> 2),
806 0x00000000,
807 (0x0e00 << 16) | (0x9714 >> 2),
808 0x00000000,
809 (0x0e00 << 16) | (0x9718 >> 2),
810 0x00000000,
811 (0x0e00 << 16) | (0x971c >> 2),
812 0x00000000,
813 (0x0e00 << 16) | (0x31068 >> 2),
814 0x00000000,
815 (0x4e00 << 16) | (0x31068 >> 2),
816 0x00000000,
817 (0x5e00 << 16) | (0x31068 >> 2),
818 0x00000000,
819 (0x6e00 << 16) | (0x31068 >> 2),
820 0x00000000,
821 (0x7e00 << 16) | (0x31068 >> 2),
822 0x00000000,
823 (0x0e00 << 16) | (0xcd10 >> 2),
824 0x00000000,
825 (0x0e00 << 16) | (0xcd14 >> 2),
826 0x00000000,
827 (0x0e00 << 16) | (0x88b0 >> 2),
828 0x00000000,
829 (0x0e00 << 16) | (0x88b4 >> 2),
830 0x00000000,
831 (0x0e00 << 16) | (0x88b8 >> 2),
832 0x00000000,
833 (0x0e00 << 16) | (0x88bc >> 2),
834 0x00000000,
835 (0x0400 << 16) | (0x89c0 >> 2),
836 0x00000000,
837 (0x0e00 << 16) | (0x88c4 >> 2),
838 0x00000000,
839 (0x0e00 << 16) | (0x88c8 >> 2),
840 0x00000000,
841 (0x0e00 << 16) | (0x88d0 >> 2),
842 0x00000000,
843 (0x0e00 << 16) | (0x88d4 >> 2),
844 0x00000000,
845 (0x0e00 << 16) | (0x88d8 >> 2),
846 0x00000000,
847 (0x0e00 << 16) | (0x8980 >> 2),
848 0x00000000,
849 (0x0e00 << 16) | (0x30938 >> 2),
850 0x00000000,
851 (0x0e00 << 16) | (0x3093c >> 2),
852 0x00000000,
853 (0x0e00 << 16) | (0x30940 >> 2),
854 0x00000000,
855 (0x0e00 << 16) | (0x89a0 >> 2),
856 0x00000000,
857 (0x0e00 << 16) | (0x30900 >> 2),
858 0x00000000,
859 (0x0e00 << 16) | (0x30904 >> 2),
860 0x00000000,
861 (0x0e00 << 16) | (0x89b4 >> 2),
862 0x00000000,
863 (0x0e00 << 16) | (0x3e1fc >> 2),
864 0x00000000,
865 (0x0e00 << 16) | (0x3c210 >> 2),
866 0x00000000,
867 (0x0e00 << 16) | (0x3c214 >> 2),
868 0x00000000,
869 (0x0e00 << 16) | (0x3c218 >> 2),
870 0x00000000,
871 (0x0e00 << 16) | (0x8904 >> 2),
872 0x00000000,
873 0x5,
874 (0x0e00 << 16) | (0x8c28 >> 2),
875 (0x0e00 << 16) | (0x8c2c >> 2),
876 (0x0e00 << 16) | (0x8c30 >> 2),
877 (0x0e00 << 16) | (0x8c34 >> 2),
878 (0x0e00 << 16) | (0x9600 >> 2),
879};
880
881static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
882static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
883static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
884static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
885
886/*
887 * Core functions
888 */
889/**
890 * gfx_v7_0_init_microcode - load ucode images from disk
891 *
892 * @adev: amdgpu_device pointer
893 *
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
897 */
898static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
899{
900 const char *chip_name;
901 char fw_name[30];
902 int err;
903
904 DRM_DEBUG("\n");
905
906 switch (adev->asic_type) {
907 case CHIP_BONAIRE:
908 chip_name = "bonaire";
909 break;
910 case CHIP_HAWAII:
911 chip_name = "hawaii";
912 break;
913 case CHIP_KAVERI:
914 chip_name = "kaveri";
915 break;
916 case CHIP_KABINI:
917 chip_name = "kabini";
918 break;
919 case CHIP_MULLINS:
920 chip_name = "mullins";
921 break;
922 default: BUG();
923 }
924
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
927 if (err)
928 goto out;
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
930 if (err)
931 goto out;
932
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
935 if (err)
936 goto out;
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
938 if (err)
939 goto out;
940
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
943 if (err)
944 goto out;
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
946 if (err)
947 goto out;
948
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
951 if (err)
952 goto out;
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
954 if (err)
955 goto out;
956
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
960 if (err)
961 goto out;
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
963 if (err)
964 goto out;
965 }
966
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
969 if (err)
970 goto out;
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
972
973out:
974 if (err) {
975 printk(KERN_ERR
976 "gfx7: Failed to load firmware \"%s\"\n",
977 fw_name);
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
990 }
991 return err;
992}
993
994/**
995 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
996 *
997 * @adev: amdgpu_device pointer
998 *
999 * Starting with SI, the tiling setup is done globally in a
1000 * set of 32 tiling modes. Rather than selecting each set of
1001 * parameters per surface as on older asics, we just select
1002 * which index in the tiling table we want to use, and the
1003 * surface uses those parameters (CIK).
1004 */
1005static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1006{
840a20d3
TSD		 1007 const u32 num_tile_mode_states =
1008 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1009 const u32 num_secondary_tile_mode_states =
1010 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1011 u32 reg_offset, split_equal_to_row_size;
1012 uint32_t *tile, *macrotile;
1013
1014 tile = adev->gfx.config.tile_mode_array;
1015 macrotile = adev->gfx.config.macrotile_mode_array;
a2e73f56
AD		 1016
1017 switch (adev->gfx.config.mem_row_size_in_kb) {
1018 case 1:
1019 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1020 break;
1021 case 2:
1022 default:
1023 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1024 break;
1025 case 4:
1026 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1027 break;
1028 }
1029
840a20d3
TSD		 1030 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1031 tile[reg_offset] = 0;
1032 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1033 macrotile[reg_offset] = 0;
1034
a2e73f56
AD		 1035 switch (adev->asic_type) {
1036 case CHIP_BONAIRE:
840a20d3
TSD		 1037 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1040 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1044 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1045 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1048 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1049 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1056 TILE_SPLIT(split_equal_to_row_size));
1057 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1063 TILE_SPLIT(split_equal_to_row_size));
1064 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1065 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1067 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1070 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1074 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1078 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1079 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1082 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1086 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1098 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1099 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1102 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1106 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1110 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1115 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1118 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1119 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1120 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1123 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1124 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1125 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1127 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1128 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1129 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1130 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1131 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1134 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1135 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1138 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1139
1140 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1143 NUM_BANKS(ADDR_SURF_16_BANK));
1144 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1147 NUM_BANKS(ADDR_SURF_16_BANK));
1148 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_16_BANK));
1152 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1155 NUM_BANKS(ADDR_SURF_16_BANK));
1156 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1163 NUM_BANKS(ADDR_SURF_8_BANK));
1164 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1167 NUM_BANKS(ADDR_SURF_4_BANK));
1168 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1179 NUM_BANKS(ADDR_SURF_16_BANK));
1180 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1183 NUM_BANKS(ADDR_SURF_16_BANK));
1184 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1191 NUM_BANKS(ADDR_SURF_8_BANK));
1192 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1195 NUM_BANKS(ADDR_SURF_4_BANK));
a2e73f56 1196
840a20d3
TSD		 1197 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1198 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1199 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1200 if (reg_offset != 7)
1201 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1202 break;
1203 case CHIP_HAWAII:
840a20d3
TSD		 1204 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1207 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1208 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1211 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1212 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1214 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1215 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1216 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1217 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1219 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1220 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1223 TILE_SPLIT(split_equal_to_row_size));
1224 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1227 TILE_SPLIT(split_equal_to_row_size));
1228 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1231 TILE_SPLIT(split_equal_to_row_size));
1232 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1235 TILE_SPLIT(split_equal_to_row_size));
1236 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1238 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1241 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1245 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1246 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1249 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1251 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1252 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1253 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1256 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1264 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1269 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1272 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1276 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1279 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1283 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1287 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1295 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1308 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1310 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1314 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1318 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1319 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1320 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
a2e73f56 1322
840a20d3
TSD		 1323 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1326 NUM_BANKS(ADDR_SURF_16_BANK));
1327 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1330 NUM_BANKS(ADDR_SURF_16_BANK));
1331 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1334 NUM_BANKS(ADDR_SURF_16_BANK));
1335 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1338 NUM_BANKS(ADDR_SURF_16_BANK));
1339 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1342 NUM_BANKS(ADDR_SURF_8_BANK));
1343 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1346 NUM_BANKS(ADDR_SURF_4_BANK));
1347 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_4_BANK));
1351 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1358 NUM_BANKS(ADDR_SURF_16_BANK));
1359 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_16_BANK));
1363 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_8_BANK));
1367 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_8_BANK));
1375 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_4_BANK));
1379
1380 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1381 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1382 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1383 if (reg_offset != 7)
1384 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1385 break;
1386 case CHIP_KABINI:
1387 case CHIP_KAVERI:
1388 case CHIP_MULLINS:
1389 default:
840a20d3
TSD		 1390 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391 PIPE_CONFIG(ADDR_SURF_P2) |
1392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1393 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1394 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395 PIPE_CONFIG(ADDR_SURF_P2) |
1396 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1397 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1398 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1399 PIPE_CONFIG(ADDR_SURF_P2) |
1400 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1401 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1402 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1403 PIPE_CONFIG(ADDR_SURF_P2) |
1404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1405 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1406 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1409 TILE_SPLIT(split_equal_to_row_size));
1410 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1414 PIPE_CONFIG(ADDR_SURF_P2) |
1415 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1416 TILE_SPLIT(split_equal_to_row_size));
1417 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1418 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1419 PIPE_CONFIG(ADDR_SURF_P2));
1420 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1421 PIPE_CONFIG(ADDR_SURF_P2) |
1422 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1423 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424 PIPE_CONFIG(ADDR_SURF_P2) |
1425 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P2) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1431 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1432 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1433 PIPE_CONFIG(ADDR_SURF_P2) |
1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1435 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1436 PIPE_CONFIG(ADDR_SURF_P2) |
1437 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1439 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1452 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1453 PIPE_CONFIG(ADDR_SURF_P2) |
1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1455 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1459 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1463 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1464 PIPE_CONFIG(ADDR_SURF_P2) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1468 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1471 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1473 PIPE_CONFIG(ADDR_SURF_P2) |
1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1477 PIPE_CONFIG(ADDR_SURF_P2) |
1478 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1481 PIPE_CONFIG(ADDR_SURF_P2) |
1482 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1483 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1484 PIPE_CONFIG(ADDR_SURF_P2) |
1485 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1487 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1488 PIPE_CONFIG(ADDR_SURF_P2) |
1489 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1491 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1492
1493 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1496 NUM_BANKS(ADDR_SURF_8_BANK));
1497 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1500 NUM_BANKS(ADDR_SURF_8_BANK));
1501 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1504 NUM_BANKS(ADDR_SURF_8_BANK));
1505 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1508 NUM_BANKS(ADDR_SURF_8_BANK));
1509 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1524 NUM_BANKS(ADDR_SURF_16_BANK));
1525 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528 NUM_BANKS(ADDR_SURF_16_BANK));
1529 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532 NUM_BANKS(ADDR_SURF_16_BANK));
1533 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1536 NUM_BANKS(ADDR_SURF_16_BANK));
1537 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1548 NUM_BANKS(ADDR_SURF_8_BANK));
a2e73f56 1549
840a20d3
TSD		 1550 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1551 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1552 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1553 if (reg_offset != 7)
1554 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
a2e73f56
AD		 1555 break;
1556 }
1557}
1558
1559/**
1560 * gfx_v7_0_select_se_sh - select which SE, SH to address
1561 *
1562 * @adev: amdgpu_device pointer
1563 * @se_num: shader engine to address
1564 * @sh_num: sh block to address
1565 *
1566 * Select which SE, SH combinations to address. Certain
1567 * registers are instanced per SE or SH. 0xffffffff means
1568 * broadcast to all SEs or SHs (CIK).
1569 */
1570void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1571{
1572 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1573
1574 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1575 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1576 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1577 else if (se_num == 0xffffffff)
1578 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1579 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1580 else if (sh_num == 0xffffffff)
1581 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1582 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1583 else
1584 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1585 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1586 WREG32(mmGRBM_GFX_INDEX, data);
1587}
1588
1589/**
1590 * gfx_v7_0_create_bitmask - create a bitmask
1591 *
1592 * @bit_width: length of the mask
1593 *
1594 * create a variable length bit mask (CIK).
1595 * Returns the bitmask.
1596 */
1597static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1598{
8f8e00c1 1599 return (u32)((1ULL << bit_width) - 1);
a2e73f56
AD		 1600}
1601
1602/**
8f8e00c1 1603 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
a2e73f56
AD		 1604 *
1605 * @adev: amdgpu_device pointer
a2e73f56 1606 *
8f8e00c1
AD		 1607 * Calculates the bitmask of enabled RBs (CIK).
1608 * Returns the enabled RB bitmask.
a2e73f56 1609 */
8f8e00c1 1610static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
a2e73f56
AD		 1611{
1612 u32 data, mask;
1613
1614 data = RREG32(mmCC_RB_BACKEND_DISABLE);
a2e73f56
AD		 1615 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1616
8f8e00c1 1617 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
a2e73f56
AD		 1618 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1619
8f8e00c1
AD		 1620 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1621 adev->gfx.config.max_sh_per_se);
a2e73f56 1622
8f8e00c1 1623 return (~data) & mask;
a2e73f56
AD		 1624}
1625
1626/**
1627 * gfx_v7_0_setup_rb - setup the RBs on the asic
1628 *
1629 * @adev: amdgpu_device pointer
1630 * @se_num: number of SEs (shader engines) for the asic
1631 * @sh_per_se: number of SH blocks per SE for the asic
a2e73f56
AD		 1632 *
1633 * Configures per-SE/SH RB registers (CIK).
1634 */
8f8e00c1 1635static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
a2e73f56
AD		 1636{
1637 int i, j;
8f8e00c1
AD		 1638 u32 data, tmp, num_rbs = 0;
1639 u32 active_rbs = 0;
a2e73f56
AD		 1640
1641 mutex_lock(&adev->grbm_idx_mutex);
8f8e00c1
AD		 1642 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1643 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
a2e73f56 1644 gfx_v7_0_select_se_sh(adev, i, j);
8f8e00c1 1645 data = gfx_v7_0_get_rb_active_bitmap(adev);
a2e73f56 1646 if (adev->asic_type == CHIP_HAWAII)
8f8e00c1
AD		 1647 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1648 HAWAII_RB_BITMAP_WIDTH_PER_SH);
a2e73f56 1649 else
8f8e00c1
AD		 1650 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1651 CIK_RB_BITMAP_WIDTH_PER_SH);
a2e73f56
AD		 1652 }
1653 }
1654 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1655 mutex_unlock(&adev->grbm_idx_mutex);
1656
8f8e00c1
AD		 1657 adev->gfx.config.backend_enable_mask = active_rbs;
1658 tmp = active_rbs;
1659 while (tmp >>= 1)
1660 num_rbs++;
1661 adev->gfx.config.num_rbs = num_rbs;
a2e73f56
AD		 1662}
1663
cd06bf68
BG		 1664/**
1665 * gmc_v7_0_init_compute_vmid - gart enable
1666 *
1667 * @rdev: amdgpu_device pointer
1668 *
1669 * Initialize compute vmid sh_mem registers
1670 *
1671 */
1672#define DEFAULT_SH_MEM_BASES (0x6000)
1673#define FIRST_COMPUTE_VMID (8)
1674#define LAST_COMPUTE_VMID (16)
1675static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1676{
1677 int i;
1678 uint32_t sh_mem_config;
1679 uint32_t sh_mem_bases;
1680
1681 /*
1682 * Configure apertures:
1683 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1684 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1685 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1686 */
1687 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1688 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1689 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1690 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1691 mutex_lock(&adev->srbm_mutex);
1692 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1693 cik_srbm_select(adev, 0, 0, 0, i);
1694 /* CP and shaders */
1695 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1696 WREG32(mmSH_MEM_APE1_BASE, 1);
1697 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1698 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1699 }
1700 cik_srbm_select(adev, 0, 0, 0, 0);
1701 mutex_unlock(&adev->srbm_mutex);
1702}
1703
a2e73f56
AD		 1704/**
1705 * gfx_v7_0_gpu_init - setup the 3D engine
1706 *
1707 * @adev: amdgpu_device pointer
1708 *
1709 * Configures the 3D engine and tiling configuration
1710 * registers so that the 3D engine is usable.
1711 */
1712static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1713{
d93f3ca7 1714 u32 tmp, sh_mem_cfg;
a2e73f56
AD		 1715 int i;
1716
a2e73f56
AD		 1717 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1718
d93f3ca7
AD		 1719 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1720 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1721 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
a2e73f56
AD		 1722
1723 gfx_v7_0_tiling_mode_table_init(adev);
1724
8f8e00c1 1725 gfx_v7_0_setup_rb(adev);
a2e73f56
AD		 1726
1727 /* set HW defaults for 3D engine */
1728 WREG32(mmCP_MEQ_THRESHOLDS,
d93f3ca7
AD		 1729 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1730 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
a2e73f56
AD		 1731
1732 mutex_lock(&adev->grbm_idx_mutex);
1733 /*
1734 * making sure that the following register writes will be broadcasted
1735 * to all the shaders
1736 */
1737 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1738
1739 /* XXX SH_MEM regs */
1740 /* where to put LDS, scratch, GPUVM in FSA64 space */
d93f3ca7 1741 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
74a5d165
JX		 1742 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1743
a2e73f56
AD		 1744 mutex_lock(&adev->srbm_mutex);
1745 for (i = 0; i < 16; i++) {
1746 cik_srbm_select(adev, 0, 0, 0, i);
1747 /* CP and shaders */
74a5d165 1748 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
a2e73f56
AD		 1749 WREG32(mmSH_MEM_APE1_BASE, 1);
1750 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1751 WREG32(mmSH_MEM_BASES, 0);
1752 }
1753 cik_srbm_select(adev, 0, 0, 0, 0);
1754 mutex_unlock(&adev->srbm_mutex);
1755
cd06bf68
BG		 1756 gmc_v7_0_init_compute_vmid(adev);
1757
a2e73f56
AD		 1758 WREG32(mmSX_DEBUG_1, 0x20);
1759
1760 WREG32(mmTA_CNTL_AUX, 0x00010000);
1761
1762 tmp = RREG32(mmSPI_CONFIG_CNTL);
1763 tmp |= 0x03000000;
1764 WREG32(mmSPI_CONFIG_CNTL, tmp);
1765
1766 WREG32(mmSQ_CONFIG, 1);
1767
1768 WREG32(mmDB_DEBUG, 0);
1769
1770 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1771 tmp |= 0x00000400;
1772 WREG32(mmDB_DEBUG2, tmp);
1773
1774 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1775 tmp |= 0x00020200;
1776 WREG32(mmDB_DEBUG3, tmp);
1777
1778 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1779 tmp |= 0x00018208;
1780 WREG32(mmCB_HW_CONTROL, tmp);
1781
1782 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1783
1784 WREG32(mmPA_SC_FIFO_SIZE,
1785 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1786 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1787 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1788 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1789
1790 WREG32(mmVGT_NUM_INSTANCES, 1);
1791
1792 WREG32(mmCP_PERFMON_CNTL, 0);
1793
1794 WREG32(mmSQ_CONFIG, 0);
1795
1796 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1797 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1798 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1799
1800 WREG32(mmVGT_CACHE_INVALIDATION,
1801 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1802 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1803
1804 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1805 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1806
1807 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1808 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1809 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1810 mutex_unlock(&adev->grbm_idx_mutex);
1811
1812 udelay(50);
1813}
1814
1815/*
1816 * GPU scratch registers helpers function.
1817 */
1818/**
1819 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1820 *
1821 * @adev: amdgpu_device pointer
1822 *
1823 * Set up the number and offset of the CP scratch registers.
1824 * NOTE: use of CP scratch registers is a legacy inferface and
1825 * is not used by default on newer asics (r6xx+). On newer asics,
1826 * memory buffers are used for fences rather than scratch regs.
1827 */
1828static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1829{
1830 int i;
1831
1832 adev->gfx.scratch.num_reg = 7;
1833 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1834 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1835 adev->gfx.scratch.free[i] = true;
1836 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1837 }
1838}
1839
1840/**
1841 * gfx_v7_0_ring_test_ring - basic gfx ring test
1842 *
1843 * @adev: amdgpu_device pointer
1844 * @ring: amdgpu_ring structure holding ring information
1845 *
1846 * Allocate a scratch register and write to it using the gfx ring (CIK).
1847 * Provides a basic gfx ring test to verify that the ring is working.
1848 * Used by gfx_v7_0_cp_gfx_resume();
1849 * Returns 0 on success, error on failure.
1850 */
1851static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1852{
1853 struct amdgpu_device *adev = ring->adev;
1854 uint32_t scratch;
1855 uint32_t tmp = 0;
1856 unsigned i;
1857 int r;
1858
1859 r = amdgpu_gfx_scratch_get(adev, &scratch);
1860 if (r) {
1861 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1862 return r;
1863 }
1864 WREG32(scratch, 0xCAFEDEAD);
a27de35c 1865 r = amdgpu_ring_alloc(ring, 3);
a2e73f56
AD		 1866 if (r) {
1867 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1868 amdgpu_gfx_scratch_free(adev, scratch);
1869 return r;
1870 }
1871 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1872 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1873 amdgpu_ring_write(ring, 0xDEADBEEF);
a27de35c 1874 amdgpu_ring_commit(ring);
a2e73f56
AD		 1875
1876 for (i = 0; i < adev->usec_timeout; i++) {
1877 tmp = RREG32(scratch);
1878 if (tmp == 0xDEADBEEF)
1879 break;
1880 DRM_UDELAY(1);
1881 }
1882 if (i < adev->usec_timeout) {
1883 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1884 } else {
1885 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1886 ring->idx, scratch, tmp);
1887 r = -EINVAL;
1888 }
1889 amdgpu_gfx_scratch_free(adev, scratch);
1890 return r;
1891}
1892
1893/**
d2edb07b 1894 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
a2e73f56
AD		 1895 *
1896 * @adev: amdgpu_device pointer
1897 * @ridx: amdgpu ring index
1898 *
1899 * Emits an hdp flush on the cp.
1900 */
d2edb07b 1901static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
a2e73f56
AD		 1902{
1903 u32 ref_and_mask;
d9b5327a 1904 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
a2e73f56
AD		 1905
1906 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1907 switch (ring->me) {
1908 case 1:
1909 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1910 break;
1911 case 2:
1912 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1913 break;
1914 default:
1915 return;
1916 }
1917 } else {
1918 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1919 }
1920
1921 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1922 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1923 WAIT_REG_MEM_FUNCTION(3) | /* == */
d9b5327a 1924 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
a2e73f56
AD		 1925 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1926 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1927 amdgpu_ring_write(ring, ref_and_mask);
1928 amdgpu_ring_write(ring, ref_and_mask);
1929 amdgpu_ring_write(ring, 0x20); /* poll interval */
1930}
1931
1932/**
1933 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1934 *
1935 * @adev: amdgpu_device pointer
1936 * @fence: amdgpu fence object
1937 *
1938 * Emits a fence sequnce number on the gfx ring and flushes
1939 * GPU caches.
1940 */
1941static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 1942 u64 seq, unsigned flags)
a2e73f56 1943{
890ee23f
CZ		 1944 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1945 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
a2e73f56
AD		 1946 /* Workaround for cache flush problems. First send a dummy EOP
1947 * event down the pipe with seq one below.
1948 */
1949 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1950 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1951 EOP_TC_ACTION_EN |
1952 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1953 EVENT_INDEX(5)));
1954 amdgpu_ring_write(ring, addr & 0xfffffffc);
1955 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1956 DATA_SEL(1) | INT_SEL(0));
1957 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1958 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1959
1960 /* Then send the real EOP event down the pipe. */
1961 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1962 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1963 EOP_TC_ACTION_EN |
1964 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1965 EVENT_INDEX(5)));
1966 amdgpu_ring_write(ring, addr & 0xfffffffc);
1967 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 1968 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 1969 amdgpu_ring_write(ring, lower_32_bits(seq));
1970 amdgpu_ring_write(ring, upper_32_bits(seq));
1971}
1972
1973/**
1974 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
1975 *
1976 * @adev: amdgpu_device pointer
1977 * @fence: amdgpu fence object
1978 *
1979 * Emits a fence sequnce number on the compute ring and flushes
1980 * GPU caches.
1981 */
1982static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
1983 u64 addr, u64 seq,
890ee23f 1984 unsigned flags)
a2e73f56 1985{
890ee23f
CZ		 1986 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1987 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1988
a2e73f56
AD		 1989 /* RELEASE_MEM - flush caches, send int */
1990 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
1991 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1992 EOP_TC_ACTION_EN |
1993 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1994 EVENT_INDEX(5)));
890ee23f 1995 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
a2e73f56
AD		 1996 amdgpu_ring_write(ring, addr & 0xfffffffc);
1997 amdgpu_ring_write(ring, upper_32_bits(addr));
1998 amdgpu_ring_write(ring, lower_32_bits(seq));
1999 amdgpu_ring_write(ring, upper_32_bits(seq));
2000}
2001
a2e73f56
AD		 2002/*
2003 * IB stuff
2004 */
2005/**
2006 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2007 *
2008 * @ring: amdgpu_ring structure holding ring information
2009 * @ib: amdgpu indirect buffer object
2010 *
2011 * Emits an DE (drawing engine) or CE (constant engine) IB
2012 * on the gfx ring. IBs are usually generated by userspace
2013 * acceleration drivers and submitted to the kernel for
2014 * sheduling on the ring. This function schedules the IB
2015 * on the gfx ring for execution by the GPU.
2016 */
93323131 2017static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
a2e73f56
AD		 2018 struct amdgpu_ib *ib)
2019{
3cb485f3 2020 bool need_ctx_switch = ring->current_ctx != ib->ctx;
a2e73f56
AD		 2021 u32 header, control = 0;
2022 u32 next_rptr = ring->wptr + 5;
aa2bdb24
JZ		 2023
2024 /* drop the CE preamble IB for the same context */
93323131 2025 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
aa2bdb24
JZ		 2026 return;
2027
93323131 2028 if (need_ctx_switch)
a2e73f56
AD		 2029 next_rptr += 2;
2030
2031 next_rptr += 4;
2032 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2033 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2034 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2035 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2036 amdgpu_ring_write(ring, next_rptr);
2037
a2e73f56 2038 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
93323131 2039 if (need_ctx_switch) {
a2e73f56
AD		 2040 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2041 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 2042 }
2043
de807f81 2044 if (ib->flags & AMDGPU_IB_FLAG_CE)
a2e73f56
AD		 2045 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2046 else
2047 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2048
2049 control |= ib->length_dw |
2050 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2051
2052 amdgpu_ring_write(ring, header);
2053 amdgpu_ring_write(ring,
2054#ifdef __BIG_ENDIAN
2055 (2 << 0) |
2056#endif
2057 (ib->gpu_addr & 0xFFFFFFFC));
2058 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2059 amdgpu_ring_write(ring, control);
2060}
2061
93323131 2062static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2063 struct amdgpu_ib *ib)
2064{
2065 u32 header, control = 0;
2066 u32 next_rptr = ring->wptr + 5;
2067
2068 control |= INDIRECT_BUFFER_VALID;
2069 next_rptr += 4;
2070 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2071 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2072 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2073 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2074 amdgpu_ring_write(ring, next_rptr);
2075
2076 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2077
2078 control |= ib->length_dw |
2079 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2080
2081 amdgpu_ring_write(ring, header);
2082 amdgpu_ring_write(ring,
2083#ifdef __BIG_ENDIAN
2084 (2 << 0) |
2085#endif
2086 (ib->gpu_addr & 0xFFFFFFFC));
2087 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2088 amdgpu_ring_write(ring, control);
2089}
2090
a2e73f56
AD		 2091/**
2092 * gfx_v7_0_ring_test_ib - basic ring IB test
2093 *
2094 * @ring: amdgpu_ring structure holding ring information
2095 *
2096 * Allocate an IB and execute it on the gfx ring (CIK).
2097 * Provides a basic gfx ring test to verify that IBs are working.
2098 * Returns 0 on success, error on failure.
2099 */
2100static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2101{
2102 struct amdgpu_device *adev = ring->adev;
2103 struct amdgpu_ib ib;
1763552e 2104 struct fence *f = NULL;
a2e73f56
AD		 2105 uint32_t scratch;
2106 uint32_t tmp = 0;
2107 unsigned i;
2108 int r;
2109
2110 r = amdgpu_gfx_scratch_get(adev, &scratch);
2111 if (r) {
2112 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2113 return r;
2114 }
2115 WREG32(scratch, 0xCAFEDEAD);
b203dd95 2116 memset(&ib, 0, sizeof(ib));
b07c60c0 2117 r = amdgpu_ib_get(adev, NULL, 256, &ib);
a2e73f56
AD		 2118 if (r) {
2119 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 2120 goto err1;
a2e73f56
AD		 2121 }
2122 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2123 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2124 ib.ptr[2] = 0xDEADBEEF;
2125 ib.length_dw = 3;
42d13693 2126
e86f9cee
CK		 2127 r = amdgpu_ib_schedule(ring, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED,
2128 NULL, &f);
42d13693
CZ		 2129 if (r)
2130 goto err2;
2131
1763552e 2132 r = fence_wait(f, false);
a2e73f56
AD		 2133 if (r) {
2134 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 2135 goto err2;
a2e73f56
AD		 2136 }
2137 for (i = 0; i < adev->usec_timeout; i++) {
2138 tmp = RREG32(scratch);
2139 if (tmp == 0xDEADBEEF)
2140 break;
2141 DRM_UDELAY(1);
2142 }
2143 if (i < adev->usec_timeout) {
2144 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 2145 ring->idx, i);
2146 goto err2;
a2e73f56
AD		 2147 } else {
2148 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2149 scratch, tmp);
2150 r = -EINVAL;
2151 }
42d13693
CZ		 2152
2153err2:
281b4223 2154 fence_put(f);
a2e73f56 2155 amdgpu_ib_free(adev, &ib);
42d13693
CZ		 2156err1:
2157 amdgpu_gfx_scratch_free(adev, scratch);
a2e73f56
AD		 2158 return r;
2159}
2160
2161/*
2162 * CP.
2163 * On CIK, gfx and compute now have independant command processors.
2164 *
2165 * GFX
2166 * Gfx consists of a single ring and can process both gfx jobs and
2167 * compute jobs. The gfx CP consists of three microengines (ME):
2168 * PFP - Pre-Fetch Parser
2169 * ME - Micro Engine
2170 * CE - Constant Engine
2171 * The PFP and ME make up what is considered the Drawing Engine (DE).
2172 * The CE is an asynchronous engine used for updating buffer desciptors
2173 * used by the DE so that they can be loaded into cache in parallel
2174 * while the DE is processing state update packets.
2175 *
2176 * Compute
2177 * The compute CP consists of two microengines (ME):
2178 * MEC1 - Compute MicroEngine 1
2179 * MEC2 - Compute MicroEngine 2
2180 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2181 * The queues are exposed to userspace and are programmed directly
2182 * by the compute runtime.
2183 */
2184/**
2185 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2186 *
2187 * @adev: amdgpu_device pointer
2188 * @enable: enable or disable the MEs
2189 *
2190 * Halts or unhalts the gfx MEs.
2191 */
2192static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2193{
2194 int i;
2195
2196 if (enable) {
2197 WREG32(mmCP_ME_CNTL, 0);
2198 } else {
2199 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2200 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2201 adev->gfx.gfx_ring[i].ready = false;
2202 }
2203 udelay(50);
2204}
2205
2206/**
2207 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2208 *
2209 * @adev: amdgpu_device pointer
2210 *
2211 * Loads the gfx PFP, ME, and CE ucode.
2212 * Returns 0 for success, -EINVAL if the ucode is not available.
2213 */
2214static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2215{
2216 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2217 const struct gfx_firmware_header_v1_0 *ce_hdr;
2218 const struct gfx_firmware_header_v1_0 *me_hdr;
2219 const __le32 *fw_data;
2220 unsigned i, fw_size;
2221
2222 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2223 return -EINVAL;
2224
2225 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2226 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2227 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2228
2229 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2230 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2231 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2232 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2233 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2234 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
02558a00
KW		 2235 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2236 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2237 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
a2e73f56
AD		 2238
2239 gfx_v7_0_cp_gfx_enable(adev, false);
2240
2241 /* PFP */
2242 fw_data = (const __le32 *)
2243 (adev->gfx.pfp_fw->data +
2244 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2245 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2246 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2247 for (i = 0; i < fw_size; i++)
2248 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2249 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2250
2251 /* CE */
2252 fw_data = (const __le32 *)
2253 (adev->gfx.ce_fw->data +
2254 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2255 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2256 WREG32(mmCP_CE_UCODE_ADDR, 0);
2257 for (i = 0; i < fw_size; i++)
2258 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2259 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2260
2261 /* ME */
2262 fw_data = (const __le32 *)
2263 (adev->gfx.me_fw->data +
2264 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2265 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2266 WREG32(mmCP_ME_RAM_WADDR, 0);
2267 for (i = 0; i < fw_size; i++)
2268 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2269 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2270
2271 return 0;
2272}
2273
2274/**
2275 * gfx_v7_0_cp_gfx_start - start the gfx ring
2276 *
2277 * @adev: amdgpu_device pointer
2278 *
2279 * Enables the ring and loads the clear state context and other
2280 * packets required to init the ring.
2281 * Returns 0 for success, error for failure.
2282 */
2283static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2284{
2285 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2286 const struct cs_section_def *sect = NULL;
2287 const struct cs_extent_def *ext = NULL;
2288 int r, i;
2289
2290 /* init the CP */
2291 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2292 WREG32(mmCP_ENDIAN_SWAP, 0);
2293 WREG32(mmCP_DEVICE_ID, 1);
2294
2295 gfx_v7_0_cp_gfx_enable(adev, true);
2296
a27de35c 2297 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
a2e73f56
AD		 2298 if (r) {
2299 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2300 return r;
2301 }
2302
2303 /* init the CE partitions. CE only used for gfx on CIK */
2304 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2305 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2306 amdgpu_ring_write(ring, 0x8000);
2307 amdgpu_ring_write(ring, 0x8000);
2308
2309 /* clear state buffer */
2310 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2311 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2312
2313 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2314 amdgpu_ring_write(ring, 0x80000000);
2315 amdgpu_ring_write(ring, 0x80000000);
2316
2317 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2318 for (ext = sect->section; ext->extent != NULL; ++ext) {
2319 if (sect->id == SECT_CONTEXT) {
2320 amdgpu_ring_write(ring,
2321 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2322 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2323 for (i = 0; i < ext->reg_count; i++)
2324 amdgpu_ring_write(ring, ext->extent[i]);
2325 }
2326 }
2327 }
2328
2329 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2330 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2331 switch (adev->asic_type) {
2332 case CHIP_BONAIRE:
2333 amdgpu_ring_write(ring, 0x16000012);
2334 amdgpu_ring_write(ring, 0x00000000);
2335 break;
2336 case CHIP_KAVERI:
2337 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2338 amdgpu_ring_write(ring, 0x00000000);
2339 break;
2340 case CHIP_KABINI:
2341 case CHIP_MULLINS:
2342 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2343 amdgpu_ring_write(ring, 0x00000000);
2344 break;
2345 case CHIP_HAWAII:
2346 amdgpu_ring_write(ring, 0x3a00161a);
2347 amdgpu_ring_write(ring, 0x0000002e);
2348 break;
2349 default:
2350 amdgpu_ring_write(ring, 0x00000000);
2351 amdgpu_ring_write(ring, 0x00000000);
2352 break;
2353 }
2354
2355 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2356 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2357
2358 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2359 amdgpu_ring_write(ring, 0);
2360
2361 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2362 amdgpu_ring_write(ring, 0x00000316);
2363 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2364 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2365
a27de35c 2366 amdgpu_ring_commit(ring);
a2e73f56
AD		 2367
2368 return 0;
2369}
2370
2371/**
2372 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2373 *
2374 * @adev: amdgpu_device pointer
2375 *
2376 * Program the location and size of the gfx ring buffer
2377 * and test it to make sure it's working.
2378 * Returns 0 for success, error for failure.
2379 */
2380static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2381{
2382 struct amdgpu_ring *ring;
2383 u32 tmp;
2384 u32 rb_bufsz;
2385 u64 rb_addr, rptr_addr;
2386 int r;
2387
2388 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2389 if (adev->asic_type != CHIP_HAWAII)
2390 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2391
2392 /* Set the write pointer delay */
2393 WREG32(mmCP_RB_WPTR_DELAY, 0);
2394
2395 /* set the RB to use vmid 0 */
2396 WREG32(mmCP_RB_VMID, 0);
2397
2398 WREG32(mmSCRATCH_ADDR, 0);
2399
2400 /* ring 0 - compute and gfx */
2401 /* Set ring buffer size */
2402 ring = &adev->gfx.gfx_ring[0];
2403 rb_bufsz = order_base_2(ring->ring_size / 8);
2404 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2405#ifdef __BIG_ENDIAN
454fc95e 2406 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
a2e73f56
AD		 2407#endif
2408 WREG32(mmCP_RB0_CNTL, tmp);
2409
2410 /* Initialize the ring buffer's read and write pointers */
2411 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2412 ring->wptr = 0;
2413 WREG32(mmCP_RB0_WPTR, ring->wptr);
2414
2415 /* set the wb address wether it's enabled or not */
2416 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2417 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2418 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2419
2420 /* scratch register shadowing is no longer supported */
2421 WREG32(mmSCRATCH_UMSK, 0);
2422
2423 mdelay(1);
2424 WREG32(mmCP_RB0_CNTL, tmp);
2425
2426 rb_addr = ring->gpu_addr >> 8;
2427 WREG32(mmCP_RB0_BASE, rb_addr);
2428 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2429
2430 /* start the ring */
2431 gfx_v7_0_cp_gfx_start(adev);
2432 ring->ready = true;
2433 r = amdgpu_ring_test_ring(ring);
2434 if (r) {
2435 ring->ready = false;
2436 return r;
2437 }
2438
2439 return 0;
2440}
2441
2442static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2443{
7edd6b2f 2444 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2445}
2446
2447static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2448{
2449 struct amdgpu_device *adev = ring->adev;
a2e73f56 2450
7edd6b2f 2451 return RREG32(mmCP_RB0_WPTR);
a2e73f56
AD		 2452}
2453
2454static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2455{
2456 struct amdgpu_device *adev = ring->adev;
2457
2458 WREG32(mmCP_RB0_WPTR, ring->wptr);
2459 (void)RREG32(mmCP_RB0_WPTR);
2460}
2461
2462static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2463{
7edd6b2f 2464 return ring->adev->wb.wb[ring->rptr_offs];
a2e73f56
AD		 2465}
2466
2467static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2468{
a2e73f56 2469 /* XXX check if swapping is necessary on BE */
7edd6b2f 2470 return ring->adev->wb.wb[ring->wptr_offs];
a2e73f56
AD		 2471}
2472
2473static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2474{
2475 struct amdgpu_device *adev = ring->adev;
2476
2477 /* XXX check if swapping is necessary on BE */
2478 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2479 WDOORBELL32(ring->doorbell_index, ring->wptr);
2480}
2481
2482/**
2483 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2484 *
2485 * @adev: amdgpu_device pointer
2486 * @enable: enable or disable the MEs
2487 *
2488 * Halts or unhalts the compute MEs.
2489 */
2490static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2491{
2492 int i;
2493
2494 if (enable) {
2495 WREG32(mmCP_MEC_CNTL, 0);
2496 } else {
2497 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2498 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2499 adev->gfx.compute_ring[i].ready = false;
2500 }
2501 udelay(50);
2502}
2503
2504/**
2505 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2506 *
2507 * @adev: amdgpu_device pointer
2508 *
2509 * Loads the compute MEC1&2 ucode.
2510 * Returns 0 for success, -EINVAL if the ucode is not available.
2511 */
2512static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2513{
2514 const struct gfx_firmware_header_v1_0 *mec_hdr;
2515 const __le32 *fw_data;
2516 unsigned i, fw_size;
2517
2518 if (!adev->gfx.mec_fw)
2519 return -EINVAL;
2520
2521 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2522 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2523 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
351643d7
JZ		 2524 adev->gfx.mec_feature_version = le32_to_cpu(
2525 mec_hdr->ucode_feature_version);
a2e73f56
AD		 2526
2527 gfx_v7_0_cp_compute_enable(adev, false);
2528
2529 /* MEC1 */
2530 fw_data = (const __le32 *)
2531 (adev->gfx.mec_fw->data +
2532 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2533 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2534 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2535 for (i = 0; i < fw_size; i++)
2536 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2537 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2538
2539 if (adev->asic_type == CHIP_KAVERI) {
2540 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2541
2542 if (!adev->gfx.mec2_fw)
2543 return -EINVAL;
2544
2545 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2546 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2547 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
351643d7
JZ		 2548 adev->gfx.mec2_feature_version = le32_to_cpu(
2549 mec2_hdr->ucode_feature_version);
a2e73f56
AD		 2550
2551 /* MEC2 */
2552 fw_data = (const __le32 *)
2553 (adev->gfx.mec2_fw->data +
2554 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2555 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2556 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2557 for (i = 0; i < fw_size; i++)
2558 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2559 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2560 }
2561
2562 return 0;
2563}
2564
a2e73f56
AD		 2565/**
2566 * gfx_v7_0_cp_compute_fini - stop the compute queues
2567 *
2568 * @adev: amdgpu_device pointer
2569 *
2570 * Stop the compute queues and tear down the driver queue
2571 * info.
2572 */
2573static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2574{
2575 int i, r;
2576
2577 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2578 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2579
2580 if (ring->mqd_obj) {
2581 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2582 if (unlikely(r != 0))
2583 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2584
2585 amdgpu_bo_unpin(ring->mqd_obj);
2586 amdgpu_bo_unreserve(ring->mqd_obj);
2587
2588 amdgpu_bo_unref(&ring->mqd_obj);
2589 ring->mqd_obj = NULL;
2590 }
2591 }
2592}
2593
2594static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2595{
2596 int r;
2597
2598 if (adev->gfx.mec.hpd_eop_obj) {
2599 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2600 if (unlikely(r != 0))
2601 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2602 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2603 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2604
2605 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2606 adev->gfx.mec.hpd_eop_obj = NULL;
2607 }
2608}
2609
2610#define MEC_HPD_SIZE 2048
2611
2612static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2613{
2614 int r;
2615 u32 *hpd;
2616
2617 /*
2618 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2619 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2620 * Nonetheless, we assign only 1 pipe because all other pipes will
2621 * be handled by KFD
2622 */
2623 adev->gfx.mec.num_mec = 1;
2624 adev->gfx.mec.num_pipe = 1;
2625 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2626
2627 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2628 r = amdgpu_bo_create(adev,
2629 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2630 PAGE_SIZE, true,
72d7668b 2631 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2632 &adev->gfx.mec.hpd_eop_obj);
2633 if (r) {
2634 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2635 return r;
2636 }
2637 }
2638
2639 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2640 if (unlikely(r != 0)) {
2641 gfx_v7_0_mec_fini(adev);
2642 return r;
2643 }
2644 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2645 &adev->gfx.mec.hpd_eop_gpu_addr);
2646 if (r) {
2647 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2648 gfx_v7_0_mec_fini(adev);
2649 return r;
2650 }
2651 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2652 if (r) {
2653 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2654 gfx_v7_0_mec_fini(adev);
2655 return r;
2656 }
2657
2658 /* clear memory. Not sure if this is required or not */
2659 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2660
2661 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2662 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2663
2664 return 0;
2665}
2666
2667struct hqd_registers
2668{
2669 u32 cp_mqd_base_addr;
2670 u32 cp_mqd_base_addr_hi;
2671 u32 cp_hqd_active;
2672 u32 cp_hqd_vmid;
2673 u32 cp_hqd_persistent_state;
2674 u32 cp_hqd_pipe_priority;
2675 u32 cp_hqd_queue_priority;
2676 u32 cp_hqd_quantum;
2677 u32 cp_hqd_pq_base;
2678 u32 cp_hqd_pq_base_hi;
2679 u32 cp_hqd_pq_rptr;
2680 u32 cp_hqd_pq_rptr_report_addr;
2681 u32 cp_hqd_pq_rptr_report_addr_hi;
2682 u32 cp_hqd_pq_wptr_poll_addr;
2683 u32 cp_hqd_pq_wptr_poll_addr_hi;
2684 u32 cp_hqd_pq_doorbell_control;
2685 u32 cp_hqd_pq_wptr;
2686 u32 cp_hqd_pq_control;
2687 u32 cp_hqd_ib_base_addr;
2688 u32 cp_hqd_ib_base_addr_hi;
2689 u32 cp_hqd_ib_rptr;
2690 u32 cp_hqd_ib_control;
2691 u32 cp_hqd_iq_timer;
2692 u32 cp_hqd_iq_rptr;
2693 u32 cp_hqd_dequeue_request;
2694 u32 cp_hqd_dma_offload;
2695 u32 cp_hqd_sema_cmd;
2696 u32 cp_hqd_msg_type;
2697 u32 cp_hqd_atomic0_preop_lo;
2698 u32 cp_hqd_atomic0_preop_hi;
2699 u32 cp_hqd_atomic1_preop_lo;
2700 u32 cp_hqd_atomic1_preop_hi;
2701 u32 cp_hqd_hq_scheduler0;
2702 u32 cp_hqd_hq_scheduler1;
2703 u32 cp_mqd_control;
2704};
2705
2706struct bonaire_mqd
2707{
2708 u32 header;
2709 u32 dispatch_initiator;
2710 u32 dimensions[3];
2711 u32 start_idx[3];
2712 u32 num_threads[3];
2713 u32 pipeline_stat_enable;
2714 u32 perf_counter_enable;
2715 u32 pgm[2];
2716 u32 tba[2];
2717 u32 tma[2];
2718 u32 pgm_rsrc[2];
2719 u32 vmid;
2720 u32 resource_limits;
2721 u32 static_thread_mgmt01[2];
2722 u32 tmp_ring_size;
2723 u32 static_thread_mgmt23[2];
2724 u32 restart[3];
2725 u32 thread_trace_enable;
2726 u32 reserved1;
2727 u32 user_data[16];
2728 u32 vgtcs_invoke_count[2];
2729 struct hqd_registers queue_state;
2730 u32 dequeue_cntr;
2731 u32 interrupt_queue[64];
2732};
2733
2734/**
2735 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2736 *
2737 * @adev: amdgpu_device pointer
2738 *
2739 * Program the compute queues and test them to make sure they
2740 * are working.
2741 * Returns 0 for success, error for failure.
2742 */
2743static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2744{
2745 int r, i, j;
2746 u32 tmp;
2747 bool use_doorbell = true;
2748 u64 hqd_gpu_addr;
2749 u64 mqd_gpu_addr;
2750 u64 eop_gpu_addr;
2751 u64 wb_gpu_addr;
2752 u32 *buf;
2753 struct bonaire_mqd *mqd;
2754
6e9821b2 2755 gfx_v7_0_cp_compute_enable(adev, true);
a2e73f56
AD		 2756
2757 /* fix up chicken bits */
2758 tmp = RREG32(mmCP_CPF_DEBUG);
2759 tmp |= (1 << 23);
2760 WREG32(mmCP_CPF_DEBUG, tmp);
2761
2762 /* init the pipes */
2763 mutex_lock(&adev->srbm_mutex);
2764 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2765 int me = (i < 4) ? 1 : 2;
2766 int pipe = (i < 4) ? i : (i - 4);
2767
2768 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2769
2770 cik_srbm_select(adev, me, pipe, 0, 0);
2771
2772 /* write the EOP addr */
2773 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2774 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2775
2776 /* set the VMID assigned */
2777 WREG32(mmCP_HPD_EOP_VMID, 0);
2778
2779 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2780 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2781 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2782 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2783 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2784 }
2785 cik_srbm_select(adev, 0, 0, 0, 0);
2786 mutex_unlock(&adev->srbm_mutex);
2787
2788 /* init the queues. Just two for now. */
2789 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2790 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2791
2792 if (ring->mqd_obj == NULL) {
2793 r = amdgpu_bo_create(adev,
2794 sizeof(struct bonaire_mqd),
2795 PAGE_SIZE, true,
72d7668b 2796 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
a2e73f56
AD		 2797 &ring->mqd_obj);
2798 if (r) {
2799 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2800 return r;
2801 }
2802 }
2803
2804 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2805 if (unlikely(r != 0)) {
2806 gfx_v7_0_cp_compute_fini(adev);
2807 return r;
2808 }
2809 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2810 &mqd_gpu_addr);
2811 if (r) {
2812 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2813 gfx_v7_0_cp_compute_fini(adev);
2814 return r;
2815 }
2816 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2817 if (r) {
2818 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2819 gfx_v7_0_cp_compute_fini(adev);
2820 return r;
2821 }
2822
2823 /* init the mqd struct */
2824 memset(buf, 0, sizeof(struct bonaire_mqd));
2825
2826 mqd = (struct bonaire_mqd *)buf;
2827 mqd->header = 0xC0310800;
2828 mqd->static_thread_mgmt01[0] = 0xffffffff;
2829 mqd->static_thread_mgmt01[1] = 0xffffffff;
2830 mqd->static_thread_mgmt23[0] = 0xffffffff;
2831 mqd->static_thread_mgmt23[1] = 0xffffffff;
2832
2833 mutex_lock(&adev->srbm_mutex);
2834 cik_srbm_select(adev, ring->me,
2835 ring->pipe,
2836 ring->queue, 0);
2837
2838 /* disable wptr polling */
2839 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2840 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2841 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2842
2843 /* enable doorbell? */
2844 mqd->queue_state.cp_hqd_pq_doorbell_control =
2845 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2846 if (use_doorbell)
2847 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2848 else
2849 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2850 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2851 mqd->queue_state.cp_hqd_pq_doorbell_control);
2852
2853 /* disable the queue if it's active */
2854 mqd->queue_state.cp_hqd_dequeue_request = 0;
2855 mqd->queue_state.cp_hqd_pq_rptr = 0;
2856 mqd->queue_state.cp_hqd_pq_wptr= 0;
2857 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2858 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2859 for (j = 0; j < adev->usec_timeout; j++) {
2860 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2861 break;
2862 udelay(1);
2863 }
2864 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2865 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2866 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2867 }
2868
2869 /* set the pointer to the MQD */
2870 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2871 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2872 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2873 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2874 /* set MQD vmid to 0 */
2875 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2876 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2877 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2878
2879 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2880 hqd_gpu_addr = ring->gpu_addr >> 8;
2881 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2882 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2883 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2884 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2885
2886 /* set up the HQD, this is similar to CP_RB0_CNTL */
2887 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2888 mqd->queue_state.cp_hqd_pq_control &=
2889 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2890 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2891
2892 mqd->queue_state.cp_hqd_pq_control |=
2893 order_base_2(ring->ring_size / 8);
2894 mqd->queue_state.cp_hqd_pq_control |=
2895 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2896#ifdef __BIG_ENDIAN
454fc95e
AD		 2897 mqd->queue_state.cp_hqd_pq_control |=
2898 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
a2e73f56
AD		 2899#endif
2900 mqd->queue_state.cp_hqd_pq_control &=
2901 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2902 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2903 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2904 mqd->queue_state.cp_hqd_pq_control |=
2905 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2906 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2907 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2908
2909 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2910 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2911 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2912 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2913 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2914 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2915 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2916
2917 /* set the wb address wether it's enabled or not */
2918 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2919 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2920 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2921 upper_32_bits(wb_gpu_addr) & 0xffff;
2922 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2923 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2924 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2925 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2926
2927 /* enable the doorbell if requested */
2928 if (use_doorbell) {
2929 mqd->queue_state.cp_hqd_pq_doorbell_control =
2930 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2931 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2932 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2933 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2934 (ring->doorbell_index <<
2935 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2936 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2937 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2938 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2939 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2940 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2941
2942 } else {
2943 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2944 }
2945 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2946 mqd->queue_state.cp_hqd_pq_doorbell_control);
2947
2948 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2949 ring->wptr = 0;
2950 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2951 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2952 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2953
2954 /* set the vmid for the queue */
2955 mqd->queue_state.cp_hqd_vmid = 0;
2956 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2957
2958 /* activate the queue */
2959 mqd->queue_state.cp_hqd_active = 1;
2960 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2961
2962 cik_srbm_select(adev, 0, 0, 0, 0);
2963 mutex_unlock(&adev->srbm_mutex);
2964
2965 amdgpu_bo_kunmap(ring->mqd_obj);
2966 amdgpu_bo_unreserve(ring->mqd_obj);
2967
2968 ring->ready = true;
2969 r = amdgpu_ring_test_ring(ring);
2970 if (r)
2971 ring->ready = false;
2972 }
2973
2974 return 0;
2975}
2976
2977static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
2978{
2979 gfx_v7_0_cp_gfx_enable(adev, enable);
2980 gfx_v7_0_cp_compute_enable(adev, enable);
2981}
2982
2983static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
2984{
2985 int r;
2986
2987 r = gfx_v7_0_cp_gfx_load_microcode(adev);
2988 if (r)
2989 return r;
2990 r = gfx_v7_0_cp_compute_load_microcode(adev);
2991 if (r)
2992 return r;
2993
2994 return 0;
2995}
2996
2997static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2998 bool enable)
2999{
3000 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3001
3002 if (enable)
3003 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3004 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3005 else
3006 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3007 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3008 WREG32(mmCP_INT_CNTL_RING0, tmp);
3009}
3010
3011static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3012{
3013 int r;
3014
3015 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3016
3017 r = gfx_v7_0_cp_load_microcode(adev);
3018 if (r)
3019 return r;
3020
3021 r = gfx_v7_0_cp_gfx_resume(adev);
3022 if (r)
3023 return r;
3024 r = gfx_v7_0_cp_compute_resume(adev);
3025 if (r)
3026 return r;
3027
3028 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3029
3030 return 0;
3031}
3032
a2e73f56
AD		 3033/*
3034 * vm
3035 * VMID 0 is the physical GPU addresses as used by the kernel.
3036 * VMIDs 1-15 are used for userspace clients and are handled
3037 * by the amdgpu vm/hsa code.
3038 */
3039/**
3040 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3041 *
3042 * @adev: amdgpu_device pointer
3043 *
3044 * Update the page table base and flush the VM TLB
3045 * using the CP (CIK).
3046 */
3047static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3048 unsigned vm_id, uint64_t pd_addr)
3049{
3050 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
5c3422b0 3051 if (usepfp) {
3052 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3053 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3054 amdgpu_ring_write(ring, 0);
3055 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3056 amdgpu_ring_write(ring, 0);
3057 }
a2e73f56
AD		 3058
3059 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3060 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3061 WRITE_DATA_DST_SEL(0)));
3062 if (vm_id < 8) {
3063 amdgpu_ring_write(ring,
3064 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3065 } else {
3066 amdgpu_ring_write(ring,
3067 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3068 }
3069 amdgpu_ring_write(ring, 0);
3070 amdgpu_ring_write(ring, pd_addr >> 12);
3071
a2e73f56
AD		 3072 /* bits 0-15 are the VM contexts0-15 */
3073 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3074 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3075 WRITE_DATA_DST_SEL(0)));
3076 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3077 amdgpu_ring_write(ring, 0);
3078 amdgpu_ring_write(ring, 1 << vm_id);
3079
3080 /* wait for the invalidate to complete */
3081 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3082 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3083 WAIT_REG_MEM_FUNCTION(0) | /* always */
3084 WAIT_REG_MEM_ENGINE(0))); /* me */
3085 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3086 amdgpu_ring_write(ring, 0);
3087 amdgpu_ring_write(ring, 0); /* ref */
3088 amdgpu_ring_write(ring, 0); /* mask */
3089 amdgpu_ring_write(ring, 0x20); /* poll interval */
3090
3091 /* compute doesn't have PFP */
3092 if (usepfp) {
3093 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3094 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3095 amdgpu_ring_write(ring, 0x0);
3096
3097 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
5c3422b0 3098 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3099 amdgpu_ring_write(ring, 0);
3100 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3101 amdgpu_ring_write(ring, 0);
a2e73f56
AD		 3102 }
3103}
3104
3105/*
3106 * RLC
3107 * The RLC is a multi-purpose microengine that handles a
3108 * variety of functions.
3109 */
3110static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3111{
3112 int r;
3113
3114 /* save restore block */
3115 if (adev->gfx.rlc.save_restore_obj) {
3116 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3117 if (unlikely(r != 0))
3118 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3119 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3120 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3121
3122 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3123 adev->gfx.rlc.save_restore_obj = NULL;
3124 }
3125
3126 /* clear state block */
3127 if (adev->gfx.rlc.clear_state_obj) {
3128 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3129 if (unlikely(r != 0))
3130 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3131 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3132 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3133
3134 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3135 adev->gfx.rlc.clear_state_obj = NULL;
3136 }
3137
3138 /* clear state block */
3139 if (adev->gfx.rlc.cp_table_obj) {
3140 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3141 if (unlikely(r != 0))
3142 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3143 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3144 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3145
3146 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3147 adev->gfx.rlc.cp_table_obj = NULL;
3148 }
3149}
3150
3151static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3152{
3153 const u32 *src_ptr;
3154 volatile u32 *dst_ptr;
3155 u32 dws, i;
3156 const struct cs_section_def *cs_data;
3157 int r;
3158
3159 /* allocate rlc buffers */
2f7d10b3 3160 if (adev->flags & AMD_IS_APU) {
a2e73f56
AD		 3161 if (adev->asic_type == CHIP_KAVERI) {
3162 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3163 adev->gfx.rlc.reg_list_size =
3164 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3165 } else {
3166 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3167 adev->gfx.rlc.reg_list_size =
3168 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3169 }
3170 }
3171 adev->gfx.rlc.cs_data = ci_cs_data;
3172 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3173
3174 src_ptr = adev->gfx.rlc.reg_list;
3175 dws = adev->gfx.rlc.reg_list_size;
3176 dws += (5 * 16) + 48 + 48 + 64;
3177
3178 cs_data = adev->gfx.rlc.cs_data;
3179
3180 if (src_ptr) {
3181 /* save restore block */
3182 if (adev->gfx.rlc.save_restore_obj == NULL) {
3183 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3184 AMDGPU_GEM_DOMAIN_VRAM,
3185 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3186 NULL, NULL,
3187 &adev->gfx.rlc.save_restore_obj);
a2e73f56
AD		 3188 if (r) {
3189 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3190 return r;
3191 }
3192 }
3193
3194 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3195 if (unlikely(r != 0)) {
3196 gfx_v7_0_rlc_fini(adev);
3197 return r;
3198 }
3199 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3200 &adev->gfx.rlc.save_restore_gpu_addr);
3201 if (r) {
3202 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3203 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3204 gfx_v7_0_rlc_fini(adev);
3205 return r;
3206 }
3207
3208 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3209 if (r) {
3210 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3211 gfx_v7_0_rlc_fini(adev);
3212 return r;
3213 }
3214 /* write the sr buffer */
3215 dst_ptr = adev->gfx.rlc.sr_ptr;
3216 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3217 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3218 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3219 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3220 }
3221
3222 if (cs_data) {
3223 /* clear state block */
3224 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3225
3226 if (adev->gfx.rlc.clear_state_obj == NULL) {
3227 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
857d913d
AD		 3228 AMDGPU_GEM_DOMAIN_VRAM,
3229 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3230 NULL, NULL,
3231 &adev->gfx.rlc.clear_state_obj);
a2e73f56
AD		 3232 if (r) {
3233 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3234 gfx_v7_0_rlc_fini(adev);
3235 return r;
3236 }
3237 }
3238 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3239 if (unlikely(r != 0)) {
3240 gfx_v7_0_rlc_fini(adev);
3241 return r;
3242 }
3243 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3244 &adev->gfx.rlc.clear_state_gpu_addr);
3245 if (r) {
3246 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3247 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3248 gfx_v7_0_rlc_fini(adev);
3249 return r;
3250 }
3251
3252 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3253 if (r) {
3254 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3255 gfx_v7_0_rlc_fini(adev);
3256 return r;
3257 }
3258 /* set up the cs buffer */
3259 dst_ptr = adev->gfx.rlc.cs_ptr;
3260 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3261 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3262 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3263 }
3264
3265 if (adev->gfx.rlc.cp_table_size) {
3266 if (adev->gfx.rlc.cp_table_obj == NULL) {
3267 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
857d913d
AD		 3268 AMDGPU_GEM_DOMAIN_VRAM,
3269 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
72d7668b
CK		 3270 NULL, NULL,
3271 &adev->gfx.rlc.cp_table_obj);
a2e73f56
AD		 3272 if (r) {
3273 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3274 gfx_v7_0_rlc_fini(adev);
3275 return r;
3276 }
3277 }
3278
3279 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3280 if (unlikely(r != 0)) {
3281 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3282 gfx_v7_0_rlc_fini(adev);
3283 return r;
3284 }
3285 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3286 &adev->gfx.rlc.cp_table_gpu_addr);
3287 if (r) {
3288 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3289 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3290 gfx_v7_0_rlc_fini(adev);
3291 return r;
3292 }
3293 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3294 if (r) {
3295 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3296 gfx_v7_0_rlc_fini(adev);
3297 return r;
3298 }
3299
3300 gfx_v7_0_init_cp_pg_table(adev);
3301
3302 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3303 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3304
3305 }
3306
3307 return 0;
3308}
3309
3310static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3311{
3312 u32 tmp;
3313
3314 tmp = RREG32(mmRLC_LB_CNTL);
3315 if (enable)
3316 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3317 else
3318 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3319 WREG32(mmRLC_LB_CNTL, tmp);
3320}
3321
3322static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3323{
3324 u32 i, j, k;
3325 u32 mask;
3326
3327 mutex_lock(&adev->grbm_idx_mutex);
3328 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3329 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3330 gfx_v7_0_select_se_sh(adev, i, j);
3331 for (k = 0; k < adev->usec_timeout; k++) {
3332 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3333 break;
3334 udelay(1);
3335 }
3336 }
3337 }
3338 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3339 mutex_unlock(&adev->grbm_idx_mutex);
3340
3341 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3342 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3343 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3344 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3345 for (k = 0; k < adev->usec_timeout; k++) {
3346 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3347 break;
3348 udelay(1);
3349 }
3350}
3351
3352static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3353{
3354 u32 tmp;
3355
3356 tmp = RREG32(mmRLC_CNTL);
3357 if (tmp != rlc)
3358 WREG32(mmRLC_CNTL, rlc);
3359}
3360
3361static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3362{
3363 u32 data, orig;
3364
3365 orig = data = RREG32(mmRLC_CNTL);
3366
3367 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3368 u32 i;
3369
3370 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3371 WREG32(mmRLC_CNTL, data);
3372
3373 for (i = 0; i < adev->usec_timeout; i++) {
3374 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3375 break;
3376 udelay(1);
3377 }
3378
3379 gfx_v7_0_wait_for_rlc_serdes(adev);
3380 }
3381
3382 return orig;
3383}
3384
3385void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3386{
3387 u32 tmp, i, mask;
3388
3389 tmp = 0x1 | (1 << 1);
3390 WREG32(mmRLC_GPR_REG2, tmp);
3391
3392 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3393 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3394 for (i = 0; i < adev->usec_timeout; i++) {
3395 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3396 break;
3397 udelay(1);
3398 }
3399
3400 for (i = 0; i < adev->usec_timeout; i++) {
3401 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3402 break;
3403 udelay(1);
3404 }
3405}
3406
3407void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3408{
3409 u32 tmp;
3410
3411 tmp = 0x1 | (0 << 1);
3412 WREG32(mmRLC_GPR_REG2, tmp);
3413}
3414
3415/**
3416 * gfx_v7_0_rlc_stop - stop the RLC ME
3417 *
3418 * @adev: amdgpu_device pointer
3419 *
3420 * Halt the RLC ME (MicroEngine) (CIK).
3421 */
3422void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3423{
3424 WREG32(mmRLC_CNTL, 0);
3425
3426 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3427
3428 gfx_v7_0_wait_for_rlc_serdes(adev);
3429}
3430
3431/**
3432 * gfx_v7_0_rlc_start - start the RLC ME
3433 *
3434 * @adev: amdgpu_device pointer
3435 *
3436 * Unhalt the RLC ME (MicroEngine) (CIK).
3437 */
3438static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3439{
3440 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3441
3442 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3443
3444 udelay(50);
3445}
3446
3447static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3448{
3449 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3450
3451 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3452 WREG32(mmGRBM_SOFT_RESET, tmp);
3453 udelay(50);
3454 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3455 WREG32(mmGRBM_SOFT_RESET, tmp);
3456 udelay(50);
3457}
3458
3459/**
3460 * gfx_v7_0_rlc_resume - setup the RLC hw
3461 *
3462 * @adev: amdgpu_device pointer
3463 *
3464 * Initialize the RLC registers, load the ucode,
3465 * and start the RLC (CIK).
3466 * Returns 0 for success, -EINVAL if the ucode is not available.
3467 */
3468static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3469{
3470 const struct rlc_firmware_header_v1_0 *hdr;
3471 const __le32 *fw_data;
3472 unsigned i, fw_size;
3473 u32 tmp;
3474
3475 if (!adev->gfx.rlc_fw)
3476 return -EINVAL;
3477
3478 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3479 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3480 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
351643d7
JZ		 3481 adev->gfx.rlc_feature_version = le32_to_cpu(
3482 hdr->ucode_feature_version);
a2e73f56
AD		 3483
3484 gfx_v7_0_rlc_stop(adev);
3485
3486 /* disable CG */
3487 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3488 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3489
3490 gfx_v7_0_rlc_reset(adev);
3491
3492 gfx_v7_0_init_pg(adev);
3493
3494 WREG32(mmRLC_LB_CNTR_INIT, 0);
3495 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3496
3497 mutex_lock(&adev->grbm_idx_mutex);
3498 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3499 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3500 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3501 WREG32(mmRLC_LB_CNTL, 0x80000004);
3502 mutex_unlock(&adev->grbm_idx_mutex);
3503
3504 WREG32(mmRLC_MC_CNTL, 0);
3505 WREG32(mmRLC_UCODE_CNTL, 0);
3506
3507 fw_data = (const __le32 *)
3508 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3509 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3510 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3511 for (i = 0; i < fw_size; i++)
3512 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3513 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3514
3515 /* XXX - find out what chips support lbpw */
3516 gfx_v7_0_enable_lbpw(adev, false);
3517
3518 if (adev->asic_type == CHIP_BONAIRE)
3519 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3520
3521 gfx_v7_0_rlc_start(adev);
3522
3523 return 0;
3524}
3525
3526static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3527{
3528 u32 data, orig, tmp, tmp2;
3529
3530 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3531
3532 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {
3533 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3534
3535 tmp = gfx_v7_0_halt_rlc(adev);
3536
3537 mutex_lock(&adev->grbm_idx_mutex);
3538 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3539 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3540 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3541 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3542 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3543 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3544 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3545 mutex_unlock(&adev->grbm_idx_mutex);
3546
3547 gfx_v7_0_update_rlc(adev, tmp);
3548
3549 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3550 } else {
3551 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3552
3553 RREG32(mmCB_CGTT_SCLK_CTRL);
3554 RREG32(mmCB_CGTT_SCLK_CTRL);
3555 RREG32(mmCB_CGTT_SCLK_CTRL);
3556 RREG32(mmCB_CGTT_SCLK_CTRL);
3557
3558 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3559 }
3560
3561 if (orig != data)
3562 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3563
3564}
3565
3566static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3567{
3568 u32 data, orig, tmp = 0;
3569
3570 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {
3571 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {
3572 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {
3573 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3574 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3575 if (orig != data)
3576 WREG32(mmCP_MEM_SLP_CNTL, data);
3577 }
3578 }
3579
3580 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3581 data |= 0x00000001;
3582 data &= 0xfffffffd;
3583 if (orig != data)
3584 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3585
3586 tmp = gfx_v7_0_halt_rlc(adev);
3587
3588 mutex_lock(&adev->grbm_idx_mutex);
3589 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3590 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3591 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3592 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3593 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3594 WREG32(mmRLC_SERDES_WR_CTRL, data);
3595 mutex_unlock(&adev->grbm_idx_mutex);
3596
3597 gfx_v7_0_update_rlc(adev, tmp);
3598
3599 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {
3600 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3601 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3602 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3603 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3604 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3605 if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&
3606 (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))
3607 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3608 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3609 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3610 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3611 if (orig != data)
3612 WREG32(mmCGTS_SM_CTRL_REG, data);
3613 }
3614 } else {
3615 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3616 data |= 0x00000003;
3617 if (orig != data)
3618 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3619
3620 data = RREG32(mmRLC_MEM_SLP_CNTL);
3621 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3622 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3623 WREG32(mmRLC_MEM_SLP_CNTL, data);
3624 }
3625
3626 data = RREG32(mmCP_MEM_SLP_CNTL);
3627 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3628 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3629 WREG32(mmCP_MEM_SLP_CNTL, data);
3630 }
3631
3632 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3633 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3634 if (orig != data)
3635 WREG32(mmCGTS_SM_CTRL_REG, data);
3636
3637 tmp = gfx_v7_0_halt_rlc(adev);
3638
3639 mutex_lock(&adev->grbm_idx_mutex);
3640 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3641 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3642 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3643 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3644 WREG32(mmRLC_SERDES_WR_CTRL, data);
3645 mutex_unlock(&adev->grbm_idx_mutex);
3646
3647 gfx_v7_0_update_rlc(adev, tmp);
3648 }
3649}
3650
3651static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3652 bool enable)
3653{
3654 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3655 /* order matters! */
3656 if (enable) {
3657 gfx_v7_0_enable_mgcg(adev, true);
3658 gfx_v7_0_enable_cgcg(adev, true);
3659 } else {
3660 gfx_v7_0_enable_cgcg(adev, false);
3661 gfx_v7_0_enable_mgcg(adev, false);
3662 }
3663 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3664}
3665
3666static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3667 bool enable)
3668{
3669 u32 data, orig;
3670
3671 orig = data = RREG32(mmRLC_PG_CNTL);
3672 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
3673 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3674 else
3675 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3676 if (orig != data)
3677 WREG32(mmRLC_PG_CNTL, data);
3678}
3679
3680static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3681 bool enable)
3682{
3683 u32 data, orig;
3684
3685 orig = data = RREG32(mmRLC_PG_CNTL);
3686 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
3687 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3688 else
3689 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3690 if (orig != data)
3691 WREG32(mmRLC_PG_CNTL, data);
3692}
3693
3694static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3695{
3696 u32 data, orig;
3697
3698 orig = data = RREG32(mmRLC_PG_CNTL);
3699 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))
3700 data &= ~0x8000;
3701 else
3702 data |= 0x8000;
3703 if (orig != data)
3704 WREG32(mmRLC_PG_CNTL, data);
3705}
3706
3707static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3708{
3709 u32 data, orig;
3710
3711 orig = data = RREG32(mmRLC_PG_CNTL);
3712 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))
3713 data &= ~0x2000;
3714 else
3715 data |= 0x2000;
3716 if (orig != data)
3717 WREG32(mmRLC_PG_CNTL, data);
3718}
3719
3720static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3721{
3722 const __le32 *fw_data;
3723 volatile u32 *dst_ptr;
3724 int me, i, max_me = 4;
3725 u32 bo_offset = 0;
3726 u32 table_offset, table_size;
3727
3728 if (adev->asic_type == CHIP_KAVERI)
3729 max_me = 5;
3730
3731 if (adev->gfx.rlc.cp_table_ptr == NULL)
3732 return;
3733
3734 /* write the cp table buffer */
3735 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3736 for (me = 0; me < max_me; me++) {
3737 if (me == 0) {
3738 const struct gfx_firmware_header_v1_0 *hdr =
3739 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3740 fw_data = (const __le32 *)
3741 (adev->gfx.ce_fw->data +
3742 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3743 table_offset = le32_to_cpu(hdr->jt_offset);
3744 table_size = le32_to_cpu(hdr->jt_size);
3745 } else if (me == 1) {
3746 const struct gfx_firmware_header_v1_0 *hdr =
3747 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3748 fw_data = (const __le32 *)
3749 (adev->gfx.pfp_fw->data +
3750 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3751 table_offset = le32_to_cpu(hdr->jt_offset);
3752 table_size = le32_to_cpu(hdr->jt_size);
3753 } else if (me == 2) {
3754 const struct gfx_firmware_header_v1_0 *hdr =
3755 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3756 fw_data = (const __le32 *)
3757 (adev->gfx.me_fw->data +
3758 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3759 table_offset = le32_to_cpu(hdr->jt_offset);
3760 table_size = le32_to_cpu(hdr->jt_size);
3761 } else if (me == 3) {
3762 const struct gfx_firmware_header_v1_0 *hdr =
3763 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3764 fw_data = (const __le32 *)
3765 (adev->gfx.mec_fw->data +
3766 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3767 table_offset = le32_to_cpu(hdr->jt_offset);
3768 table_size = le32_to_cpu(hdr->jt_size);
3769 } else {
3770 const struct gfx_firmware_header_v1_0 *hdr =
3771 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3772 fw_data = (const __le32 *)
3773 (adev->gfx.mec2_fw->data +
3774 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3775 table_offset = le32_to_cpu(hdr->jt_offset);
3776 table_size = le32_to_cpu(hdr->jt_size);
3777 }
3778
3779 for (i = 0; i < table_size; i ++) {
3780 dst_ptr[bo_offset + i] =
3781 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3782 }
3783
3784 bo_offset += table_size;
3785 }
3786}
3787
3788static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3789 bool enable)
3790{
3791 u32 data, orig;
3792
3793 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {
3794 orig = data = RREG32(mmRLC_PG_CNTL);
3795 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3796 if (orig != data)
3797 WREG32(mmRLC_PG_CNTL, data);
3798
3799 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3800 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3801 if (orig != data)
3802 WREG32(mmRLC_AUTO_PG_CTRL, data);
3803 } else {
3804 orig = data = RREG32(mmRLC_PG_CNTL);
3805 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3806 if (orig != data)
3807 WREG32(mmRLC_PG_CNTL, data);
3808
3809 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3810 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3811 if (orig != data)
3812 WREG32(mmRLC_AUTO_PG_CTRL, data);
3813
3814 data = RREG32(mmDB_RENDER_CONTROL);
3815 }
3816}
3817
8f8e00c1 3818static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
a2e73f56 3819{
8f8e00c1 3820 u32 data, mask;
a2e73f56 3821
8f8e00c1
AD		 3822 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3823 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
a2e73f56 3824
8f8e00c1
AD		 3825 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3826 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
a2e73f56 3827
8f8e00c1
AD		 3828 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
3829 adev->gfx.config.max_sh_per_se);
a2e73f56 3830
8f8e00c1 3831 return (~data) & mask;
a2e73f56
AD		 3832}
3833
3834static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3835{
3836 uint32_t tmp, active_cu_number;
3837 struct amdgpu_cu_info cu_info;
3838
3839 gfx_v7_0_get_cu_info(adev, &cu_info);
3840 tmp = cu_info.ao_cu_mask;
3841 active_cu_number = cu_info.number;
3842
3843 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);
3844
3845 tmp = RREG32(mmRLC_MAX_PG_CU);
3846 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3847 tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3848 WREG32(mmRLC_MAX_PG_CU, tmp);
3849}
3850
3851static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3852 bool enable)
3853{
3854 u32 data, orig;
3855
3856 orig = data = RREG32(mmRLC_PG_CNTL);
3857 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))
3858 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3859 else
3860 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3861 if (orig != data)
3862 WREG32(mmRLC_PG_CNTL, data);
3863}
3864
3865static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3866 bool enable)
3867{
3868 u32 data, orig;
3869
3870 orig = data = RREG32(mmRLC_PG_CNTL);
3871 if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))
3872 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3873 else
3874 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3875 if (orig != data)
3876 WREG32(mmRLC_PG_CNTL, data);
3877}
3878
3879#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3880#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3881
3882static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3883{
3884 u32 data, orig;
3885 u32 i;
3886
3887 if (adev->gfx.rlc.cs_data) {
3888 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3889 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3890 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3891 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3892 } else {
3893 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3894 for (i = 0; i < 3; i++)
3895 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3896 }
3897 if (adev->gfx.rlc.reg_list) {
3898 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3899 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3900 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3901 }
3902
3903 orig = data = RREG32(mmRLC_PG_CNTL);
3904 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3905 if (orig != data)
3906 WREG32(mmRLC_PG_CNTL, data);
3907
3908 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3909 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3910
3911 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3912 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3913 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3914 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3915
3916 data = 0x10101010;
3917 WREG32(mmRLC_PG_DELAY, data);
3918
3919 data = RREG32(mmRLC_PG_DELAY_2);
3920 data &= ~0xff;
3921 data |= 0x3;
3922 WREG32(mmRLC_PG_DELAY_2, data);
3923
3924 data = RREG32(mmRLC_AUTO_PG_CTRL);
3925 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3926 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3927 WREG32(mmRLC_AUTO_PG_CTRL, data);
3928
3929}
3930
3931static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3932{
3933 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3934 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3935 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3936}
3937
3938static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3939{
3940 u32 count = 0;
3941 const struct cs_section_def *sect = NULL;
3942 const struct cs_extent_def *ext = NULL;
3943
3944 if (adev->gfx.rlc.cs_data == NULL)
3945 return 0;
3946
3947 /* begin clear state */
3948 count += 2;
3949 /* context control state */
3950 count += 3;
3951
3952 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3953 for (ext = sect->section; ext->extent != NULL; ++ext) {
3954 if (sect->id == SECT_CONTEXT)
3955 count += 2 + ext->reg_count;
3956 else
3957 return 0;
3958 }
3959 }
3960 /* pa_sc_raster_config/pa_sc_raster_config1 */
3961 count += 4;
3962 /* end clear state */
3963 count += 2;
3964 /* clear state */
3965 count += 2;
3966
3967 return count;
3968}
3969
3970static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
3971 volatile u32 *buffer)
3972{
3973 u32 count = 0, i;
3974 const struct cs_section_def *sect = NULL;
3975 const struct cs_extent_def *ext = NULL;
3976
3977 if (adev->gfx.rlc.cs_data == NULL)
3978 return;
3979 if (buffer == NULL)
3980 return;
3981
3982 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3983 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3984
3985 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3986 buffer[count++] = cpu_to_le32(0x80000000);
3987 buffer[count++] = cpu_to_le32(0x80000000);
3988
3989 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3990 for (ext = sect->section; ext->extent != NULL; ++ext) {
3991 if (sect->id == SECT_CONTEXT) {
3992 buffer[count++] =
3993 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3994 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3995 for (i = 0; i < ext->reg_count; i++)
3996 buffer[count++] = cpu_to_le32(ext->extent[i]);
3997 } else {
3998 return;
3999 }
4000 }
4001 }
4002
4003 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4004 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4005 switch (adev->asic_type) {
4006 case CHIP_BONAIRE:
4007 buffer[count++] = cpu_to_le32(0x16000012);
4008 buffer[count++] = cpu_to_le32(0x00000000);
4009 break;
4010 case CHIP_KAVERI:
4011 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4012 buffer[count++] = cpu_to_le32(0x00000000);
4013 break;
4014 case CHIP_KABINI:
4015 case CHIP_MULLINS:
4016 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4017 buffer[count++] = cpu_to_le32(0x00000000);
4018 break;
4019 case CHIP_HAWAII:
4020 buffer[count++] = cpu_to_le32(0x3a00161a);
4021 buffer[count++] = cpu_to_le32(0x0000002e);
4022 break;
4023 default:
4024 buffer[count++] = cpu_to_le32(0x00000000);
4025 buffer[count++] = cpu_to_le32(0x00000000);
4026 break;
4027 }
4028
4029 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4030 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4031
4032 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4033 buffer[count++] = cpu_to_le32(0);
4034}
4035
4036static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4037{
4038 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4039 AMDGPU_PG_SUPPORT_GFX_SMG |
4040 AMDGPU_PG_SUPPORT_GFX_DMG |
4041 AMDGPU_PG_SUPPORT_CP |
4042 AMDGPU_PG_SUPPORT_GDS |
4043 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4044 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4045 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4046 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4047 gfx_v7_0_init_gfx_cgpg(adev);
4048 gfx_v7_0_enable_cp_pg(adev, true);
4049 gfx_v7_0_enable_gds_pg(adev, true);
4050 }
4051 gfx_v7_0_init_ao_cu_mask(adev);
4052 gfx_v7_0_update_gfx_pg(adev, true);
4053 }
4054}
4055
4056static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4057{
4058 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4059 AMDGPU_PG_SUPPORT_GFX_SMG |
4060 AMDGPU_PG_SUPPORT_GFX_DMG |
4061 AMDGPU_PG_SUPPORT_CP |
4062 AMDGPU_PG_SUPPORT_GDS |
4063 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4064 gfx_v7_0_update_gfx_pg(adev, false);
4065 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4066 gfx_v7_0_enable_cp_pg(adev, false);
4067 gfx_v7_0_enable_gds_pg(adev, false);
4068 }
4069 }
4070}
4071
4072/**
4073 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4074 *
4075 * @adev: amdgpu_device pointer
4076 *
4077 * Fetches a GPU clock counter snapshot (SI).
4078 * Returns the 64 bit clock counter snapshot.
4079 */
4080uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4081{
4082 uint64_t clock;
4083
4084 mutex_lock(&adev->gfx.gpu_clock_mutex);
4085 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4086 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4087 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4088 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4089 return clock;
4090}
4091
4092static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4093 uint32_t vmid,
4094 uint32_t gds_base, uint32_t gds_size,
4095 uint32_t gws_base, uint32_t gws_size,
4096 uint32_t oa_base, uint32_t oa_size)
4097{
4098 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4099 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4100
4101 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4102 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4103
4104 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4105 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4106
4107 /* GDS Base */
4108 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4109 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4110 WRITE_DATA_DST_SEL(0)));
4111 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4112 amdgpu_ring_write(ring, 0);
4113 amdgpu_ring_write(ring, gds_base);
4114
4115 /* GDS Size */
4116 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4117 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4118 WRITE_DATA_DST_SEL(0)));
4119 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4120 amdgpu_ring_write(ring, 0);
4121 amdgpu_ring_write(ring, gds_size);
4122
4123 /* GWS */
4124 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4125 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4126 WRITE_DATA_DST_SEL(0)));
4127 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4128 amdgpu_ring_write(ring, 0);
4129 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4130
4131 /* OA */
4132 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4133 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4134 WRITE_DATA_DST_SEL(0)));
4135 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4136 amdgpu_ring_write(ring, 0);
4137 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4138}
4139
5fc3aeeb 4140static int gfx_v7_0_early_init(void *handle)
a2e73f56 4141{
5fc3aeeb 4142 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4143
4144 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4145 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4146 gfx_v7_0_set_ring_funcs(adev);
4147 gfx_v7_0_set_irq_funcs(adev);
4148 gfx_v7_0_set_gds_init(adev);
4149
4150 return 0;
4151}
4152
ef720532
AD		 4153static int gfx_v7_0_late_init(void *handle)
4154{
4155 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4156 int r;
4157
4158 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4159 if (r)
4160 return r;
4161
4162 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4163 if (r)
4164 return r;
4165
4166 return 0;
4167}
4168
d93f3ca7
AD		 4169static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4170{
4171 u32 gb_addr_config;
4172 u32 mc_shared_chmap, mc_arb_ramcfg;
4173 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4174 u32 tmp;
4175
4176 switch (adev->asic_type) {
4177 case CHIP_BONAIRE:
4178 adev->gfx.config.max_shader_engines = 2;
4179 adev->gfx.config.max_tile_pipes = 4;
4180 adev->gfx.config.max_cu_per_sh = 7;
4181 adev->gfx.config.max_sh_per_se = 1;
4182 adev->gfx.config.max_backends_per_se = 2;
4183 adev->gfx.config.max_texture_channel_caches = 4;
4184 adev->gfx.config.max_gprs = 256;
4185 adev->gfx.config.max_gs_threads = 32;
4186 adev->gfx.config.max_hw_contexts = 8;
4187
4188 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4189 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4190 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4191 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4192 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4193 break;
4194 case CHIP_HAWAII:
4195 adev->gfx.config.max_shader_engines = 4;
4196 adev->gfx.config.max_tile_pipes = 16;
4197 adev->gfx.config.max_cu_per_sh = 11;
4198 adev->gfx.config.max_sh_per_se = 1;
4199 adev->gfx.config.max_backends_per_se = 4;
4200 adev->gfx.config.max_texture_channel_caches = 16;
4201 adev->gfx.config.max_gprs = 256;
4202 adev->gfx.config.max_gs_threads = 32;
4203 adev->gfx.config.max_hw_contexts = 8;
4204
4205 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4206 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4207 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4208 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4209 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4210 break;
4211 case CHIP_KAVERI:
4212 adev->gfx.config.max_shader_engines = 1;
4213 adev->gfx.config.max_tile_pipes = 4;
4214 if ((adev->pdev->device == 0x1304) ||
4215 (adev->pdev->device == 0x1305) ||
4216 (adev->pdev->device == 0x130C) ||
4217 (adev->pdev->device == 0x130F) ||
4218 (adev->pdev->device == 0x1310) ||
4219 (adev->pdev->device == 0x1311) ||
4220 (adev->pdev->device == 0x131C)) {
4221 adev->gfx.config.max_cu_per_sh = 8;
4222 adev->gfx.config.max_backends_per_se = 2;
4223 } else if ((adev->pdev->device == 0x1309) ||
4224 (adev->pdev->device == 0x130A) ||
4225 (adev->pdev->device == 0x130D) ||
4226 (adev->pdev->device == 0x1313) ||
4227 (adev->pdev->device == 0x131D)) {
4228 adev->gfx.config.max_cu_per_sh = 6;
4229 adev->gfx.config.max_backends_per_se = 2;
4230 } else if ((adev->pdev->device == 0x1306) ||
4231 (adev->pdev->device == 0x1307) ||
4232 (adev->pdev->device == 0x130B) ||
4233 (adev->pdev->device == 0x130E) ||
4234 (adev->pdev->device == 0x1315) ||
4235 (adev->pdev->device == 0x131B)) {
4236 adev->gfx.config.max_cu_per_sh = 4;
4237 adev->gfx.config.max_backends_per_se = 1;
4238 } else {
4239 adev->gfx.config.max_cu_per_sh = 3;
4240 adev->gfx.config.max_backends_per_se = 1;
4241 }
4242 adev->gfx.config.max_sh_per_se = 1;
4243 adev->gfx.config.max_texture_channel_caches = 4;
4244 adev->gfx.config.max_gprs = 256;
4245 adev->gfx.config.max_gs_threads = 16;
4246 adev->gfx.config.max_hw_contexts = 8;
4247
4248 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4249 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4250 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4251 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4252 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4253 break;
4254 case CHIP_KABINI:
4255 case CHIP_MULLINS:
4256 default:
4257 adev->gfx.config.max_shader_engines = 1;
4258 adev->gfx.config.max_tile_pipes = 2;
4259 adev->gfx.config.max_cu_per_sh = 2;
4260 adev->gfx.config.max_sh_per_se = 1;
4261 adev->gfx.config.max_backends_per_se = 1;
4262 adev->gfx.config.max_texture_channel_caches = 2;
4263 adev->gfx.config.max_gprs = 256;
4264 adev->gfx.config.max_gs_threads = 16;
4265 adev->gfx.config.max_hw_contexts = 8;
4266
4267 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4268 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4269 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4270 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4271 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4272 break;
4273 }
4274
4275 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4276 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4277 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4278
4279 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4280 adev->gfx.config.mem_max_burst_length_bytes = 256;
4281 if (adev->flags & AMD_IS_APU) {
4282 /* Get memory bank mapping mode. */
4283 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4284 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4285 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4286
4287 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4288 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4289 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4290
4291 /* Validate settings in case only one DIMM installed. */
4292 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4293 dimm00_addr_map = 0;
4294 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4295 dimm01_addr_map = 0;
4296 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4297 dimm10_addr_map = 0;
4298 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4299 dimm11_addr_map = 0;
4300
4301 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4302 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4303 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4304 adev->gfx.config.mem_row_size_in_kb = 2;
4305 else
4306 adev->gfx.config.mem_row_size_in_kb = 1;
4307 } else {
4308 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4309 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4310 if (adev->gfx.config.mem_row_size_in_kb > 4)
4311 adev->gfx.config.mem_row_size_in_kb = 4;
4312 }
4313 /* XXX use MC settings? */
4314 adev->gfx.config.shader_engine_tile_size = 32;
4315 adev->gfx.config.num_gpus = 1;
4316 adev->gfx.config.multi_gpu_tile_size = 64;
4317
4318 /* fix up row size */
4319 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4320 switch (adev->gfx.config.mem_row_size_in_kb) {
4321 case 1:
4322 default:
4323 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4324 break;
4325 case 2:
4326 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4327 break;
4328 case 4:
4329 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4330 break;
4331 }
4332 adev->gfx.config.gb_addr_config = gb_addr_config;
4333}
4334
5fc3aeeb 4335static int gfx_v7_0_sw_init(void *handle)
a2e73f56
AD		 4336{
4337 struct amdgpu_ring *ring;
5fc3aeeb 4338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4339 int i, r;
4340
4341 /* EOP Event */
4342 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4343 if (r)
4344 return r;
4345
4346 /* Privileged reg */
4347 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4348 if (r)
4349 return r;
4350
4351 /* Privileged inst */
4352 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4353 if (r)
4354 return r;
4355
4356 gfx_v7_0_scratch_init(adev);
4357
4358 r = gfx_v7_0_init_microcode(adev);
4359 if (r) {
4360 DRM_ERROR("Failed to load gfx firmware!\n");
4361 return r;
4362 }
4363
4364 r = gfx_v7_0_rlc_init(adev);
4365 if (r) {
4366 DRM_ERROR("Failed to init rlc BOs!\n");
4367 return r;
4368 }
4369
4370 /* allocate mec buffers */
4371 r = gfx_v7_0_mec_init(adev);
4372 if (r) {
4373 DRM_ERROR("Failed to init MEC BOs!\n");
4374 return r;
4375 }
4376
a2e73f56
AD		 4377 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4378 ring = &adev->gfx.gfx_ring[i];
4379 ring->ring_obj = NULL;
4380 sprintf(ring->name, "gfx");
4381 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4382 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4383 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4384 AMDGPU_RING_TYPE_GFX);
4385 if (r)
4386 return r;
4387 }
4388
4389 /* set up the compute queues */
4390 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4391 unsigned irq_type;
4392
4393 /* max 32 queues per MEC */
4394 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4395 DRM_ERROR("Too many (%d) compute rings!\n", i);
4396 break;
4397 }
4398 ring = &adev->gfx.compute_ring[i];
4399 ring->ring_obj = NULL;
4400 ring->use_doorbell = true;
4401 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4402 ring->me = 1; /* first MEC */
4403 ring->pipe = i / 8;
4404 ring->queue = i % 8;
4405 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
4406 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4407 /* type-2 packets are deprecated on MEC, use type-3 instead */
4408 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4409 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4410 &adev->gfx.eop_irq, irq_type,
4411 AMDGPU_RING_TYPE_COMPUTE);
4412 if (r)
4413 return r;
4414 }
4415
4416 /* reserve GDS, GWS and OA resource for gfx */
4417 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4418 PAGE_SIZE, true,
4419 AMDGPU_GEM_DOMAIN_GDS, 0,
72d7668b 4420 NULL, NULL, &adev->gds.gds_gfx_bo);
a2e73f56
AD		 4421 if (r)
4422 return r;
4423
4424 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4425 PAGE_SIZE, true,
4426 AMDGPU_GEM_DOMAIN_GWS, 0,
72d7668b 4427 NULL, NULL, &adev->gds.gws_gfx_bo);
a2e73f56
AD		 4428 if (r)
4429 return r;
4430
4431 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4432 PAGE_SIZE, true,
4433 AMDGPU_GEM_DOMAIN_OA, 0,
72d7668b 4434 NULL, NULL, &adev->gds.oa_gfx_bo);
a2e73f56
AD		 4435 if (r)
4436 return r;
4437
d93f3ca7
AD		 4438 adev->gfx.ce_ram_size = 0x8000;
4439
4440 gfx_v7_0_gpu_early_init(adev);
4441
a2e73f56
AD		 4442 return r;
4443}
4444
5fc3aeeb 4445static int gfx_v7_0_sw_fini(void *handle)
a2e73f56
AD		 4446{
4447 int i;
5fc3aeeb 4448 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4449
4450 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4451 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4452 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4453
4454 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4455 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4456 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4457 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4458
a2e73f56
AD		 4459 gfx_v7_0_cp_compute_fini(adev);
4460 gfx_v7_0_rlc_fini(adev);
4461 gfx_v7_0_mec_fini(adev);
4462
4463 return 0;
4464}
4465
5fc3aeeb 4466static int gfx_v7_0_hw_init(void *handle)
a2e73f56
AD		 4467{
4468 int r;
5fc3aeeb 4469 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4470
4471 gfx_v7_0_gpu_init(adev);
4472
4473 /* init rlc */
4474 r = gfx_v7_0_rlc_resume(adev);
4475 if (r)
4476 return r;
4477
4478 r = gfx_v7_0_cp_resume(adev);
4479 if (r)
4480 return r;
4481
4482 return r;
4483}
4484
5fc3aeeb 4485static int gfx_v7_0_hw_fini(void *handle)
a2e73f56 4486{
5fc3aeeb 4487 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4488
ef720532
AD		 4489 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4490 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
a2e73f56
AD		 4491 gfx_v7_0_cp_enable(adev, false);
4492 gfx_v7_0_rlc_stop(adev);
4493 gfx_v7_0_fini_pg(adev);
4494
4495 return 0;
4496}
4497
5fc3aeeb 4498static int gfx_v7_0_suspend(void *handle)
a2e73f56 4499{
5fc3aeeb 4500 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4501
a2e73f56
AD		 4502 return gfx_v7_0_hw_fini(adev);
4503}
4504
5fc3aeeb 4505static int gfx_v7_0_resume(void *handle)
a2e73f56 4506{
5fc3aeeb 4507 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4508
a2e73f56
AD		 4509 return gfx_v7_0_hw_init(adev);
4510}
4511
5fc3aeeb 4512static bool gfx_v7_0_is_idle(void *handle)
a2e73f56 4513{
5fc3aeeb 4514 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4515
a2e73f56
AD		 4516 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4517 return false;
4518 else
4519 return true;
4520}
4521
5fc3aeeb 4522static int gfx_v7_0_wait_for_idle(void *handle)
a2e73f56
AD		 4523{
4524 unsigned i;
4525 u32 tmp;
5fc3aeeb 4526 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4527
4528 for (i = 0; i < adev->usec_timeout; i++) {
4529 /* read MC_STATUS */
4530 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4531
4532 if (!tmp)
4533 return 0;
4534 udelay(1);
4535 }
4536 return -ETIMEDOUT;
4537}
4538
5fc3aeeb 4539static void gfx_v7_0_print_status(void *handle)
a2e73f56
AD		 4540{
4541 int i;
5fc3aeeb 4542 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4543
4544 dev_info(adev->dev, "GFX 7.x registers\n");
4545 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
4546 RREG32(mmGRBM_STATUS));
4547 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
4548 RREG32(mmGRBM_STATUS2));
4549 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4550 RREG32(mmGRBM_STATUS_SE0));
4551 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4552 RREG32(mmGRBM_STATUS_SE1));
4553 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4554 RREG32(mmGRBM_STATUS_SE2));
4555 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4556 RREG32(mmGRBM_STATUS_SE3));
4557 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4558 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4559 RREG32(mmCP_STALLED_STAT1));
4560 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4561 RREG32(mmCP_STALLED_STAT2));
4562 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4563 RREG32(mmCP_STALLED_STAT3));
4564 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4565 RREG32(mmCP_CPF_BUSY_STAT));
4566 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4567 RREG32(mmCP_CPF_STALLED_STAT1));
4568 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4569 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4570 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4571 RREG32(mmCP_CPC_STALLED_STAT1));
4572 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4573
4574 for (i = 0; i < 32; i++) {
4575 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
4576 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4577 }
4578 for (i = 0; i < 16; i++) {
4579 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
4580 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4581 }
4582 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4583 dev_info(adev->dev, " se: %d\n", i);
4584 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
4585 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
4586 RREG32(mmPA_SC_RASTER_CONFIG));
4587 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
4588 RREG32(mmPA_SC_RASTER_CONFIG_1));
4589 }
4590 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4591
4592 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
4593 RREG32(mmGB_ADDR_CONFIG));
4594 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
4595 RREG32(mmHDP_ADDR_CONFIG));
4596 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
4597 RREG32(mmDMIF_ADDR_CALC));
a2e73f56
AD		 4598
4599 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
4600 RREG32(mmCP_MEQ_THRESHOLDS));
4601 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
4602 RREG32(mmSX_DEBUG_1));
4603 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
4604 RREG32(mmTA_CNTL_AUX));
4605 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
4606 RREG32(mmSPI_CONFIG_CNTL));
4607 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
4608 RREG32(mmSQ_CONFIG));
4609 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
4610 RREG32(mmDB_DEBUG));
4611 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
4612 RREG32(mmDB_DEBUG2));
4613 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
4614 RREG32(mmDB_DEBUG3));
4615 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
4616 RREG32(mmCB_HW_CONTROL));
4617 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
4618 RREG32(mmSPI_CONFIG_CNTL_1));
4619 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
4620 RREG32(mmPA_SC_FIFO_SIZE));
4621 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
4622 RREG32(mmVGT_NUM_INSTANCES));
4623 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
4624 RREG32(mmCP_PERFMON_CNTL));
4625 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4626 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4627 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
4628 RREG32(mmVGT_CACHE_INVALIDATION));
4629 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
4630 RREG32(mmVGT_GS_VERTEX_REUSE));
4631 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4632 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4633 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
4634 RREG32(mmPA_CL_ENHANCE));
4635 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
4636 RREG32(mmPA_SC_ENHANCE));
4637
4638 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
4639 RREG32(mmCP_ME_CNTL));
4640 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
4641 RREG32(mmCP_MAX_CONTEXT));
4642 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
4643 RREG32(mmCP_ENDIAN_SWAP));
4644 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
4645 RREG32(mmCP_DEVICE_ID));
4646
4647 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
4648 RREG32(mmCP_SEM_WAIT_TIMER));
4649 if (adev->asic_type != CHIP_HAWAII)
4650 dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
4651 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
4652
4653 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
4654 RREG32(mmCP_RB_WPTR_DELAY));
4655 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
4656 RREG32(mmCP_RB_VMID));
4657 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4658 RREG32(mmCP_RB0_CNTL));
4659 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
4660 RREG32(mmCP_RB0_WPTR));
4661 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
4662 RREG32(mmCP_RB0_RPTR_ADDR));
4663 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4664 RREG32(mmCP_RB0_RPTR_ADDR_HI));
4665 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4666 RREG32(mmCP_RB0_CNTL));
4667 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
4668 RREG32(mmCP_RB0_BASE));
4669 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
4670 RREG32(mmCP_RB0_BASE_HI));
4671 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
4672 RREG32(mmCP_MEC_CNTL));
4673 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
4674 RREG32(mmCP_CPF_DEBUG));
4675
4676 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
4677 RREG32(mmSCRATCH_ADDR));
4678 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
4679 RREG32(mmSCRATCH_UMSK));
4680
4681 /* init the pipes */
4682 mutex_lock(&adev->srbm_mutex);
4683 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
4684 int me = (i < 4) ? 1 : 2;
4685 int pipe = (i < 4) ? i : (i - 4);
4686 int queue;
4687
4688 dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe);
4689 cik_srbm_select(adev, me, pipe, 0, 0);
4690 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n",
4691 RREG32(mmCP_HPD_EOP_BASE_ADDR));
4692 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
4693 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
4694 dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n",
4695 RREG32(mmCP_HPD_EOP_VMID));
4696 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n",
4697 RREG32(mmCP_HPD_EOP_CONTROL));
4698
0fd64291 4699 for (queue = 0; queue < 8; queue++) {
a2e73f56
AD		 4700 cik_srbm_select(adev, me, pipe, queue, 0);
4701 dev_info(adev->dev, " queue: %d\n", queue);
4702 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
4703 RREG32(mmCP_PQ_WPTR_POLL_CNTL));
4704 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
4705 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
4706 dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n",
4707 RREG32(mmCP_HQD_ACTIVE));
4708 dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
4709 RREG32(mmCP_HQD_DEQUEUE_REQUEST));
4710 dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n",
4711 RREG32(mmCP_HQD_PQ_RPTR));
4712 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
4713 RREG32(mmCP_HQD_PQ_WPTR));
4714 dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n",
4715 RREG32(mmCP_HQD_PQ_BASE));
4716 dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n",
4717 RREG32(mmCP_HQD_PQ_BASE_HI));
4718 dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n",
4719 RREG32(mmCP_HQD_PQ_CONTROL));
4720 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
4721 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
4722 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
4723 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
4724 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
4725 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
4726 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
4727 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
4728 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
4729 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
4730 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
4731 RREG32(mmCP_HQD_PQ_WPTR));
4732 dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n",
4733 RREG32(mmCP_HQD_VMID));
4734 dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n",
4735 RREG32(mmCP_MQD_BASE_ADDR));
4736 dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n",
4737 RREG32(mmCP_MQD_BASE_ADDR_HI));
4738 dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n",
4739 RREG32(mmCP_MQD_CONTROL));
4740 }
4741 }
4742 cik_srbm_select(adev, 0, 0, 0, 0);
4743 mutex_unlock(&adev->srbm_mutex);
4744
4745 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
4746 RREG32(mmCP_INT_CNTL_RING0));
4747 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4748 RREG32(mmRLC_LB_CNTL));
4749 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
4750 RREG32(mmRLC_CNTL));
4751 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
4752 RREG32(mmRLC_CGCG_CGLS_CTRL));
4753 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
4754 RREG32(mmRLC_LB_CNTR_INIT));
4755 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
4756 RREG32(mmRLC_LB_CNTR_MAX));
4757 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
4758 RREG32(mmRLC_LB_INIT_CU_MASK));
4759 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
4760 RREG32(mmRLC_LB_PARAMS));
4761 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4762 RREG32(mmRLC_LB_CNTL));
4763 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
4764 RREG32(mmRLC_MC_CNTL));
4765 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
4766 RREG32(mmRLC_UCODE_CNTL));
4767
4768 if (adev->asic_type == CHIP_BONAIRE)
4769 dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
4770 RREG32(mmRLC_DRIVER_CPDMA_STATUS));
4771
4772 mutex_lock(&adev->srbm_mutex);
4773 for (i = 0; i < 16; i++) {
4774 cik_srbm_select(adev, 0, 0, 0, i);
4775 dev_info(adev->dev, " VM %d:\n", i);
4776 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
4777 RREG32(mmSH_MEM_CONFIG));
4778 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
4779 RREG32(mmSH_MEM_APE1_BASE));
4780 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
4781 RREG32(mmSH_MEM_APE1_LIMIT));
4782 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
4783 RREG32(mmSH_MEM_BASES));
4784 }
4785 cik_srbm_select(adev, 0, 0, 0, 0);
4786 mutex_unlock(&adev->srbm_mutex);
4787}
4788
5fc3aeeb 4789static int gfx_v7_0_soft_reset(void *handle)
a2e73f56
AD		 4790{
4791 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4792 u32 tmp;
5fc3aeeb 4793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56
AD		 4794
4795 /* GRBM_STATUS */
4796 tmp = RREG32(mmGRBM_STATUS);
4797 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4798 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4799 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4800 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4801 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4802 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4803 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4804 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4805
4806 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4807 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4808 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4809 }
4810
4811 /* GRBM_STATUS2 */
4812 tmp = RREG32(mmGRBM_STATUS2);
4813 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4814 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4815
4816 /* SRBM_STATUS */
4817 tmp = RREG32(mmSRBM_STATUS);
4818 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4819 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4820
4821 if (grbm_soft_reset || srbm_soft_reset) {
5fc3aeeb 4822 gfx_v7_0_print_status((void *)adev);
a2e73f56
AD		 4823 /* disable CG/PG */
4824 gfx_v7_0_fini_pg(adev);
4825 gfx_v7_0_update_cg(adev, false);
4826
4827 /* stop the rlc */
4828 gfx_v7_0_rlc_stop(adev);
4829
4830 /* Disable GFX parsing/prefetching */
4831 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4832
4833 /* Disable MEC parsing/prefetching */
4834 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4835
4836 if (grbm_soft_reset) {
4837 tmp = RREG32(mmGRBM_SOFT_RESET);
4838 tmp |= grbm_soft_reset;
4839 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4840 WREG32(mmGRBM_SOFT_RESET, tmp);
4841 tmp = RREG32(mmGRBM_SOFT_RESET);
4842
4843 udelay(50);
4844
4845 tmp &= ~grbm_soft_reset;
4846 WREG32(mmGRBM_SOFT_RESET, tmp);
4847 tmp = RREG32(mmGRBM_SOFT_RESET);
4848 }
4849
4850 if (srbm_soft_reset) {
4851 tmp = RREG32(mmSRBM_SOFT_RESET);
4852 tmp |= srbm_soft_reset;
4853 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4854 WREG32(mmSRBM_SOFT_RESET, tmp);
4855 tmp = RREG32(mmSRBM_SOFT_RESET);
4856
4857 udelay(50);
4858
4859 tmp &= ~srbm_soft_reset;
4860 WREG32(mmSRBM_SOFT_RESET, tmp);
4861 tmp = RREG32(mmSRBM_SOFT_RESET);
4862 }
4863 /* Wait a little for things to settle down */
4864 udelay(50);
5fc3aeeb 4865 gfx_v7_0_print_status((void *)adev);
a2e73f56
AD		 4866 }
4867 return 0;
4868}
4869
4870static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4871 enum amdgpu_interrupt_state state)
4872{
4873 u32 cp_int_cntl;
4874
4875 switch (state) {
4876 case AMDGPU_IRQ_STATE_DISABLE:
4877 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4878 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4879 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4880 break;
4881 case AMDGPU_IRQ_STATE_ENABLE:
4882 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4883 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4884 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4885 break;
4886 default:
4887 break;
4888 }
4889}
4890
4891static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4892 int me, int pipe,
4893 enum amdgpu_interrupt_state state)
4894{
4895 u32 mec_int_cntl, mec_int_cntl_reg;
4896
4897 /*
4898 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4899 * handles the setting of interrupts for this specific pipe. All other
4900 * pipes' interrupts are set by amdkfd.
4901 */
4902
4903 if (me == 1) {
4904 switch (pipe) {
4905 case 0:
4906 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4907 break;
4908 default:
4909 DRM_DEBUG("invalid pipe %d\n", pipe);
4910 return;
4911 }
4912 } else {
4913 DRM_DEBUG("invalid me %d\n", me);
4914 return;
4915 }
4916
4917 switch (state) {
4918 case AMDGPU_IRQ_STATE_DISABLE:
4919 mec_int_cntl = RREG32(mec_int_cntl_reg);
4920 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4921 WREG32(mec_int_cntl_reg, mec_int_cntl);
4922 break;
4923 case AMDGPU_IRQ_STATE_ENABLE:
4924 mec_int_cntl = RREG32(mec_int_cntl_reg);
4925 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4926 WREG32(mec_int_cntl_reg, mec_int_cntl);
4927 break;
4928 default:
4929 break;
4930 }
4931}
4932
4933static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4934 struct amdgpu_irq_src *src,
4935 unsigned type,
4936 enum amdgpu_interrupt_state state)
4937{
4938 u32 cp_int_cntl;
4939
4940 switch (state) {
4941 case AMDGPU_IRQ_STATE_DISABLE:
4942 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4943 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4944 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4945 break;
4946 case AMDGPU_IRQ_STATE_ENABLE:
4947 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4948 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4949 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4950 break;
4951 default:
4952 break;
4953 }
4954
4955 return 0;
4956}
4957
4958static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4959 struct amdgpu_irq_src *src,
4960 unsigned type,
4961 enum amdgpu_interrupt_state state)
4962{
4963 u32 cp_int_cntl;
4964
4965 switch (state) {
4966 case AMDGPU_IRQ_STATE_DISABLE:
4967 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4968 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4969 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4970 break;
4971 case AMDGPU_IRQ_STATE_ENABLE:
4972 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4973 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4974 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4975 break;
4976 default:
4977 break;
4978 }
4979
4980 return 0;
4981}
4982
4983static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4984 struct amdgpu_irq_src *src,
4985 unsigned type,
4986 enum amdgpu_interrupt_state state)
4987{
4988 switch (type) {
4989 case AMDGPU_CP_IRQ_GFX_EOP:
4990 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4991 break;
4992 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4993 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4994 break;
4995 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4996 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4997 break;
4998 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4999 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5000 break;
5001 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5002 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5003 break;
5004 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5005 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5006 break;
5007 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5008 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5009 break;
5010 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5011 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5012 break;
5013 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5014 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5015 break;
5016 default:
5017 break;
5018 }
5019 return 0;
5020}
5021
5022static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5023 struct amdgpu_irq_src *source,
5024 struct amdgpu_iv_entry *entry)
5025{
5026 u8 me_id, pipe_id;
5027 struct amdgpu_ring *ring;
5028 int i;
5029
5030 DRM_DEBUG("IH: CP EOP\n");
5031 me_id = (entry->ring_id & 0x0c) >> 2;
5032 pipe_id = (entry->ring_id & 0x03) >> 0;
5033 switch (me_id) {
5034 case 0:
5035 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5036 break;
5037 case 1:
5038 case 2:
5039 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5040 ring = &adev->gfx.compute_ring[i];
5041 if ((ring->me == me_id) & (ring->pipe == pipe_id))
5042 amdgpu_fence_process(ring);
5043 }
5044 break;
5045 }
5046 return 0;
5047}
5048
5049static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5050 struct amdgpu_irq_src *source,
5051 struct amdgpu_iv_entry *entry)
5052{
5053 DRM_ERROR("Illegal register access in command stream\n");
5054 schedule_work(&adev->reset_work);
5055 return 0;
5056}
5057
5058static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5059 struct amdgpu_irq_src *source,
5060 struct amdgpu_iv_entry *entry)
5061{
5062 DRM_ERROR("Illegal instruction in command stream\n");
5063 // XXX soft reset the gfx block only
5064 schedule_work(&adev->reset_work);
5065 return 0;
5066}
5067
5fc3aeeb 5068static int gfx_v7_0_set_clockgating_state(void *handle,
5069 enum amd_clockgating_state state)
a2e73f56
AD		 5070{
5071 bool gate = false;
5fc3aeeb 5072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5073
5fc3aeeb 5074 if (state == AMD_CG_STATE_GATE)
a2e73f56
AD		 5075 gate = true;
5076
5077 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5078 /* order matters! */
5079 if (gate) {
5080 gfx_v7_0_enable_mgcg(adev, true);
5081 gfx_v7_0_enable_cgcg(adev, true);
5082 } else {
5083 gfx_v7_0_enable_cgcg(adev, false);
5084 gfx_v7_0_enable_mgcg(adev, false);
5085 }
5086 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5087
5088 return 0;
5089}
5090
5fc3aeeb 5091static int gfx_v7_0_set_powergating_state(void *handle,
5092 enum amd_powergating_state state)
a2e73f56
AD		 5093{
5094 bool gate = false;
5fc3aeeb 5095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
a2e73f56 5096
5fc3aeeb 5097 if (state == AMD_PG_STATE_GATE)
a2e73f56
AD		 5098 gate = true;
5099
5100 if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
5101 AMDGPU_PG_SUPPORT_GFX_SMG |
5102 AMDGPU_PG_SUPPORT_GFX_DMG |
5103 AMDGPU_PG_SUPPORT_CP |
5104 AMDGPU_PG_SUPPORT_GDS |
5105 AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
5106 gfx_v7_0_update_gfx_pg(adev, gate);
5107 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
5108 gfx_v7_0_enable_cp_pg(adev, gate);
5109 gfx_v7_0_enable_gds_pg(adev, gate);
5110 }
5111 }
5112
5113 return 0;
5114}
5115
5fc3aeeb 5116const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
a2e73f56 5117 .early_init = gfx_v7_0_early_init,
ef720532 5118 .late_init = gfx_v7_0_late_init,
a2e73f56
AD		 5119 .sw_init = gfx_v7_0_sw_init,
5120 .sw_fini = gfx_v7_0_sw_fini,
5121 .hw_init = gfx_v7_0_hw_init,
5122 .hw_fini = gfx_v7_0_hw_fini,
5123 .suspend = gfx_v7_0_suspend,
5124 .resume = gfx_v7_0_resume,
5125 .is_idle = gfx_v7_0_is_idle,
5126 .wait_for_idle = gfx_v7_0_wait_for_idle,
5127 .soft_reset = gfx_v7_0_soft_reset,
5128 .print_status = gfx_v7_0_print_status,
5129 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5130 .set_powergating_state = gfx_v7_0_set_powergating_state,
5131};
5132
a2e73f56
AD		 5133static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5134 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
5135 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5136 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5137 .parse_cs = NULL,
93323131 5138 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
a2e73f56 5139 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
a2e73f56
AD		 5140 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5141 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d2edb07b 5142 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
a2e73f56
AD		 5143 .test_ring = gfx_v7_0_ring_test_ring,
5144 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5145 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5146 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5147};
5148
5149static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5150 .get_rptr = gfx_v7_0_ring_get_rptr_compute,
5151 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5152 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5153 .parse_cs = NULL,
93323131 5154 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
a2e73f56 5155 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
a2e73f56
AD		 5156 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5157 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
d9b5327a 5158 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
a2e73f56
AD		 5159 .test_ring = gfx_v7_0_ring_test_ring,
5160 .test_ib = gfx_v7_0_ring_test_ib,
edff0e28 5161 .insert_nop = amdgpu_ring_insert_nop,
9e5d5309 5162 .pad_ib = amdgpu_ring_generic_pad_ib,
a2e73f56
AD		 5163};
5164
5165static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5166{
5167 int i;
5168
5169 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5170 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5171 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5172 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5173}
5174
5175static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5176 .set = gfx_v7_0_set_eop_interrupt_state,
5177 .process = gfx_v7_0_eop_irq,
5178};
5179
5180static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5181 .set = gfx_v7_0_set_priv_reg_fault_state,
5182 .process = gfx_v7_0_priv_reg_irq,
5183};
5184
5185static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5186 .set = gfx_v7_0_set_priv_inst_fault_state,
5187 .process = gfx_v7_0_priv_inst_irq,
5188};
5189
5190static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5191{
5192 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5193 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5194
5195 adev->gfx.priv_reg_irq.num_types = 1;
5196 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5197
5198 adev->gfx.priv_inst_irq.num_types = 1;
5199 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5200}
5201
5202static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5203{
5204 /* init asci gds info */
5205 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5206 adev->gds.gws.total_size = 64;
5207 adev->gds.oa.total_size = 16;
5208
5209 if (adev->gds.mem.total_size == 64 * 1024) {
5210 adev->gds.mem.gfx_partition_size = 4096;
5211 adev->gds.mem.cs_partition_size = 4096;
5212
5213 adev->gds.gws.gfx_partition_size = 4;
5214 adev->gds.gws.cs_partition_size = 4;
5215
5216 adev->gds.oa.gfx_partition_size = 4;
5217 adev->gds.oa.cs_partition_size = 1;
5218 } else {
5219 adev->gds.mem.gfx_partition_size = 1024;
5220 adev->gds.mem.cs_partition_size = 1024;
5221
5222 adev->gds.gws.gfx_partition_size = 16;
5223 adev->gds.gws.cs_partition_size = 16;
5224
5225 adev->gds.oa.gfx_partition_size = 4;
5226 adev->gds.oa.cs_partition_size = 4;
5227 }
5228}
5229
5230
5231int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
5cb60bf6 5232 struct amdgpu_cu_info *cu_info)
a2e73f56
AD		 5233{
5234 int i, j, k, counter, active_cu_number = 0;
5235 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5236
5237 if (!adev || !cu_info)
5238 return -EINVAL;
5239
5240 mutex_lock(&adev->grbm_idx_mutex);
5241 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5242 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5243 mask = 1;
5244 ao_bitmap = 0;
5245 counter = 0;
8f8e00c1
AD		 5246 gfx_v7_0_select_se_sh(adev, i, j);
5247 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
a2e73f56
AD		 5248 cu_info->bitmap[i][j] = bitmap;
5249
8f8e00c1 5250 for (k = 0; k < 16; k ++) {
a2e73f56
AD		 5251 if (bitmap & mask) {
5252 if (counter < 2)
5253 ao_bitmap |= mask;
5254 counter ++;
5255 }
5256 mask <<= 1;
5257 }
5258 active_cu_number += counter;
5259 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5260 }
5261 }
8f8e00c1
AD		 5262 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5263 mutex_unlock(&adev->grbm_idx_mutex);
a2e73f56
AD		 5264
5265 cu_info->number = active_cu_number;
5266 cu_info->ao_cu_mask = ao_cu_mask;
8f8e00c1 5267
a2e73f56
AD		 5268 return 0;
5269}
Linux kernel - Deliverables
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