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drm/amdgpu: use kernel fence for sdma ib test
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_gfx.h"
27#include "vi.h"
28#include "vid.h"
29#include "amdgpu_ucode.h"
30#include "clearstate_vi.h"
31
32#include "gmc/gmc_8_2_d.h"
33#include "gmc/gmc_8_2_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44#include "gca/gfx_8_0_enum.h"
45
46#include "uvd/uvd_5_0_d.h"
47#include "uvd/uvd_5_0_sh_mask.h"
48
49#include "dce/dce_10_0_d.h"
50#include "dce/dce_10_0_sh_mask.h"
51
52#define GFX8_NUM_GFX_RINGS 1
53#define GFX8_NUM_COMPUTE_RINGS 8
54
55#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
56#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
57#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
58
59#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
60#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
61#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
62#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
63#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
64#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
65#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
66#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
67#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
68
c65444fe
JZ		 69MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
70MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
71MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
72MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
73MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
74MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
75
76MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
77MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
78MODULE_FIRMWARE("amdgpu/tonga_me.bin");
79MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
80MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
81MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
82
83MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
84MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
85MODULE_FIRMWARE("amdgpu/topaz_me.bin");
86MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
87MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
88MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
aaa36a97 89
af15a2d5
DZ		 90MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
91MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
92MODULE_FIRMWARE("amdgpu/fiji_me.bin");
93MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
94MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
95MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
96
aaa36a97
AD		 97static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
98{
99 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
100 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
101 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
102 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
103 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
104 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
105 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
106 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
107 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
108 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
109 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
110 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
111 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
112 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
113 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
114 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
115};
116
117static const u32 golden_settings_tonga_a11[] =
118{
119 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
120 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
121 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
122 mmGB_GPU_ID, 0x0000000f, 0x00000000,
123 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
124 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
125 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 126 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 127 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
128 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 129 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 130 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
131 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
132 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
6a00a09e 133 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
aaa36a97
AD		 134};
135
136static const u32 tonga_golden_common_all[] =
137{
138 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
139 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
140 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
141 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
142 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
143 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
144 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
145 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
146};
147
148static const u32 tonga_mgcg_cgcg_init[] =
149{
150 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
151 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
152 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
153 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
154 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
155 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
156 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
157 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
158 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
159 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
160 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
161 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
162 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
163 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
164 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
165 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
166 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
167 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
168 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
169 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
170 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
171 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
172 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
173 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
174 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
175 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
176 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
177 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
178 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
179 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
180 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
181 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
182 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
183 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
184 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
185 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
186 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
187 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
188 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
189 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
190 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
191 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
192 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
193 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
194 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
195 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
196 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
197 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
198 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
199 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
200 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
201 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
202 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
203 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
204 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
205 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
206 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
207 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
208 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
209 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
210 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
211 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
212 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
213 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
214 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
215 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
216 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
217 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
218 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
219 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
220 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
221 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
222 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
223 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
224 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
225};
226
af15a2d5
DZ		 227static const u32 fiji_golden_common_all[] =
228{
229 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
230 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
231 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
232 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
233 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
234 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
235 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
236 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
237};
238
239static const u32 golden_settings_fiji_a10[] =
240{
241 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
242 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
243 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
244 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
245 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
246 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
247 mmTCC_CTRL, 0x00100000, 0xf30fff7f,
248 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
249 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
250 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
251};
252
253static const u32 fiji_mgcg_cgcg_init[] =
254{
255 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
256 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
257 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
258 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
259 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
260 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
261 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
262 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
263 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
264 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
265 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
266 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
267 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
268 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
269 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
270 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
271 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
272 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
273 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
274 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
275 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
276 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
277 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
278 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
279 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
280 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
281 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
282 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
283 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
284 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
285 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
286 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
287 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
288 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
289 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
290};
291
aaa36a97
AD		 292static const u32 golden_settings_iceland_a11[] =
293{
294 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
295 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
296 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
297 mmGB_GPU_ID, 0x0000000f, 0x00000000,
298 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
299 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
300 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
301 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
6a00a09e 302 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97
AD		 303 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
304 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
6a00a09e 305 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 306 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
307 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
308 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
309};
310
311static const u32 iceland_golden_common_all[] =
312{
313 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
314 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
315 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
316 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
317 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
318 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
319 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
320 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
321};
322
323static const u32 iceland_mgcg_cgcg_init[] =
324{
325 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
326 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
327 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
328 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
329 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
330 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
331 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
332 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
333 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
334 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
335 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
336 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
337 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
338 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
339 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
340 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
341 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
342 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
343 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
344 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
345 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
346 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
347 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
348 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
349 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
350 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
351 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
352 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
353 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
354 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
355 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
356 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
357 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
358 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
359 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
360 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
361 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
362 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
363 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
364 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
365 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
366 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
367 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
368 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
369 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
370 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
371 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
372 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
373 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
374 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
375 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
376 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
377 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
378 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
379 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
380 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
381 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
382 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
383 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
384 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
385 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
386 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
387 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
388 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
389};
390
391static const u32 cz_golden_settings_a11[] =
392{
393 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
394 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
395 mmGB_GPU_ID, 0x0000000f, 0x00000000,
396 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
397 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
6a00a09e 398 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
aaa36a97 399 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
6a00a09e 400 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
aaa36a97
AD		 401 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
402 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
403};
404
405static const u32 cz_golden_common_all[] =
406{
407 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
408 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
409 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
410 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
411 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
412 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
413 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
414 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
415};
416
417static const u32 cz_mgcg_cgcg_init[] =
418{
419 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
420 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
421 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
422 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
423 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
424 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
425 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
426 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
427 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
428 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
429 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
430 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
431 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
432 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
433 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
434 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
435 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
436 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
437 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
438 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
439 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
440 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
441 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
444 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
445 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
446 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
447 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
448 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
449 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
450 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
451 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
452 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
453 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
454 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
455 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
456 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
457 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
458 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
459 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
460 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
461 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
462 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
463 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
464 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
465 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
466 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
467 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
468 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
469 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
470 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
471 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
472 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
473 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
474 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
475 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
476 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
477 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
478 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
479 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
480 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
481 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
482 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
483 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
484 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
485 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
486 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
487 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
488 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
489 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
490 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
491 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
492 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
493 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
494};
495
496static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
497static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
498static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
499
500static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
501{
502 switch (adev->asic_type) {
503 case CHIP_TOPAZ:
504 amdgpu_program_register_sequence(adev,
505 iceland_mgcg_cgcg_init,
506 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
507 amdgpu_program_register_sequence(adev,
508 golden_settings_iceland_a11,
509 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
510 amdgpu_program_register_sequence(adev,
511 iceland_golden_common_all,
512 (const u32)ARRAY_SIZE(iceland_golden_common_all));
513 break;
af15a2d5
DZ		 514 case CHIP_FIJI:
515 amdgpu_program_register_sequence(adev,
516 fiji_mgcg_cgcg_init,
517 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
518 amdgpu_program_register_sequence(adev,
519 golden_settings_fiji_a10,
520 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
521 amdgpu_program_register_sequence(adev,
522 fiji_golden_common_all,
523 (const u32)ARRAY_SIZE(fiji_golden_common_all));
524 break;
525
aaa36a97
AD		 526 case CHIP_TONGA:
527 amdgpu_program_register_sequence(adev,
528 tonga_mgcg_cgcg_init,
529 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
530 amdgpu_program_register_sequence(adev,
531 golden_settings_tonga_a11,
532 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
533 amdgpu_program_register_sequence(adev,
534 tonga_golden_common_all,
535 (const u32)ARRAY_SIZE(tonga_golden_common_all));
536 break;
537 case CHIP_CARRIZO:
538 amdgpu_program_register_sequence(adev,
539 cz_mgcg_cgcg_init,
540 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
541 amdgpu_program_register_sequence(adev,
542 cz_golden_settings_a11,
543 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
544 amdgpu_program_register_sequence(adev,
545 cz_golden_common_all,
546 (const u32)ARRAY_SIZE(cz_golden_common_all));
547 break;
548 default:
549 break;
550 }
551}
552
553static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
554{
555 int i;
556
557 adev->gfx.scratch.num_reg = 7;
558 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
559 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
560 adev->gfx.scratch.free[i] = true;
561 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
562 }
563}
564
565static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
566{
567 struct amdgpu_device *adev = ring->adev;
568 uint32_t scratch;
569 uint32_t tmp = 0;
570 unsigned i;
571 int r;
572
573 r = amdgpu_gfx_scratch_get(adev, &scratch);
574 if (r) {
575 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
576 return r;
577 }
578 WREG32(scratch, 0xCAFEDEAD);
579 r = amdgpu_ring_lock(ring, 3);
580 if (r) {
581 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
582 ring->idx, r);
583 amdgpu_gfx_scratch_free(adev, scratch);
584 return r;
585 }
586 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
587 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
588 amdgpu_ring_write(ring, 0xDEADBEEF);
589 amdgpu_ring_unlock_commit(ring);
590
591 for (i = 0; i < adev->usec_timeout; i++) {
592 tmp = RREG32(scratch);
593 if (tmp == 0xDEADBEEF)
594 break;
595 DRM_UDELAY(1);
596 }
597 if (i < adev->usec_timeout) {
598 DRM_INFO("ring test on %d succeeded in %d usecs\n",
599 ring->idx, i);
600 } else {
601 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
602 ring->idx, scratch, tmp);
603 r = -EINVAL;
604 }
605 amdgpu_gfx_scratch_free(adev, scratch);
606 return r;
607}
608
609static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
610{
611 struct amdgpu_device *adev = ring->adev;
612 struct amdgpu_ib ib;
613 uint32_t scratch;
614 uint32_t tmp = 0;
615 unsigned i;
616 int r;
617
618 r = amdgpu_gfx_scratch_get(adev, &scratch);
619 if (r) {
620 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
621 return r;
622 }
623 WREG32(scratch, 0xCAFEDEAD);
624 r = amdgpu_ib_get(ring, NULL, 256, &ib);
625 if (r) {
626 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
42d13693 627 goto err1;
aaa36a97
AD		 628 }
629 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
630 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
631 ib.ptr[2] = 0xDEADBEEF;
632 ib.length_dw = 3;
42d13693
CZ		 633
634 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
635 AMDGPU_FENCE_OWNER_UNDEFINED);
636 if (r)
637 goto err2;
638
ab3cb0ce 639 r = fence_wait(&ib.fence->base, false);
aaa36a97
AD		 640 if (r) {
641 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
42d13693 642 goto err2;
aaa36a97
AD		 643 }
644 for (i = 0; i < adev->usec_timeout; i++) {
645 tmp = RREG32(scratch);
646 if (tmp == 0xDEADBEEF)
647 break;
648 DRM_UDELAY(1);
649 }
650 if (i < adev->usec_timeout) {
651 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
42d13693
CZ		 652 ring->idx, i);
653 goto err2;
aaa36a97
AD		 654 } else {
655 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
656 scratch, tmp);
657 r = -EINVAL;
658 }
42d13693 659err2:
aaa36a97 660 amdgpu_ib_free(adev, &ib);
42d13693
CZ		 661err1:
662 amdgpu_gfx_scratch_free(adev, scratch);
aaa36a97
AD		 663 return r;
664}
665
666static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
667{
668 const char *chip_name;
669 char fw_name[30];
670 int err;
671 struct amdgpu_firmware_info *info = NULL;
672 const struct common_firmware_header *header = NULL;
595fd013 673 const struct gfx_firmware_header_v1_0 *cp_hdr;
aaa36a97
AD		 674
675 DRM_DEBUG("\n");
676
677 switch (adev->asic_type) {
678 case CHIP_TOPAZ:
679 chip_name = "topaz";
680 break;
681 case CHIP_TONGA:
682 chip_name = "tonga";
683 break;
684 case CHIP_CARRIZO:
685 chip_name = "carrizo";
686 break;
af15a2d5
DZ		 687 case CHIP_FIJI:
688 chip_name = "fiji";
689 break;
aaa36a97
AD		 690 default:
691 BUG();
692 }
693
c65444fe 694 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
aaa36a97
AD		 695 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
696 if (err)
697 goto out;
698 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
699 if (err)
700 goto out;
595fd013
JZ		 701 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
702 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
703 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 704
c65444fe 705 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
aaa36a97
AD		 706 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
707 if (err)
708 goto out;
709 err = amdgpu_ucode_validate(adev->gfx.me_fw);
710 if (err)
711 goto out;
595fd013
JZ		 712 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
713 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
714 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 715
c65444fe 716 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
aaa36a97
AD		 717 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
718 if (err)
719 goto out;
720 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
721 if (err)
722 goto out;
595fd013
JZ		 723 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
724 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
725 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 726
c65444fe 727 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
aaa36a97
AD		 728 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
729 if (err)
730 goto out;
731 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
595fd013
JZ		 732 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
733 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
734 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 735
c65444fe 736 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
aaa36a97
AD		 737 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
738 if (err)
739 goto out;
740 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
741 if (err)
742 goto out;
595fd013
JZ		 743 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
744 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
745 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
aaa36a97 746
c65444fe 747 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
aaa36a97
AD		 748 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
749 if (!err) {
750 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
751 if (err)
752 goto out;
595fd013
JZ		 753 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
754 adev->gfx.mec2_fw->data;
755 adev->gfx.mec2_fw_version = le32_to_cpu(
756 cp_hdr->header.ucode_version);
757 adev->gfx.mec2_feature_version = le32_to_cpu(
758 cp_hdr->ucode_feature_version);
aaa36a97
AD		 759 } else {
760 err = 0;
761 adev->gfx.mec2_fw = NULL;
762 }
763
764 if (adev->firmware.smu_load) {
765 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
766 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
767 info->fw = adev->gfx.pfp_fw;
768 header = (const struct common_firmware_header *)info->fw->data;
769 adev->firmware.fw_size +=
770 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
771
772 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
773 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
774 info->fw = adev->gfx.me_fw;
775 header = (const struct common_firmware_header *)info->fw->data;
776 adev->firmware.fw_size +=
777 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
778
779 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
780 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
781 info->fw = adev->gfx.ce_fw;
782 header = (const struct common_firmware_header *)info->fw->data;
783 adev->firmware.fw_size +=
784 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
785
786 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
787 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
788 info->fw = adev->gfx.rlc_fw;
789 header = (const struct common_firmware_header *)info->fw->data;
790 adev->firmware.fw_size +=
791 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
792
793 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
794 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
795 info->fw = adev->gfx.mec_fw;
796 header = (const struct common_firmware_header *)info->fw->data;
797 adev->firmware.fw_size +=
798 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
799
800 if (adev->gfx.mec2_fw) {
801 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
802 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
803 info->fw = adev->gfx.mec2_fw;
804 header = (const struct common_firmware_header *)info->fw->data;
805 adev->firmware.fw_size +=
806 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
807 }
808
809 }
810
811out:
812 if (err) {
813 dev_err(adev->dev,
814 "gfx8: Failed to load firmware \"%s\"\n",
815 fw_name);
816 release_firmware(adev->gfx.pfp_fw);
817 adev->gfx.pfp_fw = NULL;
818 release_firmware(adev->gfx.me_fw);
819 adev->gfx.me_fw = NULL;
820 release_firmware(adev->gfx.ce_fw);
821 adev->gfx.ce_fw = NULL;
822 release_firmware(adev->gfx.rlc_fw);
823 adev->gfx.rlc_fw = NULL;
824 release_firmware(adev->gfx.mec_fw);
825 adev->gfx.mec_fw = NULL;
826 release_firmware(adev->gfx.mec2_fw);
827 adev->gfx.mec2_fw = NULL;
828 }
829 return err;
830}
831
832static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
833{
834 int r;
835
836 if (adev->gfx.mec.hpd_eop_obj) {
837 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
838 if (unlikely(r != 0))
839 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
840 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
841 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
842
843 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
844 adev->gfx.mec.hpd_eop_obj = NULL;
845 }
846}
847
848#define MEC_HPD_SIZE 2048
849
850static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
851{
852 int r;
853 u32 *hpd;
854
855 /*
856 * we assign only 1 pipe because all other pipes will
857 * be handled by KFD
858 */
859 adev->gfx.mec.num_mec = 1;
860 adev->gfx.mec.num_pipe = 1;
861 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
862
863 if (adev->gfx.mec.hpd_eop_obj == NULL) {
864 r = amdgpu_bo_create(adev,
865 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
866 PAGE_SIZE, true,
867 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
868 &adev->gfx.mec.hpd_eop_obj);
869 if (r) {
870 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
871 return r;
872 }
873 }
874
875 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
876 if (unlikely(r != 0)) {
877 gfx_v8_0_mec_fini(adev);
878 return r;
879 }
880 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
881 &adev->gfx.mec.hpd_eop_gpu_addr);
882 if (r) {
883 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
884 gfx_v8_0_mec_fini(adev);
885 return r;
886 }
887 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
888 if (r) {
889 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
890 gfx_v8_0_mec_fini(adev);
891 return r;
892 }
893
894 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
895
896 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
897 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
898
899 return 0;
900}
901
5fc3aeeb 902static int gfx_v8_0_sw_init(void *handle)
aaa36a97
AD		 903{
904 int i, r;
905 struct amdgpu_ring *ring;
5fc3aeeb 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 907
908 /* EOP Event */
909 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
910 if (r)
911 return r;
912
913 /* Privileged reg */
914 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
915 if (r)
916 return r;
917
918 /* Privileged inst */
919 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
920 if (r)
921 return r;
922
923 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
924
925 gfx_v8_0_scratch_init(adev);
926
927 r = gfx_v8_0_init_microcode(adev);
928 if (r) {
929 DRM_ERROR("Failed to load gfx firmware!\n");
930 return r;
931 }
932
933 r = gfx_v8_0_mec_init(adev);
934 if (r) {
935 DRM_ERROR("Failed to init MEC BOs!\n");
936 return r;
937 }
938
939 r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
940 if (r) {
941 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
942 return r;
943 }
944
945 /* set up the gfx ring */
946 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
947 ring = &adev->gfx.gfx_ring[i];
948 ring->ring_obj = NULL;
949 sprintf(ring->name, "gfx");
950 /* no gfx doorbells on iceland */
951 if (adev->asic_type != CHIP_TOPAZ) {
952 ring->use_doorbell = true;
953 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
954 }
955
956 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
957 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
958 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
959 AMDGPU_RING_TYPE_GFX);
960 if (r)
961 return r;
962 }
963
964 /* set up the compute queues */
965 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
966 unsigned irq_type;
967
968 /* max 32 queues per MEC */
969 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
970 DRM_ERROR("Too many (%d) compute rings!\n", i);
971 break;
972 }
973 ring = &adev->gfx.compute_ring[i];
974 ring->ring_obj = NULL;
975 ring->use_doorbell = true;
976 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
977 ring->me = 1; /* first MEC */
978 ring->pipe = i / 8;
979 ring->queue = i % 8;
980 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
981 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
982 /* type-2 packets are deprecated on MEC, use type-3 instead */
983 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
984 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
985 &adev->gfx.eop_irq, irq_type,
986 AMDGPU_RING_TYPE_COMPUTE);
987 if (r)
988 return r;
989 }
990
991 /* reserve GDS, GWS and OA resource for gfx */
992 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
993 PAGE_SIZE, true,
994 AMDGPU_GEM_DOMAIN_GDS, 0,
995 NULL, &adev->gds.gds_gfx_bo);
996 if (r)
997 return r;
998
999 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1000 PAGE_SIZE, true,
1001 AMDGPU_GEM_DOMAIN_GWS, 0,
1002 NULL, &adev->gds.gws_gfx_bo);
1003 if (r)
1004 return r;
1005
1006 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1007 PAGE_SIZE, true,
1008 AMDGPU_GEM_DOMAIN_OA, 0,
1009 NULL, &adev->gds.oa_gfx_bo);
1010 if (r)
1011 return r;
1012
a101a899
KW		 1013 adev->gfx.ce_ram_size = 0x8000;
1014
aaa36a97
AD		 1015 return 0;
1016}
1017
5fc3aeeb 1018static int gfx_v8_0_sw_fini(void *handle)
aaa36a97
AD		 1019{
1020 int i;
5fc3aeeb 1021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1022
1023 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1024 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1025 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1026
1027 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1028 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1029 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1030 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1031
1032 amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
1033
1034 gfx_v8_0_mec_fini(adev);
1035
1036 return 0;
1037}
1038
1039static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1040{
1041 const u32 num_tile_mode_states = 32;
1042 const u32 num_secondary_tile_mode_states = 16;
1043 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1044
1045 switch (adev->gfx.config.mem_row_size_in_kb) {
1046 case 1:
1047 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1048 break;
1049 case 2:
1050 default:
1051 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1052 break;
1053 case 4:
1054 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1055 break;
1056 }
1057
1058 switch (adev->asic_type) {
1059 case CHIP_TOPAZ:
1060 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1061 switch (reg_offset) {
1062 case 0:
1063 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064 PIPE_CONFIG(ADDR_SURF_P2) |
1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1066 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1067 break;
1068 case 1:
1069 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P2) |
1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1072 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1073 break;
1074 case 2:
1075 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1076 PIPE_CONFIG(ADDR_SURF_P2) |
1077 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1079 break;
1080 case 3:
1081 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1082 PIPE_CONFIG(ADDR_SURF_P2) |
1083 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1085 break;
1086 case 4:
1087 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1088 PIPE_CONFIG(ADDR_SURF_P2) |
1089 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1090 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1091 break;
1092 case 5:
1093 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1094 PIPE_CONFIG(ADDR_SURF_P2) |
1095 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1096 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1097 break;
1098 case 6:
1099 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1100 PIPE_CONFIG(ADDR_SURF_P2) |
1101 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1102 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1103 break;
1104 case 8:
1105 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1106 PIPE_CONFIG(ADDR_SURF_P2));
1107 break;
1108 case 9:
1109 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1110 PIPE_CONFIG(ADDR_SURF_P2) |
1111 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1112 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1113 break;
1114 case 10:
1115 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116 PIPE_CONFIG(ADDR_SURF_P2) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1118 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1119 break;
1120 case 11:
1121 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1122 PIPE_CONFIG(ADDR_SURF_P2) |
1123 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1125 break;
1126 case 13:
1127 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1128 PIPE_CONFIG(ADDR_SURF_P2) |
1129 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1130 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1131 break;
1132 case 14:
1133 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1134 PIPE_CONFIG(ADDR_SURF_P2) |
1135 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1136 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1137 break;
1138 case 15:
1139 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1140 PIPE_CONFIG(ADDR_SURF_P2) |
1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1143 break;
1144 case 16:
1145 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1146 PIPE_CONFIG(ADDR_SURF_P2) |
1147 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1148 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1149 break;
1150 case 18:
1151 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1152 PIPE_CONFIG(ADDR_SURF_P2) |
1153 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1154 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1155 break;
1156 case 19:
1157 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1158 PIPE_CONFIG(ADDR_SURF_P2) |
1159 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1160 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1161 break;
1162 case 20:
1163 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1164 PIPE_CONFIG(ADDR_SURF_P2) |
1165 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1166 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1167 break;
1168 case 21:
1169 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1170 PIPE_CONFIG(ADDR_SURF_P2) |
1171 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1172 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1173 break;
1174 case 22:
1175 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1176 PIPE_CONFIG(ADDR_SURF_P2) |
1177 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1178 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1179 break;
1180 case 24:
1181 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1182 PIPE_CONFIG(ADDR_SURF_P2) |
1183 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1185 break;
1186 case 25:
1187 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1188 PIPE_CONFIG(ADDR_SURF_P2) |
1189 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1190 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1191 break;
1192 case 26:
1193 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1194 PIPE_CONFIG(ADDR_SURF_P2) |
1195 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1196 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1197 break;
1198 case 27:
1199 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1200 PIPE_CONFIG(ADDR_SURF_P2) |
1201 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1202 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1203 break;
1204 case 28:
1205 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1206 PIPE_CONFIG(ADDR_SURF_P2) |
1207 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1208 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1209 break;
1210 case 29:
1211 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1212 PIPE_CONFIG(ADDR_SURF_P2) |
1213 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1214 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1215 break;
1216 case 7:
1217 case 12:
1218 case 17:
1219 case 23:
1220 /* unused idx */
1221 continue;
1222 default:
1223 gb_tile_moden = 0;
1224 break;
1225 };
1226 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1227 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1228 }
1229 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1230 switch (reg_offset) {
1231 case 0:
1232 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1233 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1235 NUM_BANKS(ADDR_SURF_8_BANK));
1236 break;
1237 case 1:
1238 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1241 NUM_BANKS(ADDR_SURF_8_BANK));
1242 break;
1243 case 2:
1244 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1247 NUM_BANKS(ADDR_SURF_8_BANK));
1248 break;
1249 case 3:
1250 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1253 NUM_BANKS(ADDR_SURF_8_BANK));
1254 break;
1255 case 4:
1256 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1257 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1258 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1259 NUM_BANKS(ADDR_SURF_8_BANK));
1260 break;
1261 case 5:
1262 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1265 NUM_BANKS(ADDR_SURF_8_BANK));
1266 break;
1267 case 6:
1268 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1271 NUM_BANKS(ADDR_SURF_8_BANK));
1272 break;
1273 case 8:
1274 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1277 NUM_BANKS(ADDR_SURF_16_BANK));
1278 break;
1279 case 9:
1280 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1281 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1282 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1283 NUM_BANKS(ADDR_SURF_16_BANK));
1284 break;
1285 case 10:
1286 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1289 NUM_BANKS(ADDR_SURF_16_BANK));
1290 break;
1291 case 11:
1292 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1293 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1294 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1295 NUM_BANKS(ADDR_SURF_16_BANK));
1296 break;
1297 case 12:
1298 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1300 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1301 NUM_BANKS(ADDR_SURF_16_BANK));
1302 break;
1303 case 13:
1304 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1305 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1306 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1307 NUM_BANKS(ADDR_SURF_16_BANK));
1308 break;
1309 case 14:
1310 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1311 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1312 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1313 NUM_BANKS(ADDR_SURF_8_BANK));
1314 break;
1315 case 7:
1316 /* unused idx */
1317 continue;
1318 default:
1319 gb_tile_moden = 0;
1320 break;
1321 };
1322 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1323 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1324 }
af15a2d5 1325 case CHIP_FIJI:
aaa36a97
AD		 1326 case CHIP_TONGA:
1327 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1328 switch (reg_offset) {
1329 case 0:
1330 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1331 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1334 break;
1335 case 1:
1336 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1337 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1338 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1339 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1340 break;
1341 case 2:
1342 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1343 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1344 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1345 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1346 break;
1347 case 3:
1348 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1349 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1350 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1351 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1352 break;
1353 case 4:
1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1355 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1356 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1357 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1358 break;
1359 case 5:
1360 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1361 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1362 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1363 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1364 break;
1365 case 6:
1366 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1367 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1369 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1370 break;
1371 case 7:
1372 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1373 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1375 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1376 break;
1377 case 8:
1378 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1379 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1380 break;
1381 case 9:
1382 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1383 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1384 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1385 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1386 break;
1387 case 10:
1388 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1389 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1390 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1392 break;
1393 case 11:
1394 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1395 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1396 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1397 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1398 break;
1399 case 12:
1400 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1401 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1402 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1404 break;
1405 case 13:
1406 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1409 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1410 break;
1411 case 14:
1412 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1413 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1414 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1416 break;
1417 case 15:
1418 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1419 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1420 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1421 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1422 break;
1423 case 16:
1424 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1425 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1426 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1428 break;
1429 case 17:
1430 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1431 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1432 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1433 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1434 break;
1435 case 18:
1436 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1437 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1440 break;
1441 case 19:
1442 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1443 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1444 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1445 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1446 break;
1447 case 20:
1448 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1449 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1452 break;
1453 case 21:
1454 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1455 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1456 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1457 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1458 break;
1459 case 22:
1460 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1461 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1462 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1464 break;
1465 case 23:
1466 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1467 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1468 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1469 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1470 break;
1471 case 24:
1472 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1473 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476 break;
1477 case 25:
1478 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1479 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1480 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1481 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1482 break;
1483 case 26:
1484 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1485 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1488 break;
1489 case 27:
1490 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1491 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1492 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1493 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1494 break;
1495 case 28:
1496 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1497 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1499 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1500 break;
1501 case 29:
1502 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1503 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1504 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1505 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1506 break;
1507 case 30:
1508 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1509 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1510 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1511 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1512 break;
1513 default:
1514 gb_tile_moden = 0;
1515 break;
1516 };
1517 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1518 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1519 }
1520 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1521 switch (reg_offset) {
1522 case 0:
1523 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1526 NUM_BANKS(ADDR_SURF_16_BANK));
1527 break;
1528 case 1:
1529 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532 NUM_BANKS(ADDR_SURF_16_BANK));
1533 break;
1534 case 2:
1535 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1538 NUM_BANKS(ADDR_SURF_16_BANK));
1539 break;
1540 case 3:
1541 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 break;
1546 case 4:
1547 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1550 NUM_BANKS(ADDR_SURF_16_BANK));
1551 break;
1552 case 5:
1553 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1556 NUM_BANKS(ADDR_SURF_16_BANK));
1557 break;
1558 case 6:
1559 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1562 NUM_BANKS(ADDR_SURF_16_BANK));
1563 break;
1564 case 8:
1565 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1568 NUM_BANKS(ADDR_SURF_16_BANK));
1569 break;
1570 case 9:
1571 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1572 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1573 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1574 NUM_BANKS(ADDR_SURF_16_BANK));
1575 break;
1576 case 10:
1577 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1580 NUM_BANKS(ADDR_SURF_16_BANK));
1581 break;
1582 case 11:
1583 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1586 NUM_BANKS(ADDR_SURF_16_BANK));
1587 break;
1588 case 12:
1589 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1590 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1591 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1592 NUM_BANKS(ADDR_SURF_8_BANK));
1593 break;
1594 case 13:
1595 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1598 NUM_BANKS(ADDR_SURF_4_BANK));
1599 break;
1600 case 14:
1601 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1604 NUM_BANKS(ADDR_SURF_4_BANK));
1605 break;
1606 case 7:
1607 /* unused idx */
1608 continue;
1609 default:
1610 gb_tile_moden = 0;
1611 break;
1612 };
1613 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1614 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1615 }
1616 break;
1617 case CHIP_CARRIZO:
1618 default:
1619 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1620 switch (reg_offset) {
1621 case 0:
1622 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1623 PIPE_CONFIG(ADDR_SURF_P2) |
1624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1625 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1626 break;
1627 case 1:
1628 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1629 PIPE_CONFIG(ADDR_SURF_P2) |
1630 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1631 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1632 break;
1633 case 2:
1634 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1635 PIPE_CONFIG(ADDR_SURF_P2) |
1636 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1637 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1638 break;
1639 case 3:
1640 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1641 PIPE_CONFIG(ADDR_SURF_P2) |
1642 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1643 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1644 break;
1645 case 4:
1646 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1647 PIPE_CONFIG(ADDR_SURF_P2) |
1648 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1649 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1650 break;
1651 case 5:
1652 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1653 PIPE_CONFIG(ADDR_SURF_P2) |
1654 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1655 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1656 break;
1657 case 6:
1658 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1659 PIPE_CONFIG(ADDR_SURF_P2) |
1660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1661 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1662 break;
1663 case 8:
1664 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1665 PIPE_CONFIG(ADDR_SURF_P2));
1666 break;
1667 case 9:
1668 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1669 PIPE_CONFIG(ADDR_SURF_P2) |
1670 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1671 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1672 break;
1673 case 10:
1674 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1675 PIPE_CONFIG(ADDR_SURF_P2) |
1676 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1677 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1678 break;
1679 case 11:
1680 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1681 PIPE_CONFIG(ADDR_SURF_P2) |
1682 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1683 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1684 break;
1685 case 13:
1686 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1687 PIPE_CONFIG(ADDR_SURF_P2) |
1688 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1689 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1690 break;
1691 case 14:
1692 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1693 PIPE_CONFIG(ADDR_SURF_P2) |
1694 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1695 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1696 break;
1697 case 15:
1698 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1699 PIPE_CONFIG(ADDR_SURF_P2) |
1700 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1701 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1702 break;
1703 case 16:
1704 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1705 PIPE_CONFIG(ADDR_SURF_P2) |
1706 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1707 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1708 break;
1709 case 18:
1710 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1711 PIPE_CONFIG(ADDR_SURF_P2) |
1712 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1713 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1714 break;
1715 case 19:
1716 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1717 PIPE_CONFIG(ADDR_SURF_P2) |
1718 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1719 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1720 break;
1721 case 20:
1722 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1723 PIPE_CONFIG(ADDR_SURF_P2) |
1724 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1725 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1726 break;
1727 case 21:
1728 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1729 PIPE_CONFIG(ADDR_SURF_P2) |
1730 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1731 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1732 break;
1733 case 22:
1734 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1735 PIPE_CONFIG(ADDR_SURF_P2) |
1736 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1737 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1738 break;
1739 case 24:
1740 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1741 PIPE_CONFIG(ADDR_SURF_P2) |
1742 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1743 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1744 break;
1745 case 25:
1746 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1747 PIPE_CONFIG(ADDR_SURF_P2) |
1748 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1749 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1750 break;
1751 case 26:
1752 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1753 PIPE_CONFIG(ADDR_SURF_P2) |
1754 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1755 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1756 break;
1757 case 27:
1758 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1759 PIPE_CONFIG(ADDR_SURF_P2) |
1760 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1761 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1762 break;
1763 case 28:
1764 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1765 PIPE_CONFIG(ADDR_SURF_P2) |
1766 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1767 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1768 break;
1769 case 29:
1770 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1771 PIPE_CONFIG(ADDR_SURF_P2) |
1772 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1773 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1774 break;
1775 case 7:
1776 case 12:
1777 case 17:
1778 case 23:
1779 /* unused idx */
1780 continue;
1781 default:
1782 gb_tile_moden = 0;
1783 break;
1784 };
1785 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1786 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1787 }
1788 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1789 switch (reg_offset) {
1790 case 0:
1791 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1792 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1793 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1794 NUM_BANKS(ADDR_SURF_8_BANK));
1795 break;
1796 case 1:
1797 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1800 NUM_BANKS(ADDR_SURF_8_BANK));
1801 break;
1802 case 2:
1803 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1804 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1805 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1806 NUM_BANKS(ADDR_SURF_8_BANK));
1807 break;
1808 case 3:
1809 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1812 NUM_BANKS(ADDR_SURF_8_BANK));
1813 break;
1814 case 4:
1815 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1816 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1817 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1818 NUM_BANKS(ADDR_SURF_8_BANK));
1819 break;
1820 case 5:
1821 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1824 NUM_BANKS(ADDR_SURF_8_BANK));
1825 break;
1826 case 6:
1827 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1830 NUM_BANKS(ADDR_SURF_8_BANK));
1831 break;
1832 case 8:
1833 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1836 NUM_BANKS(ADDR_SURF_16_BANK));
1837 break;
1838 case 9:
1839 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1842 NUM_BANKS(ADDR_SURF_16_BANK));
1843 break;
1844 case 10:
1845 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1846 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1847 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1848 NUM_BANKS(ADDR_SURF_16_BANK));
1849 break;
1850 case 11:
1851 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1852 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1853 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1854 NUM_BANKS(ADDR_SURF_16_BANK));
1855 break;
1856 case 12:
1857 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1860 NUM_BANKS(ADDR_SURF_16_BANK));
1861 break;
1862 case 13:
1863 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1866 NUM_BANKS(ADDR_SURF_16_BANK));
1867 break;
1868 case 14:
1869 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1870 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1871 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1872 NUM_BANKS(ADDR_SURF_8_BANK));
1873 break;
1874 case 7:
1875 /* unused idx */
1876 continue;
1877 default:
1878 gb_tile_moden = 0;
1879 break;
1880 };
1881 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1882 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1883 }
1884 }
1885}
1886
1887static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1888{
1889 u32 i, mask = 0;
1890
1891 for (i = 0; i < bit_width; i++) {
1892 mask <<= 1;
1893 mask |= 1;
1894 }
1895 return mask;
1896}
1897
1898void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1899{
1900 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1901
1902 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1903 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1904 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1905 } else if (se_num == 0xffffffff) {
1906 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1907 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1908 } else if (sh_num == 0xffffffff) {
1909 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1910 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1911 } else {
1912 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1913 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1914 }
1915 WREG32(mmGRBM_GFX_INDEX, data);
1916}
1917
1918static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1919 u32 max_rb_num_per_se,
1920 u32 sh_per_se)
1921{
1922 u32 data, mask;
1923
1924 data = RREG32(mmCC_RB_BACKEND_DISABLE);
4f2d3ad6 1925 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
aaa36a97
AD		 1926
1927 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1928
1929 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1930
1931 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1932
1933 return data & mask;
1934}
1935
1936static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1937 u32 se_num, u32 sh_per_se,
1938 u32 max_rb_num_per_se)
1939{
1940 int i, j;
1941 u32 data, mask;
1942 u32 disabled_rbs = 0;
1943 u32 enabled_rbs = 0;
1944
1945 mutex_lock(&adev->grbm_idx_mutex);
1946 for (i = 0; i < se_num; i++) {
1947 for (j = 0; j < sh_per_se; j++) {
1948 gfx_v8_0_select_se_sh(adev, i, j);
1949 data = gfx_v8_0_get_rb_disabled(adev,
1950 max_rb_num_per_se, sh_per_se);
1951 disabled_rbs |= data << ((i * sh_per_se + j) *
1952 RB_BITMAP_WIDTH_PER_SH);
1953 }
1954 }
1955 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1956 mutex_unlock(&adev->grbm_idx_mutex);
1957
1958 mask = 1;
1959 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1960 if (!(disabled_rbs & mask))
1961 enabled_rbs |= mask;
1962 mask <<= 1;
1963 }
1964
1965 adev->gfx.config.backend_enable_mask = enabled_rbs;
1966
1967 mutex_lock(&adev->grbm_idx_mutex);
1968 for (i = 0; i < se_num; i++) {
1969 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1970 data = 0;
1971 for (j = 0; j < sh_per_se; j++) {
1972 switch (enabled_rbs & 3) {
1973 case 0:
1974 if (j == 0)
1975 data |= (RASTER_CONFIG_RB_MAP_3 <<
1976 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1977 else
1978 data |= (RASTER_CONFIG_RB_MAP_0 <<
1979 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1980 break;
1981 case 1:
1982 data |= (RASTER_CONFIG_RB_MAP_0 <<
1983 (i * sh_per_se + j) * 2);
1984 break;
1985 case 2:
1986 data |= (RASTER_CONFIG_RB_MAP_3 <<
1987 (i * sh_per_se + j) * 2);
1988 break;
1989 case 3:
1990 default:
1991 data |= (RASTER_CONFIG_RB_MAP_2 <<
1992 (i * sh_per_se + j) * 2);
1993 break;
1994 }
1995 enabled_rbs >>= 2;
1996 }
1997 WREG32(mmPA_SC_RASTER_CONFIG, data);
1998 }
1999 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2000 mutex_unlock(&adev->grbm_idx_mutex);
2001}
2002
cd06bf68
BG		 2003/**
2004 * gmc_v8_0_init_compute_vmid - gart enable
2005 *
2006 * @rdev: amdgpu_device pointer
2007 *
2008 * Initialize compute vmid sh_mem registers
2009 *
2010 */
2011#define DEFAULT_SH_MEM_BASES (0x6000)
2012#define FIRST_COMPUTE_VMID (8)
2013#define LAST_COMPUTE_VMID (16)
2014static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2015{
2016 int i;
2017 uint32_t sh_mem_config;
2018 uint32_t sh_mem_bases;
2019
2020 /*
2021 * Configure apertures:
2022 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2023 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2024 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2025 */
2026 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2027
2028 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2029 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2030 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2031 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2032 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2033 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2034
2035 mutex_lock(&adev->srbm_mutex);
2036 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2037 vi_srbm_select(adev, 0, 0, 0, i);
2038 /* CP and shaders */
2039 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2040 WREG32(mmSH_MEM_APE1_BASE, 1);
2041 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2042 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2043 }
2044 vi_srbm_select(adev, 0, 0, 0, 0);
2045 mutex_unlock(&adev->srbm_mutex);
2046}
2047
aaa36a97
AD		 2048static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2049{
2050 u32 gb_addr_config;
2051 u32 mc_shared_chmap, mc_arb_ramcfg;
2052 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
2053 u32 tmp;
2054 int i;
2055
2056 switch (adev->asic_type) {
2057 case CHIP_TOPAZ:
2058 adev->gfx.config.max_shader_engines = 1;
2059 adev->gfx.config.max_tile_pipes = 2;
2060 adev->gfx.config.max_cu_per_sh = 6;
2061 adev->gfx.config.max_sh_per_se = 1;
2062 adev->gfx.config.max_backends_per_se = 2;
2063 adev->gfx.config.max_texture_channel_caches = 2;
2064 adev->gfx.config.max_gprs = 256;
2065 adev->gfx.config.max_gs_threads = 32;
2066 adev->gfx.config.max_hw_contexts = 8;
2067
2068 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2069 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2070 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2071 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2072 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
2073 break;
af15a2d5
DZ		 2074 case CHIP_FIJI:
2075 adev->gfx.config.max_shader_engines = 4;
2076 adev->gfx.config.max_tile_pipes = 16;
2077 adev->gfx.config.max_cu_per_sh = 16;
2078 adev->gfx.config.max_sh_per_se = 1;
2079 adev->gfx.config.max_backends_per_se = 4;
2080 adev->gfx.config.max_texture_channel_caches = 8;
2081 adev->gfx.config.max_gprs = 256;
2082 adev->gfx.config.max_gs_threads = 32;
2083 adev->gfx.config.max_hw_contexts = 8;
2084
2085 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2086 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2087 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2088 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2089 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2090 break;
aaa36a97
AD		 2091 case CHIP_TONGA:
2092 adev->gfx.config.max_shader_engines = 4;
2093 adev->gfx.config.max_tile_pipes = 8;
2094 adev->gfx.config.max_cu_per_sh = 8;
2095 adev->gfx.config.max_sh_per_se = 1;
2096 adev->gfx.config.max_backends_per_se = 2;
2097 adev->gfx.config.max_texture_channel_caches = 8;
2098 adev->gfx.config.max_gprs = 256;
2099 adev->gfx.config.max_gs_threads = 32;
2100 adev->gfx.config.max_hw_contexts = 8;
2101
2102 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2103 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2104 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2105 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2106 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2107 break;
2108 case CHIP_CARRIZO:
2109 adev->gfx.config.max_shader_engines = 1;
2110 adev->gfx.config.max_tile_pipes = 2;
aaa36a97 2111 adev->gfx.config.max_sh_per_se = 1;
a0e2f50b 2112 adev->gfx.config.max_backends_per_se = 2;
bd5c97bc
AD		 2113
2114 switch (adev->pdev->revision) {
2115 case 0xc4:
2116 case 0x84:
2117 case 0xc8:
2118 case 0xcc:
2119 /* B10 */
2120 adev->gfx.config.max_cu_per_sh = 8;
bd5c97bc
AD		 2121 break;
2122 case 0xc5:
2123 case 0x81:
2124 case 0x85:
2125 case 0xc9:
2126 case 0xcd:
2127 /* B8 */
2128 adev->gfx.config.max_cu_per_sh = 6;
bd5c97bc
AD		 2129 break;
2130 case 0xc6:
2131 case 0xca:
2132 case 0xce:
2133 /* B6 */
2134 adev->gfx.config.max_cu_per_sh = 6;
bd5c97bc
AD		 2135 break;
2136 case 0xc7:
2137 case 0x87:
2138 case 0xcb:
2139 default:
2140 /* B4 */
2141 adev->gfx.config.max_cu_per_sh = 4;
bd5c97bc
AD		 2142 break;
2143 }
2144
aaa36a97
AD		 2145 adev->gfx.config.max_texture_channel_caches = 2;
2146 adev->gfx.config.max_gprs = 256;
2147 adev->gfx.config.max_gs_threads = 32;
2148 adev->gfx.config.max_hw_contexts = 8;
2149
2150 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2151 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2152 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2153 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2154 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
2155 break;
2156 default:
2157 adev->gfx.config.max_shader_engines = 2;
2158 adev->gfx.config.max_tile_pipes = 4;
2159 adev->gfx.config.max_cu_per_sh = 2;
2160 adev->gfx.config.max_sh_per_se = 1;
2161 adev->gfx.config.max_backends_per_se = 2;
2162 adev->gfx.config.max_texture_channel_caches = 4;
2163 adev->gfx.config.max_gprs = 256;
2164 adev->gfx.config.max_gs_threads = 32;
2165 adev->gfx.config.max_hw_contexts = 8;
2166
2167 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2168 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2169 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2170 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2171 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2172 break;
2173 }
2174
2175 tmp = RREG32(mmGRBM_CNTL);
2176 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2177 WREG32(mmGRBM_CNTL, tmp);
2178
2179 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2180 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2181 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2182
2183 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2184 adev->gfx.config.mem_max_burst_length_bytes = 256;
2f7d10b3 2185 if (adev->flags & AMD_IS_APU) {
aaa36a97
AD		 2186 /* Get memory bank mapping mode. */
2187 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2188 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2189 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2190
2191 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2192 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2193 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2194
2195 /* Validate settings in case only one DIMM installed. */
2196 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2197 dimm00_addr_map = 0;
2198 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2199 dimm01_addr_map = 0;
2200 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2201 dimm10_addr_map = 0;
2202 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2203 dimm11_addr_map = 0;
2204
2205 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2206 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2207 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2208 adev->gfx.config.mem_row_size_in_kb = 2;
2209 else
2210 adev->gfx.config.mem_row_size_in_kb = 1;
2211 } else {
2212 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2213 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2214 if (adev->gfx.config.mem_row_size_in_kb > 4)
2215 adev->gfx.config.mem_row_size_in_kb = 4;
2216 }
2217
2218 adev->gfx.config.shader_engine_tile_size = 32;
2219 adev->gfx.config.num_gpus = 1;
2220 adev->gfx.config.multi_gpu_tile_size = 64;
2221
2222 /* fix up row size */
2223 switch (adev->gfx.config.mem_row_size_in_kb) {
2224 case 1:
2225 default:
2226 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2227 break;
2228 case 2:
2229 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2230 break;
2231 case 4:
2232 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2233 break;
2234 }
2235 adev->gfx.config.gb_addr_config = gb_addr_config;
2236
2237 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2238 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2239 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2240 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2241 gb_addr_config & 0x70);
2242 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2243 gb_addr_config & 0x70);
2244 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2245 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2246 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2247
2248 gfx_v8_0_tiling_mode_table_init(adev);
2249
2250 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2251 adev->gfx.config.max_sh_per_se,
2252 adev->gfx.config.max_backends_per_se);
2253
2254 /* XXX SH_MEM regs */
2255 /* where to put LDS, scratch, GPUVM in FSA64 space */
2256 mutex_lock(&adev->srbm_mutex);
2257 for (i = 0; i < 16; i++) {
2258 vi_srbm_select(adev, 0, 0, 0, i);
2259 /* CP and shaders */
2260 if (i == 0) {
2261 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2262 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
74a5d165
JX		 2263 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2264 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 2265 WREG32(mmSH_MEM_CONFIG, tmp);
2266 } else {
2267 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2268 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
74a5d165
JX		 2269 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2270 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
aaa36a97
AD		 2271 WREG32(mmSH_MEM_CONFIG, tmp);
2272 }
2273
2274 WREG32(mmSH_MEM_APE1_BASE, 1);
2275 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2276 WREG32(mmSH_MEM_BASES, 0);
2277 }
2278 vi_srbm_select(adev, 0, 0, 0, 0);
2279 mutex_unlock(&adev->srbm_mutex);
2280
cd06bf68
BG		 2281 gmc_v8_0_init_compute_vmid(adev);
2282
aaa36a97
AD		 2283 mutex_lock(&adev->grbm_idx_mutex);
2284 /*
2285 * making sure that the following register writes will be broadcasted
2286 * to all the shaders
2287 */
2288 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2289
2290 WREG32(mmPA_SC_FIFO_SIZE,
2291 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2292 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2293 (adev->gfx.config.sc_prim_fifo_size_backend <<
2294 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2295 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2296 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2297 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2298 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2299 mutex_unlock(&adev->grbm_idx_mutex);
2300
2301}
2302
2303static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2304{
2305 u32 i, j, k;
2306 u32 mask;
2307
2308 mutex_lock(&adev->grbm_idx_mutex);
2309 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2310 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2311 gfx_v8_0_select_se_sh(adev, i, j);
2312 for (k = 0; k < adev->usec_timeout; k++) {
2313 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2314 break;
2315 udelay(1);
2316 }
2317 }
2318 }
2319 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2320 mutex_unlock(&adev->grbm_idx_mutex);
2321
2322 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2323 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2324 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2325 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2326 for (k = 0; k < adev->usec_timeout; k++) {
2327 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2328 break;
2329 udelay(1);
2330 }
2331}
2332
2333static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2334 bool enable)
2335{
2336 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2337
2338 if (enable) {
2339 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2340 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2341 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2342 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2343 } else {
2344 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2345 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2346 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2347 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2348 }
2349 WREG32(mmCP_INT_CNTL_RING0, tmp);
2350}
2351
2352void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2353{
2354 u32 tmp = RREG32(mmRLC_CNTL);
2355
2356 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2357 WREG32(mmRLC_CNTL, tmp);
2358
2359 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2360
2361 gfx_v8_0_wait_for_rlc_serdes(adev);
2362}
2363
2364static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2365{
2366 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2367
2368 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2369 WREG32(mmGRBM_SOFT_RESET, tmp);
2370 udelay(50);
2371 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2372 WREG32(mmGRBM_SOFT_RESET, tmp);
2373 udelay(50);
2374}
2375
2376static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2377{
2378 u32 tmp = RREG32(mmRLC_CNTL);
2379
2380 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2381 WREG32(mmRLC_CNTL, tmp);
2382
2383 /* carrizo do enable cp interrupt after cp inited */
2384 if (adev->asic_type != CHIP_CARRIZO)
2385 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2386
2387 udelay(50);
2388}
2389
2390static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2391{
2392 const struct rlc_firmware_header_v2_0 *hdr;
2393 const __le32 *fw_data;
2394 unsigned i, fw_size;
2395
2396 if (!adev->gfx.rlc_fw)
2397 return -EINVAL;
2398
2399 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2400 amdgpu_ucode_print_rlc_hdr(&hdr->header);
aaa36a97
AD		 2401
2402 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2403 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2404 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2405
2406 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2407 for (i = 0; i < fw_size; i++)
2408 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2409 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2410
2411 return 0;
2412}
2413
2414static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2415{
2416 int r;
2417
2418 gfx_v8_0_rlc_stop(adev);
2419
2420 /* disable CG */
2421 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2422
2423 /* disable PG */
2424 WREG32(mmRLC_PG_CNTL, 0);
2425
2426 gfx_v8_0_rlc_reset(adev);
2427
2428 if (!adev->firmware.smu_load) {
2429 /* legacy rlc firmware loading */
2430 r = gfx_v8_0_rlc_load_microcode(adev);
2431 if (r)
2432 return r;
2433 } else {
2434 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2435 AMDGPU_UCODE_ID_RLC_G);
2436 if (r)
2437 return -EINVAL;
2438 }
2439
2440 gfx_v8_0_rlc_start(adev);
2441
2442 return 0;
2443}
2444
2445static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2446{
2447 int i;
2448 u32 tmp = RREG32(mmCP_ME_CNTL);
2449
2450 if (enable) {
2451 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2452 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2453 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2454 } else {
2455 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2456 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2457 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2458 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2459 adev->gfx.gfx_ring[i].ready = false;
2460 }
2461 WREG32(mmCP_ME_CNTL, tmp);
2462 udelay(50);
2463}
2464
2465static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2466{
2467 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2468 const struct gfx_firmware_header_v1_0 *ce_hdr;
2469 const struct gfx_firmware_header_v1_0 *me_hdr;
2470 const __le32 *fw_data;
2471 unsigned i, fw_size;
2472
2473 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2474 return -EINVAL;
2475
2476 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2477 adev->gfx.pfp_fw->data;
2478 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2479 adev->gfx.ce_fw->data;
2480 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2481 adev->gfx.me_fw->data;
2482
2483 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2484 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2485 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
aaa36a97
AD		 2486
2487 gfx_v8_0_cp_gfx_enable(adev, false);
2488
2489 /* PFP */
2490 fw_data = (const __le32 *)
2491 (adev->gfx.pfp_fw->data +
2492 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2493 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2494 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2495 for (i = 0; i < fw_size; i++)
2496 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2497 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2498
2499 /* CE */
2500 fw_data = (const __le32 *)
2501 (adev->gfx.ce_fw->data +
2502 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2503 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2504 WREG32(mmCP_CE_UCODE_ADDR, 0);
2505 for (i = 0; i < fw_size; i++)
2506 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2507 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2508
2509 /* ME */
2510 fw_data = (const __le32 *)
2511 (adev->gfx.me_fw->data +
2512 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2513 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2514 WREG32(mmCP_ME_RAM_WADDR, 0);
2515 for (i = 0; i < fw_size; i++)
2516 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2517 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2518
2519 return 0;
2520}
2521
2522static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2523{
2524 u32 count = 0;
2525 const struct cs_section_def *sect = NULL;
2526 const struct cs_extent_def *ext = NULL;
2527
2528 /* begin clear state */
2529 count += 2;
2530 /* context control state */
2531 count += 3;
2532
2533 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2534 for (ext = sect->section; ext->extent != NULL; ++ext) {
2535 if (sect->id == SECT_CONTEXT)
2536 count += 2 + ext->reg_count;
2537 else
2538 return 0;
2539 }
2540 }
2541 /* pa_sc_raster_config/pa_sc_raster_config1 */
2542 count += 4;
2543 /* end clear state */
2544 count += 2;
2545 /* clear state */
2546 count += 2;
2547
2548 return count;
2549}
2550
2551static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2552{
2553 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2554 const struct cs_section_def *sect = NULL;
2555 const struct cs_extent_def *ext = NULL;
2556 int r, i;
2557
2558 /* init the CP */
2559 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2560 WREG32(mmCP_ENDIAN_SWAP, 0);
2561 WREG32(mmCP_DEVICE_ID, 1);
2562
2563 gfx_v8_0_cp_gfx_enable(adev, true);
2564
2565 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2566 if (r) {
2567 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2568 return r;
2569 }
2570
2571 /* clear state buffer */
2572 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2573 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2574
2575 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2576 amdgpu_ring_write(ring, 0x80000000);
2577 amdgpu_ring_write(ring, 0x80000000);
2578
2579 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2580 for (ext = sect->section; ext->extent != NULL; ++ext) {
2581 if (sect->id == SECT_CONTEXT) {
2582 amdgpu_ring_write(ring,
2583 PACKET3(PACKET3_SET_CONTEXT_REG,
2584 ext->reg_count));
2585 amdgpu_ring_write(ring,
2586 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2587 for (i = 0; i < ext->reg_count; i++)
2588 amdgpu_ring_write(ring, ext->extent[i]);
2589 }
2590 }
2591 }
2592
2593 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2594 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2595 switch (adev->asic_type) {
2596 case CHIP_TONGA:
af15a2d5 2597 case CHIP_FIJI:
aaa36a97
AD		 2598 amdgpu_ring_write(ring, 0x16000012);
2599 amdgpu_ring_write(ring, 0x0000002A);
2600 break;
2601 case CHIP_TOPAZ:
2602 case CHIP_CARRIZO:
2603 amdgpu_ring_write(ring, 0x00000002);
2604 amdgpu_ring_write(ring, 0x00000000);
2605 break;
2606 default:
2607 BUG();
2608 }
2609
2610 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2611 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2612
2613 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2614 amdgpu_ring_write(ring, 0);
2615
2616 /* init the CE partitions */
2617 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2618 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2619 amdgpu_ring_write(ring, 0x8000);
2620 amdgpu_ring_write(ring, 0x8000);
2621
2622 amdgpu_ring_unlock_commit(ring);
2623
2624 return 0;
2625}
2626
2627static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2628{
2629 struct amdgpu_ring *ring;
2630 u32 tmp;
2631 u32 rb_bufsz;
2632 u64 rb_addr, rptr_addr;
2633 int r;
2634
2635 /* Set the write pointer delay */
2636 WREG32(mmCP_RB_WPTR_DELAY, 0);
2637
2638 /* set the RB to use vmid 0 */
2639 WREG32(mmCP_RB_VMID, 0);
2640
2641 /* Set ring buffer size */
2642 ring = &adev->gfx.gfx_ring[0];
2643 rb_bufsz = order_base_2(ring->ring_size / 8);
2644 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2645 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2646 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2647 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2648#ifdef __BIG_ENDIAN
2649 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2650#endif
2651 WREG32(mmCP_RB0_CNTL, tmp);
2652
2653 /* Initialize the ring buffer's read and write pointers */
2654 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2655 ring->wptr = 0;
2656 WREG32(mmCP_RB0_WPTR, ring->wptr);
2657
2658 /* set the wb address wether it's enabled or not */
2659 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2660 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2661 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2662
2663 mdelay(1);
2664 WREG32(mmCP_RB0_CNTL, tmp);
2665
2666 rb_addr = ring->gpu_addr >> 8;
2667 WREG32(mmCP_RB0_BASE, rb_addr);
2668 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2669
2670 /* no gfx doorbells on iceland */
2671 if (adev->asic_type != CHIP_TOPAZ) {
2672 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2673 if (ring->use_doorbell) {
2674 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2675 DOORBELL_OFFSET, ring->doorbell_index);
2676 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2677 DOORBELL_EN, 1);
2678 } else {
2679 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2680 DOORBELL_EN, 0);
2681 }
2682 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2683
2684 if (adev->asic_type == CHIP_TONGA) {
2685 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2686 DOORBELL_RANGE_LOWER,
2687 AMDGPU_DOORBELL_GFX_RING0);
2688 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2689
2690 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2691 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2692 }
2693
2694 }
2695
2696 /* start the ring */
2697 gfx_v8_0_cp_gfx_start(adev);
2698 ring->ready = true;
2699 r = amdgpu_ring_test_ring(ring);
2700 if (r) {
2701 ring->ready = false;
2702 return r;
2703 }
2704
2705 return 0;
2706}
2707
2708static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2709{
2710 int i;
2711
2712 if (enable) {
2713 WREG32(mmCP_MEC_CNTL, 0);
2714 } else {
2715 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2716 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2717 adev->gfx.compute_ring[i].ready = false;
2718 }
2719 udelay(50);
2720}
2721
2722static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2723{
2724 gfx_v8_0_cp_compute_enable(adev, true);
2725
2726 return 0;
2727}
2728
2729static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2730{
2731 const struct gfx_firmware_header_v1_0 *mec_hdr;
2732 const __le32 *fw_data;
2733 unsigned i, fw_size;
2734
2735 if (!adev->gfx.mec_fw)
2736 return -EINVAL;
2737
2738 gfx_v8_0_cp_compute_enable(adev, false);
2739
2740 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2741 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
aaa36a97
AD		 2742
2743 fw_data = (const __le32 *)
2744 (adev->gfx.mec_fw->data +
2745 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2746 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2747
2748 /* MEC1 */
2749 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2750 for (i = 0; i < fw_size; i++)
2751 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2752 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2753
2754 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2755 if (adev->gfx.mec2_fw) {
2756 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2757
2758 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2759 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
aaa36a97
AD		 2760
2761 fw_data = (const __le32 *)
2762 (adev->gfx.mec2_fw->data +
2763 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2764 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2765
2766 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2767 for (i = 0; i < fw_size; i++)
2768 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2769 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2770 }
2771
2772 return 0;
2773}
2774
2775struct vi_mqd {
2776 uint32_t header; /* ordinal0 */
2777 uint32_t compute_dispatch_initiator; /* ordinal1 */
2778 uint32_t compute_dim_x; /* ordinal2 */
2779 uint32_t compute_dim_y; /* ordinal3 */
2780 uint32_t compute_dim_z; /* ordinal4 */
2781 uint32_t compute_start_x; /* ordinal5 */
2782 uint32_t compute_start_y; /* ordinal6 */
2783 uint32_t compute_start_z; /* ordinal7 */
2784 uint32_t compute_num_thread_x; /* ordinal8 */
2785 uint32_t compute_num_thread_y; /* ordinal9 */
2786 uint32_t compute_num_thread_z; /* ordinal10 */
2787 uint32_t compute_pipelinestat_enable; /* ordinal11 */
2788 uint32_t compute_perfcount_enable; /* ordinal12 */
2789 uint32_t compute_pgm_lo; /* ordinal13 */
2790 uint32_t compute_pgm_hi; /* ordinal14 */
2791 uint32_t compute_tba_lo; /* ordinal15 */
2792 uint32_t compute_tba_hi; /* ordinal16 */
2793 uint32_t compute_tma_lo; /* ordinal17 */
2794 uint32_t compute_tma_hi; /* ordinal18 */
2795 uint32_t compute_pgm_rsrc1; /* ordinal19 */
2796 uint32_t compute_pgm_rsrc2; /* ordinal20 */
2797 uint32_t compute_vmid; /* ordinal21 */
2798 uint32_t compute_resource_limits; /* ordinal22 */
2799 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
2800 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
2801 uint32_t compute_tmpring_size; /* ordinal25 */
2802 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
2803 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
2804 uint32_t compute_restart_x; /* ordinal28 */
2805 uint32_t compute_restart_y; /* ordinal29 */
2806 uint32_t compute_restart_z; /* ordinal30 */
2807 uint32_t compute_thread_trace_enable; /* ordinal31 */
2808 uint32_t compute_misc_reserved; /* ordinal32 */
2809 uint32_t compute_dispatch_id; /* ordinal33 */
2810 uint32_t compute_threadgroup_id; /* ordinal34 */
2811 uint32_t compute_relaunch; /* ordinal35 */
2812 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
2813 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
2814 uint32_t compute_wave_restore_control; /* ordinal38 */
2815 uint32_t reserved9; /* ordinal39 */
2816 uint32_t reserved10; /* ordinal40 */
2817 uint32_t reserved11; /* ordinal41 */
2818 uint32_t reserved12; /* ordinal42 */
2819 uint32_t reserved13; /* ordinal43 */
2820 uint32_t reserved14; /* ordinal44 */
2821 uint32_t reserved15; /* ordinal45 */
2822 uint32_t reserved16; /* ordinal46 */
2823 uint32_t reserved17; /* ordinal47 */
2824 uint32_t reserved18; /* ordinal48 */
2825 uint32_t reserved19; /* ordinal49 */
2826 uint32_t reserved20; /* ordinal50 */
2827 uint32_t reserved21; /* ordinal51 */
2828 uint32_t reserved22; /* ordinal52 */
2829 uint32_t reserved23; /* ordinal53 */
2830 uint32_t reserved24; /* ordinal54 */
2831 uint32_t reserved25; /* ordinal55 */
2832 uint32_t reserved26; /* ordinal56 */
2833 uint32_t reserved27; /* ordinal57 */
2834 uint32_t reserved28; /* ordinal58 */
2835 uint32_t reserved29; /* ordinal59 */
2836 uint32_t reserved30; /* ordinal60 */
2837 uint32_t reserved31; /* ordinal61 */
2838 uint32_t reserved32; /* ordinal62 */
2839 uint32_t reserved33; /* ordinal63 */
2840 uint32_t reserved34; /* ordinal64 */
2841 uint32_t compute_user_data_0; /* ordinal65 */
2842 uint32_t compute_user_data_1; /* ordinal66 */
2843 uint32_t compute_user_data_2; /* ordinal67 */
2844 uint32_t compute_user_data_3; /* ordinal68 */
2845 uint32_t compute_user_data_4; /* ordinal69 */
2846 uint32_t compute_user_data_5; /* ordinal70 */
2847 uint32_t compute_user_data_6; /* ordinal71 */
2848 uint32_t compute_user_data_7; /* ordinal72 */
2849 uint32_t compute_user_data_8; /* ordinal73 */
2850 uint32_t compute_user_data_9; /* ordinal74 */
2851 uint32_t compute_user_data_10; /* ordinal75 */
2852 uint32_t compute_user_data_11; /* ordinal76 */
2853 uint32_t compute_user_data_12; /* ordinal77 */
2854 uint32_t compute_user_data_13; /* ordinal78 */
2855 uint32_t compute_user_data_14; /* ordinal79 */
2856 uint32_t compute_user_data_15; /* ordinal80 */
2857 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
2858 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
2859 uint32_t reserved35; /* ordinal83 */
2860 uint32_t reserved36; /* ordinal84 */
2861 uint32_t reserved37; /* ordinal85 */
2862 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
2863 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
2864 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
2865 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
2866 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
2867 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
2868 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
2869 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
2870 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
2871 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
2872 uint32_t reserved38; /* ordinal96 */
2873 uint32_t reserved39; /* ordinal97 */
2874 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
2875 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
2876 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
2877 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
2878 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
2879 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
2880 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
2881 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
2882 uint32_t reserved40; /* ordinal106 */
2883 uint32_t reserved41; /* ordinal107 */
2884 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
2885 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
2886 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
2887 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
2888 uint32_t reserved42; /* ordinal112 */
2889 uint32_t reserved43; /* ordinal113 */
2890 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
2891 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
2892 uint32_t cp_packet_id_lo; /* ordinal116 */
2893 uint32_t cp_packet_id_hi; /* ordinal117 */
2894 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
2895 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
2896 uint32_t gds_save_base_addr_lo; /* ordinal120 */
2897 uint32_t gds_save_base_addr_hi; /* ordinal121 */
2898 uint32_t gds_save_mask_lo; /* ordinal122 */
2899 uint32_t gds_save_mask_hi; /* ordinal123 */
2900 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
2901 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
2902 uint32_t reserved44; /* ordinal126 */
2903 uint32_t reserved45; /* ordinal127 */
2904 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
2905 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
2906 uint32_t cp_hqd_active; /* ordinal130 */
2907 uint32_t cp_hqd_vmid; /* ordinal131 */
2908 uint32_t cp_hqd_persistent_state; /* ordinal132 */
2909 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
2910 uint32_t cp_hqd_queue_priority; /* ordinal134 */
2911 uint32_t cp_hqd_quantum; /* ordinal135 */
2912 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
2913 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
2914 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
2915 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
2916 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
2917 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
2918 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
2919 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
2920 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
2921 uint32_t cp_hqd_pq_control; /* ordinal145 */
2922 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
2923 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
2924 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
2925 uint32_t cp_hqd_ib_control; /* ordinal149 */
2926 uint32_t cp_hqd_iq_timer; /* ordinal150 */
2927 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
2928 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
2929 uint32_t cp_hqd_dma_offload; /* ordinal153 */
2930 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
2931 uint32_t cp_hqd_msg_type; /* ordinal155 */
2932 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
2933 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
2934 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
2935 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
2936 uint32_t cp_hqd_hq_status0; /* ordinal160 */
2937 uint32_t cp_hqd_hq_control0; /* ordinal161 */
2938 uint32_t cp_mqd_control; /* ordinal162 */
2939 uint32_t cp_hqd_hq_status1; /* ordinal163 */
2940 uint32_t cp_hqd_hq_control1; /* ordinal164 */
2941 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
2942 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
2943 uint32_t cp_hqd_eop_control; /* ordinal167 */
2944 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
2945 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
2946 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
2947 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
2948 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
2949 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
2950 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
2951 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
2952 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
2953 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
2954 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
2955 uint32_t cp_hqd_error; /* ordinal179 */
2956 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
2957 uint32_t cp_hqd_eop_dones; /* ordinal181 */
2958 uint32_t reserved46; /* ordinal182 */
2959 uint32_t reserved47; /* ordinal183 */
2960 uint32_t reserved48; /* ordinal184 */
2961 uint32_t reserved49; /* ordinal185 */
2962 uint32_t reserved50; /* ordinal186 */
2963 uint32_t reserved51; /* ordinal187 */
2964 uint32_t reserved52; /* ordinal188 */
2965 uint32_t reserved53; /* ordinal189 */
2966 uint32_t reserved54; /* ordinal190 */
2967 uint32_t reserved55; /* ordinal191 */
2968 uint32_t iqtimer_pkt_header; /* ordinal192 */
2969 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
2970 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
2971 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
2972 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
2973 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
2974 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
2975 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
2976 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
2977 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
2978 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
2979 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
2980 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
2981 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
2982 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
2983 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
2984 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
2985 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
2986 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
2987 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
2988 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
2989 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
2990 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
2991 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
2992 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
2993 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
2994 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
2995 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
2996 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
2997 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
2998 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
2999 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
3000 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
3001 uint32_t reserved56; /* ordinal225 */
3002 uint32_t reserved57; /* ordinal226 */
3003 uint32_t reserved58; /* ordinal227 */
3004 uint32_t set_resources_header; /* ordinal228 */
3005 uint32_t set_resources_dw1; /* ordinal229 */
3006 uint32_t set_resources_dw2; /* ordinal230 */
3007 uint32_t set_resources_dw3; /* ordinal231 */
3008 uint32_t set_resources_dw4; /* ordinal232 */
3009 uint32_t set_resources_dw5; /* ordinal233 */
3010 uint32_t set_resources_dw6; /* ordinal234 */
3011 uint32_t set_resources_dw7; /* ordinal235 */
3012 uint32_t reserved59; /* ordinal236 */
3013 uint32_t reserved60; /* ordinal237 */
3014 uint32_t reserved61; /* ordinal238 */
3015 uint32_t reserved62; /* ordinal239 */
3016 uint32_t reserved63; /* ordinal240 */
3017 uint32_t reserved64; /* ordinal241 */
3018 uint32_t reserved65; /* ordinal242 */
3019 uint32_t reserved66; /* ordinal243 */
3020 uint32_t reserved67; /* ordinal244 */
3021 uint32_t reserved68; /* ordinal245 */
3022 uint32_t reserved69; /* ordinal246 */
3023 uint32_t reserved70; /* ordinal247 */
3024 uint32_t reserved71; /* ordinal248 */
3025 uint32_t reserved72; /* ordinal249 */
3026 uint32_t reserved73; /* ordinal250 */
3027 uint32_t reserved74; /* ordinal251 */
3028 uint32_t reserved75; /* ordinal252 */
3029 uint32_t reserved76; /* ordinal253 */
3030 uint32_t reserved77; /* ordinal254 */
3031 uint32_t reserved78; /* ordinal255 */
3032
3033 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3034};
3035
3036static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3037{
3038 int i, r;
3039
3040 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3041 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3042
3043 if (ring->mqd_obj) {
3044 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3045 if (unlikely(r != 0))
3046 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3047
3048 amdgpu_bo_unpin(ring->mqd_obj);
3049 amdgpu_bo_unreserve(ring->mqd_obj);
3050
3051 amdgpu_bo_unref(&ring->mqd_obj);
3052 ring->mqd_obj = NULL;
3053 }
3054 }
3055}
3056
3057static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3058{
3059 int r, i, j;
3060 u32 tmp;
3061 bool use_doorbell = true;
3062 u64 hqd_gpu_addr;
3063 u64 mqd_gpu_addr;
3064 u64 eop_gpu_addr;
3065 u64 wb_gpu_addr;
3066 u32 *buf;
3067 struct vi_mqd *mqd;
3068
3069 /* init the pipes */
3070 mutex_lock(&adev->srbm_mutex);
3071 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3072 int me = (i < 4) ? 1 : 2;
3073 int pipe = (i < 4) ? i : (i - 4);
3074
3075 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3076 eop_gpu_addr >>= 8;
3077
3078 vi_srbm_select(adev, me, pipe, 0, 0);
3079
3080 /* write the EOP addr */
3081 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3082 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3083
3084 /* set the VMID assigned */
3085 WREG32(mmCP_HQD_VMID, 0);
3086
3087 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3088 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3089 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3090 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3091 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3092 }
3093 vi_srbm_select(adev, 0, 0, 0, 0);
3094 mutex_unlock(&adev->srbm_mutex);
3095
3096 /* init the queues. Just two for now. */
3097 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3098 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3099
3100 if (ring->mqd_obj == NULL) {
3101 r = amdgpu_bo_create(adev,
3102 sizeof(struct vi_mqd),
3103 PAGE_SIZE, true,
3104 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3105 &ring->mqd_obj);
3106 if (r) {
3107 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3108 return r;
3109 }
3110 }
3111
3112 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3113 if (unlikely(r != 0)) {
3114 gfx_v8_0_cp_compute_fini(adev);
3115 return r;
3116 }
3117 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3118 &mqd_gpu_addr);
3119 if (r) {
3120 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3121 gfx_v8_0_cp_compute_fini(adev);
3122 return r;
3123 }
3124 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3125 if (r) {
3126 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3127 gfx_v8_0_cp_compute_fini(adev);
3128 return r;
3129 }
3130
3131 /* init the mqd struct */
3132 memset(buf, 0, sizeof(struct vi_mqd));
3133
3134 mqd = (struct vi_mqd *)buf;
3135 mqd->header = 0xC0310800;
3136 mqd->compute_pipelinestat_enable = 0x00000001;
3137 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3138 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3139 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3140 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3141 mqd->compute_misc_reserved = 0x00000003;
3142
3143 mutex_lock(&adev->srbm_mutex);
3144 vi_srbm_select(adev, ring->me,
3145 ring->pipe,
3146 ring->queue, 0);
3147
3148 /* disable wptr polling */
3149 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3150 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3151 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3152
3153 mqd->cp_hqd_eop_base_addr_lo =
3154 RREG32(mmCP_HQD_EOP_BASE_ADDR);
3155 mqd->cp_hqd_eop_base_addr_hi =
3156 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3157
3158 /* enable doorbell? */
3159 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3160 if (use_doorbell) {
3161 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3162 } else {
3163 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3164 }
3165 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3166 mqd->cp_hqd_pq_doorbell_control = tmp;
3167
3168 /* disable the queue if it's active */
3169 mqd->cp_hqd_dequeue_request = 0;
3170 mqd->cp_hqd_pq_rptr = 0;
3171 mqd->cp_hqd_pq_wptr= 0;
3172 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3173 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3174 for (j = 0; j < adev->usec_timeout; j++) {
3175 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3176 break;
3177 udelay(1);
3178 }
3179 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3180 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3181 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3182 }
3183
3184 /* set the pointer to the MQD */
3185 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3186 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3187 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3188 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3189
3190 /* set MQD vmid to 0 */
3191 tmp = RREG32(mmCP_MQD_CONTROL);
3192 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3193 WREG32(mmCP_MQD_CONTROL, tmp);
3194 mqd->cp_mqd_control = tmp;
3195
3196 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3197 hqd_gpu_addr = ring->gpu_addr >> 8;
3198 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3199 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3200 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3201 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3202
3203 /* set up the HQD, this is similar to CP_RB0_CNTL */
3204 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3205 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3206 (order_base_2(ring->ring_size / 4) - 1));
3207 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3208 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3209#ifdef __BIG_ENDIAN
3210 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3211#endif
3212 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3213 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3214 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3215 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3216 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3217 mqd->cp_hqd_pq_control = tmp;
3218
3219 /* set the wb address wether it's enabled or not */
3220 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3221 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3222 mqd->cp_hqd_pq_rptr_report_addr_hi =
3223 upper_32_bits(wb_gpu_addr) & 0xffff;
3224 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3225 mqd->cp_hqd_pq_rptr_report_addr_lo);
3226 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3227 mqd->cp_hqd_pq_rptr_report_addr_hi);
3228
3229 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3230 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3231 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3232 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3233 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3234 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3235 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3236
3237 /* enable the doorbell if requested */
3238 if (use_doorbell) {
3239 if (adev->asic_type == CHIP_CARRIZO) {
3240 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3241 AMDGPU_DOORBELL_KIQ << 2);
3242 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
b8826b0c 3243 AMDGPU_DOORBELL_MEC_RING7 << 2);
aaa36a97
AD		 3244 }
3245 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3246 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3247 DOORBELL_OFFSET, ring->doorbell_index);
3248 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3249 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3250 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3251 mqd->cp_hqd_pq_doorbell_control = tmp;
3252
3253 } else {
3254 mqd->cp_hqd_pq_doorbell_control = 0;
3255 }
3256 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3257 mqd->cp_hqd_pq_doorbell_control);
3258
845253e7
SJ		 3259 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3260 ring->wptr = 0;
3261 mqd->cp_hqd_pq_wptr = ring->wptr;
3262 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3263 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3264
aaa36a97
AD		 3265 /* set the vmid for the queue */
3266 mqd->cp_hqd_vmid = 0;
3267 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3268
3269 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3270 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3271 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3272 mqd->cp_hqd_persistent_state = tmp;
3273
3274 /* activate the queue */
3275 mqd->cp_hqd_active = 1;
3276 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3277
3278 vi_srbm_select(adev, 0, 0, 0, 0);
3279 mutex_unlock(&adev->srbm_mutex);
3280
3281 amdgpu_bo_kunmap(ring->mqd_obj);
3282 amdgpu_bo_unreserve(ring->mqd_obj);
3283 }
3284
3285 if (use_doorbell) {
3286 tmp = RREG32(mmCP_PQ_STATUS);
3287 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3288 WREG32(mmCP_PQ_STATUS, tmp);
3289 }
3290
3291 r = gfx_v8_0_cp_compute_start(adev);
3292 if (r)
3293 return r;
3294
3295 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3296 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3297
3298 ring->ready = true;
3299 r = amdgpu_ring_test_ring(ring);
3300 if (r)
3301 ring->ready = false;
3302 }
3303
3304 return 0;
3305}
3306
3307static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3308{
3309 int r;
3310
3311 if (adev->asic_type != CHIP_CARRIZO)
3312 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3313
3314 if (!adev->firmware.smu_load) {
3315 /* legacy firmware loading */
3316 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3317 if (r)
3318 return r;
3319
3320 r = gfx_v8_0_cp_compute_load_microcode(adev);
3321 if (r)
3322 return r;
3323 } else {
3324 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3325 AMDGPU_UCODE_ID_CP_CE);
3326 if (r)
3327 return -EINVAL;
3328
3329 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3330 AMDGPU_UCODE_ID_CP_PFP);
3331 if (r)
3332 return -EINVAL;
3333
3334 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3335 AMDGPU_UCODE_ID_CP_ME);
3336 if (r)
3337 return -EINVAL;
3338
3339 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3340 AMDGPU_UCODE_ID_CP_MEC1);
3341 if (r)
3342 return -EINVAL;
3343 }
3344
3345 r = gfx_v8_0_cp_gfx_resume(adev);
3346 if (r)
3347 return r;
3348
3349 r = gfx_v8_0_cp_compute_resume(adev);
3350 if (r)
3351 return r;
3352
3353 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3354
3355 return 0;
3356}
3357
3358static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3359{
3360 gfx_v8_0_cp_gfx_enable(adev, enable);
3361 gfx_v8_0_cp_compute_enable(adev, enable);
3362}
3363
5fc3aeeb 3364static int gfx_v8_0_hw_init(void *handle)
aaa36a97
AD		 3365{
3366 int r;
5fc3aeeb 3367 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3368
3369 gfx_v8_0_init_golden_registers(adev);
3370
3371 gfx_v8_0_gpu_init(adev);
3372
3373 r = gfx_v8_0_rlc_resume(adev);
3374 if (r)
3375 return r;
3376
3377 r = gfx_v8_0_cp_resume(adev);
3378 if (r)
3379 return r;
3380
3381 return r;
3382}
3383
5fc3aeeb 3384static int gfx_v8_0_hw_fini(void *handle)
aaa36a97 3385{
5fc3aeeb 3386 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3387
aaa36a97
AD		 3388 gfx_v8_0_cp_enable(adev, false);
3389 gfx_v8_0_rlc_stop(adev);
3390 gfx_v8_0_cp_compute_fini(adev);
3391
3392 return 0;
3393}
3394
5fc3aeeb 3395static int gfx_v8_0_suspend(void *handle)
aaa36a97 3396{
5fc3aeeb 3397 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3398
aaa36a97
AD		 3399 return gfx_v8_0_hw_fini(adev);
3400}
3401
5fc3aeeb 3402static int gfx_v8_0_resume(void *handle)
aaa36a97 3403{
5fc3aeeb 3404 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3405
aaa36a97
AD		 3406 return gfx_v8_0_hw_init(adev);
3407}
3408
5fc3aeeb 3409static bool gfx_v8_0_is_idle(void *handle)
aaa36a97 3410{
5fc3aeeb 3411 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3412
aaa36a97
AD		 3413 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3414 return false;
3415 else
3416 return true;
3417}
3418
5fc3aeeb 3419static int gfx_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 3420{
3421 unsigned i;
3422 u32 tmp;
5fc3aeeb 3423 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3424
3425 for (i = 0; i < adev->usec_timeout; i++) {
3426 /* read MC_STATUS */
3427 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3428
3429 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3430 return 0;
3431 udelay(1);
3432 }
3433 return -ETIMEDOUT;
3434}
3435
5fc3aeeb 3436static void gfx_v8_0_print_status(void *handle)
aaa36a97
AD		 3437{
3438 int i;
5fc3aeeb 3439 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3440
3441 dev_info(adev->dev, "GFX 8.x registers\n");
3442 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3443 RREG32(mmGRBM_STATUS));
3444 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3445 RREG32(mmGRBM_STATUS2));
3446 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3447 RREG32(mmGRBM_STATUS_SE0));
3448 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3449 RREG32(mmGRBM_STATUS_SE1));
3450 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3451 RREG32(mmGRBM_STATUS_SE2));
3452 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3453 RREG32(mmGRBM_STATUS_SE3));
3454 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3455 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3456 RREG32(mmCP_STALLED_STAT1));
3457 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3458 RREG32(mmCP_STALLED_STAT2));
3459 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3460 RREG32(mmCP_STALLED_STAT3));
3461 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3462 RREG32(mmCP_CPF_BUSY_STAT));
3463 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3464 RREG32(mmCP_CPF_STALLED_STAT1));
3465 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3466 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3467 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3468 RREG32(mmCP_CPC_STALLED_STAT1));
3469 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3470
3471 for (i = 0; i < 32; i++) {
3472 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3473 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3474 }
3475 for (i = 0; i < 16; i++) {
3476 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3477 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3478 }
3479 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3480 dev_info(adev->dev, " se: %d\n", i);
3481 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3482 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3483 RREG32(mmPA_SC_RASTER_CONFIG));
3484 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3485 RREG32(mmPA_SC_RASTER_CONFIG_1));
3486 }
3487 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3488
3489 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3490 RREG32(mmGB_ADDR_CONFIG));
3491 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3492 RREG32(mmHDP_ADDR_CONFIG));
3493 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3494 RREG32(mmDMIF_ADDR_CALC));
3495 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
3496 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3497 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
3498 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3499 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3500 RREG32(mmUVD_UDEC_ADDR_CONFIG));
3501 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3502 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3503 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3504 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3505
3506 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3507 RREG32(mmCP_MEQ_THRESHOLDS));
3508 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3509 RREG32(mmSX_DEBUG_1));
3510 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3511 RREG32(mmTA_CNTL_AUX));
3512 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3513 RREG32(mmSPI_CONFIG_CNTL));
3514 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3515 RREG32(mmSQ_CONFIG));
3516 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3517 RREG32(mmDB_DEBUG));
3518 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3519 RREG32(mmDB_DEBUG2));
3520 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3521 RREG32(mmDB_DEBUG3));
3522 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3523 RREG32(mmCB_HW_CONTROL));
3524 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3525 RREG32(mmSPI_CONFIG_CNTL_1));
3526 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3527 RREG32(mmPA_SC_FIFO_SIZE));
3528 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3529 RREG32(mmVGT_NUM_INSTANCES));
3530 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3531 RREG32(mmCP_PERFMON_CNTL));
3532 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3533 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3534 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3535 RREG32(mmVGT_CACHE_INVALIDATION));
3536 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3537 RREG32(mmVGT_GS_VERTEX_REUSE));
3538 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3539 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3540 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3541 RREG32(mmPA_CL_ENHANCE));
3542 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3543 RREG32(mmPA_SC_ENHANCE));
3544
3545 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3546 RREG32(mmCP_ME_CNTL));
3547 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3548 RREG32(mmCP_MAX_CONTEXT));
3549 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3550 RREG32(mmCP_ENDIAN_SWAP));
3551 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3552 RREG32(mmCP_DEVICE_ID));
3553
3554 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
3555 RREG32(mmCP_SEM_WAIT_TIMER));
3556
3557 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
3558 RREG32(mmCP_RB_WPTR_DELAY));
3559 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
3560 RREG32(mmCP_RB_VMID));
3561 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3562 RREG32(mmCP_RB0_CNTL));
3563 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
3564 RREG32(mmCP_RB0_WPTR));
3565 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
3566 RREG32(mmCP_RB0_RPTR_ADDR));
3567 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3568 RREG32(mmCP_RB0_RPTR_ADDR_HI));
3569 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3570 RREG32(mmCP_RB0_CNTL));
3571 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
3572 RREG32(mmCP_RB0_BASE));
3573 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
3574 RREG32(mmCP_RB0_BASE_HI));
3575 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
3576 RREG32(mmCP_MEC_CNTL));
3577 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
3578 RREG32(mmCP_CPF_DEBUG));
3579
3580 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
3581 RREG32(mmSCRATCH_ADDR));
3582 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
3583 RREG32(mmSCRATCH_UMSK));
3584
3585 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
3586 RREG32(mmCP_INT_CNTL_RING0));
3587 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3588 RREG32(mmRLC_LB_CNTL));
3589 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
3590 RREG32(mmRLC_CNTL));
3591 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
3592 RREG32(mmRLC_CGCG_CGLS_CTRL));
3593 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
3594 RREG32(mmRLC_LB_CNTR_INIT));
3595 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
3596 RREG32(mmRLC_LB_CNTR_MAX));
3597 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
3598 RREG32(mmRLC_LB_INIT_CU_MASK));
3599 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
3600 RREG32(mmRLC_LB_PARAMS));
3601 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3602 RREG32(mmRLC_LB_CNTL));
3603 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
3604 RREG32(mmRLC_MC_CNTL));
3605 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
3606 RREG32(mmRLC_UCODE_CNTL));
3607
3608 mutex_lock(&adev->srbm_mutex);
3609 for (i = 0; i < 16; i++) {
3610 vi_srbm_select(adev, 0, 0, 0, i);
3611 dev_info(adev->dev, " VM %d:\n", i);
3612 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
3613 RREG32(mmSH_MEM_CONFIG));
3614 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
3615 RREG32(mmSH_MEM_APE1_BASE));
3616 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
3617 RREG32(mmSH_MEM_APE1_LIMIT));
3618 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
3619 RREG32(mmSH_MEM_BASES));
3620 }
3621 vi_srbm_select(adev, 0, 0, 0, 0);
3622 mutex_unlock(&adev->srbm_mutex);
3623}
3624
5fc3aeeb 3625static int gfx_v8_0_soft_reset(void *handle)
aaa36a97
AD		 3626{
3627 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3628 u32 tmp;
5fc3aeeb 3629 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3630
3631 /* GRBM_STATUS */
3632 tmp = RREG32(mmGRBM_STATUS);
3633 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3634 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3635 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3636 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3637 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3638 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3639 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3640 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3641 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3642 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3643 }
3644
3645 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3646 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3647 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3648 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3649 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3650 }
3651
3652 /* GRBM_STATUS2 */
3653 tmp = RREG32(mmGRBM_STATUS2);
3654 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3655 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3656 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3657
3658 /* SRBM_STATUS */
3659 tmp = RREG32(mmSRBM_STATUS);
3660 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3661 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3662 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3663
3664 if (grbm_soft_reset || srbm_soft_reset) {
5fc3aeeb 3665 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 3666 /* stop the rlc */
3667 gfx_v8_0_rlc_stop(adev);
3668
3669 /* Disable GFX parsing/prefetching */
3670 gfx_v8_0_cp_gfx_enable(adev, false);
3671
3672 /* Disable MEC parsing/prefetching */
3673 /* XXX todo */
3674
3675 if (grbm_soft_reset) {
3676 tmp = RREG32(mmGRBM_SOFT_RESET);
3677 tmp |= grbm_soft_reset;
3678 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3679 WREG32(mmGRBM_SOFT_RESET, tmp);
3680 tmp = RREG32(mmGRBM_SOFT_RESET);
3681
3682 udelay(50);
3683
3684 tmp &= ~grbm_soft_reset;
3685 WREG32(mmGRBM_SOFT_RESET, tmp);
3686 tmp = RREG32(mmGRBM_SOFT_RESET);
3687 }
3688
3689 if (srbm_soft_reset) {
3690 tmp = RREG32(mmSRBM_SOFT_RESET);
3691 tmp |= srbm_soft_reset;
3692 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3693 WREG32(mmSRBM_SOFT_RESET, tmp);
3694 tmp = RREG32(mmSRBM_SOFT_RESET);
3695
3696 udelay(50);
3697
3698 tmp &= ~srbm_soft_reset;
3699 WREG32(mmSRBM_SOFT_RESET, tmp);
3700 tmp = RREG32(mmSRBM_SOFT_RESET);
3701 }
3702 /* Wait a little for things to settle down */
3703 udelay(50);
5fc3aeeb 3704 gfx_v8_0_print_status((void *)adev);
aaa36a97
AD		 3705 }
3706 return 0;
3707}
3708
3709/**
3710 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3711 *
3712 * @adev: amdgpu_device pointer
3713 *
3714 * Fetches a GPU clock counter snapshot.
3715 * Returns the 64 bit clock counter snapshot.
3716 */
3717uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3718{
3719 uint64_t clock;
3720
3721 mutex_lock(&adev->gfx.gpu_clock_mutex);
3722 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3723 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3724 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3725 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3726 return clock;
3727}
3728
3729static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3730 uint32_t vmid,
3731 uint32_t gds_base, uint32_t gds_size,
3732 uint32_t gws_base, uint32_t gws_size,
3733 uint32_t oa_base, uint32_t oa_size)
3734{
3735 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3736 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3737
3738 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3739 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3740
3741 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3742 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3743
3744 /* GDS Base */
3745 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3746 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3747 WRITE_DATA_DST_SEL(0)));
3748 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3749 amdgpu_ring_write(ring, 0);
3750 amdgpu_ring_write(ring, gds_base);
3751
3752 /* GDS Size */
3753 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3754 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3755 WRITE_DATA_DST_SEL(0)));
3756 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3757 amdgpu_ring_write(ring, 0);
3758 amdgpu_ring_write(ring, gds_size);
3759
3760 /* GWS */
3761 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3762 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3763 WRITE_DATA_DST_SEL(0)));
3764 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3765 amdgpu_ring_write(ring, 0);
3766 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3767
3768 /* OA */
3769 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3770 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3771 WRITE_DATA_DST_SEL(0)));
3772 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3773 amdgpu_ring_write(ring, 0);
3774 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3775}
3776
5fc3aeeb 3777static int gfx_v8_0_early_init(void *handle)
aaa36a97 3778{
5fc3aeeb 3779 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 3780
3781 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3782 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3783 gfx_v8_0_set_ring_funcs(adev);
3784 gfx_v8_0_set_irq_funcs(adev);
3785 gfx_v8_0_set_gds_init(adev);
3786
3787 return 0;
3788}
3789
5fc3aeeb 3790static int gfx_v8_0_set_powergating_state(void *handle,
3791 enum amd_powergating_state state)
aaa36a97
AD		 3792{
3793 return 0;
3794}
3795
5fc3aeeb 3796static int gfx_v8_0_set_clockgating_state(void *handle,
3797 enum amd_clockgating_state state)
aaa36a97
AD		 3798{
3799 return 0;
3800}
3801
3802static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3803{
3804 u32 rptr;
3805
3806 rptr = ring->adev->wb.wb[ring->rptr_offs];
3807
3808 return rptr;
3809}
3810
3811static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3812{
3813 struct amdgpu_device *adev = ring->adev;
3814 u32 wptr;
3815
3816 if (ring->use_doorbell)
3817 /* XXX check if swapping is necessary on BE */
3818 wptr = ring->adev->wb.wb[ring->wptr_offs];
3819 else
3820 wptr = RREG32(mmCP_RB0_WPTR);
3821
3822 return wptr;
3823}
3824
3825static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3826{
3827 struct amdgpu_device *adev = ring->adev;
3828
3829 if (ring->use_doorbell) {
3830 /* XXX check if swapping is necessary on BE */
3831 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3832 WDOORBELL32(ring->doorbell_index, ring->wptr);
3833 } else {
3834 WREG32(mmCP_RB0_WPTR, ring->wptr);
3835 (void)RREG32(mmCP_RB0_WPTR);
3836 }
3837}
3838
d2edb07b 3839static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
aaa36a97
AD		 3840{
3841 u32 ref_and_mask, reg_mem_engine;
3842
3843 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3844 switch (ring->me) {
3845 case 1:
3846 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3847 break;
3848 case 2:
3849 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3850 break;
3851 default:
3852 return;
3853 }
3854 reg_mem_engine = 0;
3855 } else {
3856 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3857 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3858 }
3859
3860 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3861 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3862 WAIT_REG_MEM_FUNCTION(3) | /* == */
3863 reg_mem_engine));
3864 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3865 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3866 amdgpu_ring_write(ring, ref_and_mask);
3867 amdgpu_ring_write(ring, ref_and_mask);
3868 amdgpu_ring_write(ring, 0x20); /* poll interval */
3869}
3870
93323131 3871static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
aaa36a97
AD		 3872 struct amdgpu_ib *ib)
3873{
3cb485f3 3874 bool need_ctx_switch = ring->current_ctx != ib->ctx;
aaa36a97
AD		 3875 u32 header, control = 0;
3876 u32 next_rptr = ring->wptr + 5;
aa2bdb24
JZ		 3877
3878 /* drop the CE preamble IB for the same context */
93323131 3879 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
aa2bdb24
JZ		 3880 return;
3881
93323131 3882 if (need_ctx_switch)
aaa36a97
AD		 3883 next_rptr += 2;
3884
3885 next_rptr += 4;
3886 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3887 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3888 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3889 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3890 amdgpu_ring_write(ring, next_rptr);
3891
aaa36a97 3892 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
93323131 3893 if (need_ctx_switch) {
aaa36a97
AD		 3894 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3895 amdgpu_ring_write(ring, 0);
aaa36a97
AD		 3896 }
3897
de807f81 3898 if (ib->flags & AMDGPU_IB_FLAG_CE)
aaa36a97
AD		 3899 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3900 else
3901 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3902
3903 control |= ib->length_dw |
3904 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3905
3906 amdgpu_ring_write(ring, header);
3907 amdgpu_ring_write(ring,
3908#ifdef __BIG_ENDIAN
3909 (2 << 0) |
3910#endif
3911 (ib->gpu_addr & 0xFFFFFFFC));
3912 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3913 amdgpu_ring_write(ring, control);
3914}
3915
93323131 3916static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3917 struct amdgpu_ib *ib)
3918{
3919 u32 header, control = 0;
3920 u32 next_rptr = ring->wptr + 5;
3921
3922 control |= INDIRECT_BUFFER_VALID;
3923
3924 next_rptr += 4;
3925 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3926 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3927 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3928 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3929 amdgpu_ring_write(ring, next_rptr);
3930
3931 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3932
3933 control |= ib->length_dw |
3934 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3935
3936 amdgpu_ring_write(ring, header);
3937 amdgpu_ring_write(ring,
3938#ifdef __BIG_ENDIAN
3939 (2 << 0) |
3940#endif
3941 (ib->gpu_addr & 0xFFFFFFFC));
3942 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3943 amdgpu_ring_write(ring, control);
3944}
3945
aaa36a97 3946static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
890ee23f 3947 u64 seq, unsigned flags)
aaa36a97 3948{
890ee23f
CZ		 3949 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3950 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3951
aaa36a97
AD		 3952 /* EVENT_WRITE_EOP - flush caches, send int */
3953 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3954 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3955 EOP_TC_ACTION_EN |
3956 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3957 EVENT_INDEX(5)));
3958 amdgpu_ring_write(ring, addr & 0xfffffffc);
3959 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
890ee23f 3960 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 3961 amdgpu_ring_write(ring, lower_32_bits(seq));
3962 amdgpu_ring_write(ring, upper_32_bits(seq));
3963}
3964
3965/**
3966 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3967 *
3968 * @ring: amdgpu ring buffer object
3969 * @semaphore: amdgpu semaphore object
3970 * @emit_wait: Is this a sempahore wait?
3971 *
3972 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3973 * from running ahead of semaphore waits.
3974 */
3975static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3976 struct amdgpu_semaphore *semaphore,
3977 bool emit_wait)
3978{
3979 uint64_t addr = semaphore->gpu_addr;
3980 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3981
3982 if (ring->adev->asic_type == CHIP_TOPAZ ||
af15a2d5
DZ		 3983 ring->adev->asic_type == CHIP_TONGA ||
3984 ring->adev->asic_type == CHIP_FIJI)
147dbfbc
DZ		 3985 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3986 return false;
3987 else {
aaa36a97
AD		 3988 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3989 amdgpu_ring_write(ring, lower_32_bits(addr));
3990 amdgpu_ring_write(ring, upper_32_bits(addr));
3991 amdgpu_ring_write(ring, sel);
3992 }
3993
3994 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3995 /* Prevent the PFP from running ahead of the semaphore wait */
3996 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3997 amdgpu_ring_write(ring, 0x0);
3998 }
3999
4000 return true;
4001}
4002
4003static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
4004{
4005 struct amdgpu_device *adev = ring->adev;
4006 u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
4007
4008 /* instruct DE to set a magic number */
4009 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4010 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4011 WRITE_DATA_DST_SEL(5)));
4012 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4013 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4014 amdgpu_ring_write(ring, 1);
4015
4016 /* let CE wait till condition satisfied */
4017 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4018 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4019 WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4020 WAIT_REG_MEM_FUNCTION(3) | /* == */
4021 WAIT_REG_MEM_ENGINE(2))); /* ce */
4022 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4023 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4024 amdgpu_ring_write(ring, 1);
4025 amdgpu_ring_write(ring, 0xffffffff);
4026 amdgpu_ring_write(ring, 4); /* poll interval */
4027
4028 /* instruct CE to reset wb of ce_sync to zero */
4029 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4030 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4031 WRITE_DATA_DST_SEL(5) |
4032 WR_CONFIRM));
4033 amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
4034 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
4035 amdgpu_ring_write(ring, 0);
4036}
4037
4038static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4039 unsigned vm_id, uint64_t pd_addr)
4040{
4041 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
aaa36a97
AD		 4042
4043 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4044 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4045 WRITE_DATA_DST_SEL(0)));
4046 if (vm_id < 8) {
4047 amdgpu_ring_write(ring,
4048 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4049 } else {
4050 amdgpu_ring_write(ring,
4051 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4052 }
4053 amdgpu_ring_write(ring, 0);
4054 amdgpu_ring_write(ring, pd_addr >> 12);
4055
aaa36a97
AD		 4056 /* bits 0-15 are the VM contexts0-15 */
4057 /* invalidate the cache */
4058 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4059 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4060 WRITE_DATA_DST_SEL(0)));
4061 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4062 amdgpu_ring_write(ring, 0);
4063 amdgpu_ring_write(ring, 1 << vm_id);
4064
4065 /* wait for the invalidate to complete */
4066 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4067 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4068 WAIT_REG_MEM_FUNCTION(0) | /* always */
4069 WAIT_REG_MEM_ENGINE(0))); /* me */
4070 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4071 amdgpu_ring_write(ring, 0);
4072 amdgpu_ring_write(ring, 0); /* ref */
4073 amdgpu_ring_write(ring, 0); /* mask */
4074 amdgpu_ring_write(ring, 0x20); /* poll interval */
4075
4076 /* compute doesn't have PFP */
4077 if (usepfp) {
4078 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4079 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4080 amdgpu_ring_write(ring, 0x0);
4081
4082 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4083 gfx_v8_0_ce_sync_me(ring);
4084 }
4085}
4086
4087static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
4088{
4089 if (gfx_v8_0_is_idle(ring->adev)) {
4090 amdgpu_ring_lockup_update(ring);
4091 return false;
4092 }
4093 return amdgpu_ring_test_lockup(ring);
4094}
4095
4096static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4097{
4098 return ring->adev->wb.wb[ring->rptr_offs];
4099}
4100
4101static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4102{
4103 return ring->adev->wb.wb[ring->wptr_offs];
4104}
4105
4106static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4107{
4108 struct amdgpu_device *adev = ring->adev;
4109
4110 /* XXX check if swapping is necessary on BE */
4111 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4112 WDOORBELL32(ring->doorbell_index, ring->wptr);
4113}
4114
4115static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4116 u64 addr, u64 seq,
890ee23f 4117 unsigned flags)
aaa36a97 4118{
890ee23f
CZ		 4119 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4120 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4121
aaa36a97
AD		 4122 /* RELEASE_MEM - flush caches, send int */
4123 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4124 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4125 EOP_TC_ACTION_EN |
4126 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4127 EVENT_INDEX(5)));
890ee23f 4128 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
aaa36a97
AD		 4129 amdgpu_ring_write(ring, addr & 0xfffffffc);
4130 amdgpu_ring_write(ring, upper_32_bits(addr));
4131 amdgpu_ring_write(ring, lower_32_bits(seq));
4132 amdgpu_ring_write(ring, upper_32_bits(seq));
4133}
4134
4135static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4136 enum amdgpu_interrupt_state state)
4137{
4138 u32 cp_int_cntl;
4139
4140 switch (state) {
4141 case AMDGPU_IRQ_STATE_DISABLE:
4142 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4143 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4144 TIME_STAMP_INT_ENABLE, 0);
4145 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4146 break;
4147 case AMDGPU_IRQ_STATE_ENABLE:
4148 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4149 cp_int_cntl =
4150 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4151 TIME_STAMP_INT_ENABLE, 1);
4152 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4153 break;
4154 default:
4155 break;
4156 }
4157}
4158
4159static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4160 int me, int pipe,
4161 enum amdgpu_interrupt_state state)
4162{
4163 u32 mec_int_cntl, mec_int_cntl_reg;
4164
4165 /*
4166 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4167 * handles the setting of interrupts for this specific pipe. All other
4168 * pipes' interrupts are set by amdkfd.
4169 */
4170
4171 if (me == 1) {
4172 switch (pipe) {
4173 case 0:
4174 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4175 break;
4176 default:
4177 DRM_DEBUG("invalid pipe %d\n", pipe);
4178 return;
4179 }
4180 } else {
4181 DRM_DEBUG("invalid me %d\n", me);
4182 return;
4183 }
4184
4185 switch (state) {
4186 case AMDGPU_IRQ_STATE_DISABLE:
4187 mec_int_cntl = RREG32(mec_int_cntl_reg);
4188 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4189 TIME_STAMP_INT_ENABLE, 0);
4190 WREG32(mec_int_cntl_reg, mec_int_cntl);
4191 break;
4192 case AMDGPU_IRQ_STATE_ENABLE:
4193 mec_int_cntl = RREG32(mec_int_cntl_reg);
4194 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4195 TIME_STAMP_INT_ENABLE, 1);
4196 WREG32(mec_int_cntl_reg, mec_int_cntl);
4197 break;
4198 default:
4199 break;
4200 }
4201}
4202
4203static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4204 struct amdgpu_irq_src *source,
4205 unsigned type,
4206 enum amdgpu_interrupt_state state)
4207{
4208 u32 cp_int_cntl;
4209
4210 switch (state) {
4211 case AMDGPU_IRQ_STATE_DISABLE:
4212 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4213 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4214 PRIV_REG_INT_ENABLE, 0);
4215 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4216 break;
4217 case AMDGPU_IRQ_STATE_ENABLE:
4218 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4219 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4220 PRIV_REG_INT_ENABLE, 0);
4221 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4222 break;
4223 default:
4224 break;
4225 }
4226
4227 return 0;
4228}
4229
4230static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4231 struct amdgpu_irq_src *source,
4232 unsigned type,
4233 enum amdgpu_interrupt_state state)
4234{
4235 u32 cp_int_cntl;
4236
4237 switch (state) {
4238 case AMDGPU_IRQ_STATE_DISABLE:
4239 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4240 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4241 PRIV_INSTR_INT_ENABLE, 0);
4242 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4243 break;
4244 case AMDGPU_IRQ_STATE_ENABLE:
4245 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4246 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4247 PRIV_INSTR_INT_ENABLE, 1);
4248 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4249 break;
4250 default:
4251 break;
4252 }
4253
4254 return 0;
4255}
4256
4257static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4258 struct amdgpu_irq_src *src,
4259 unsigned type,
4260 enum amdgpu_interrupt_state state)
4261{
4262 switch (type) {
4263 case AMDGPU_CP_IRQ_GFX_EOP:
4264 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4265 break;
4266 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4267 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4268 break;
4269 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4270 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4271 break;
4272 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4273 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4274 break;
4275 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4276 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4277 break;
4278 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4279 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4280 break;
4281 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4282 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4283 break;
4284 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4285 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4286 break;
4287 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4288 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4289 break;
4290 default:
4291 break;
4292 }
4293 return 0;
4294}
4295
4296static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4297 struct amdgpu_irq_src *source,
4298 struct amdgpu_iv_entry *entry)
4299{
4300 int i;
4301 u8 me_id, pipe_id, queue_id;
4302 struct amdgpu_ring *ring;
4303
4304 DRM_DEBUG("IH: CP EOP\n");
4305 me_id = (entry->ring_id & 0x0c) >> 2;
4306 pipe_id = (entry->ring_id & 0x03) >> 0;
4307 queue_id = (entry->ring_id & 0x70) >> 4;
4308
4309 switch (me_id) {
4310 case 0:
4311 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4312 break;
4313 case 1:
4314 case 2:
4315 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4316 ring = &adev->gfx.compute_ring[i];
4317 /* Per-queue interrupt is supported for MEC starting from VI.
4318 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4319 */
4320 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4321 amdgpu_fence_process(ring);
4322 }
4323 break;
4324 }
4325 return 0;
4326}
4327
4328static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4329 struct amdgpu_irq_src *source,
4330 struct amdgpu_iv_entry *entry)
4331{
4332 DRM_ERROR("Illegal register access in command stream\n");
4333 schedule_work(&adev->reset_work);
4334 return 0;
4335}
4336
4337static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4338 struct amdgpu_irq_src *source,
4339 struct amdgpu_iv_entry *entry)
4340{
4341 DRM_ERROR("Illegal instruction in command stream\n");
4342 schedule_work(&adev->reset_work);
4343 return 0;
4344}
4345
5fc3aeeb 4346const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
aaa36a97
AD		 4347 .early_init = gfx_v8_0_early_init,
4348 .late_init = NULL,
4349 .sw_init = gfx_v8_0_sw_init,
4350 .sw_fini = gfx_v8_0_sw_fini,
4351 .hw_init = gfx_v8_0_hw_init,
4352 .hw_fini = gfx_v8_0_hw_fini,
4353 .suspend = gfx_v8_0_suspend,
4354 .resume = gfx_v8_0_resume,
4355 .is_idle = gfx_v8_0_is_idle,
4356 .wait_for_idle = gfx_v8_0_wait_for_idle,
4357 .soft_reset = gfx_v8_0_soft_reset,
4358 .print_status = gfx_v8_0_print_status,
4359 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4360 .set_powergating_state = gfx_v8_0_set_powergating_state,
4361};
4362
4363static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4364 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4365 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4366 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4367 .parse_cs = NULL,
93323131 4368 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
aaa36a97
AD		 4369 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4370 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4371 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4372 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
d2edb07b 4373 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
aaa36a97
AD		 4374 .test_ring = gfx_v8_0_ring_test_ring,
4375 .test_ib = gfx_v8_0_ring_test_ib,
4376 .is_lockup = gfx_v8_0_ring_is_lockup,
4377};
4378
4379static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4380 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4381 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4382 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4383 .parse_cs = NULL,
93323131 4384 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
aaa36a97
AD		 4385 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4386 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4387 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4388 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
35074d2d 4389 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
aaa36a97
AD		 4390 .test_ring = gfx_v8_0_ring_test_ring,
4391 .test_ib = gfx_v8_0_ring_test_ib,
4392 .is_lockup = gfx_v8_0_ring_is_lockup,
4393};
4394
4395static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4396{
4397 int i;
4398
4399 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4400 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4401
4402 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4403 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4404}
4405
4406static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4407 .set = gfx_v8_0_set_eop_interrupt_state,
4408 .process = gfx_v8_0_eop_irq,
4409};
4410
4411static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4412 .set = gfx_v8_0_set_priv_reg_fault_state,
4413 .process = gfx_v8_0_priv_reg_irq,
4414};
4415
4416static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4417 .set = gfx_v8_0_set_priv_inst_fault_state,
4418 .process = gfx_v8_0_priv_inst_irq,
4419};
4420
4421static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4422{
4423 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4424 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4425
4426 adev->gfx.priv_reg_irq.num_types = 1;
4427 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4428
4429 adev->gfx.priv_inst_irq.num_types = 1;
4430 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4431}
4432
4433static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4434{
4435 /* init asci gds info */
4436 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4437 adev->gds.gws.total_size = 64;
4438 adev->gds.oa.total_size = 16;
4439
4440 if (adev->gds.mem.total_size == 64 * 1024) {
4441 adev->gds.mem.gfx_partition_size = 4096;
4442 adev->gds.mem.cs_partition_size = 4096;
4443
4444 adev->gds.gws.gfx_partition_size = 4;
4445 adev->gds.gws.cs_partition_size = 4;
4446
4447 adev->gds.oa.gfx_partition_size = 4;
4448 adev->gds.oa.cs_partition_size = 1;
4449 } else {
4450 adev->gds.mem.gfx_partition_size = 1024;
4451 adev->gds.mem.cs_partition_size = 1024;
4452
4453 adev->gds.gws.gfx_partition_size = 16;
4454 adev->gds.gws.cs_partition_size = 16;
4455
4456 adev->gds.oa.gfx_partition_size = 4;
4457 adev->gds.oa.cs_partition_size = 4;
4458 }
4459}
4460
4461static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4462 u32 se, u32 sh)
4463{
4464 u32 mask = 0, tmp, tmp1;
4465 int i;
4466
4467 gfx_v8_0_select_se_sh(adev, se, sh);
4468 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4469 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4470 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4471
4472 tmp &= 0xffff0000;
4473
4474 tmp |= tmp1;
4475 tmp >>= 16;
4476
4477 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4478 mask <<= 1;
4479 mask |= 1;
4480 }
4481
4482 return (~tmp) & mask;
4483}
4484
4485int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4486 struct amdgpu_cu_info *cu_info)
4487{
4488 int i, j, k, counter, active_cu_number = 0;
4489 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4490
4491 if (!adev || !cu_info)
4492 return -EINVAL;
4493
4494 mutex_lock(&adev->grbm_idx_mutex);
4495 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4496 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4497 mask = 1;
4498 ao_bitmap = 0;
4499 counter = 0;
4500 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4501 cu_info->bitmap[i][j] = bitmap;
4502
4503 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4504 if (bitmap & mask) {
4505 if (counter < 2)
4506 ao_bitmap |= mask;
4507 counter ++;
4508 }
4509 mask <<= 1;
4510 }
4511 active_cu_number += counter;
4512 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4513 }
4514 }
4515
4516 cu_info->number = active_cu_number;
4517 cu_info->ao_cu_mask = ao_cu_mask;
4518 mutex_unlock(&adev->grbm_idx_mutex);
4519 return 0;
4520}
Linux kernel - Deliverables
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