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Merge remote-tracking branch 'iommu/next'
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / gmc_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v8_0.h"
27#include "amdgpu_ucode.h"
28
29#include "gmc/gmc_8_1_d.h"
30#include "gmc/gmc_8_1_sh_mask.h"
31
32#include "bif/bif_5_0_d.h"
33#include "bif/bif_5_0_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "vid.h"
39#include "vi.h"
40
81c59f54 41
aaa36a97
AD		 42static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
34e3205e 44static int gmc_v8_0_wait_for_idle(void *handle);
aaa36a97 45
c65444fe 46MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
2cc0c0b5
FC		 47MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
48MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
aaa36a97
AD		 49
50static const u32 golden_settings_tonga_a11[] =
51{
52 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
53 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
54 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
55 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
56 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
57 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
58 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
59};
60
61static const u32 tonga_mgcg_cgcg_init[] =
62{
63 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
64};
65
127a2628
DZ		 66static const u32 golden_settings_fiji_a10[] =
67{
68 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
69 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
70 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
71 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72};
73
74static const u32 fiji_mgcg_cgcg_init[] =
75{
76 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
77};
78
2cc0c0b5 79static const u32 golden_settings_polaris11_a11[] =
c9778572
FC		 80{
81 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
82 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
85};
86
2cc0c0b5 87static const u32 golden_settings_polaris10_a11[] =
c9778572
FC		 88{
89 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
90 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
91 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
92 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
93 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
94};
95
aaa36a97
AD		 96static const u32 cz_mgcg_cgcg_init[] =
97{
98 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
99};
100
aade2f04
SL		 101static const u32 stoney_mgcg_cgcg_init[] =
102{
103 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
104};
105
6d51c813
HR		 106static const u32 golden_settings_stoney_common[] =
107{
108 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
109 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
110};
aade2f04 111
aaa36a97
AD		 112static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
113{
114 switch (adev->asic_type) {
127a2628
DZ		 115 case CHIP_FIJI:
116 amdgpu_program_register_sequence(adev,
117 fiji_mgcg_cgcg_init,
118 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
119 amdgpu_program_register_sequence(adev,
120 golden_settings_fiji_a10,
121 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
122 break;
aaa36a97
AD		 123 case CHIP_TONGA:
124 amdgpu_program_register_sequence(adev,
125 tonga_mgcg_cgcg_init,
126 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
127 amdgpu_program_register_sequence(adev,
128 golden_settings_tonga_a11,
129 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
130 break;
2cc0c0b5 131 case CHIP_POLARIS11:
c9778572 132 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 133 golden_settings_polaris11_a11,
134 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
c9778572 135 break;
2cc0c0b5 136 case CHIP_POLARIS10:
c9778572 137 amdgpu_program_register_sequence(adev,
2cc0c0b5
FC		 138 golden_settings_polaris10_a11,
139 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
c9778572 140 break;
aaa36a97
AD		 141 case CHIP_CARRIZO:
142 amdgpu_program_register_sequence(adev,
143 cz_mgcg_cgcg_init,
144 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
145 break;
aade2f04
SL		 146 case CHIP_STONEY:
147 amdgpu_program_register_sequence(adev,
148 stoney_mgcg_cgcg_init,
149 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
6d51c813
HR		 150 amdgpu_program_register_sequence(adev,
151 golden_settings_stoney_common,
152 (const u32)ARRAY_SIZE(golden_settings_stoney_common));
aade2f04 153 break;
aaa36a97
AD		 154 default:
155 break;
156 }
157}
158
ccd73f24
AD		 159static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
160 struct amdgpu_mode_mc_save *save)
aaa36a97
AD		 161{
162 u32 blackout;
163
164 if (adev->mode_info.num_crtc)
165 amdgpu_display_stop_mc_access(adev, save);
166
34e3205e 167 gmc_v8_0_wait_for_idle(adev);
aaa36a97
AD		 168
169 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
170 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
171 /* Block CPU access */
172 WREG32(mmBIF_FB_EN, 0);
173 /* blackout the MC */
174 blackout = REG_SET_FIELD(blackout,
175 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
176 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
177 }
178 /* wait for the MC to settle */
179 udelay(100);
180}
181
ccd73f24
AD		 182static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
183 struct amdgpu_mode_mc_save *save)
aaa36a97
AD		 184{
185 u32 tmp;
186
187 /* unblackout the MC */
188 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
189 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
190 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
191 /* allow CPU access */
192 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
193 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
194 WREG32(mmBIF_FB_EN, tmp);
195
196 if (adev->mode_info.num_crtc)
197 amdgpu_display_resume_mc_access(adev, save);
198}
199
200/**
201 * gmc_v8_0_init_microcode - load ucode images from disk
202 *
203 * @adev: amdgpu_device pointer
204 *
205 * Use the firmware interface to load the ucode images into
206 * the driver (not loaded into hw).
207 * Returns 0 on success, error on failure.
208 */
209static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
210{
211 const char *chip_name;
212 char fw_name[30];
213 int err;
214
215 DRM_DEBUG("\n");
216
217 switch (adev->asic_type) {
aaa36a97
AD		 218 case CHIP_TONGA:
219 chip_name = "tonga";
220 break;
2cc0c0b5
FC		 221 case CHIP_POLARIS11:
222 chip_name = "polaris11";
c9778572 223 break;
2cc0c0b5
FC		 224 case CHIP_POLARIS10:
225 chip_name = "polaris10";
c9778572 226 break;
127a2628 227 case CHIP_FIJI:
aaa36a97 228 case CHIP_CARRIZO:
aade2f04 229 case CHIP_STONEY:
aaa36a97
AD		 230 return 0;
231 default: BUG();
232 }
233
c65444fe 234 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
aaa36a97
AD		 235 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
236 if (err)
237 goto out;
238 err = amdgpu_ucode_validate(adev->mc.fw);
239
240out:
241 if (err) {
242 printk(KERN_ERR
243 "mc: Failed to load firmware \"%s\"\n",
244 fw_name);
245 release_firmware(adev->mc.fw);
246 adev->mc.fw = NULL;
247 }
248 return err;
249}
250
251/**
252 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
253 *
254 * @adev: amdgpu_device pointer
255 *
256 * Load the GDDR MC ucode into the hw (CIK).
257 * Returns 0 on success, error on failure.
258 */
259static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
260{
261 const struct mc_firmware_header_v1_0 *hdr;
262 const __le32 *fw_data = NULL;
263 const __le32 *io_mc_regs = NULL;
887656f0 264 u32 running;
aaa36a97
AD		 265 int i, ucode_size, regs_size;
266
267 if (!adev->mc.fw)
268 return -EINVAL;
269
c12d2871
AD		 270 /* Skip MC ucode loading on SR-IOV capable boards.
271 * vbios does this for us in asic_init in that case.
272 */
273 if (adev->virtualization.supports_sr_iov)
274 return 0;
275
aaa36a97
AD		 276 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
277 amdgpu_ucode_print_mc_hdr(&hdr->header);
278
279 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
280 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
281 io_mc_regs = (const __le32 *)
282 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
283 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
284 fw_data = (const __le32 *)
285 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
286
287 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
288
289 if (running == 0) {
aaa36a97
AD		 290 /* reset the engine and set to writable */
291 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
292 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
293
294 /* load mc io regs */
295 for (i = 0; i < regs_size; i++) {
296 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
297 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
298 }
299 /* load the MC ucode */
300 for (i = 0; i < ucode_size; i++)
301 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
302
303 /* put the engine back into the active state */
304 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
305 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
306 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
307
308 /* wait for training to complete */
309 for (i = 0; i < adev->usec_timeout; i++) {
310 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
311 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
312 break;
313 udelay(1);
314 }
315 for (i = 0; i < adev->usec_timeout; i++) {
316 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
317 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
318 break;
319 udelay(1);
320 }
aaa36a97
AD		 321 }
322
323 return 0;
324}
325
326static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
327 struct amdgpu_mc *mc)
328{
329 if (mc->mc_vram_size > 0xFFC0000000ULL) {
330 /* leave room for at least 1024M GTT */
331 dev_warn(adev->dev, "limiting VRAM\n");
332 mc->real_vram_size = 0xFFC0000000ULL;
333 mc->mc_vram_size = 0xFFC0000000ULL;
334 }
335 amdgpu_vram_location(adev, &adev->mc, 0);
336 adev->mc.gtt_base_align = 0;
337 amdgpu_gtt_location(adev, mc);
338}
339
340/**
341 * gmc_v8_0_mc_program - program the GPU memory controller
342 *
343 * @adev: amdgpu_device pointer
344 *
345 * Set the location of vram, gart, and AGP in the GPU's
346 * physical address space (CIK).
347 */
348static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
349{
350 struct amdgpu_mode_mc_save save;
351 u32 tmp;
352 int i, j;
353
354 /* Initialize HDP */
355 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
356 WREG32((0xb05 + j), 0x00000000);
357 WREG32((0xb06 + j), 0x00000000);
358 WREG32((0xb07 + j), 0x00000000);
359 WREG32((0xb08 + j), 0x00000000);
360 WREG32((0xb09 + j), 0x00000000);
361 }
362 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
363
364 if (adev->mode_info.num_crtc)
365 amdgpu_display_set_vga_render_state(adev, false);
366
367 gmc_v8_0_mc_stop(adev, &save);
34e3205e 368 if (gmc_v8_0_wait_for_idle((void *)adev)) {
aaa36a97
AD		 369 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
370 }
371 /* Update configuration */
372 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
373 adev->mc.vram_start >> 12);
374 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
375 adev->mc.vram_end >> 12);
376 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
377 adev->vram_scratch.gpu_addr >> 12);
378 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
379 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
380 WREG32(mmMC_VM_FB_LOCATION, tmp);
381 /* XXX double check these! */
382 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
383 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
384 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
385 WREG32(mmMC_VM_AGP_BASE, 0);
386 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
387 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
34e3205e 388 if (gmc_v8_0_wait_for_idle((void *)adev)) {
aaa36a97
AD		 389 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
390 }
391 gmc_v8_0_mc_resume(adev, &save);
392
393 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
394
395 tmp = RREG32(mmHDP_MISC_CNTL);
13459bd0 396 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
aaa36a97
AD		 397 WREG32(mmHDP_MISC_CNTL, tmp);
398
399 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
400 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
401}
402
403/**
404 * gmc_v8_0_mc_init - initialize the memory controller driver params
405 *
406 * @adev: amdgpu_device pointer
407 *
408 * Look up the amount of vram, vram width, and decide how to place
409 * vram and gart within the GPU's physical address space (CIK).
410 * Returns 0 for success.
411 */
412static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
413{
414 u32 tmp;
415 int chansize, numchan;
416
417 /* Get VRAM informations */
418 tmp = RREG32(mmMC_ARB_RAMCFG);
419 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
420 chansize = 64;
421 } else {
422 chansize = 32;
423 }
424 tmp = RREG32(mmMC_SHARED_CHMAP);
425 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
426 case 0:
427 default:
428 numchan = 1;
429 break;
430 case 1:
431 numchan = 2;
432 break;
433 case 2:
434 numchan = 4;
435 break;
436 case 3:
437 numchan = 8;
438 break;
439 case 4:
440 numchan = 3;
441 break;
442 case 5:
443 numchan = 6;
444 break;
445 case 6:
446 numchan = 10;
447 break;
448 case 7:
449 numchan = 12;
450 break;
451 case 8:
452 numchan = 16;
453 break;
454 }
455 adev->mc.vram_width = numchan * chansize;
456 /* Could aper size report 0 ? */
457 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
458 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
459 /* size in MB on si */
460 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
461 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
462 adev->mc.visible_vram_size = adev->mc.aper_size;
463
a1493cd5
AD		 464 /* In case the PCI BAR is larger than the actual amount of vram */
465 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
466 adev->mc.visible_vram_size = adev->mc.real_vram_size;
467
aaa36a97
AD		 468 /* unless the user had overridden it, set the gart
469 * size equal to the 1024 or vram, whichever is larger.
470 */
471 if (amdgpu_gart_size == -1)
a693e050 472 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
aaa36a97
AD		 473 else
474 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
475
476 gmc_v8_0_vram_gtt_location(adev, &adev->mc);
477
478 return 0;
479}
480
481/*
482 * GART
483 * VMID 0 is the physical GPU addresses as used by the kernel.
484 * VMIDs 1-15 are used for userspace clients and are handled
485 * by the amdgpu vm/hsa code.
486 */
487
488/**
489 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
490 *
491 * @adev: amdgpu_device pointer
492 * @vmid: vm instance to flush
493 *
494 * Flush the TLB for the requested page table (CIK).
495 */
496static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
497 uint32_t vmid)
498{
499 /* flush hdp cache */
500 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
501
502 /* bits 0-15 are the VM contexts0-15 */
503 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
504}
505
506/**
507 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
508 *
509 * @adev: amdgpu_device pointer
510 * @cpu_pt_addr: cpu address of the page table
511 * @gpu_page_idx: entry in the page table to update
512 * @addr: dst addr to write into pte/pde
513 * @flags: access flags
514 *
515 * Update the page tables using the CPU.
516 */
517static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
518 void *cpu_pt_addr,
519 uint32_t gpu_page_idx,
520 uint64_t addr,
521 uint32_t flags)
522{
523 void __iomem *ptr = (void *)cpu_pt_addr;
524 uint64_t value;
525
526 /*
527 * PTE format on VI:
528 * 63:40 reserved
529 * 39:12 4k physical page base address
530 * 11:7 fragment
531 * 6 write
532 * 5 read
533 * 4 exe
534 * 3 reserved
535 * 2 snooped
536 * 1 system
537 * 0 valid
538 *
539 * PDE format on VI:
540 * 63:59 block fragment size
541 * 58:40 reserved
542 * 39:1 physical base address of PTE
543 * bits 5:1 must be 0.
544 * 0 valid
545 */
546 value = addr & 0x000000FFFFFFF000ULL;
547 value |= flags;
548 writeq(value, ptr + (gpu_page_idx * 8));
549
550 return 0;
551}
552
d9c13156
CK		 553/**
554 * gmc_v8_0_set_fault_enable_default - update VM fault handling
555 *
556 * @adev: amdgpu_device pointer
557 * @value: true redirects VM faults to the default page
558 */
559static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
560 bool value)
561{
562 u32 tmp;
563
564 tmp = RREG32(mmVM_CONTEXT1_CNTL);
565 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
566 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
567 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
568 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
569 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
570 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
571 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
572 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
573 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
574 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
575 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
576 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
577 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
578 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
579 WREG32(mmVM_CONTEXT1_CNTL, tmp);
580}
581
aaa36a97
AD		 582/**
583 * gmc_v8_0_gart_enable - gart enable
584 *
585 * @adev: amdgpu_device pointer
586 *
587 * This sets up the TLBs, programs the page tables for VMID0,
588 * sets up the hw for VMIDs 1-15 which are allocated on
589 * demand, and sets up the global locations for the LDS, GDS,
590 * and GPUVM for FSA64 clients (CIK).
591 * Returns 0 for success, errors for failure.
592 */
593static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
594{
595 int r, i;
596 u32 tmp;
597
598 if (adev->gart.robj == NULL) {
599 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
600 return -EINVAL;
601 }
602 r = amdgpu_gart_table_vram_pin(adev);
603 if (r)
604 return r;
605 /* Setup TLB control */
606 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
607 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
608 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
609 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
610 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
611 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
612 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
613 /* Setup L2 cache */
614 tmp = RREG32(mmVM_L2_CNTL);
615 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
616 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
618 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
619 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
620 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
a80b3047 621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
aaa36a97
AD		 622 WREG32(mmVM_L2_CNTL, tmp);
623 tmp = RREG32(mmVM_L2_CNTL2);
624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
626 WREG32(mmVM_L2_CNTL2, tmp);
627 tmp = RREG32(mmVM_L2_CNTL3);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
631 WREG32(mmVM_L2_CNTL3, tmp);
632 /* XXX: set to enable PTE/PDE in system memory */
633 tmp = RREG32(mmVM_L2_CNTL4);
634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
646 WREG32(mmVM_L2_CNTL4, tmp);
647 /* setup context0 */
648 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
9c97b5ab 649 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
aaa36a97
AD		 650 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
651 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
652 (u32)(adev->dummy_page.addr >> 12));
653 WREG32(mmVM_CONTEXT0_CNTL2, 0);
654 tmp = RREG32(mmVM_CONTEXT0_CNTL);
655 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
656 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
657 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
658 WREG32(mmVM_CONTEXT0_CNTL, tmp);
659
660 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
661 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
662 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
663
664 /* empty context1-15 */
665 /* FIXME start with 4G, once using 2 level pt switch to full
666 * vm size space
667 */
668 /* set vm size, must be a multiple of 4 */
669 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
25a595e4 670 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
aaa36a97
AD		 671 for (i = 1; i < 16; i++) {
672 if (i < 8)
673 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
674 adev->gart.table_addr >> 12);
675 else
676 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
677 adev->gart.table_addr >> 12);
678 }
679
680 /* enable context1-15 */
681 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
682 (u32)(adev->dummy_page.addr >> 12));
683 WREG32(mmVM_CONTEXT1_CNTL2, 4);
684 tmp = RREG32(mmVM_CONTEXT1_CNTL);
685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
686 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
aaa36a97 687 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 688 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 689 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 690 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 691 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 692 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97
AD		 693 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
694 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
695 amdgpu_vm_block_size - 9);
696 WREG32(mmVM_CONTEXT1_CNTL, tmp);
d9c13156
CK		 697 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
698 gmc_v8_0_set_fault_enable_default(adev, false);
699 else
700 gmc_v8_0_set_fault_enable_default(adev, true);
aaa36a97
AD		 701
702 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
703 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
704 (unsigned)(adev->mc.gtt_size >> 20),
705 (unsigned long long)adev->gart.table_addr);
706 adev->gart.ready = true;
707 return 0;
708}
709
710static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
711{
712 int r;
713
714 if (adev->gart.robj) {
715 WARN(1, "R600 PCIE GART already initialized\n");
716 return 0;
717 }
718 /* Initialize common gart structure */
719 r = amdgpu_gart_init(adev);
720 if (r)
721 return r;
722 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
723 return amdgpu_gart_table_vram_alloc(adev);
724}
725
726/**
727 * gmc_v8_0_gart_disable - gart disable
728 *
729 * @adev: amdgpu_device pointer
730 *
731 * This disables all VM page table (CIK).
732 */
733static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
734{
735 u32 tmp;
736
737 /* Disable all tables */
738 WREG32(mmVM_CONTEXT0_CNTL, 0);
739 WREG32(mmVM_CONTEXT1_CNTL, 0);
740 /* Setup TLB control */
741 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
742 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
743 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
744 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
745 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
746 /* Setup L2 cache */
747 tmp = RREG32(mmVM_L2_CNTL);
748 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
749 WREG32(mmVM_L2_CNTL, tmp);
750 WREG32(mmVM_L2_CNTL2, 0);
751 amdgpu_gart_table_vram_unpin(adev);
752}
753
754/**
755 * gmc_v8_0_gart_fini - vm fini callback
756 *
757 * @adev: amdgpu_device pointer
758 *
759 * Tears down the driver GART/VM setup (CIK).
760 */
761static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
762{
763 amdgpu_gart_table_vram_free(adev);
764 amdgpu_gart_fini(adev);
765}
766
767/*
768 * vm
769 * VMID 0 is the physical GPU addresses as used by the kernel.
770 * VMIDs 1-15 are used for userspace clients and are handled
771 * by the amdgpu vm/hsa code.
772 */
773/**
774 * gmc_v8_0_vm_init - cik vm init callback
775 *
776 * @adev: amdgpu_device pointer
777 *
778 * Inits cik specific vm parameters (number of VMs, base of vram for
779 * VMIDs 1-15) (CIK).
780 * Returns 0 for success.
781 */
782static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
783{
784 /*
785 * number of VMs
786 * VMID 0 is reserved for System
787 * amdgpu graphics/compute will use VMIDs 1-7
788 * amdkfd will use VMIDs 8-15
789 */
a9a78b32
CK		 790 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
791 amdgpu_vm_manager_init(adev);
aaa36a97
AD		 792
793 /* base offset of vram pages */
2f7d10b3 794 if (adev->flags & AMD_IS_APU) {
aaa36a97
AD		 795 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
796 tmp <<= 22;
797 adev->vm_manager.vram_base_offset = tmp;
798 } else
799 adev->vm_manager.vram_base_offset = 0;
800
801 return 0;
802}
803
804/**
805 * gmc_v8_0_vm_fini - cik vm fini callback
806 *
807 * @adev: amdgpu_device pointer
808 *
809 * Tear down any asic specific VM setup (CIK).
810 */
811static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
812{
813}
814
815/**
816 * gmc_v8_0_vm_decode_fault - print human readable fault info
817 *
818 * @adev: amdgpu_device pointer
819 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
820 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
821 *
822 * Print human readable fault information (CIK).
823 */
824static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
825 u32 status, u32 addr, u32 mc_client)
826{
827 u32 mc_id;
828 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
829 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
830 PROTECTIONS);
831 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
832 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
833
834 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
835 MEMORY_CLIENT_ID);
836
837 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
838 protections, vmid, addr,
839 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
840 MEMORY_CLIENT_RW) ?
841 "write" : "read", block, mc_client, mc_id);
842}
843
81c59f54
KW		 844static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
845{
846 switch (mc_seq_vram_type) {
847 case MC_SEQ_MISC0__MT__GDDR1:
848 return AMDGPU_VRAM_TYPE_GDDR1;
849 case MC_SEQ_MISC0__MT__DDR2:
850 return AMDGPU_VRAM_TYPE_DDR2;
851 case MC_SEQ_MISC0__MT__GDDR3:
852 return AMDGPU_VRAM_TYPE_GDDR3;
853 case MC_SEQ_MISC0__MT__GDDR4:
854 return AMDGPU_VRAM_TYPE_GDDR4;
855 case MC_SEQ_MISC0__MT__GDDR5:
856 return AMDGPU_VRAM_TYPE_GDDR5;
857 case MC_SEQ_MISC0__MT__HBM:
858 return AMDGPU_VRAM_TYPE_HBM;
859 case MC_SEQ_MISC0__MT__DDR3:
860 return AMDGPU_VRAM_TYPE_DDR3;
861 default:
862 return AMDGPU_VRAM_TYPE_UNKNOWN;
863 }
864}
865
5fc3aeeb 866static int gmc_v8_0_early_init(void *handle)
aaa36a97 867{
5fc3aeeb 868 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
869
aaa36a97
AD		 870 gmc_v8_0_set_gart_funcs(adev);
871 gmc_v8_0_set_irq_funcs(adev);
872
aaa36a97
AD		 873 return 0;
874}
875
140b519f
CK		 876static int gmc_v8_0_late_init(void *handle)
877{
878 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
879
afc45421
FC		 880 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
881 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
882 else
883 return 0;
140b519f
CK		 884}
885
b634de4f
AD		 886#define mmMC_SEQ_MISC0_FIJI 0xA71
887
5fc3aeeb 888static int gmc_v8_0_sw_init(void *handle)
aaa36a97
AD		 889{
890 int r;
891 int dma_bits;
5fc3aeeb 892 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 893
d1518a1d
AD		 894 if (adev->flags & AMD_IS_APU) {
895 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
896 } else {
b634de4f
AD		 897 u32 tmp;
898
899 if (adev->asic_type == CHIP_FIJI)
900 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
901 else
902 tmp = RREG32(mmMC_SEQ_MISC0);
d1518a1d
AD		 903 tmp &= MC_SEQ_MISC0__MT__MASK;
904 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
905 }
906
aaa36a97
AD		 907 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
908 if (r)
909 return r;
910
911 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
912 if (r)
913 return r;
914
915 /* Adjust VM size here.
916 * Currently set to 4GB ((1 << 20) 4k pages).
917 * Max GPUVM size for cayman and SI is 40 bits.
918 */
919 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
920
921 /* Set the internal MC address mask
922 * This is the max address of the GPU's
923 * internal address space.
924 */
925 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
926
927 /* set DMA mask + need_dma32 flags.
928 * PCIE - can handle 40-bits.
929 * IGP - can handle 40-bits
930 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
931 */
932 adev->need_dma32 = false;
933 dma_bits = adev->need_dma32 ? 32 : 40;
934 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
935 if (r) {
936 adev->need_dma32 = true;
937 dma_bits = 32;
938 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
939 }
940 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
941 if (r) {
942 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
943 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
944 }
945
946 r = gmc_v8_0_init_microcode(adev);
947 if (r) {
948 DRM_ERROR("Failed to load mc firmware!\n");
949 return r;
950 }
951
a693e050
KW		 952 r = amdgpu_ttm_global_init(adev);
953 if (r) {
954 return r;
955 }
956
aaa36a97
AD		 957 r = gmc_v8_0_mc_init(adev);
958 if (r)
959 return r;
960
961 /* Memory manager */
962 r = amdgpu_bo_init(adev);
963 if (r)
964 return r;
965
966 r = gmc_v8_0_gart_init(adev);
967 if (r)
968 return r;
969
970 if (!adev->vm_manager.enabled) {
971 r = gmc_v8_0_vm_init(adev);
972 if (r) {
973 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
974 return r;
975 }
976 adev->vm_manager.enabled = true;
977 }
978
979 return r;
980}
981
5fc3aeeb 982static int gmc_v8_0_sw_fini(void *handle)
aaa36a97 983{
5fc3aeeb 984 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 985
986 if (adev->vm_manager.enabled) {
ea89f8c9 987 amdgpu_vm_manager_fini(adev);
aaa36a97
AD		 988 gmc_v8_0_vm_fini(adev);
989 adev->vm_manager.enabled = false;
990 }
991 gmc_v8_0_gart_fini(adev);
418aa0c2 992 amdgpu_gem_force_release(adev);
aaa36a97
AD		 993 amdgpu_bo_fini(adev);
994
995 return 0;
996}
997
5fc3aeeb 998static int gmc_v8_0_hw_init(void *handle)
aaa36a97
AD		 999{
1000 int r;
5fc3aeeb 1001 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1002
1003 gmc_v8_0_init_golden_registers(adev);
1004
1005 gmc_v8_0_mc_program(adev);
1006
8878d854 1007 if (adev->asic_type == CHIP_TONGA) {
aaa36a97
AD		 1008 r = gmc_v8_0_mc_load_microcode(adev);
1009 if (r) {
1010 DRM_ERROR("Failed to load MC firmware!\n");
1011 return r;
1012 }
1013 }
1014
1015 r = gmc_v8_0_gart_enable(adev);
1016 if (r)
1017 return r;
1018
1019 return r;
1020}
1021
5fc3aeeb 1022static int gmc_v8_0_hw_fini(void *handle)
aaa36a97 1023{
5fc3aeeb 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025
140b519f 1026 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
aaa36a97
AD		 1027 gmc_v8_0_gart_disable(adev);
1028
1029 return 0;
1030}
1031
5fc3aeeb 1032static int gmc_v8_0_suspend(void *handle)
aaa36a97 1033{
5fc3aeeb 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1035
1036 if (adev->vm_manager.enabled) {
aaa36a97
AD		 1037 gmc_v8_0_vm_fini(adev);
1038 adev->vm_manager.enabled = false;
1039 }
1040 gmc_v8_0_hw_fini(adev);
1041
1042 return 0;
1043}
1044
5fc3aeeb 1045static int gmc_v8_0_resume(void *handle)
aaa36a97
AD		 1046{
1047 int r;
5fc3aeeb 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1049
1050 r = gmc_v8_0_hw_init(adev);
1051 if (r)
1052 return r;
1053
1054 if (!adev->vm_manager.enabled) {
1055 r = gmc_v8_0_vm_init(adev);
1056 if (r) {
1057 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1058 return r;
1059 }
1060 adev->vm_manager.enabled = true;
1061 }
1062
1063 return r;
1064}
1065
5fc3aeeb 1066static bool gmc_v8_0_is_idle(void *handle)
aaa36a97 1067{
5fc3aeeb 1068 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1069 u32 tmp = RREG32(mmSRBM_STATUS);
1070
1071 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1072 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1073 return false;
1074
1075 return true;
1076}
1077
5fc3aeeb 1078static int gmc_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 1079{
1080 unsigned i;
1081 u32 tmp;
5fc3aeeb 1082 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1083
1084 for (i = 0; i < adev->usec_timeout; i++) {
1085 /* read MC_STATUS */
1086 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1087 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1088 SRBM_STATUS__MCC_BUSY_MASK |
1089 SRBM_STATUS__MCD_BUSY_MASK |
1090 SRBM_STATUS__VMC_BUSY_MASK |
1091 SRBM_STATUS__VMC1_BUSY_MASK);
1092 if (!tmp)
1093 return 0;
1094 udelay(1);
1095 }
1096 return -ETIMEDOUT;
1097
1098}
1099
50b0197a 1100static int gmc_v8_0_check_soft_reset(void *handle)
aaa36a97 1101{
aaa36a97 1102 u32 srbm_soft_reset = 0;
5fc3aeeb 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1104 u32 tmp = RREG32(mmSRBM_STATUS);
1105
1106 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1107 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1108 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1109
1110 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1111 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
2f7d10b3 1112 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 1113 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1114 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1115 }
aaa36a97 1116 if (srbm_soft_reset) {
50b0197a
CZ		 1117 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang = true;
1118 adev->mc.srbm_soft_reset = srbm_soft_reset;
1119 } else {
1120 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang = false;
1121 adev->mc.srbm_soft_reset = 0;
1122 }
1123 return 0;
1124}
aaa36a97 1125
50b0197a
CZ		 1126static int gmc_v8_0_pre_soft_reset(void *handle)
1127{
1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1129
1130 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang)
1131 return 0;
1132
1133 gmc_v8_0_mc_stop(adev, &adev->mc.save);
1134 if (gmc_v8_0_wait_for_idle(adev)) {
1135 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1136 }
1137
1138 return 0;
1139}
aaa36a97 1140
50b0197a
CZ		 1141static int gmc_v8_0_soft_reset(void *handle)
1142{
1143 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1144 u32 srbm_soft_reset;
1145
1146 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang)
1147 return 0;
1148 srbm_soft_reset = adev->mc.srbm_soft_reset;
1149
1150 if (srbm_soft_reset) {
1151 u32 tmp;
aaa36a97
AD		 1152
1153 tmp = RREG32(mmSRBM_SOFT_RESET);
1154 tmp |= srbm_soft_reset;
1155 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1156 WREG32(mmSRBM_SOFT_RESET, tmp);
1157 tmp = RREG32(mmSRBM_SOFT_RESET);
1158
1159 udelay(50);
1160
1161 tmp &= ~srbm_soft_reset;
1162 WREG32(mmSRBM_SOFT_RESET, tmp);
1163 tmp = RREG32(mmSRBM_SOFT_RESET);
1164
1165 /* Wait a little for things to settle down */
1166 udelay(50);
aaa36a97
AD		 1167 }
1168
1169 return 0;
1170}
1171
50b0197a
CZ		 1172static int gmc_v8_0_post_soft_reset(void *handle)
1173{
1174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1175
1176 if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang)
1177 return 0;
1178
1179 gmc_v8_0_mc_resume(adev, &adev->mc.save);
1180 return 0;
1181}
1182
aaa36a97
AD		 1183static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1184 struct amdgpu_irq_src *src,
1185 unsigned type,
1186 enum amdgpu_interrupt_state state)
1187{
1188 u32 tmp;
1189 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1190 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1191 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1192 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1193 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1194 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1195 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1196
1197 switch (state) {
1198 case AMDGPU_IRQ_STATE_DISABLE:
1199 /* system context */
1200 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1201 tmp &= ~bits;
1202 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1203 /* VMs */
1204 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1205 tmp &= ~bits;
1206 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1207 break;
1208 case AMDGPU_IRQ_STATE_ENABLE:
1209 /* system context */
1210 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1211 tmp |= bits;
1212 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1213 /* VMs */
1214 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1215 tmp |= bits;
1216 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1217 break;
1218 default:
1219 break;
1220 }
1221
1222 return 0;
1223}
1224
1225static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1226 struct amdgpu_irq_src *source,
1227 struct amdgpu_iv_entry *entry)
1228{
1229 u32 addr, status, mc_client;
1230
1231 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1232 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1233 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
ce0c6bcd
CK		 1234 /* reset addr and status */
1235 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1236
1237 if (!addr && !status)
1238 return 0;
1239
d9c13156
CK		 1240 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1241 gmc_v8_0_set_fault_enable_default(adev, false);
1242
aaa36a97
AD		 1243 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1244 entry->src_id, entry->src_data);
1245 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1246 addr);
1247 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1248 status);
1249 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
aaa36a97
AD		 1250
1251 return 0;
1252}
1253
a0d69786 1254static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
3fde56b8 1255 bool enable)
a0d69786
EH		 1256{
1257 uint32_t data;
1258
3fde56b8 1259 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
a0d69786
EH		 1260 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1261 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1262 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1263
1264 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1265 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1266 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1267
1268 data = RREG32(mmMC_HUB_MISC_VM_CG);
1269 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1270 WREG32(mmMC_HUB_MISC_VM_CG, data);
1271
1272 data = RREG32(mmMC_XPB_CLK_GAT);
1273 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1274 WREG32(mmMC_XPB_CLK_GAT, data);
1275
1276 data = RREG32(mmATC_MISC_CG);
1277 data |= ATC_MISC_CG__ENABLE_MASK;
1278 WREG32(mmATC_MISC_CG, data);
1279
1280 data = RREG32(mmMC_CITF_MISC_WR_CG);
1281 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1282 WREG32(mmMC_CITF_MISC_WR_CG, data);
1283
1284 data = RREG32(mmMC_CITF_MISC_RD_CG);
1285 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1286 WREG32(mmMC_CITF_MISC_RD_CG, data);
1287
1288 data = RREG32(mmMC_CITF_MISC_VM_CG);
1289 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1290 WREG32(mmMC_CITF_MISC_VM_CG, data);
1291
1292 data = RREG32(mmVM_L2_CG);
1293 data |= VM_L2_CG__ENABLE_MASK;
1294 WREG32(mmVM_L2_CG, data);
1295 } else {
1296 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1297 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1298 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1299
1300 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1301 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1302 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1303
1304 data = RREG32(mmMC_HUB_MISC_VM_CG);
1305 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1306 WREG32(mmMC_HUB_MISC_VM_CG, data);
1307
1308 data = RREG32(mmMC_XPB_CLK_GAT);
1309 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1310 WREG32(mmMC_XPB_CLK_GAT, data);
1311
1312 data = RREG32(mmATC_MISC_CG);
1313 data &= ~ATC_MISC_CG__ENABLE_MASK;
1314 WREG32(mmATC_MISC_CG, data);
1315
1316 data = RREG32(mmMC_CITF_MISC_WR_CG);
1317 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1318 WREG32(mmMC_CITF_MISC_WR_CG, data);
1319
1320 data = RREG32(mmMC_CITF_MISC_RD_CG);
1321 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1322 WREG32(mmMC_CITF_MISC_RD_CG, data);
1323
1324 data = RREG32(mmMC_CITF_MISC_VM_CG);
1325 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1326 WREG32(mmMC_CITF_MISC_VM_CG, data);
1327
1328 data = RREG32(mmVM_L2_CG);
1329 data &= ~VM_L2_CG__ENABLE_MASK;
1330 WREG32(mmVM_L2_CG, data);
1331 }
1332}
1333
1334static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
3fde56b8 1335 bool enable)
a0d69786
EH		 1336{
1337 uint32_t data;
1338
3fde56b8 1339 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
a0d69786
EH		 1340 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1341 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1342 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1343
1344 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1345 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1346 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1347
1348 data = RREG32(mmMC_HUB_MISC_VM_CG);
1349 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1350 WREG32(mmMC_HUB_MISC_VM_CG, data);
1351
1352 data = RREG32(mmMC_XPB_CLK_GAT);
1353 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1354 WREG32(mmMC_XPB_CLK_GAT, data);
1355
1356 data = RREG32(mmATC_MISC_CG);
1357 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1358 WREG32(mmATC_MISC_CG, data);
1359
1360 data = RREG32(mmMC_CITF_MISC_WR_CG);
1361 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1362 WREG32(mmMC_CITF_MISC_WR_CG, data);
1363
1364 data = RREG32(mmMC_CITF_MISC_RD_CG);
1365 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1366 WREG32(mmMC_CITF_MISC_RD_CG, data);
1367
1368 data = RREG32(mmMC_CITF_MISC_VM_CG);
1369 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1370 WREG32(mmMC_CITF_MISC_VM_CG, data);
1371
1372 data = RREG32(mmVM_L2_CG);
1373 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1374 WREG32(mmVM_L2_CG, data);
1375 } else {
1376 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1377 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1378 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1379
1380 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1381 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1382 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1383
1384 data = RREG32(mmMC_HUB_MISC_VM_CG);
1385 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1386 WREG32(mmMC_HUB_MISC_VM_CG, data);
1387
1388 data = RREG32(mmMC_XPB_CLK_GAT);
1389 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1390 WREG32(mmMC_XPB_CLK_GAT, data);
1391
1392 data = RREG32(mmATC_MISC_CG);
1393 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1394 WREG32(mmATC_MISC_CG, data);
1395
1396 data = RREG32(mmMC_CITF_MISC_WR_CG);
1397 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1398 WREG32(mmMC_CITF_MISC_WR_CG, data);
1399
1400 data = RREG32(mmMC_CITF_MISC_RD_CG);
1401 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1402 WREG32(mmMC_CITF_MISC_RD_CG, data);
1403
1404 data = RREG32(mmMC_CITF_MISC_VM_CG);
1405 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1406 WREG32(mmMC_CITF_MISC_VM_CG, data);
1407
1408 data = RREG32(mmVM_L2_CG);
1409 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1410 WREG32(mmVM_L2_CG, data);
1411 }
1412}
1413
5fc3aeeb 1414static int gmc_v8_0_set_clockgating_state(void *handle,
1415 enum amd_clockgating_state state)
aaa36a97 1416{
a0d69786
EH		 1417 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1418
1419 switch (adev->asic_type) {
1420 case CHIP_FIJI:
1421 fiji_update_mc_medium_grain_clock_gating(adev,
1422 state == AMD_CG_STATE_GATE ? true : false);
1423 fiji_update_mc_light_sleep(adev,
1424 state == AMD_CG_STATE_GATE ? true : false);
1425 break;
1426 default:
1427 break;
1428 }
aaa36a97
AD		 1429 return 0;
1430}
1431
5fc3aeeb 1432static int gmc_v8_0_set_powergating_state(void *handle,
1433 enum amd_powergating_state state)
aaa36a97
AD		 1434{
1435 return 0;
1436}
1437
5fc3aeeb 1438const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
88a907d6 1439 .name = "gmc_v8_0",
aaa36a97 1440 .early_init = gmc_v8_0_early_init,
140b519f 1441 .late_init = gmc_v8_0_late_init,
aaa36a97
AD		 1442 .sw_init = gmc_v8_0_sw_init,
1443 .sw_fini = gmc_v8_0_sw_fini,
1444 .hw_init = gmc_v8_0_hw_init,
1445 .hw_fini = gmc_v8_0_hw_fini,
1446 .suspend = gmc_v8_0_suspend,
1447 .resume = gmc_v8_0_resume,
1448 .is_idle = gmc_v8_0_is_idle,
1449 .wait_for_idle = gmc_v8_0_wait_for_idle,
50b0197a
CZ		 1450 .check_soft_reset = gmc_v8_0_check_soft_reset,
1451 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
aaa36a97 1452 .soft_reset = gmc_v8_0_soft_reset,
50b0197a 1453 .post_soft_reset = gmc_v8_0_post_soft_reset,
aaa36a97
AD		 1454 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1455 .set_powergating_state = gmc_v8_0_set_powergating_state,
1456};
1457
1458static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1459 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1460 .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1461};
1462
1463static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1464 .set = gmc_v8_0_vm_fault_interrupt_state,
1465 .process = gmc_v8_0_process_interrupt,
1466};
1467
1468static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1469{
1470 if (adev->gart.gart_funcs == NULL)
1471 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1472}
1473
1474static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1475{
1476 adev->mc.vm_fault.num_types = 1;
1477 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1478}
Linux kernel - Deliverables
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