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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / gmc_v8_0.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "drmP.h"
25#include "amdgpu.h"
26#include "gmc_v8_0.h"
27#include "amdgpu_ucode.h"
28
29#include "gmc/gmc_8_1_d.h"
30#include "gmc/gmc_8_1_sh_mask.h"
31
32#include "bif/bif_5_0_d.h"
33#include "bif/bif_5_0_sh_mask.h"
34
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37
38#include "vid.h"
39#include "vi.h"
40
81c59f54 41
aaa36a97
AD		 42static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
44
c65444fe 45MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
aaa36a97
AD		 46
47static const u32 golden_settings_tonga_a11[] =
48{
49 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
50 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
51 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
52 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
53 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
54 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
55 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
56};
57
58static const u32 tonga_mgcg_cgcg_init[] =
59{
60 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
61};
62
127a2628
DZ		 63static const u32 golden_settings_fiji_a10[] =
64{
65 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
66 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
67 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
68 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
69};
70
71static const u32 fiji_mgcg_cgcg_init[] =
72{
73 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
74};
75
aaa36a97
AD		 76static const u32 cz_mgcg_cgcg_init[] =
77{
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
79};
80
aade2f04
SL		 81static const u32 stoney_mgcg_cgcg_init[] =
82{
83 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
84};
85
86
aaa36a97
AD		 87static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
88{
89 switch (adev->asic_type) {
127a2628
DZ		 90 case CHIP_FIJI:
91 amdgpu_program_register_sequence(adev,
92 fiji_mgcg_cgcg_init,
93 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
94 amdgpu_program_register_sequence(adev,
95 golden_settings_fiji_a10,
96 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
97 break;
aaa36a97
AD		 98 case CHIP_TONGA:
99 amdgpu_program_register_sequence(adev,
100 tonga_mgcg_cgcg_init,
101 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
102 amdgpu_program_register_sequence(adev,
103 golden_settings_tonga_a11,
104 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
105 break;
106 case CHIP_CARRIZO:
107 amdgpu_program_register_sequence(adev,
108 cz_mgcg_cgcg_init,
109 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
110 break;
aade2f04
SL		 111 case CHIP_STONEY:
112 amdgpu_program_register_sequence(adev,
113 stoney_mgcg_cgcg_init,
114 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
115 break;
aaa36a97
AD		 116 default:
117 break;
118 }
119}
120
121/**
122 * gmc8_mc_wait_for_idle - wait for MC idle callback.
123 *
124 * @adev: amdgpu_device pointer
125 *
126 * Wait for the MC (memory controller) to be idle.
127 * (evergreen+).
128 * Returns 0 if the MC is idle, -1 if not.
129 */
130int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
131{
132 unsigned i;
133 u32 tmp;
134
135 for (i = 0; i < adev->usec_timeout; i++) {
136 /* read MC_STATUS */
137 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
138 SRBM_STATUS__MCB_BUSY_MASK |
139 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
140 SRBM_STATUS__MCC_BUSY_MASK |
141 SRBM_STATUS__MCD_BUSY_MASK |
142 SRBM_STATUS__VMC1_BUSY_MASK);
143 if (!tmp)
144 return 0;
145 udelay(1);
146 }
147 return -1;
148}
149
150void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
151 struct amdgpu_mode_mc_save *save)
152{
153 u32 blackout;
154
155 if (adev->mode_info.num_crtc)
156 amdgpu_display_stop_mc_access(adev, save);
157
158 amdgpu_asic_wait_for_mc_idle(adev);
159
160 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
161 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
162 /* Block CPU access */
163 WREG32(mmBIF_FB_EN, 0);
164 /* blackout the MC */
165 blackout = REG_SET_FIELD(blackout,
166 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
167 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
168 }
169 /* wait for the MC to settle */
170 udelay(100);
171}
172
173void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
174 struct amdgpu_mode_mc_save *save)
175{
176 u32 tmp;
177
178 /* unblackout the MC */
179 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
180 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
181 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
182 /* allow CPU access */
183 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
184 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
185 WREG32(mmBIF_FB_EN, tmp);
186
187 if (adev->mode_info.num_crtc)
188 amdgpu_display_resume_mc_access(adev, save);
189}
190
191/**
192 * gmc_v8_0_init_microcode - load ucode images from disk
193 *
194 * @adev: amdgpu_device pointer
195 *
196 * Use the firmware interface to load the ucode images into
197 * the driver (not loaded into hw).
198 * Returns 0 on success, error on failure.
199 */
200static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
201{
202 const char *chip_name;
203 char fw_name[30];
204 int err;
205
206 DRM_DEBUG("\n");
207
208 switch (adev->asic_type) {
aaa36a97
AD		 209 case CHIP_TONGA:
210 chip_name = "tonga";
211 break;
127a2628 212 case CHIP_FIJI:
aaa36a97 213 case CHIP_CARRIZO:
aade2f04 214 case CHIP_STONEY:
aaa36a97
AD		 215 return 0;
216 default: BUG();
217 }
218
c65444fe 219 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
aaa36a97
AD		 220 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
221 if (err)
222 goto out;
223 err = amdgpu_ucode_validate(adev->mc.fw);
224
225out:
226 if (err) {
227 printk(KERN_ERR
228 "mc: Failed to load firmware \"%s\"\n",
229 fw_name);
230 release_firmware(adev->mc.fw);
231 adev->mc.fw = NULL;
232 }
233 return err;
234}
235
236/**
237 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
238 *
239 * @adev: amdgpu_device pointer
240 *
241 * Load the GDDR MC ucode into the hw (CIK).
242 * Returns 0 on success, error on failure.
243 */
244static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
245{
246 const struct mc_firmware_header_v1_0 *hdr;
247 const __le32 *fw_data = NULL;
248 const __le32 *io_mc_regs = NULL;
249 u32 running, blackout = 0;
250 int i, ucode_size, regs_size;
251
252 if (!adev->mc.fw)
253 return -EINVAL;
254
c12d2871
AD		 255 /* Skip MC ucode loading on SR-IOV capable boards.
256 * vbios does this for us in asic_init in that case.
257 */
258 if (adev->virtualization.supports_sr_iov)
259 return 0;
260
aaa36a97
AD		 261 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
262 amdgpu_ucode_print_mc_hdr(&hdr->header);
263
264 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
265 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
266 io_mc_regs = (const __le32 *)
267 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
268 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
269 fw_data = (const __le32 *)
270 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
271
272 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
273
274 if (running == 0) {
275 if (running) {
276 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
277 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
278 }
279
280 /* reset the engine and set to writable */
281 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
282 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
283
284 /* load mc io regs */
285 for (i = 0; i < regs_size; i++) {
286 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
287 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
288 }
289 /* load the MC ucode */
290 for (i = 0; i < ucode_size; i++)
291 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
292
293 /* put the engine back into the active state */
294 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
295 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
296 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
297
298 /* wait for training to complete */
299 for (i = 0; i < adev->usec_timeout; i++) {
300 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
301 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
302 break;
303 udelay(1);
304 }
305 for (i = 0; i < adev->usec_timeout; i++) {
306 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
307 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
308 break;
309 udelay(1);
310 }
311
312 if (running)
313 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
314 }
315
316 return 0;
317}
318
319static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
320 struct amdgpu_mc *mc)
321{
322 if (mc->mc_vram_size > 0xFFC0000000ULL) {
323 /* leave room for at least 1024M GTT */
324 dev_warn(adev->dev, "limiting VRAM\n");
325 mc->real_vram_size = 0xFFC0000000ULL;
326 mc->mc_vram_size = 0xFFC0000000ULL;
327 }
328 amdgpu_vram_location(adev, &adev->mc, 0);
329 adev->mc.gtt_base_align = 0;
330 amdgpu_gtt_location(adev, mc);
331}
332
333/**
334 * gmc_v8_0_mc_program - program the GPU memory controller
335 *
336 * @adev: amdgpu_device pointer
337 *
338 * Set the location of vram, gart, and AGP in the GPU's
339 * physical address space (CIK).
340 */
341static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
342{
343 struct amdgpu_mode_mc_save save;
344 u32 tmp;
345 int i, j;
346
347 /* Initialize HDP */
348 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
349 WREG32((0xb05 + j), 0x00000000);
350 WREG32((0xb06 + j), 0x00000000);
351 WREG32((0xb07 + j), 0x00000000);
352 WREG32((0xb08 + j), 0x00000000);
353 WREG32((0xb09 + j), 0x00000000);
354 }
355 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
356
357 if (adev->mode_info.num_crtc)
358 amdgpu_display_set_vga_render_state(adev, false);
359
360 gmc_v8_0_mc_stop(adev, &save);
361 if (amdgpu_asic_wait_for_mc_idle(adev)) {
362 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
363 }
364 /* Update configuration */
365 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
366 adev->mc.vram_start >> 12);
367 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
368 adev->mc.vram_end >> 12);
369 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
370 adev->vram_scratch.gpu_addr >> 12);
371 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
372 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
373 WREG32(mmMC_VM_FB_LOCATION, tmp);
374 /* XXX double check these! */
375 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
376 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
377 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
378 WREG32(mmMC_VM_AGP_BASE, 0);
379 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
380 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
381 if (amdgpu_asic_wait_for_mc_idle(adev)) {
382 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
383 }
384 gmc_v8_0_mc_resume(adev, &save);
385
386 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
387
388 tmp = RREG32(mmHDP_MISC_CNTL);
13459bd0 389 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
aaa36a97
AD		 390 WREG32(mmHDP_MISC_CNTL, tmp);
391
392 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
393 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
394}
395
396/**
397 * gmc_v8_0_mc_init - initialize the memory controller driver params
398 *
399 * @adev: amdgpu_device pointer
400 *
401 * Look up the amount of vram, vram width, and decide how to place
402 * vram and gart within the GPU's physical address space (CIK).
403 * Returns 0 for success.
404 */
405static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
406{
407 u32 tmp;
408 int chansize, numchan;
409
410 /* Get VRAM informations */
411 tmp = RREG32(mmMC_ARB_RAMCFG);
412 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
413 chansize = 64;
414 } else {
415 chansize = 32;
416 }
417 tmp = RREG32(mmMC_SHARED_CHMAP);
418 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
419 case 0:
420 default:
421 numchan = 1;
422 break;
423 case 1:
424 numchan = 2;
425 break;
426 case 2:
427 numchan = 4;
428 break;
429 case 3:
430 numchan = 8;
431 break;
432 case 4:
433 numchan = 3;
434 break;
435 case 5:
436 numchan = 6;
437 break;
438 case 6:
439 numchan = 10;
440 break;
441 case 7:
442 numchan = 12;
443 break;
444 case 8:
445 numchan = 16;
446 break;
447 }
448 adev->mc.vram_width = numchan * chansize;
449 /* Could aper size report 0 ? */
450 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
451 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
452 /* size in MB on si */
453 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
454 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
455 adev->mc.visible_vram_size = adev->mc.aper_size;
456
a1493cd5
AD		 457 /* In case the PCI BAR is larger than the actual amount of vram */
458 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
459 adev->mc.visible_vram_size = adev->mc.real_vram_size;
460
aaa36a97
AD		 461 /* unless the user had overridden it, set the gart
462 * size equal to the 1024 or vram, whichever is larger.
463 */
464 if (amdgpu_gart_size == -1)
465 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
466 else
467 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
468
469 gmc_v8_0_vram_gtt_location(adev, &adev->mc);
470
471 return 0;
472}
473
474/*
475 * GART
476 * VMID 0 is the physical GPU addresses as used by the kernel.
477 * VMIDs 1-15 are used for userspace clients and are handled
478 * by the amdgpu vm/hsa code.
479 */
480
481/**
482 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
483 *
484 * @adev: amdgpu_device pointer
485 * @vmid: vm instance to flush
486 *
487 * Flush the TLB for the requested page table (CIK).
488 */
489static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
490 uint32_t vmid)
491{
492 /* flush hdp cache */
493 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
494
495 /* bits 0-15 are the VM contexts0-15 */
496 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
497}
498
499/**
500 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
501 *
502 * @adev: amdgpu_device pointer
503 * @cpu_pt_addr: cpu address of the page table
504 * @gpu_page_idx: entry in the page table to update
505 * @addr: dst addr to write into pte/pde
506 * @flags: access flags
507 *
508 * Update the page tables using the CPU.
509 */
510static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
511 void *cpu_pt_addr,
512 uint32_t gpu_page_idx,
513 uint64_t addr,
514 uint32_t flags)
515{
516 void __iomem *ptr = (void *)cpu_pt_addr;
517 uint64_t value;
518
519 /*
520 * PTE format on VI:
521 * 63:40 reserved
522 * 39:12 4k physical page base address
523 * 11:7 fragment
524 * 6 write
525 * 5 read
526 * 4 exe
527 * 3 reserved
528 * 2 snooped
529 * 1 system
530 * 0 valid
531 *
532 * PDE format on VI:
533 * 63:59 block fragment size
534 * 58:40 reserved
535 * 39:1 physical base address of PTE
536 * bits 5:1 must be 0.
537 * 0 valid
538 */
539 value = addr & 0x000000FFFFFFF000ULL;
540 value |= flags;
541 writeq(value, ptr + (gpu_page_idx * 8));
542
543 return 0;
544}
545
d9c13156
CK		 546/**
547 * gmc_v8_0_set_fault_enable_default - update VM fault handling
548 *
549 * @adev: amdgpu_device pointer
550 * @value: true redirects VM faults to the default page
551 */
552static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
553 bool value)
554{
555 u32 tmp;
556
557 tmp = RREG32(mmVM_CONTEXT1_CNTL);
558 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
559 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
561 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
562 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
563 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
564 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
565 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
566 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
567 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
568 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
569 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
570 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
571 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
572 WREG32(mmVM_CONTEXT1_CNTL, tmp);
573}
574
aaa36a97
AD		 575/**
576 * gmc_v8_0_gart_enable - gart enable
577 *
578 * @adev: amdgpu_device pointer
579 *
580 * This sets up the TLBs, programs the page tables for VMID0,
581 * sets up the hw for VMIDs 1-15 which are allocated on
582 * demand, and sets up the global locations for the LDS, GDS,
583 * and GPUVM for FSA64 clients (CIK).
584 * Returns 0 for success, errors for failure.
585 */
586static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
587{
588 int r, i;
589 u32 tmp;
590
591 if (adev->gart.robj == NULL) {
592 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
593 return -EINVAL;
594 }
595 r = amdgpu_gart_table_vram_pin(adev);
596 if (r)
597 return r;
598 /* Setup TLB control */
599 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
600 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
601 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
602 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
603 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
604 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
605 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
606 /* Setup L2 cache */
607 tmp = RREG32(mmVM_L2_CNTL);
608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
609 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
610 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
612 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
613 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
a80b3047 614 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
aaa36a97
AD		 615 WREG32(mmVM_L2_CNTL, tmp);
616 tmp = RREG32(mmVM_L2_CNTL2);
617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
618 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
619 WREG32(mmVM_L2_CNTL2, tmp);
620 tmp = RREG32(mmVM_L2_CNTL3);
621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
624 WREG32(mmVM_L2_CNTL3, tmp);
625 /* XXX: set to enable PTE/PDE in system memory */
626 tmp = RREG32(mmVM_L2_CNTL4);
627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
639 WREG32(mmVM_L2_CNTL4, tmp);
640 /* setup context0 */
641 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
9c97b5ab 642 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
aaa36a97
AD		 643 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
644 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
645 (u32)(adev->dummy_page.addr >> 12));
646 WREG32(mmVM_CONTEXT0_CNTL2, 0);
647 tmp = RREG32(mmVM_CONTEXT0_CNTL);
648 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
649 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
650 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
651 WREG32(mmVM_CONTEXT0_CNTL, tmp);
652
653 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
654 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
655 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
656
657 /* empty context1-15 */
658 /* FIXME start with 4G, once using 2 level pt switch to full
659 * vm size space
660 */
661 /* set vm size, must be a multiple of 4 */
662 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
25a595e4 663 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
aaa36a97
AD		 664 for (i = 1; i < 16; i++) {
665 if (i < 8)
666 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
667 adev->gart.table_addr >> 12);
668 else
669 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
670 adev->gart.table_addr >> 12);
671 }
672
673 /* enable context1-15 */
674 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
675 (u32)(adev->dummy_page.addr >> 12));
676 WREG32(mmVM_CONTEXT1_CNTL2, 4);
677 tmp = RREG32(mmVM_CONTEXT1_CNTL);
678 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
aaa36a97 680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 681 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 682 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 683 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 684 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97 685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
aaa36a97
AD		 686 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
687 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
688 amdgpu_vm_block_size - 9);
689 WREG32(mmVM_CONTEXT1_CNTL, tmp);
d9c13156
CK		 690 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
691 gmc_v8_0_set_fault_enable_default(adev, false);
692 else
693 gmc_v8_0_set_fault_enable_default(adev, true);
aaa36a97
AD		 694
695 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
696 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
697 (unsigned)(adev->mc.gtt_size >> 20),
698 (unsigned long long)adev->gart.table_addr);
699 adev->gart.ready = true;
700 return 0;
701}
702
703static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
704{
705 int r;
706
707 if (adev->gart.robj) {
708 WARN(1, "R600 PCIE GART already initialized\n");
709 return 0;
710 }
711 /* Initialize common gart structure */
712 r = amdgpu_gart_init(adev);
713 if (r)
714 return r;
715 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
716 return amdgpu_gart_table_vram_alloc(adev);
717}
718
719/**
720 * gmc_v8_0_gart_disable - gart disable
721 *
722 * @adev: amdgpu_device pointer
723 *
724 * This disables all VM page table (CIK).
725 */
726static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
727{
728 u32 tmp;
729
730 /* Disable all tables */
731 WREG32(mmVM_CONTEXT0_CNTL, 0);
732 WREG32(mmVM_CONTEXT1_CNTL, 0);
733 /* Setup TLB control */
734 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
735 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
736 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
737 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
738 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
739 /* Setup L2 cache */
740 tmp = RREG32(mmVM_L2_CNTL);
741 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
742 WREG32(mmVM_L2_CNTL, tmp);
743 WREG32(mmVM_L2_CNTL2, 0);
744 amdgpu_gart_table_vram_unpin(adev);
745}
746
747/**
748 * gmc_v8_0_gart_fini - vm fini callback
749 *
750 * @adev: amdgpu_device pointer
751 *
752 * Tears down the driver GART/VM setup (CIK).
753 */
754static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
755{
756 amdgpu_gart_table_vram_free(adev);
757 amdgpu_gart_fini(adev);
758}
759
760/*
761 * vm
762 * VMID 0 is the physical GPU addresses as used by the kernel.
763 * VMIDs 1-15 are used for userspace clients and are handled
764 * by the amdgpu vm/hsa code.
765 */
766/**
767 * gmc_v8_0_vm_init - cik vm init callback
768 *
769 * @adev: amdgpu_device pointer
770 *
771 * Inits cik specific vm parameters (number of VMs, base of vram for
772 * VMIDs 1-15) (CIK).
773 * Returns 0 for success.
774 */
775static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
776{
777 /*
778 * number of VMs
779 * VMID 0 is reserved for System
780 * amdgpu graphics/compute will use VMIDs 1-7
781 * amdkfd will use VMIDs 8-15
782 */
a9a78b32
CK		 783 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
784 amdgpu_vm_manager_init(adev);
aaa36a97
AD		 785
786 /* base offset of vram pages */
2f7d10b3 787 if (adev->flags & AMD_IS_APU) {
aaa36a97
AD		 788 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
789 tmp <<= 22;
790 adev->vm_manager.vram_base_offset = tmp;
791 } else
792 adev->vm_manager.vram_base_offset = 0;
793
794 return 0;
795}
796
797/**
798 * gmc_v8_0_vm_fini - cik vm fini callback
799 *
800 * @adev: amdgpu_device pointer
801 *
802 * Tear down any asic specific VM setup (CIK).
803 */
804static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
805{
806}
807
808/**
809 * gmc_v8_0_vm_decode_fault - print human readable fault info
810 *
811 * @adev: amdgpu_device pointer
812 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
813 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
814 *
815 * Print human readable fault information (CIK).
816 */
817static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
818 u32 status, u32 addr, u32 mc_client)
819{
820 u32 mc_id;
821 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
822 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
823 PROTECTIONS);
824 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
825 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
826
827 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
828 MEMORY_CLIENT_ID);
829
830 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
831 protections, vmid, addr,
832 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
833 MEMORY_CLIENT_RW) ?
834 "write" : "read", block, mc_client, mc_id);
835}
836
81c59f54
KW		 837static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
838{
839 switch (mc_seq_vram_type) {
840 case MC_SEQ_MISC0__MT__GDDR1:
841 return AMDGPU_VRAM_TYPE_GDDR1;
842 case MC_SEQ_MISC0__MT__DDR2:
843 return AMDGPU_VRAM_TYPE_DDR2;
844 case MC_SEQ_MISC0__MT__GDDR3:
845 return AMDGPU_VRAM_TYPE_GDDR3;
846 case MC_SEQ_MISC0__MT__GDDR4:
847 return AMDGPU_VRAM_TYPE_GDDR4;
848 case MC_SEQ_MISC0__MT__GDDR5:
849 return AMDGPU_VRAM_TYPE_GDDR5;
850 case MC_SEQ_MISC0__MT__HBM:
851 return AMDGPU_VRAM_TYPE_HBM;
852 case MC_SEQ_MISC0__MT__DDR3:
853 return AMDGPU_VRAM_TYPE_DDR3;
854 default:
855 return AMDGPU_VRAM_TYPE_UNKNOWN;
856 }
857}
858
5fc3aeeb 859static int gmc_v8_0_early_init(void *handle)
aaa36a97 860{
5fc3aeeb 861 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
862
aaa36a97
AD		 863 gmc_v8_0_set_gart_funcs(adev);
864 gmc_v8_0_set_irq_funcs(adev);
865
aaa36a97
AD		 866 return 0;
867}
868
140b519f
CK		 869static int gmc_v8_0_late_init(void *handle)
870{
871 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
872
873 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
874}
875
b634de4f
AD		 876#define mmMC_SEQ_MISC0_FIJI 0xA71
877
5fc3aeeb 878static int gmc_v8_0_sw_init(void *handle)
aaa36a97
AD		 879{
880 int r;
881 int dma_bits;
5fc3aeeb 882 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 883
d1518a1d
AD		 884 if (adev->flags & AMD_IS_APU) {
885 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
886 } else {
b634de4f
AD		 887 u32 tmp;
888
889 if (adev->asic_type == CHIP_FIJI)
890 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
891 else
892 tmp = RREG32(mmMC_SEQ_MISC0);
d1518a1d
AD		 893 tmp &= MC_SEQ_MISC0__MT__MASK;
894 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
895 }
896
aaa36a97
AD		 897 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
898 if (r)
899 return r;
900
901 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
902 if (r)
903 return r;
904
905 /* Adjust VM size here.
906 * Currently set to 4GB ((1 << 20) 4k pages).
907 * Max GPUVM size for cayman and SI is 40 bits.
908 */
909 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
910
911 /* Set the internal MC address mask
912 * This is the max address of the GPU's
913 * internal address space.
914 */
915 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
916
917 /* set DMA mask + need_dma32 flags.
918 * PCIE - can handle 40-bits.
919 * IGP - can handle 40-bits
920 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
921 */
922 adev->need_dma32 = false;
923 dma_bits = adev->need_dma32 ? 32 : 40;
924 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
925 if (r) {
926 adev->need_dma32 = true;
927 dma_bits = 32;
928 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
929 }
930 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
931 if (r) {
932 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
933 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
934 }
935
936 r = gmc_v8_0_init_microcode(adev);
937 if (r) {
938 DRM_ERROR("Failed to load mc firmware!\n");
939 return r;
940 }
941
942 r = gmc_v8_0_mc_init(adev);
943 if (r)
944 return r;
945
946 /* Memory manager */
947 r = amdgpu_bo_init(adev);
948 if (r)
949 return r;
950
951 r = gmc_v8_0_gart_init(adev);
952 if (r)
953 return r;
954
955 if (!adev->vm_manager.enabled) {
956 r = gmc_v8_0_vm_init(adev);
957 if (r) {
958 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
959 return r;
960 }
961 adev->vm_manager.enabled = true;
962 }
963
964 return r;
965}
966
5fc3aeeb 967static int gmc_v8_0_sw_fini(void *handle)
aaa36a97 968{
5fc3aeeb 969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 970
971 if (adev->vm_manager.enabled) {
ea89f8c9 972 amdgpu_vm_manager_fini(adev);
aaa36a97
AD		 973 gmc_v8_0_vm_fini(adev);
974 adev->vm_manager.enabled = false;
975 }
976 gmc_v8_0_gart_fini(adev);
418aa0c2 977 amdgpu_gem_force_release(adev);
aaa36a97
AD		 978 amdgpu_bo_fini(adev);
979
980 return 0;
981}
982
5fc3aeeb 983static int gmc_v8_0_hw_init(void *handle)
aaa36a97
AD		 984{
985 int r;
5fc3aeeb 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 987
988 gmc_v8_0_init_golden_registers(adev);
989
990 gmc_v8_0_mc_program(adev);
991
8878d854 992 if (adev->asic_type == CHIP_TONGA) {
aaa36a97
AD		 993 r = gmc_v8_0_mc_load_microcode(adev);
994 if (r) {
995 DRM_ERROR("Failed to load MC firmware!\n");
996 return r;
997 }
998 }
999
1000 r = gmc_v8_0_gart_enable(adev);
1001 if (r)
1002 return r;
1003
1004 return r;
1005}
1006
5fc3aeeb 1007static int gmc_v8_0_hw_fini(void *handle)
aaa36a97 1008{
5fc3aeeb 1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1010
140b519f 1011 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
aaa36a97
AD		 1012 gmc_v8_0_gart_disable(adev);
1013
1014 return 0;
1015}
1016
5fc3aeeb 1017static int gmc_v8_0_suspend(void *handle)
aaa36a97 1018{
5fc3aeeb 1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1020
1021 if (adev->vm_manager.enabled) {
aaa36a97
AD		 1022 gmc_v8_0_vm_fini(adev);
1023 adev->vm_manager.enabled = false;
1024 }
1025 gmc_v8_0_hw_fini(adev);
1026
1027 return 0;
1028}
1029
5fc3aeeb 1030static int gmc_v8_0_resume(void *handle)
aaa36a97
AD		 1031{
1032 int r;
5fc3aeeb 1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1034
1035 r = gmc_v8_0_hw_init(adev);
1036 if (r)
1037 return r;
1038
1039 if (!adev->vm_manager.enabled) {
1040 r = gmc_v8_0_vm_init(adev);
1041 if (r) {
1042 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1043 return r;
1044 }
1045 adev->vm_manager.enabled = true;
1046 }
1047
1048 return r;
1049}
1050
5fc3aeeb 1051static bool gmc_v8_0_is_idle(void *handle)
aaa36a97 1052{
5fc3aeeb 1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1054 u32 tmp = RREG32(mmSRBM_STATUS);
1055
1056 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1057 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1058 return false;
1059
1060 return true;
1061}
1062
5fc3aeeb 1063static int gmc_v8_0_wait_for_idle(void *handle)
aaa36a97
AD		 1064{
1065 unsigned i;
1066 u32 tmp;
5fc3aeeb 1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1068
1069 for (i = 0; i < adev->usec_timeout; i++) {
1070 /* read MC_STATUS */
1071 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1072 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1073 SRBM_STATUS__MCC_BUSY_MASK |
1074 SRBM_STATUS__MCD_BUSY_MASK |
1075 SRBM_STATUS__VMC_BUSY_MASK |
1076 SRBM_STATUS__VMC1_BUSY_MASK);
1077 if (!tmp)
1078 return 0;
1079 udelay(1);
1080 }
1081 return -ETIMEDOUT;
1082
1083}
1084
5fc3aeeb 1085static void gmc_v8_0_print_status(void *handle)
aaa36a97
AD		 1086{
1087 int i, j;
5fc3aeeb 1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1089
1090 dev_info(adev->dev, "GMC 8.x registers\n");
1091 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1092 RREG32(mmSRBM_STATUS));
1093 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1094 RREG32(mmSRBM_STATUS2));
1095
1096 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1097 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1098 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1099 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1100 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1101 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1102 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1103 RREG32(mmVM_L2_CNTL));
1104 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1105 RREG32(mmVM_L2_CNTL2));
1106 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1107 RREG32(mmVM_L2_CNTL3));
1108 dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n",
1109 RREG32(mmVM_L2_CNTL4));
1110 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1111 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1112 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1113 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1114 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1115 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1116 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1117 RREG32(mmVM_CONTEXT0_CNTL2));
1118 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1119 RREG32(mmVM_CONTEXT0_CNTL));
1120 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1121 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1122 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1123 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1124 dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1125 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1126 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1127 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1128 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1129 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1130 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1131 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1132 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1133 RREG32(mmVM_CONTEXT1_CNTL2));
1134 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1135 RREG32(mmVM_CONTEXT1_CNTL));
1136 for (i = 0; i < 16; i++) {
1137 if (i < 8)
1138 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1139 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1140 else
1141 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1142 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1143 }
1144 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1145 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1146 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1147 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1148 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1149 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1150 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1151 RREG32(mmMC_VM_FB_LOCATION));
1152 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1153 RREG32(mmMC_VM_AGP_BASE));
1154 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1155 RREG32(mmMC_VM_AGP_TOP));
1156 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1157 RREG32(mmMC_VM_AGP_BOT));
1158
1159 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1160 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1161 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1162 RREG32(mmHDP_NONSURFACE_BASE));
1163 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1164 RREG32(mmHDP_NONSURFACE_INFO));
1165 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1166 RREG32(mmHDP_NONSURFACE_SIZE));
1167 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1168 RREG32(mmHDP_MISC_CNTL));
1169 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1170 RREG32(mmHDP_HOST_PATH_CNTL));
1171
1172 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1173 dev_info(adev->dev, " %d:\n", i);
1174 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1175 0xb05 + j, RREG32(0xb05 + j));
1176 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1177 0xb06 + j, RREG32(0xb06 + j));
1178 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1179 0xb07 + j, RREG32(0xb07 + j));
1180 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1181 0xb08 + j, RREG32(0xb08 + j));
1182 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1183 0xb09 + j, RREG32(0xb09 + j));
1184 }
1185
1186 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1187 RREG32(mmBIF_FB_EN));
1188}
1189
5fc3aeeb 1190static int gmc_v8_0_soft_reset(void *handle)
aaa36a97
AD		 1191{
1192 struct amdgpu_mode_mc_save save;
1193 u32 srbm_soft_reset = 0;
5fc3aeeb 1194 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97
AD		 1195 u32 tmp = RREG32(mmSRBM_STATUS);
1196
1197 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1198 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1199 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1200
1201 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1202 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
2f7d10b3 1203 if (!(adev->flags & AMD_IS_APU))
aaa36a97
AD		 1204 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1205 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1206 }
1207
1208 if (srbm_soft_reset) {
5fc3aeeb 1209 gmc_v8_0_print_status((void *)adev);
aaa36a97
AD		 1210
1211 gmc_v8_0_mc_stop(adev, &save);
1212 if (gmc_v8_0_wait_for_idle(adev)) {
1213 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1214 }
1215
1216
1217 tmp = RREG32(mmSRBM_SOFT_RESET);
1218 tmp |= srbm_soft_reset;
1219 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1220 WREG32(mmSRBM_SOFT_RESET, tmp);
1221 tmp = RREG32(mmSRBM_SOFT_RESET);
1222
1223 udelay(50);
1224
1225 tmp &= ~srbm_soft_reset;
1226 WREG32(mmSRBM_SOFT_RESET, tmp);
1227 tmp = RREG32(mmSRBM_SOFT_RESET);
1228
1229 /* Wait a little for things to settle down */
1230 udelay(50);
1231
1232 gmc_v8_0_mc_resume(adev, &save);
1233 udelay(50);
1234
5fc3aeeb 1235 gmc_v8_0_print_status((void *)adev);
aaa36a97
AD		 1236 }
1237
1238 return 0;
1239}
1240
1241static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1242 struct amdgpu_irq_src *src,
1243 unsigned type,
1244 enum amdgpu_interrupt_state state)
1245{
1246 u32 tmp;
1247 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1248 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1249 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1250 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1251 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1252 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1253 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1254
1255 switch (state) {
1256 case AMDGPU_IRQ_STATE_DISABLE:
1257 /* system context */
1258 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1259 tmp &= ~bits;
1260 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1261 /* VMs */
1262 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1263 tmp &= ~bits;
1264 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1265 break;
1266 case AMDGPU_IRQ_STATE_ENABLE:
1267 /* system context */
1268 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1269 tmp |= bits;
1270 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1271 /* VMs */
1272 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1273 tmp |= bits;
1274 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1275 break;
1276 default:
1277 break;
1278 }
1279
1280 return 0;
1281}
1282
1283static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1284 struct amdgpu_irq_src *source,
1285 struct amdgpu_iv_entry *entry)
1286{
1287 u32 addr, status, mc_client;
1288
1289 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1290 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1291 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
ce0c6bcd
CK		 1292 /* reset addr and status */
1293 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1294
1295 if (!addr && !status)
1296 return 0;
1297
d9c13156
CK		 1298 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1299 gmc_v8_0_set_fault_enable_default(adev, false);
1300
aaa36a97
AD		 1301 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1302 entry->src_id, entry->src_data);
1303 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1304 addr);
1305 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1306 status);
1307 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
aaa36a97
AD		 1308
1309 return 0;
1310}
1311
a0d69786
EH		 1312static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1313 bool enable)
1314{
1315 uint32_t data;
1316
1317 if (enable) {
1318 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1319 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1320 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1321
1322 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1323 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1324 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1325
1326 data = RREG32(mmMC_HUB_MISC_VM_CG);
1327 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1328 WREG32(mmMC_HUB_MISC_VM_CG, data);
1329
1330 data = RREG32(mmMC_XPB_CLK_GAT);
1331 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1332 WREG32(mmMC_XPB_CLK_GAT, data);
1333
1334 data = RREG32(mmATC_MISC_CG);
1335 data |= ATC_MISC_CG__ENABLE_MASK;
1336 WREG32(mmATC_MISC_CG, data);
1337
1338 data = RREG32(mmMC_CITF_MISC_WR_CG);
1339 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1340 WREG32(mmMC_CITF_MISC_WR_CG, data);
1341
1342 data = RREG32(mmMC_CITF_MISC_RD_CG);
1343 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1344 WREG32(mmMC_CITF_MISC_RD_CG, data);
1345
1346 data = RREG32(mmMC_CITF_MISC_VM_CG);
1347 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1348 WREG32(mmMC_CITF_MISC_VM_CG, data);
1349
1350 data = RREG32(mmVM_L2_CG);
1351 data |= VM_L2_CG__ENABLE_MASK;
1352 WREG32(mmVM_L2_CG, data);
1353 } else {
1354 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1355 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1356 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1357
1358 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1359 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1360 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1361
1362 data = RREG32(mmMC_HUB_MISC_VM_CG);
1363 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1364 WREG32(mmMC_HUB_MISC_VM_CG, data);
1365
1366 data = RREG32(mmMC_XPB_CLK_GAT);
1367 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1368 WREG32(mmMC_XPB_CLK_GAT, data);
1369
1370 data = RREG32(mmATC_MISC_CG);
1371 data &= ~ATC_MISC_CG__ENABLE_MASK;
1372 WREG32(mmATC_MISC_CG, data);
1373
1374 data = RREG32(mmMC_CITF_MISC_WR_CG);
1375 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1376 WREG32(mmMC_CITF_MISC_WR_CG, data);
1377
1378 data = RREG32(mmMC_CITF_MISC_RD_CG);
1379 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1380 WREG32(mmMC_CITF_MISC_RD_CG, data);
1381
1382 data = RREG32(mmMC_CITF_MISC_VM_CG);
1383 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1384 WREG32(mmMC_CITF_MISC_VM_CG, data);
1385
1386 data = RREG32(mmVM_L2_CG);
1387 data &= ~VM_L2_CG__ENABLE_MASK;
1388 WREG32(mmVM_L2_CG, data);
1389 }
1390}
1391
1392static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1393 bool enable)
1394{
1395 uint32_t data;
1396
1397 if (enable) {
1398 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1399 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1400 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1401
1402 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1403 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1404 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1405
1406 data = RREG32(mmMC_HUB_MISC_VM_CG);
1407 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1408 WREG32(mmMC_HUB_MISC_VM_CG, data);
1409
1410 data = RREG32(mmMC_XPB_CLK_GAT);
1411 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1412 WREG32(mmMC_XPB_CLK_GAT, data);
1413
1414 data = RREG32(mmATC_MISC_CG);
1415 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1416 WREG32(mmATC_MISC_CG, data);
1417
1418 data = RREG32(mmMC_CITF_MISC_WR_CG);
1419 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1420 WREG32(mmMC_CITF_MISC_WR_CG, data);
1421
1422 data = RREG32(mmMC_CITF_MISC_RD_CG);
1423 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1424 WREG32(mmMC_CITF_MISC_RD_CG, data);
1425
1426 data = RREG32(mmMC_CITF_MISC_VM_CG);
1427 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1428 WREG32(mmMC_CITF_MISC_VM_CG, data);
1429
1430 data = RREG32(mmVM_L2_CG);
1431 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1432 WREG32(mmVM_L2_CG, data);
1433 } else {
1434 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1435 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1436 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1437
1438 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1439 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1440 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1441
1442 data = RREG32(mmMC_HUB_MISC_VM_CG);
1443 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1444 WREG32(mmMC_HUB_MISC_VM_CG, data);
1445
1446 data = RREG32(mmMC_XPB_CLK_GAT);
1447 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1448 WREG32(mmMC_XPB_CLK_GAT, data);
1449
1450 data = RREG32(mmATC_MISC_CG);
1451 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1452 WREG32(mmATC_MISC_CG, data);
1453
1454 data = RREG32(mmMC_CITF_MISC_WR_CG);
1455 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1456 WREG32(mmMC_CITF_MISC_WR_CG, data);
1457
1458 data = RREG32(mmMC_CITF_MISC_RD_CG);
1459 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1460 WREG32(mmMC_CITF_MISC_RD_CG, data);
1461
1462 data = RREG32(mmMC_CITF_MISC_VM_CG);
1463 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1464 WREG32(mmMC_CITF_MISC_VM_CG, data);
1465
1466 data = RREG32(mmVM_L2_CG);
1467 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1468 WREG32(mmVM_L2_CG, data);
1469 }
1470}
1471
5fc3aeeb 1472static int gmc_v8_0_set_clockgating_state(void *handle,
1473 enum amd_clockgating_state state)
aaa36a97 1474{
a0d69786
EH		 1475 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1476
1477 switch (adev->asic_type) {
1478 case CHIP_FIJI:
1479 fiji_update_mc_medium_grain_clock_gating(adev,
1480 state == AMD_CG_STATE_GATE ? true : false);
1481 fiji_update_mc_light_sleep(adev,
1482 state == AMD_CG_STATE_GATE ? true : false);
1483 break;
1484 default:
1485 break;
1486 }
aaa36a97
AD		 1487 return 0;
1488}
1489
5fc3aeeb 1490static int gmc_v8_0_set_powergating_state(void *handle,
1491 enum amd_powergating_state state)
aaa36a97
AD		 1492{
1493 return 0;
1494}
1495
5fc3aeeb 1496const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
aaa36a97 1497 .early_init = gmc_v8_0_early_init,
140b519f 1498 .late_init = gmc_v8_0_late_init,
aaa36a97
AD		 1499 .sw_init = gmc_v8_0_sw_init,
1500 .sw_fini = gmc_v8_0_sw_fini,
1501 .hw_init = gmc_v8_0_hw_init,
1502 .hw_fini = gmc_v8_0_hw_fini,
1503 .suspend = gmc_v8_0_suspend,
1504 .resume = gmc_v8_0_resume,
1505 .is_idle = gmc_v8_0_is_idle,
1506 .wait_for_idle = gmc_v8_0_wait_for_idle,
1507 .soft_reset = gmc_v8_0_soft_reset,
1508 .print_status = gmc_v8_0_print_status,
1509 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1510 .set_powergating_state = gmc_v8_0_set_powergating_state,
1511};
1512
1513static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1514 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1515 .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1516};
1517
1518static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1519 .set = gmc_v8_0_vm_fault_interrupt_state,
1520 .process = gmc_v8_0_process_interrupt,
1521};
1522
1523static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1524{
1525 if (adev->gart.gart_funcs == NULL)
1526 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1527}
1528
1529static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1530{
1531 adev->mc.vm_fault.num_types = 1;
1532 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1533}
Linux kernel - Deliverables
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