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aaa36a97 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Alex Deucher | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include <drm/drmP.h> | |
26 | #include "amdgpu.h" | |
27 | #include "amdgpu_ucode.h" | |
28 | #include "amdgpu_trace.h" | |
29 | #include "vi.h" | |
30 | #include "vid.h" | |
31 | ||
32 | #include "oss/oss_2_4_d.h" | |
33 | #include "oss/oss_2_4_sh_mask.h" | |
34 | ||
16a8a49b KW |
35 | #include "gmc/gmc_7_1_d.h" |
36 | #include "gmc/gmc_7_1_sh_mask.h" | |
aaa36a97 AD |
37 | |
38 | #include "gca/gfx_8_0_d.h" | |
74a5d165 | 39 | #include "gca/gfx_8_0_enum.h" |
aaa36a97 AD |
40 | #include "gca/gfx_8_0_sh_mask.h" |
41 | ||
42 | #include "bif/bif_5_0_d.h" | |
43 | #include "bif/bif_5_0_sh_mask.h" | |
44 | ||
45 | #include "iceland_sdma_pkt_open.h" | |
46 | ||
47 | static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); | |
48 | static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); | |
49 | static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); | |
50 | static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); | |
51 | ||
c65444fe JZ |
52 | MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); |
53 | MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); | |
aaa36a97 AD |
54 | |
55 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = | |
56 | { | |
57 | SDMA0_REGISTER_OFFSET, | |
58 | SDMA1_REGISTER_OFFSET | |
59 | }; | |
60 | ||
61 | static const u32 golden_settings_iceland_a11[] = | |
62 | { | |
63 | mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
64 | mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, | |
65 | mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, | |
66 | mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, | |
67 | }; | |
68 | ||
69 | static const u32 iceland_mgcg_cgcg_init[] = | |
70 | { | |
71 | mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, | |
72 | mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 | |
73 | }; | |
74 | ||
75 | /* | |
76 | * sDMA - System DMA | |
77 | * Starting with CIK, the GPU has new asynchronous | |
78 | * DMA engines. These engines are used for compute | |
79 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | |
80 | * and each one supports 1 ring buffer used for gfx | |
81 | * and 2 queues used for compute. | |
82 | * | |
83 | * The programming model is very similar to the CP | |
84 | * (ring buffer, IBs, etc.), but sDMA has it's own | |
85 | * packet format that is different from the PM4 format | |
86 | * used by the CP. sDMA supports copying data, writing | |
87 | * embedded data, solid fills, and a number of other | |
88 | * things. It also has support for tiling/detiling of | |
89 | * buffers. | |
90 | */ | |
91 | ||
92 | static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) | |
93 | { | |
94 | switch (adev->asic_type) { | |
95 | case CHIP_TOPAZ: | |
96 | amdgpu_program_register_sequence(adev, | |
97 | iceland_mgcg_cgcg_init, | |
98 | (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); | |
99 | amdgpu_program_register_sequence(adev, | |
100 | golden_settings_iceland_a11, | |
101 | (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); | |
102 | break; | |
103 | default: | |
104 | break; | |
105 | } | |
106 | } | |
107 | ||
9c55c520 ML |
108 | static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) |
109 | { | |
110 | int i; | |
111 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
112 | release_firmware(adev->sdma.instance[i].fw); | |
113 | adev->sdma.instance[i].fw = NULL; | |
114 | } | |
115 | } | |
116 | ||
aaa36a97 AD |
117 | /** |
118 | * sdma_v2_4_init_microcode - load ucode images from disk | |
119 | * | |
120 | * @adev: amdgpu_device pointer | |
121 | * | |
122 | * Use the firmware interface to load the ucode images into | |
123 | * the driver (not loaded into hw). | |
124 | * Returns 0 on success, error on failure. | |
125 | */ | |
126 | static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) | |
127 | { | |
128 | const char *chip_name; | |
129 | char fw_name[30]; | |
c113ea1c | 130 | int err = 0, i; |
aaa36a97 AD |
131 | struct amdgpu_firmware_info *info = NULL; |
132 | const struct common_firmware_header *header = NULL; | |
595fd013 | 133 | const struct sdma_firmware_header_v1_0 *hdr; |
aaa36a97 AD |
134 | |
135 | DRM_DEBUG("\n"); | |
136 | ||
137 | switch (adev->asic_type) { | |
138 | case CHIP_TOPAZ: | |
139 | chip_name = "topaz"; | |
140 | break; | |
141 | default: BUG(); | |
142 | } | |
143 | ||
c113ea1c | 144 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 | 145 | if (i == 0) |
c65444fe | 146 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); |
aaa36a97 | 147 | else |
c65444fe | 148 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); |
c113ea1c | 149 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); |
aaa36a97 AD |
150 | if (err) |
151 | goto out; | |
c113ea1c | 152 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); |
aaa36a97 AD |
153 | if (err) |
154 | goto out; | |
c113ea1c AD |
155 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; |
156 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); | |
157 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); | |
158 | if (adev->sdma.instance[i].feature_version >= 20) | |
159 | adev->sdma.instance[i].burst_nop = true; | |
aaa36a97 AD |
160 | |
161 | if (adev->firmware.smu_load) { | |
162 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | |
163 | info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | |
c113ea1c | 164 | info->fw = adev->sdma.instance[i].fw; |
aaa36a97 AD |
165 | header = (const struct common_firmware_header *)info->fw->data; |
166 | adev->firmware.fw_size += | |
167 | ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); | |
168 | } | |
169 | } | |
170 | ||
171 | out: | |
172 | if (err) { | |
173 | printk(KERN_ERR | |
174 | "sdma_v2_4: Failed to load firmware \"%s\"\n", | |
175 | fw_name); | |
c113ea1c AD |
176 | for (i = 0; i < adev->sdma.num_instances; i++) { |
177 | release_firmware(adev->sdma.instance[i].fw); | |
178 | adev->sdma.instance[i].fw = NULL; | |
aaa36a97 AD |
179 | } |
180 | } | |
181 | return err; | |
182 | } | |
183 | ||
184 | /** | |
185 | * sdma_v2_4_ring_get_rptr - get the current read pointer | |
186 | * | |
187 | * @ring: amdgpu ring pointer | |
188 | * | |
189 | * Get the current rptr from the hardware (VI+). | |
190 | */ | |
191 | static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) | |
192 | { | |
193 | u32 rptr; | |
194 | ||
195 | /* XXX check if swapping is necessary on BE */ | |
196 | rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; | |
197 | ||
198 | return rptr; | |
199 | } | |
200 | ||
201 | /** | |
202 | * sdma_v2_4_ring_get_wptr - get the current write pointer | |
203 | * | |
204 | * @ring: amdgpu ring pointer | |
205 | * | |
206 | * Get the current wptr from the hardware (VI+). | |
207 | */ | |
208 | static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) | |
209 | { | |
210 | struct amdgpu_device *adev = ring->adev; | |
c113ea1c | 211 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 AD |
212 | u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; |
213 | ||
214 | return wptr; | |
215 | } | |
216 | ||
217 | /** | |
218 | * sdma_v2_4_ring_set_wptr - commit the write pointer | |
219 | * | |
220 | * @ring: amdgpu ring pointer | |
221 | * | |
222 | * Write the wptr back to the hardware (VI+). | |
223 | */ | |
224 | static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) | |
225 | { | |
226 | struct amdgpu_device *adev = ring->adev; | |
c113ea1c | 227 | int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; |
aaa36a97 AD |
228 | |
229 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); | |
230 | } | |
231 | ||
ac01db3d JZ |
232 | static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
233 | { | |
c113ea1c | 234 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
235 | int i; |
236 | ||
237 | for (i = 0; i < count; i++) | |
238 | if (sdma && sdma->burst_nop && (i == 0)) | |
239 | amdgpu_ring_write(ring, ring->nop | | |
240 | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); | |
241 | else | |
242 | amdgpu_ring_write(ring, ring->nop); | |
243 | } | |
244 | ||
aaa36a97 AD |
245 | /** |
246 | * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine | |
247 | * | |
248 | * @ring: amdgpu ring pointer | |
249 | * @ib: IB object to schedule | |
250 | * | |
251 | * Schedule an IB in the DMA ring (VI). | |
252 | */ | |
253 | static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, | |
d88bf583 CK |
254 | struct amdgpu_ib *ib, |
255 | unsigned vm_id, bool ctx_switch) | |
aaa36a97 | 256 | { |
d88bf583 | 257 | u32 vmid = vm_id & 0xf; |
aaa36a97 | 258 | |
aaa36a97 | 259 | /* IB packet must end on a 8 DW boundary */ |
ac01db3d JZ |
260 | sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); |
261 | ||
aaa36a97 AD |
262 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | |
263 | SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); | |
264 | /* base must be 32 byte aligned */ | |
265 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); | |
266 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); | |
267 | amdgpu_ring_write(ring, ib->length_dw); | |
268 | amdgpu_ring_write(ring, 0); | |
269 | amdgpu_ring_write(ring, 0); | |
270 | ||
271 | } | |
272 | ||
273 | /** | |
274 | * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring | |
275 | * | |
276 | * @ring: amdgpu ring pointer | |
277 | * | |
278 | * Emit an hdp flush packet on the requested DMA ring. | |
279 | */ | |
d2edb07b | 280 | static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
aaa36a97 AD |
281 | { |
282 | u32 ref_and_mask = 0; | |
283 | ||
c113ea1c | 284 | if (ring == &ring->adev->sdma.instance[0].ring) |
aaa36a97 AD |
285 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); |
286 | else | |
287 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); | |
288 | ||
289 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
290 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | | |
291 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ | |
292 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); | |
293 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); | |
294 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | |
295 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | |
296 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
297 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
298 | } | |
299 | ||
6ad550c3 CZ |
300 | static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) |
301 | { | |
302 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | | |
303 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
304 | amdgpu_ring_write(ring, mmHDP_DEBUG0); | |
305 | amdgpu_ring_write(ring, 1); | |
306 | } | |
aaa36a97 AD |
307 | /** |
308 | * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring | |
309 | * | |
310 | * @ring: amdgpu ring pointer | |
311 | * @fence: amdgpu fence object | |
312 | * | |
313 | * Add a DMA fence packet to the ring to write | |
314 | * the fence seq number and DMA trap packet to generate | |
315 | * an interrupt if needed (VI). | |
316 | */ | |
317 | static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | |
890ee23f | 318 | unsigned flags) |
aaa36a97 | 319 | { |
890ee23f | 320 | bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; |
aaa36a97 AD |
321 | /* write the fence */ |
322 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
323 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
324 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
325 | amdgpu_ring_write(ring, lower_32_bits(seq)); | |
326 | ||
327 | /* optionally write high bits as well */ | |
890ee23f | 328 | if (write64bit) { |
aaa36a97 AD |
329 | addr += 4; |
330 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); | |
331 | amdgpu_ring_write(ring, lower_32_bits(addr)); | |
332 | amdgpu_ring_write(ring, upper_32_bits(addr)); | |
333 | amdgpu_ring_write(ring, upper_32_bits(seq)); | |
334 | } | |
335 | ||
336 | /* generate an interrupt */ | |
337 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); | |
338 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); | |
339 | } | |
340 | ||
aaa36a97 AD |
341 | /** |
342 | * sdma_v2_4_gfx_stop - stop the gfx async dma engines | |
343 | * | |
344 | * @adev: amdgpu_device pointer | |
345 | * | |
346 | * Stop the gfx async dma ring buffers (VI). | |
347 | */ | |
348 | static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) | |
349 | { | |
c113ea1c AD |
350 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; |
351 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | |
aaa36a97 AD |
352 | u32 rb_cntl, ib_cntl; |
353 | int i; | |
354 | ||
355 | if ((adev->mman.buffer_funcs_ring == sdma0) || | |
356 | (adev->mman.buffer_funcs_ring == sdma1)) | |
357 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); | |
358 | ||
c113ea1c | 359 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
360 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); |
361 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); | |
362 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
363 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
364 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); | |
365 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
366 | } | |
367 | sdma0->ready = false; | |
368 | sdma1->ready = false; | |
369 | } | |
370 | ||
371 | /** | |
372 | * sdma_v2_4_rlc_stop - stop the compute async dma engines | |
373 | * | |
374 | * @adev: amdgpu_device pointer | |
375 | * | |
376 | * Stop the compute async dma queues (VI). | |
377 | */ | |
378 | static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) | |
379 | { | |
380 | /* XXX todo */ | |
381 | } | |
382 | ||
383 | /** | |
384 | * sdma_v2_4_enable - stop the async dma engines | |
385 | * | |
386 | * @adev: amdgpu_device pointer | |
387 | * @enable: enable/disable the DMA MEs. | |
388 | * | |
389 | * Halt or unhalt the async dma engines (VI). | |
390 | */ | |
391 | static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) | |
392 | { | |
393 | u32 f32_cntl; | |
394 | int i; | |
395 | ||
004e29cc | 396 | if (!enable) { |
aaa36a97 AD |
397 | sdma_v2_4_gfx_stop(adev); |
398 | sdma_v2_4_rlc_stop(adev); | |
399 | } | |
400 | ||
c113ea1c | 401 | for (i = 0; i < adev->sdma.num_instances; i++) { |
aaa36a97 AD |
402 | f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); |
403 | if (enable) | |
404 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); | |
405 | else | |
406 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); | |
407 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); | |
408 | } | |
409 | } | |
410 | ||
411 | /** | |
412 | * sdma_v2_4_gfx_resume - setup and start the async dma engines | |
413 | * | |
414 | * @adev: amdgpu_device pointer | |
415 | * | |
416 | * Set up the gfx DMA ring buffers and enable them (VI). | |
417 | * Returns 0 for success, error for failure. | |
418 | */ | |
419 | static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) | |
420 | { | |
421 | struct amdgpu_ring *ring; | |
422 | u32 rb_cntl, ib_cntl; | |
423 | u32 rb_bufsz; | |
424 | u32 wb_offset; | |
425 | int i, j, r; | |
426 | ||
c113ea1c AD |
427 | for (i = 0; i < adev->sdma.num_instances; i++) { |
428 | ring = &adev->sdma.instance[i].ring; | |
aaa36a97 AD |
429 | wb_offset = (ring->rptr_offs * 4); |
430 | ||
431 | mutex_lock(&adev->srbm_mutex); | |
432 | for (j = 0; j < 16; j++) { | |
433 | vi_srbm_select(adev, 0, 0, 0, j); | |
434 | /* SDMA GFX */ | |
435 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); | |
436 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); | |
437 | } | |
438 | vi_srbm_select(adev, 0, 0, 0, 0); | |
439 | mutex_unlock(&adev->srbm_mutex); | |
440 | ||
c458fe94 AD |
441 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], |
442 | adev->gfx.config.gb_addr_config & 0x70); | |
443 | ||
aaa36a97 AD |
444 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); |
445 | ||
446 | /* Set ring buffer size in dwords */ | |
447 | rb_bufsz = order_base_2(ring->ring_size / 4); | |
448 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); | |
449 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); | |
450 | #ifdef __BIG_ENDIAN | |
451 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); | |
452 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, | |
453 | RPTR_WRITEBACK_SWAP_ENABLE, 1); | |
454 | #endif | |
455 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
456 | ||
457 | /* Initialize the ring buffer's read and write pointers */ | |
458 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); | |
459 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); | |
d72f7c06 ML |
460 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); |
461 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); | |
aaa36a97 AD |
462 | |
463 | /* set the wb address whether it's enabled or not */ | |
464 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], | |
465 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); | |
466 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], | |
467 | lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); | |
468 | ||
469 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); | |
470 | ||
471 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); | |
472 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); | |
473 | ||
474 | ring->wptr = 0; | |
475 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); | |
476 | ||
477 | /* enable DMA RB */ | |
478 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); | |
479 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); | |
480 | ||
481 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); | |
482 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); | |
483 | #ifdef __BIG_ENDIAN | |
484 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); | |
485 | #endif | |
486 | /* enable DMA IBs */ | |
487 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); | |
488 | ||
489 | ring->ready = true; | |
505dfe76 | 490 | } |
aaa36a97 | 491 | |
505dfe76 ML |
492 | sdma_v2_4_enable(adev, true); |
493 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
494 | ring = &adev->sdma.instance[i].ring; | |
aaa36a97 AD |
495 | r = amdgpu_ring_test_ring(ring); |
496 | if (r) { | |
497 | ring->ready = false; | |
498 | return r; | |
499 | } | |
500 | ||
501 | if (adev->mman.buffer_funcs_ring == ring) | |
502 | amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | /** | |
509 | * sdma_v2_4_rlc_resume - setup and start the async dma engines | |
510 | * | |
511 | * @adev: amdgpu_device pointer | |
512 | * | |
513 | * Set up the compute DMA queues and enable them (VI). | |
514 | * Returns 0 for success, error for failure. | |
515 | */ | |
516 | static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) | |
517 | { | |
518 | /* XXX todo */ | |
519 | return 0; | |
520 | } | |
521 | ||
522 | /** | |
523 | * sdma_v2_4_load_microcode - load the sDMA ME ucode | |
524 | * | |
525 | * @adev: amdgpu_device pointer | |
526 | * | |
527 | * Loads the sDMA0/1 ucode. | |
528 | * Returns 0 for success, -EINVAL if the ucode is not available. | |
529 | */ | |
530 | static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) | |
531 | { | |
532 | const struct sdma_firmware_header_v1_0 *hdr; | |
533 | const __le32 *fw_data; | |
534 | u32 fw_size; | |
535 | int i, j; | |
aaa36a97 AD |
536 | |
537 | /* halt the MEs */ | |
538 | sdma_v2_4_enable(adev, false); | |
539 | ||
c113ea1c AD |
540 | for (i = 0; i < adev->sdma.num_instances; i++) { |
541 | if (!adev->sdma.instance[i].fw) | |
542 | return -EINVAL; | |
543 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | |
544 | amdgpu_ucode_print_sdma_hdr(&hdr->header); | |
545 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; | |
546 | fw_data = (const __le32 *) | |
547 | (adev->sdma.instance[i].fw->data + | |
548 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)); | |
549 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); | |
550 | for (j = 0; j < fw_size; j++) | |
551 | WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); | |
552 | WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); | |
aaa36a97 AD |
553 | } |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | /** | |
559 | * sdma_v2_4_start - setup and start the async dma engines | |
560 | * | |
561 | * @adev: amdgpu_device pointer | |
562 | * | |
563 | * Set up the DMA engines and enable them (VI). | |
564 | * Returns 0 for success, error for failure. | |
565 | */ | |
566 | static int sdma_v2_4_start(struct amdgpu_device *adev) | |
567 | { | |
568 | int r; | |
569 | ||
86a42f04 HR |
570 | if (!adev->pp_enabled) { |
571 | if (!adev->firmware.smu_load) { | |
572 | r = sdma_v2_4_load_microcode(adev); | |
573 | if (r) | |
574 | return r; | |
575 | } else { | |
576 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | |
577 | AMDGPU_UCODE_ID_SDMA0); | |
578 | if (r) | |
579 | return -EINVAL; | |
580 | r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, | |
581 | AMDGPU_UCODE_ID_SDMA1); | |
582 | if (r) | |
583 | return -EINVAL; | |
584 | } | |
aaa36a97 AD |
585 | } |
586 | ||
505dfe76 ML |
587 | /* halt the engine before programing */ |
588 | sdma_v2_4_enable(adev, false); | |
aaa36a97 AD |
589 | |
590 | /* start the gfx rings and rlc compute queues */ | |
591 | r = sdma_v2_4_gfx_resume(adev); | |
592 | if (r) | |
593 | return r; | |
594 | r = sdma_v2_4_rlc_resume(adev); | |
595 | if (r) | |
596 | return r; | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | /** | |
602 | * sdma_v2_4_ring_test_ring - simple async dma engine test | |
603 | * | |
604 | * @ring: amdgpu_ring structure holding ring information | |
605 | * | |
606 | * Test the DMA engine by writing using it to write an | |
607 | * value to memory. (VI). | |
608 | * Returns 0 for success, error for failure. | |
609 | */ | |
610 | static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) | |
611 | { | |
612 | struct amdgpu_device *adev = ring->adev; | |
613 | unsigned i; | |
614 | unsigned index; | |
615 | int r; | |
616 | u32 tmp; | |
617 | u64 gpu_addr; | |
618 | ||
619 | r = amdgpu_wb_get(adev, &index); | |
620 | if (r) { | |
621 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); | |
622 | return r; | |
623 | } | |
624 | ||
625 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
626 | tmp = 0xCAFEDEAD; | |
627 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
628 | ||
a27de35c | 629 | r = amdgpu_ring_alloc(ring, 5); |
aaa36a97 AD |
630 | if (r) { |
631 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); | |
632 | amdgpu_wb_free(adev, index); | |
633 | return r; | |
634 | } | |
635 | ||
636 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
637 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); | |
638 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); | |
639 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); | |
640 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); | |
641 | amdgpu_ring_write(ring, 0xDEADBEEF); | |
a27de35c | 642 | amdgpu_ring_commit(ring); |
aaa36a97 AD |
643 | |
644 | for (i = 0; i < adev->usec_timeout; i++) { | |
645 | tmp = le32_to_cpu(adev->wb.wb[index]); | |
646 | if (tmp == 0xDEADBEEF) | |
647 | break; | |
648 | DRM_UDELAY(1); | |
649 | } | |
650 | ||
651 | if (i < adev->usec_timeout) { | |
652 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); | |
653 | } else { | |
654 | DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", | |
655 | ring->idx, tmp); | |
656 | r = -EINVAL; | |
657 | } | |
658 | amdgpu_wb_free(adev, index); | |
659 | ||
660 | return r; | |
661 | } | |
662 | ||
663 | /** | |
664 | * sdma_v2_4_ring_test_ib - test an IB on the DMA engine | |
665 | * | |
666 | * @ring: amdgpu_ring structure holding ring information | |
667 | * | |
668 | * Test a simple IB in the DMA ring (VI). | |
669 | * Returns 0 on success, error on failure. | |
670 | */ | |
bbec97aa | 671 | static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
aaa36a97 AD |
672 | { |
673 | struct amdgpu_device *adev = ring->adev; | |
674 | struct amdgpu_ib ib; | |
1763552e | 675 | struct fence *f = NULL; |
aaa36a97 | 676 | unsigned index; |
aaa36a97 AD |
677 | u32 tmp = 0; |
678 | u64 gpu_addr; | |
bbec97aa | 679 | long r; |
aaa36a97 AD |
680 | |
681 | r = amdgpu_wb_get(adev, &index); | |
682 | if (r) { | |
bbec97aa | 683 | dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); |
aaa36a97 AD |
684 | return r; |
685 | } | |
686 | ||
687 | gpu_addr = adev->wb.gpu_addr + (index * 4); | |
688 | tmp = 0xCAFEDEAD; | |
689 | adev->wb.wb[index] = cpu_to_le32(tmp); | |
b203dd95 | 690 | memset(&ib, 0, sizeof(ib)); |
b07c60c0 | 691 | r = amdgpu_ib_get(adev, NULL, 256, &ib); |
aaa36a97 | 692 | if (r) { |
bbec97aa | 693 | DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); |
0011fdaa | 694 | goto err0; |
aaa36a97 AD |
695 | } |
696 | ||
697 | ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
698 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); | |
699 | ib.ptr[1] = lower_32_bits(gpu_addr); | |
700 | ib.ptr[2] = upper_32_bits(gpu_addr); | |
701 | ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); | |
702 | ib.ptr[4] = 0xDEADBEEF; | |
703 | ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); | |
704 | ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); | |
705 | ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); | |
706 | ib.length_dw = 8; | |
707 | ||
c5637837 | 708 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f); |
0011fdaa CZ |
709 | if (r) |
710 | goto err1; | |
711 | ||
bbec97aa CK |
712 | r = fence_wait_timeout(f, false, timeout); |
713 | if (r == 0) { | |
714 | DRM_ERROR("amdgpu: IB test timed out\n"); | |
715 | r = -ETIMEDOUT; | |
716 | goto err1; | |
847927bb | 717 | } else if (r < 0) { |
bbec97aa | 718 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); |
0011fdaa | 719 | goto err1; |
aaa36a97 | 720 | } |
6d44565d CK |
721 | tmp = le32_to_cpu(adev->wb.wb[index]); |
722 | if (tmp == 0xDEADBEEF) { | |
723 | DRM_INFO("ib test on ring %d succeeded\n", ring->idx); | |
bbec97aa | 724 | r = 0; |
aaa36a97 AD |
725 | } else { |
726 | DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); | |
727 | r = -EINVAL; | |
728 | } | |
0011fdaa CZ |
729 | |
730 | err1: | |
cc55c45d | 731 | amdgpu_ib_free(adev, &ib, NULL); |
73cfa5f5 | 732 | fence_put(f); |
0011fdaa | 733 | err0: |
aaa36a97 AD |
734 | amdgpu_wb_free(adev, index); |
735 | return r; | |
736 | } | |
737 | ||
738 | /** | |
739 | * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART | |
740 | * | |
741 | * @ib: indirect buffer to fill with commands | |
742 | * @pe: addr of the page entry | |
743 | * @src: src addr to copy from | |
744 | * @count: number of page entries to update | |
745 | * | |
746 | * Update PTEs by copying them from the GART using sDMA (CIK). | |
747 | */ | |
748 | static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, | |
749 | uint64_t pe, uint64_t src, | |
750 | unsigned count) | |
751 | { | |
96105e53 CK |
752 | unsigned bytes = count * 8; |
753 | ||
754 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | | |
755 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
756 | ib->ptr[ib->length_dw++] = bytes; | |
757 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
758 | ib->ptr[ib->length_dw++] = lower_32_bits(src); | |
759 | ib->ptr[ib->length_dw++] = upper_32_bits(src); | |
760 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); | |
761 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
aaa36a97 AD |
762 | } |
763 | ||
764 | /** | |
765 | * sdma_v2_4_vm_write_pte - update PTEs by writing them manually | |
766 | * | |
767 | * @ib: indirect buffer to fill with commands | |
768 | * @pe: addr of the page entry | |
de9ea7bd | 769 | * @value: dst addr to write into pe |
aaa36a97 AD |
770 | * @count: number of page entries to update |
771 | * @incr: increase next addr by incr bytes | |
aaa36a97 AD |
772 | * |
773 | * Update PTEs by writing them manually using sDMA (CIK). | |
774 | */ | |
de9ea7bd CK |
775 | static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, |
776 | uint64_t value, unsigned count, | |
777 | uint32_t incr) | |
aaa36a97 | 778 | { |
de9ea7bd CK |
779 | unsigned ndw = count * 2; |
780 | ||
781 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | | |
782 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
783 | ib->ptr[ib->length_dw++] = pe; | |
784 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
785 | ib->ptr[ib->length_dw++] = ndw; | |
786 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { | |
787 | ib->ptr[ib->length_dw++] = lower_32_bits(value); | |
788 | ib->ptr[ib->length_dw++] = upper_32_bits(value); | |
789 | value += incr; | |
aaa36a97 AD |
790 | } |
791 | } | |
792 | ||
793 | /** | |
794 | * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA | |
795 | * | |
796 | * @ib: indirect buffer to fill with commands | |
797 | * @pe: addr of the page entry | |
798 | * @addr: dst addr to write into pe | |
799 | * @count: number of page entries to update | |
800 | * @incr: increase next addr by incr bytes | |
801 | * @flags: access flags | |
802 | * | |
803 | * Update the page tables using sDMA (CIK). | |
804 | */ | |
96105e53 | 805 | static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, |
aaa36a97 AD |
806 | uint64_t addr, unsigned count, |
807 | uint32_t incr, uint32_t flags) | |
808 | { | |
96105e53 CK |
809 | /* for physically contiguous pages (vram) */ |
810 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); | |
811 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ | |
812 | ib->ptr[ib->length_dw++] = upper_32_bits(pe); | |
813 | ib->ptr[ib->length_dw++] = flags; /* mask */ | |
814 | ib->ptr[ib->length_dw++] = 0; | |
815 | ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ | |
816 | ib->ptr[ib->length_dw++] = upper_32_bits(addr); | |
817 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | |
818 | ib->ptr[ib->length_dw++] = 0; | |
819 | ib->ptr[ib->length_dw++] = count; /* number of entries */ | |
aaa36a97 AD |
820 | } |
821 | ||
822 | /** | |
9e5d5309 | 823 | * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw |
aaa36a97 AD |
824 | * |
825 | * @ib: indirect buffer to fill with padding | |
826 | * | |
827 | */ | |
9e5d5309 | 828 | static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
aaa36a97 | 829 | { |
9e5d5309 | 830 | struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); |
ac01db3d JZ |
831 | u32 pad_count; |
832 | int i; | |
833 | ||
834 | pad_count = (8 - (ib->length_dw & 0x7)) % 8; | |
835 | for (i = 0; i < pad_count; i++) | |
836 | if (sdma && sdma->burst_nop && (i == 0)) | |
837 | ib->ptr[ib->length_dw++] = | |
838 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | | |
839 | SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); | |
840 | else | |
841 | ib->ptr[ib->length_dw++] = | |
842 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP); | |
aaa36a97 AD |
843 | } |
844 | ||
845 | /** | |
00b7c4ff | 846 | * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline |
aaa36a97 AD |
847 | * |
848 | * @ring: amdgpu_ring pointer | |
aaa36a97 | 849 | * |
00b7c4ff | 850 | * Make sure all previous operations are completed (CIK). |
aaa36a97 | 851 | */ |
00b7c4ff | 852 | static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
aaa36a97 | 853 | { |
5c55db83 CZ |
854 | uint32_t seq = ring->fence_drv.sync_seq; |
855 | uint64_t addr = ring->fence_drv.gpu_addr; | |
856 | ||
857 | /* wait for idle */ | |
858 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
859 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
860 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ | |
861 | SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); | |
862 | amdgpu_ring_write(ring, addr & 0xfffffffc); | |
863 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | |
864 | amdgpu_ring_write(ring, seq); /* reference */ | |
865 | amdgpu_ring_write(ring, 0xfffffff); /* mask */ | |
866 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
867 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ | |
00b7c4ff | 868 | } |
5c55db83 | 869 | |
00b7c4ff CK |
870 | /** |
871 | * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA | |
872 | * | |
873 | * @ring: amdgpu_ring pointer | |
874 | * @vm: amdgpu_vm pointer | |
875 | * | |
876 | * Update the page table base and flush the VM TLB | |
877 | * using sDMA (VI). | |
878 | */ | |
879 | static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, | |
880 | unsigned vm_id, uint64_t pd_addr) | |
881 | { | |
aaa36a97 AD |
882 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | |
883 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
884 | if (vm_id < 8) { | |
885 | amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); | |
886 | } else { | |
887 | amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); | |
888 | } | |
889 | amdgpu_ring_write(ring, pd_addr >> 12); | |
890 | ||
aaa36a97 AD |
891 | /* flush TLB */ |
892 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | | |
893 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); | |
894 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); | |
895 | amdgpu_ring_write(ring, 1 << vm_id); | |
896 | ||
897 | /* wait for flush */ | |
898 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | | |
899 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | | |
900 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ | |
901 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); | |
902 | amdgpu_ring_write(ring, 0); | |
903 | amdgpu_ring_write(ring, 0); /* reference */ | |
904 | amdgpu_ring_write(ring, 0); /* mask */ | |
905 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | | |
906 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ | |
907 | } | |
908 | ||
5fc3aeeb | 909 | static int sdma_v2_4_early_init(void *handle) |
aaa36a97 | 910 | { |
5fc3aeeb | 911 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
912 | ||
c113ea1c AD |
913 | adev->sdma.num_instances = SDMA_MAX_INSTANCE; |
914 | ||
aaa36a97 AD |
915 | sdma_v2_4_set_ring_funcs(adev); |
916 | sdma_v2_4_set_buffer_funcs(adev); | |
917 | sdma_v2_4_set_vm_pte_funcs(adev); | |
918 | sdma_v2_4_set_irq_funcs(adev); | |
919 | ||
920 | return 0; | |
921 | } | |
922 | ||
5fc3aeeb | 923 | static int sdma_v2_4_sw_init(void *handle) |
aaa36a97 AD |
924 | { |
925 | struct amdgpu_ring *ring; | |
c113ea1c | 926 | int r, i; |
5fc3aeeb | 927 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
928 | |
929 | /* SDMA trap event */ | |
c113ea1c | 930 | r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); |
aaa36a97 AD |
931 | if (r) |
932 | return r; | |
933 | ||
934 | /* SDMA Privileged inst */ | |
c113ea1c | 935 | r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); |
aaa36a97 AD |
936 | if (r) |
937 | return r; | |
938 | ||
939 | /* SDMA Privileged inst */ | |
c113ea1c | 940 | r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); |
aaa36a97 AD |
941 | if (r) |
942 | return r; | |
943 | ||
944 | r = sdma_v2_4_init_microcode(adev); | |
945 | if (r) { | |
946 | DRM_ERROR("Failed to load sdma firmware!\n"); | |
947 | return r; | |
948 | } | |
949 | ||
c113ea1c AD |
950 | for (i = 0; i < adev->sdma.num_instances; i++) { |
951 | ring = &adev->sdma.instance[i].ring; | |
952 | ring->ring_obj = NULL; | |
953 | ring->use_doorbell = false; | |
954 | sprintf(ring->name, "sdma%d", i); | |
b38d99c4 | 955 | r = amdgpu_ring_init(adev, ring, 1024, |
c113ea1c AD |
956 | SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, |
957 | &adev->sdma.trap_irq, | |
958 | (i == 0) ? | |
959 | AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, | |
960 | AMDGPU_RING_TYPE_SDMA); | |
961 | if (r) | |
962 | return r; | |
963 | } | |
aaa36a97 AD |
964 | |
965 | return r; | |
966 | } | |
967 | ||
5fc3aeeb | 968 | static int sdma_v2_4_sw_fini(void *handle) |
aaa36a97 | 969 | { |
5fc3aeeb | 970 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
c113ea1c | 971 | int i; |
5fc3aeeb | 972 | |
c113ea1c AD |
973 | for (i = 0; i < adev->sdma.num_instances; i++) |
974 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | |
aaa36a97 | 975 | |
9c55c520 | 976 | sdma_v2_4_free_microcode(adev); |
aaa36a97 AD |
977 | return 0; |
978 | } | |
979 | ||
5fc3aeeb | 980 | static int sdma_v2_4_hw_init(void *handle) |
aaa36a97 AD |
981 | { |
982 | int r; | |
5fc3aeeb | 983 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
984 | |
985 | sdma_v2_4_init_golden_registers(adev); | |
986 | ||
987 | r = sdma_v2_4_start(adev); | |
988 | if (r) | |
989 | return r; | |
990 | ||
991 | return r; | |
992 | } | |
993 | ||
5fc3aeeb | 994 | static int sdma_v2_4_hw_fini(void *handle) |
aaa36a97 | 995 | { |
5fc3aeeb | 996 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
997 | ||
aaa36a97 AD |
998 | sdma_v2_4_enable(adev, false); |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
5fc3aeeb | 1003 | static int sdma_v2_4_suspend(void *handle) |
aaa36a97 | 1004 | { |
5fc3aeeb | 1005 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1006 | |
1007 | return sdma_v2_4_hw_fini(adev); | |
1008 | } | |
1009 | ||
5fc3aeeb | 1010 | static int sdma_v2_4_resume(void *handle) |
aaa36a97 | 1011 | { |
5fc3aeeb | 1012 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1013 | |
1014 | return sdma_v2_4_hw_init(adev); | |
1015 | } | |
1016 | ||
5fc3aeeb | 1017 | static bool sdma_v2_4_is_idle(void *handle) |
aaa36a97 | 1018 | { |
5fc3aeeb | 1019 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1020 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1021 | ||
1022 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1023 | SRBM_STATUS2__SDMA1_BUSY_MASK)) | |
1024 | return false; | |
1025 | ||
1026 | return true; | |
1027 | } | |
1028 | ||
5fc3aeeb | 1029 | static int sdma_v2_4_wait_for_idle(void *handle) |
aaa36a97 AD |
1030 | { |
1031 | unsigned i; | |
1032 | u32 tmp; | |
5fc3aeeb | 1033 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1034 | |
1035 | for (i = 0; i < adev->usec_timeout; i++) { | |
1036 | tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | | |
1037 | SRBM_STATUS2__SDMA1_BUSY_MASK); | |
1038 | ||
1039 | if (!tmp) | |
1040 | return 0; | |
1041 | udelay(1); | |
1042 | } | |
1043 | return -ETIMEDOUT; | |
1044 | } | |
1045 | ||
5fc3aeeb | 1046 | static int sdma_v2_4_soft_reset(void *handle) |
aaa36a97 AD |
1047 | { |
1048 | u32 srbm_soft_reset = 0; | |
5fc3aeeb | 1049 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
aaa36a97 AD |
1050 | u32 tmp = RREG32(mmSRBM_STATUS2); |
1051 | ||
1052 | if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { | |
1053 | /* sdma0 */ | |
1054 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); | |
1055 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); | |
1056 | WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); | |
1057 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; | |
1058 | } | |
1059 | if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { | |
1060 | /* sdma1 */ | |
1061 | tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); | |
1062 | tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); | |
1063 | WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); | |
1064 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; | |
1065 | } | |
1066 | ||
1067 | if (srbm_soft_reset) { | |
aaa36a97 AD |
1068 | tmp = RREG32(mmSRBM_SOFT_RESET); |
1069 | tmp |= srbm_soft_reset; | |
1070 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1071 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1072 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1073 | ||
1074 | udelay(50); | |
1075 | ||
1076 | tmp &= ~srbm_soft_reset; | |
1077 | WREG32(mmSRBM_SOFT_RESET, tmp); | |
1078 | tmp = RREG32(mmSRBM_SOFT_RESET); | |
1079 | ||
1080 | /* Wait a little for things to settle down */ | |
1081 | udelay(50); | |
aaa36a97 AD |
1082 | } |
1083 | ||
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, | |
1088 | struct amdgpu_irq_src *src, | |
1089 | unsigned type, | |
1090 | enum amdgpu_interrupt_state state) | |
1091 | { | |
1092 | u32 sdma_cntl; | |
1093 | ||
1094 | switch (type) { | |
1095 | case AMDGPU_SDMA_IRQ_TRAP0: | |
1096 | switch (state) { | |
1097 | case AMDGPU_IRQ_STATE_DISABLE: | |
1098 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1099 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1100 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1101 | break; | |
1102 | case AMDGPU_IRQ_STATE_ENABLE: | |
1103 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); | |
1104 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1105 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); | |
1106 | break; | |
1107 | default: | |
1108 | break; | |
1109 | } | |
1110 | break; | |
1111 | case AMDGPU_SDMA_IRQ_TRAP1: | |
1112 | switch (state) { | |
1113 | case AMDGPU_IRQ_STATE_DISABLE: | |
1114 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1115 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); | |
1116 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1117 | break; | |
1118 | case AMDGPU_IRQ_STATE_ENABLE: | |
1119 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); | |
1120 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); | |
1121 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); | |
1122 | break; | |
1123 | default: | |
1124 | break; | |
1125 | } | |
1126 | break; | |
1127 | default: | |
1128 | break; | |
1129 | } | |
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, | |
1134 | struct amdgpu_irq_src *source, | |
1135 | struct amdgpu_iv_entry *entry) | |
1136 | { | |
1137 | u8 instance_id, queue_id; | |
1138 | ||
1139 | instance_id = (entry->ring_id & 0x3) >> 0; | |
1140 | queue_id = (entry->ring_id & 0xc) >> 2; | |
1141 | DRM_DEBUG("IH: SDMA trap\n"); | |
1142 | switch (instance_id) { | |
1143 | case 0: | |
1144 | switch (queue_id) { | |
1145 | case 0: | |
c113ea1c | 1146 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
aaa36a97 AD |
1147 | break; |
1148 | case 1: | |
1149 | /* XXX compute */ | |
1150 | break; | |
1151 | case 2: | |
1152 | /* XXX compute */ | |
1153 | break; | |
1154 | } | |
1155 | break; | |
1156 | case 1: | |
1157 | switch (queue_id) { | |
1158 | case 0: | |
c113ea1c | 1159 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
aaa36a97 AD |
1160 | break; |
1161 | case 1: | |
1162 | /* XXX compute */ | |
1163 | break; | |
1164 | case 2: | |
1165 | /* XXX compute */ | |
1166 | break; | |
1167 | } | |
1168 | break; | |
1169 | } | |
1170 | return 0; | |
1171 | } | |
1172 | ||
1173 | static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, | |
1174 | struct amdgpu_irq_src *source, | |
1175 | struct amdgpu_iv_entry *entry) | |
1176 | { | |
1177 | DRM_ERROR("Illegal instruction in SDMA command stream\n"); | |
1178 | schedule_work(&adev->reset_work); | |
1179 | return 0; | |
1180 | } | |
1181 | ||
5fc3aeeb | 1182 | static int sdma_v2_4_set_clockgating_state(void *handle, |
1183 | enum amd_clockgating_state state) | |
aaa36a97 AD |
1184 | { |
1185 | /* XXX handled via the smc on VI */ | |
aaa36a97 AD |
1186 | return 0; |
1187 | } | |
1188 | ||
5fc3aeeb | 1189 | static int sdma_v2_4_set_powergating_state(void *handle, |
1190 | enum amd_powergating_state state) | |
aaa36a97 AD |
1191 | { |
1192 | return 0; | |
1193 | } | |
1194 | ||
5fc3aeeb | 1195 | const struct amd_ip_funcs sdma_v2_4_ip_funcs = { |
88a907d6 | 1196 | .name = "sdma_v2_4", |
aaa36a97 AD |
1197 | .early_init = sdma_v2_4_early_init, |
1198 | .late_init = NULL, | |
1199 | .sw_init = sdma_v2_4_sw_init, | |
1200 | .sw_fini = sdma_v2_4_sw_fini, | |
1201 | .hw_init = sdma_v2_4_hw_init, | |
1202 | .hw_fini = sdma_v2_4_hw_fini, | |
1203 | .suspend = sdma_v2_4_suspend, | |
1204 | .resume = sdma_v2_4_resume, | |
1205 | .is_idle = sdma_v2_4_is_idle, | |
1206 | .wait_for_idle = sdma_v2_4_wait_for_idle, | |
1207 | .soft_reset = sdma_v2_4_soft_reset, | |
aaa36a97 AD |
1208 | .set_clockgating_state = sdma_v2_4_set_clockgating_state, |
1209 | .set_powergating_state = sdma_v2_4_set_powergating_state, | |
1210 | }; | |
1211 | ||
aaa36a97 AD |
1212 | static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { |
1213 | .get_rptr = sdma_v2_4_ring_get_rptr, | |
1214 | .get_wptr = sdma_v2_4_ring_get_wptr, | |
1215 | .set_wptr = sdma_v2_4_ring_set_wptr, | |
1216 | .parse_cs = NULL, | |
1217 | .emit_ib = sdma_v2_4_ring_emit_ib, | |
1218 | .emit_fence = sdma_v2_4_ring_emit_fence, | |
00b7c4ff | 1219 | .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, |
aaa36a97 | 1220 | .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, |
d2edb07b | 1221 | .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, |
6ad550c3 | 1222 | .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate, |
aaa36a97 AD |
1223 | .test_ring = sdma_v2_4_ring_test_ring, |
1224 | .test_ib = sdma_v2_4_ring_test_ib, | |
ac01db3d | 1225 | .insert_nop = sdma_v2_4_ring_insert_nop, |
9e5d5309 | 1226 | .pad_ib = sdma_v2_4_ring_pad_ib, |
aaa36a97 AD |
1227 | }; |
1228 | ||
1229 | static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) | |
1230 | { | |
c113ea1c AD |
1231 | int i; |
1232 | ||
1233 | for (i = 0; i < adev->sdma.num_instances; i++) | |
1234 | adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; | |
aaa36a97 AD |
1235 | } |
1236 | ||
1237 | static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { | |
1238 | .set = sdma_v2_4_set_trap_irq_state, | |
1239 | .process = sdma_v2_4_process_trap_irq, | |
1240 | }; | |
1241 | ||
1242 | static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { | |
1243 | .process = sdma_v2_4_process_illegal_inst_irq, | |
1244 | }; | |
1245 | ||
1246 | static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) | |
1247 | { | |
c113ea1c AD |
1248 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; |
1249 | adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; | |
1250 | adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; | |
aaa36a97 AD |
1251 | } |
1252 | ||
1253 | /** | |
1254 | * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine | |
1255 | * | |
1256 | * @ring: amdgpu_ring structure holding ring information | |
1257 | * @src_offset: src GPU address | |
1258 | * @dst_offset: dst GPU address | |
1259 | * @byte_count: number of bytes to xfer | |
1260 | * | |
1261 | * Copy GPU buffers using the DMA engine (VI). | |
1262 | * Used by the amdgpu ttm implementation to move pages if | |
1263 | * registered as the asic copy callback. | |
1264 | */ | |
c7ae72c0 | 1265 | static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1266 | uint64_t src_offset, |
1267 | uint64_t dst_offset, | |
1268 | uint32_t byte_count) | |
1269 | { | |
c7ae72c0 CZ |
1270 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | |
1271 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); | |
1272 | ib->ptr[ib->length_dw++] = byte_count; | |
1273 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | |
1274 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); | |
1275 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); | |
1276 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1277 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
aaa36a97 AD |
1278 | } |
1279 | ||
1280 | /** | |
1281 | * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine | |
1282 | * | |
1283 | * @ring: amdgpu_ring structure holding ring information | |
1284 | * @src_data: value to write to buffer | |
1285 | * @dst_offset: dst GPU address | |
1286 | * @byte_count: number of bytes to xfer | |
1287 | * | |
1288 | * Fill GPU buffers using the DMA engine (VI). | |
1289 | */ | |
6e7a3840 | 1290 | static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, |
aaa36a97 AD |
1291 | uint32_t src_data, |
1292 | uint64_t dst_offset, | |
1293 | uint32_t byte_count) | |
1294 | { | |
6e7a3840 CZ |
1295 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); |
1296 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); | |
1297 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); | |
1298 | ib->ptr[ib->length_dw++] = src_data; | |
1299 | ib->ptr[ib->length_dw++] = byte_count; | |
aaa36a97 AD |
1300 | } |
1301 | ||
1302 | static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { | |
1303 | .copy_max_bytes = 0x1fffff, | |
1304 | .copy_num_dw = 7, | |
1305 | .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, | |
1306 | ||
1307 | .fill_max_bytes = 0x1fffff, | |
1308 | .fill_num_dw = 7, | |
1309 | .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, | |
1310 | }; | |
1311 | ||
1312 | static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) | |
1313 | { | |
1314 | if (adev->mman.buffer_funcs == NULL) { | |
1315 | adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; | |
c113ea1c | 1316 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
aaa36a97 AD |
1317 | } |
1318 | } | |
1319 | ||
1320 | static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { | |
1321 | .copy_pte = sdma_v2_4_vm_copy_pte, | |
1322 | .write_pte = sdma_v2_4_vm_write_pte, | |
1323 | .set_pte_pde = sdma_v2_4_vm_set_pte_pde, | |
aaa36a97 AD |
1324 | }; |
1325 | ||
1326 | static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) | |
1327 | { | |
2d55e45a CK |
1328 | unsigned i; |
1329 | ||
aaa36a97 AD |
1330 | if (adev->vm_manager.vm_pte_funcs == NULL) { |
1331 | adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; | |
2d55e45a CK |
1332 | for (i = 0; i < adev->sdma.num_instances; i++) |
1333 | adev->vm_manager.vm_pte_rings[i] = | |
1334 | &adev->sdma.instance[i].ring; | |
1335 | ||
1336 | adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; | |
aaa36a97 AD |
1337 | } |
1338 | } |