[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / vce_v2_0.c

/*
 * Copyright 2013 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * Authors: Christian König <christian.koenig@amd.com>
 */

#include <linux/firmware.h>
#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_vce.h"
#include "cikd.h"

#include "vce/vce_2_0_d.h"
#include "vce/vce_2_0_sh_mask.h"

#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"

#define VCE_V2_0_FW_SIZE	(256 * 1024)
#define VCE_V2_0_STACK_SIZE	(64 * 1024)
#define VCE_V2_0_DATA_SIZE	(23552 * AMDGPU_MAX_VCE_HANDLES)
#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK	0x02

static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
static int vce_v2_0_wait_for_idle(void *handle);
/**
 * vce_v2_0_ring_get_rptr - get read pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware read pointer
 */
static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		return RREG32(mmVCE_RB_RPTR);
	else
		return RREG32(mmVCE_RB_RPTR2);
}

/**
 * vce_v2_0_ring_get_wptr - get write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Returns the current hardware write pointer
 */
static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		return RREG32(mmVCE_RB_WPTR);
	else
		return RREG32(mmVCE_RB_WPTR2);
}

/**
 * vce_v2_0_ring_set_wptr - set write pointer
 *
 * @ring: amdgpu_ring pointer
 *
 * Commits the write pointer to the hardware
 */
static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
{
	struct amdgpu_device *adev = ring->adev;

	if (ring == &adev->vce.ring[0])
		WREG32(mmVCE_RB_WPTR, ring->wptr);
	else
		WREG32(mmVCE_RB_WPTR2, ring->wptr);
}

static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
{
	int i, j;

	for (i = 0; i < 10; ++i) {
		for (j = 0; j < 100; ++j) {
			uint32_t status = RREG32(mmVCE_LMI_STATUS);

			if (status & 0x337f)
				return 0;
			mdelay(10);
		}
	}

	return -ETIMEDOUT;
}

static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
{
	int i, j;

	for (i = 0; i < 10; ++i) {
		for (j = 0; j < 100; ++j) {
			uint32_t status = RREG32(mmVCE_STATUS);

			if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
				return 0;
			mdelay(10);
		}

		DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
		WREG32_P(mmVCE_SOFT_RESET,
			VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
			~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(10);
		WREG32_P(mmVCE_SOFT_RESET, 0,
			~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
		mdelay(10);
	}

	return -ETIMEDOUT;
}

/**
 * vce_v2_0_start - start VCE block
 *
 * @adev: amdgpu_device pointer
 *
 * Setup and start the VCE block
 */
static int vce_v2_0_start(struct amdgpu_device *adev)
{
	struct amdgpu_ring *ring;
	int r;

	vce_v2_0_mc_resume(adev);

	/* set BUSY flag */
	WREG32_P(mmVCE_STATUS, 1, ~1);

	ring = &adev->vce.ring[0];
	WREG32(mmVCE_RB_RPTR, ring->wptr);
	WREG32(mmVCE_RB_WPTR, ring->wptr);
	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);

	ring = &adev->vce.ring[1];
	WREG32(mmVCE_RB_RPTR2, ring->wptr);
	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);

	WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
	mdelay(100);
	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);

	r = vce_v2_0_firmware_loaded(adev);

	/* clear BUSY flag */
	WREG32_P(mmVCE_STATUS, 0, ~1);

	if (r) {
		DRM_ERROR("VCE not responding, giving up!!!\n");
		return r;
	}

	return 0;
}

static int vce_v2_0_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	vce_v2_0_set_ring_funcs(adev);
	vce_v2_0_set_irq_funcs(adev);

	return 0;
}

static int vce_v2_0_sw_init(void *handle)
{
	struct amdgpu_ring *ring;
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	/* VCE */
	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
	if (r)
		return r;

	r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
		VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
	if (r)
		return r;

	r = amdgpu_vce_resume(adev);
	if (r)
		return r;

	ring = &adev->vce.ring[0];
	sprintf(ring->name, "vce0");
	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	if (r)
		return r;

	ring = &adev->vce.ring[1];
	sprintf(ring->name, "vce1");
	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_sw_fini(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_vce_suspend(adev);
	if (r)
		return r;

	r = amdgpu_vce_sw_fini(adev);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_hw_init(void *handle)
{
	struct amdgpu_ring *ring;
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = vce_v2_0_start(adev);
	if (r)
/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
		return 0;

	ring = &adev->vce.ring[0];
	ring->ready = true;
	r = amdgpu_ring_test_ring(ring);
	if (r) {
		ring->ready = false;
		return r;
	}

	ring = &adev->vce.ring[1];
	ring->ready = true;
	r = amdgpu_ring_test_ring(ring);
	if (r) {
		ring->ready = false;
		return r;
	}

	DRM_INFO("VCE initialized successfully.\n");

	return 0;
}

static int vce_v2_0_hw_fini(void *handle)
{
	return 0;
}

static int vce_v2_0_suspend(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = vce_v2_0_hw_fini(adev);
	if (r)
		return r;

	r = amdgpu_vce_suspend(adev);
	if (r)
		return r;

	return r;
}

static int vce_v2_0_resume(void *handle)
{
	int r;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	r = amdgpu_vce_resume(adev);
	if (r)
		return r;

	r = vce_v2_0_hw_init(adev);
	if (r)
		return r;

	return r;
}

static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
{
	u32 tmp;

	if (gated) {
		tmp = RREG32(mmVCE_CLOCK_GATING_B);
		tmp |= 0xe70000;
		WREG32(mmVCE_CLOCK_GATING_B, tmp);

		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
		tmp |= 0xff000000;
		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
		tmp &= ~0x3fc;
		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	} else {
		tmp = RREG32(mmVCE_CLOCK_GATING_B);
		tmp |= 0xe7;
		tmp &= ~0xe70000;
		WREG32(mmVCE_CLOCK_GATING_B, tmp);

		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
		tmp |= 0x1fe000;
		tmp &= ~0xff000000;
		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
		tmp |= 0x3fc;
		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	}
}

static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
{
	if (vce_v2_0_wait_for_idle(adev)) {
		DRM_INFO("VCE is busy, Can't set clock gateing");
		return;
	}

	WREG32_P(mmVCE_LMI_CTRL2, 0x100, ~0x100);

	if (vce_v2_0_lmi_clean(adev)) {
		DRM_INFO("LMI is busy, Can't set clock gateing");
		return;
	}

	WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	WREG32_P(mmVCE_SOFT_RESET,
		 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
		 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	WREG32(mmVCE_STATUS, 0);

	if (gated)
		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	/* LMI_MC/LMI_UMC always set in dynamic, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0} */
	if (gated) {
		/* Force CLOCK OFF , set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {*, 1} */
		WREG32(mmVCE_CLOCK_GATING_B, 0xe90010);
	} else {
		/* Force CLOCK ON, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {1, 0} */
		WREG32(mmVCE_CLOCK_GATING_B, 0x800f1);
	}

	/* Set VCE_UENC_CLOCK_GATING always in dynamic mode {*_FORCE_ON, *_FORCE_OFF} = {0, 0}*/;
	WREG32(mmVCE_UENC_CLOCK_GATING, 0x40);

	/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
	WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);

	WREG32_P(mmVCE_LMI_CTRL2, 0, ~0x100);
	if(!gated) {
		WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
		mdelay(100);
		WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);

		vce_v2_0_firmware_loaded(adev);
		WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
	}
}

static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
{
	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
}

static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
{
	bool sw_cg = false;

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
		if (sw_cg)
			vce_v2_0_set_sw_cg(adev, true);
		else
			vce_v2_0_set_dyn_cg(adev, true);
	} else {
		vce_v2_0_disable_cg(adev);

		if (sw_cg)
			vce_v2_0_set_sw_cg(adev, false);
		else
			vce_v2_0_set_dyn_cg(adev, false);
	}
}

static void vce_v2_0_init_cg(struct amdgpu_device *adev)
{
	u32 tmp;

	tmp = RREG32(mmVCE_CLOCK_GATING_A);
	tmp &= ~0xfff;
	tmp |= ((0 << 0) | (4 << 4));
	tmp |= 0x40000;
	WREG32(mmVCE_CLOCK_GATING_A, tmp);

	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	tmp &= ~0xfff;
	tmp |= ((0 << 0) | (4 << 4));
	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	tmp |= 0x10;
	tmp &= ~0x100000;
	WREG32(mmVCE_CLOCK_GATING_B, tmp);
}

static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
{
	uint64_t addr = adev->vce.gpu_addr;
	uint32_t size;

	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);

	WREG32(mmVCE_LMI_CTRL, 0x00398000);
	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
	WREG32(mmVCE_LMI_VM_CTRL, 0);

	addr += AMDGPU_VCE_FIRMWARE_OFFSET;
	size = VCE_V2_0_FW_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);

	addr += size;
	size = VCE_V2_0_STACK_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);

	addr += size;
	size = VCE_V2_0_DATA_SIZE;
	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);

	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
	WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);

	vce_v2_0_init_cg(adev);
}

static bool vce_v2_0_is_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
}

static int vce_v2_0_wait_for_idle(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	unsigned i;

	for (i = 0; i < adev->usec_timeout; i++) {
		if (vce_v2_0_is_idle(handle))
			return 0;
	}
	return -ETIMEDOUT;
}

static int vce_v2_0_soft_reset(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
	mdelay(5);

	return vce_v2_0_start(adev);
}

static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
					struct amdgpu_irq_src *source,
					unsigned type,
					enum amdgpu_interrupt_state state)
{
	uint32_t val = 0;

	if (state == AMDGPU_IRQ_STATE_ENABLE)
		val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;

	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
	return 0;
}

static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{
	DRM_DEBUG("IH: VCE\n");
	switch (entry->src_data) {
	case 0:
	case 1:
		amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
		break;
	default:
		DRM_ERROR("Unhandled interrupt: %d %d\n",
			  entry->src_id, entry->src_data);
		break;
	}

	return 0;
}

static int vce_v2_0_set_clockgating_state(void *handle,
					  enum amd_clockgating_state state)
{
	bool gate = false;
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (state == AMD_CG_STATE_GATE)
		gate = true;

	vce_v2_0_enable_mgcg(adev, gate);

	return 0;
}

static int vce_v2_0_set_powergating_state(void *handle,
					  enum amd_powergating_state state)
{
	/* This doesn't actually powergate the VCE block.
	 * That's done in the dpm code via the SMC.  This
	 * just re-inits the block as necessary.  The actual
	 * gating still happens in the dpm code.  We should
	 * revisit this when there is a cleaner line between
	 * the smc and the hw blocks
	 */
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
		return 0;

	if (state == AMD_PG_STATE_GATE)
		/* XXX do we need a vce_v2_0_stop()? */
		return 0;
	else
		return vce_v2_0_start(adev);
}

const struct amd_ip_funcs vce_v2_0_ip_funcs = {
	.name = "vce_v2_0",
	.early_init = vce_v2_0_early_init,
	.late_init = NULL,
	.sw_init = vce_v2_0_sw_init,
	.sw_fini = vce_v2_0_sw_fini,
	.hw_init = vce_v2_0_hw_init,
	.hw_fini = vce_v2_0_hw_fini,
	.suspend = vce_v2_0_suspend,
	.resume = vce_v2_0_resume,
	.is_idle = vce_v2_0_is_idle,
	.wait_for_idle = vce_v2_0_wait_for_idle,
	.soft_reset = vce_v2_0_soft_reset,
	.set_clockgating_state = vce_v2_0_set_clockgating_state,
	.set_powergating_state = vce_v2_0_set_powergating_state,
};

static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
	.get_rptr = vce_v2_0_ring_get_rptr,
	.get_wptr = vce_v2_0_ring_get_wptr,
	.set_wptr = vce_v2_0_ring_set_wptr,
	.parse_cs = amdgpu_vce_ring_parse_cs,
	.emit_ib = amdgpu_vce_ring_emit_ib,
	.emit_fence = amdgpu_vce_ring_emit_fence,
	.test_ring = amdgpu_vce_ring_test_ring,
	.test_ib = amdgpu_vce_ring_test_ib,
	.insert_nop = amdgpu_ring_insert_nop,
	.pad_ib = amdgpu_ring_generic_pad_ib,
	.begin_use = amdgpu_vce_ring_begin_use,
	.end_use = amdgpu_vce_ring_end_use,
};

static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
{
	adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
	adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
}

static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
	.set = vce_v2_0_set_interrupt_state,
	.process = vce_v2_0_process_interrupt,
};

static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
{
	adev->vce.irq.num_types = 1;
	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
};
Commit	Line	Data
a2e73f56 AD	1	/*
	2	* Copyright 2013 Advanced Micro Devices, Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	* Authors: Christian König <christian.koenig@amd.com>
	26	*/
	27
	28	#include <linux/firmware.h>
	29	#include <drm/drmP.h>
	30	#include "amdgpu.h"
	31	#include "amdgpu_vce.h"
	32	#include "cikd.h"
	33
	34	#include "vce/vce_2_0_d.h"
	35	#include "vce/vce_2_0_sh_mask.h"
	36
	37	#include "oss/oss_2_0_d.h"
	38	#include "oss/oss_2_0_sh_mask.h"
	39
e9822622 LL	40	#define VCE_V2_0_FW_SIZE (256 * 1024)
	41	#define VCE_V2_0_STACK_SIZE (64 * 1024)
	42	#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
abc8c1ce	43	#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
e9822622	44
a2e73f56 AD	45	static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
	46	static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
	47	static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
cb48a13e	48	static int vce_v2_0_wait_for_idle(void *handle);
a2e73f56 AD	49	/**
	50	* vce_v2_0_ring_get_rptr - get read pointer
	51	*
	52	* @ring: amdgpu_ring pointer
	53	*
	54	* Returns the current hardware read pointer
	55	*/
	56	static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
	57	{
	58	struct amdgpu_device *adev = ring->adev;
	59
	60	if (ring == &adev->vce.ring[0])
	61	return RREG32(mmVCE_RB_RPTR);
	62	else
	63	return RREG32(mmVCE_RB_RPTR2);
	64	}
	65
	66	/**
	67	* vce_v2_0_ring_get_wptr - get write pointer
	68	*
	69	* @ring: amdgpu_ring pointer
	70	*
	71	* Returns the current hardware write pointer
	72	*/
	73	static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
	74	{
	75	struct amdgpu_device *adev = ring->adev;
	76
	77	if (ring == &adev->vce.ring[0])
	78	return RREG32(mmVCE_RB_WPTR);
	79	else
	80	return RREG32(mmVCE_RB_WPTR2);
	81	}
	82
	83	/**
	84	* vce_v2_0_ring_set_wptr - set write pointer
	85	*
	86	* @ring: amdgpu_ring pointer
	87	*
	88	* Commits the write pointer to the hardware
	89	*/
	90	static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
	91	{
	92	struct amdgpu_device *adev = ring->adev;
	93
	94	if (ring == &adev->vce.ring[0])
	95	WREG32(mmVCE_RB_WPTR, ring->wptr);
	96	else
	97	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	98	}
	99
abc8c1ce	100	static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
	101	{
	102	int i, j;
	103
	104	for (i = 0; i < 10; ++i) {
	105	for (j = 0; j < 100; ++j) {
	106	uint32_t status = RREG32(mmVCE_LMI_STATUS);
	107
	108	if (status & 0x337f)
	109	return 0;
	110	mdelay(10);
	111	}
	112	}
	113
	114	return -ETIMEDOUT;
	115	}
	116
	117	static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
	118	{
	119	int i, j;
	120
	121	for (i = 0; i < 10; ++i) {
	122	for (j = 0; j < 100; ++j) {
	123	uint32_t status = RREG32(mmVCE_STATUS);
	124
	125	if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
	126	return 0;
	127	mdelay(10);
	128	}
	129
	130	DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
	131	WREG32_P(mmVCE_SOFT_RESET,
	132	VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
	133	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	134	mdelay(10);
	135	WREG32_P(mmVCE_SOFT_RESET, 0,
	136	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	137	mdelay(10);
	138	}
	139
	140	return -ETIMEDOUT;
	141	}
	142
a2e73f56 AD	143	/**
	144	* vce_v2_0_start - start VCE block
	145	*
	146	* @adev: amdgpu_device pointer
	147	*
	148	* Setup and start the VCE block
	149	*/
	150	static int vce_v2_0_start(struct amdgpu_device *adev)
	151	{
	152	struct amdgpu_ring *ring;
abc8c1ce	153	int r;
a2e73f56 AD	154
	155	vce_v2_0_mc_resume(adev);
	156
	157	/* set BUSY flag */
	158	WREG32_P(mmVCE_STATUS, 1, ~1);
	159
	160	ring = &adev->vce.ring[0];
	161	WREG32(mmVCE_RB_RPTR, ring->wptr);
	162	WREG32(mmVCE_RB_WPTR, ring->wptr);
	163	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
	164	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
	165	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
	166
	167	ring = &adev->vce.ring[1];
	168	WREG32(mmVCE_RB_RPTR2, ring->wptr);
	169	WREG32(mmVCE_RB_WPTR2, ring->wptr);
	170	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
	171	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
	172	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
	173
21d3cbbe TSD	174	WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
21d3cbbe TSD	175	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
a2e73f56	176	mdelay(100);
21d3cbbe	177	WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
a2e73f56	178
abc8c1ce	179	r = vce_v2_0_firmware_loaded(adev);
a2e73f56 AD	180
	181	/* clear BUSY flag */
	182	WREG32_P(mmVCE_STATUS, 0, ~1);
	183
	184	if (r) {
	185	DRM_ERROR("VCE not responding, giving up!!!\n");
	186	return r;
	187	}
	188
	189	return 0;
	190	}
	191
5fc3aeeb	192	static int vce_v2_0_early_init(void *handle)
a2e73f56	193	{
5fc3aeeb	194	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	195
a2e73f56 AD	196	vce_v2_0_set_ring_funcs(adev);
	197	vce_v2_0_set_irq_funcs(adev);
	198
	199	return 0;
	200	}
	201
5fc3aeeb	202	static int vce_v2_0_sw_init(void *handle)
a2e73f56 AD	203	{
	204	struct amdgpu_ring *ring;
	205	int r;
5fc3aeeb	206	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	207
	208	/* VCE */
	209	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
	210	if (r)
	211	return r;
	212
e9822622 LL	213	r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
e9822622 LL	214	VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
a2e73f56 AD	215	if (r)
	216	return r;
	217
	218	r = amdgpu_vce_resume(adev);
	219	if (r)
	220	return r;
	221
	222	ring = &adev->vce.ring[0];
	223	sprintf(ring->name, "vce0");
a3f1cf35	224	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
a2e73f56 AD	225	&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	226	if (r)
	227	return r;
	228
	229	ring = &adev->vce.ring[1];
	230	sprintf(ring->name, "vce1");
a3f1cf35	231	r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf,
a2e73f56 AD	232	&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
	233	if (r)
	234	return r;
	235
	236	return r;
	237	}
	238
5fc3aeeb	239	static int vce_v2_0_sw_fini(void *handle)
a2e73f56 AD	240	{
a2e73f56 AD	241	int r;
5fc3aeeb	242	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	243
	244	r = amdgpu_vce_suspend(adev);
	245	if (r)
	246	return r;
	247
	248	r = amdgpu_vce_sw_fini(adev);
	249	if (r)
	250	return r;
	251
	252	return r;
	253	}
	254
5fc3aeeb	255	static int vce_v2_0_hw_init(void *handle)
a2e73f56 AD	256	{
	257	struct amdgpu_ring *ring;
	258	int r;
5fc3aeeb	259	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	260
	261	r = vce_v2_0_start(adev);
	262	if (r)
976accc1 RZ	263	/* this error mean vcpu not in running state, so just skip ring test, not stop driver initialize */
976accc1 RZ	264	return 0;
a2e73f56 AD	265
	266	ring = &adev->vce.ring[0];
	267	ring->ready = true;
	268	r = amdgpu_ring_test_ring(ring);
	269	if (r) {
	270	ring->ready = false;
	271	return r;
	272	}
	273
	274	ring = &adev->vce.ring[1];
	275	ring->ready = true;
	276	r = amdgpu_ring_test_ring(ring);
	277	if (r) {
	278	ring->ready = false;
	279	return r;
	280	}
	281
	282	DRM_INFO("VCE initialized successfully.\n");
	283
	284	return 0;
	285	}
	286
5fc3aeeb	287	static int vce_v2_0_hw_fini(void *handle)
a2e73f56	288	{
a2e73f56 AD	289	return 0;
	290	}
	291
5fc3aeeb	292	static int vce_v2_0_suspend(void *handle)
a2e73f56 AD	293	{
a2e73f56 AD	294	int r;
5fc3aeeb	295	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	296
	297	r = vce_v2_0_hw_fini(adev);
	298	if (r)
	299	return r;
	300
	301	r = amdgpu_vce_suspend(adev);
	302	if (r)
	303	return r;
	304
	305	return r;
	306	}
	307
5fc3aeeb	308	static int vce_v2_0_resume(void *handle)
a2e73f56 AD	309	{
a2e73f56 AD	310	int r;
5fc3aeeb	311	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56 AD	312
	313	r = amdgpu_vce_resume(adev);
	314	if (r)
	315	return r;
	316
	317	r = vce_v2_0_hw_init(adev);
	318	if (r)
	319	return r;
	320
	321	return r;
	322	}
	323
	324	static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
	325	{
	326	u32 tmp;
	327
	328	if (gated) {
	329	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	330	tmp \|= 0xe70000;
	331	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	332
	333	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	334	tmp \|= 0xff000000;
	335	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	336
	337	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	338	tmp &= ~0x3fc;
	339	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	340
	341	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
70f0f5fb	342	} else {
a2e73f56 AD	343	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	344	tmp \|= 0xe7;
	345	tmp &= ~0xe70000;
	346	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	347
	348	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	349	tmp \|= 0x1fe000;
	350	tmp &= ~0xff000000;
	351	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	352
	353	tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
	354	tmp \|= 0x3fc;
	355	WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
	356	}
	357	}
	358
	359	static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
	360	{
abc8c1ce	361	if (vce_v2_0_wait_for_idle(adev)) {
	362	DRM_INFO("VCE is busy, Can't set clock gateing");
	363	return;
	364	}
a2e73f56	365
abc8c1ce	366	WREG32_P(mmVCE_LMI_CTRL2, 0x100, ~0x100);
	367
	368	if (vce_v2_0_lmi_clean(adev)) {
	369	DRM_INFO("LMI is busy, Can't set clock gateing");
	370	return;
cb48a13e RZ	371	}
cb48a13e RZ	372
abc8c1ce	373	WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	374	WREG32_P(mmVCE_SOFT_RESET,
	375	VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
	376	~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	377	WREG32(mmVCE_STATUS, 0);
	378
	379	if (gated)
	380	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
	381	/* LMI_MC/LMI_UMC always set in dynamic, set {CGC__GATE_MODE, CGC__SW_GATE} = {0, 0} */
a2e73f56	382	if (gated) {
abc8c1ce	383	/* Force CLOCK OFF , set {CGC__GATE_MODE, CGC__SW_GATE} = {, 1} /
abc8c1ce	384	WREG32(mmVCE_CLOCK_GATING_B, 0xe90010);
a2e73f56	385	} else {
abc8c1ce	386	/* Force CLOCK ON, set {CGC__GATE_MODE, CGC__SW_GATE} = {1, 0} */
abc8c1ce	387	WREG32(mmVCE_CLOCK_GATING_B, 0x800f1);
a2e73f56	388	}
a2e73f56	389
abc8c1ce	390	/* Set VCE_UENC_CLOCK_GATING always in dynamic mode {_FORCE_ON, _FORCE_OFF} = {0, 0}*/;
abc8c1ce	391	WREG32(mmVCE_UENC_CLOCK_GATING, 0x40);
a2e73f56	392
abc8c1ce	393	/* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
abc8c1ce	394	WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
a2e73f56	395
abc8c1ce	396	WREG32_P(mmVCE_LMI_CTRL2, 0, ~0x100);
	397	if(!gated) {
	398	WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
	399	mdelay(100);
	400	WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
	401
	402	vce_v2_0_firmware_loaded(adev);
	403	WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
	404	}
a2e73f56 AD	405	}
	406
	407	static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
	408	{
	409	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
	410	}
	411
	412	static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
	413	{
	414	bool sw_cg = false;
	415
e3b04bc7	416	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
a2e73f56 AD	417	if (sw_cg)
	418	vce_v2_0_set_sw_cg(adev, true);
	419	else
	420	vce_v2_0_set_dyn_cg(adev, true);
	421	} else {
	422	vce_v2_0_disable_cg(adev);
	423
	424	if (sw_cg)
	425	vce_v2_0_set_sw_cg(adev, false);
	426	else
	427	vce_v2_0_set_dyn_cg(adev, false);
	428	}
	429	}
	430
	431	static void vce_v2_0_init_cg(struct amdgpu_device *adev)
	432	{
	433	u32 tmp;
	434
	435	tmp = RREG32(mmVCE_CLOCK_GATING_A);
	436	tmp &= ~0xfff;
	437	tmp \|= ((0 << 0) \| (4 << 4));
	438	tmp \|= 0x40000;
	439	WREG32(mmVCE_CLOCK_GATING_A, tmp);
	440
	441	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
	442	tmp &= ~0xfff;
	443	tmp \|= ((0 << 0) \| (4 << 4));
	444	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
	445
	446	tmp = RREG32(mmVCE_CLOCK_GATING_B);
	447	tmp \|= 0x10;
	448	tmp &= ~0x100000;
	449	WREG32(mmVCE_CLOCK_GATING_B, tmp);
	450	}
	451
	452	static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
	453	{
	454	uint64_t addr = adev->vce.gpu_addr;
	455	uint32_t size;
	456
	457	WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
	458	WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
	459	WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
	460	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
	461
	462	WREG32(mmVCE_LMI_CTRL, 0x00398000);
	463	WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
	464	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
	465	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
	466	WREG32(mmVCE_LMI_VM_CTRL, 0);
	467
	468	addr += AMDGPU_VCE_FIRMWARE_OFFSET;
e9822622	469	size = VCE_V2_0_FW_SIZE;
a2e73f56 AD	470	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
	471	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
	472
	473	addr += size;
e9822622	474	size = VCE_V2_0_STACK_SIZE;
a2e73f56 AD	475	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
	476	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
	477
	478	addr += size;
e9822622	479	size = VCE_V2_0_DATA_SIZE;
a2e73f56 AD	480	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
	481	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
	482
	483	WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
21d3cbbe	484	WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
a2e73f56 AD	485
	486	vce_v2_0_init_cg(adev);
	487	}
	488
5fc3aeeb	489	static bool vce_v2_0_is_idle(void *handle)
a2e73f56	490	{
5fc3aeeb	491	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	492
a2e73f56 AD	493	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
	494	}
	495
5fc3aeeb	496	static int vce_v2_0_wait_for_idle(void *handle)
a2e73f56	497	{
5fc3aeeb	498	struct amdgpu_device adev = (struct amdgpu_device )handle;
21d3cbbe	499	unsigned i;
a2e73f56 AD	500
a2e73f56 AD	501	for (i = 0; i < adev->usec_timeout; i++) {
21d3cbbe	502	if (vce_v2_0_is_idle(handle))
a2e73f56 AD	503	return 0;
	504	}
	505	return -ETIMEDOUT;
	506	}
	507
5fc3aeeb	508	static int vce_v2_0_soft_reset(void *handle)
a2e73f56	509	{
5fc3aeeb	510	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	511
21d3cbbe	512	WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
a2e73f56 AD	513	mdelay(5);
	514
	515	return vce_v2_0_start(adev);
	516	}
	517
a2e73f56 AD	518	static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
	519	struct amdgpu_irq_src *source,
	520	unsigned type,
	521	enum amdgpu_interrupt_state state)
	522	{
	523	uint32_t val = 0;
	524
	525	if (state == AMDGPU_IRQ_STATE_ENABLE)
	526	val \|= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
	527
	528	WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
	529	return 0;
	530	}
	531
	532	static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
	533	struct amdgpu_irq_src *source,
	534	struct amdgpu_iv_entry *entry)
	535	{
	536	DRM_DEBUG("IH: VCE\n");
	537	switch (entry->src_data) {
	538	case 0:
a2e73f56	539	case 1:
21d3cbbe	540	amdgpu_fence_process(&adev->vce.ring[entry->src_data]);
a2e73f56 AD	541	break;
	542	default:
	543	DRM_ERROR("Unhandled interrupt: %d %d\n",
	544	entry->src_id, entry->src_data);
	545	break;
	546	}
	547
	548	return 0;
	549	}
	550
5fc3aeeb	551	static int vce_v2_0_set_clockgating_state(void *handle,
5fc3aeeb	552	enum amd_clockgating_state state)
a2e73f56 AD	553	{
a2e73f56 AD	554	bool gate = false;
5fc3aeeb	555	struct amdgpu_device adev = (struct amdgpu_device )handle;
a2e73f56	556
5fc3aeeb	557	if (state == AMD_CG_STATE_GATE)
a2e73f56 AD	558	gate = true;
	559
	560	vce_v2_0_enable_mgcg(adev, gate);
	561
	562	return 0;
	563	}
	564
5fc3aeeb	565	static int vce_v2_0_set_powergating_state(void *handle,
5fc3aeeb	566	enum amd_powergating_state state)
a2e73f56 AD	567	{
	568	/* This doesn't actually powergate the VCE block.
	569	* That's done in the dpm code via the SMC. This
	570	* just re-inits the block as necessary. The actual
	571	* gating still happens in the dpm code. We should
	572	* revisit this when there is a cleaner line between
	573	* the smc and the hw blocks
	574	*/
5fc3aeeb	575	struct amdgpu_device adev = (struct amdgpu_device )handle;
5fc3aeeb	576
e3b04bc7	577	if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
808a934f AD	578	return 0;
808a934f AD	579
5fc3aeeb	580	if (state == AMD_PG_STATE_GATE)
a2e73f56 AD	581	/* XXX do we need a vce_v2_0_stop()? */
	582	return 0;
	583	else
	584	return vce_v2_0_start(adev);
	585	}
	586
5fc3aeeb	587	const struct amd_ip_funcs vce_v2_0_ip_funcs = {
88a907d6	588	.name = "vce_v2_0",
a2e73f56 AD	589	.early_init = vce_v2_0_early_init,
	590	.late_init = NULL,
	591	.sw_init = vce_v2_0_sw_init,
	592	.sw_fini = vce_v2_0_sw_fini,
	593	.hw_init = vce_v2_0_hw_init,
	594	.hw_fini = vce_v2_0_hw_fini,
	595	.suspend = vce_v2_0_suspend,
	596	.resume = vce_v2_0_resume,
	597	.is_idle = vce_v2_0_is_idle,
	598	.wait_for_idle = vce_v2_0_wait_for_idle,
	599	.soft_reset = vce_v2_0_soft_reset,
a2e73f56 AD	600	.set_clockgating_state = vce_v2_0_set_clockgating_state,
	601	.set_powergating_state = vce_v2_0_set_powergating_state,
	602	};
	603
	604	static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
	605	.get_rptr = vce_v2_0_ring_get_rptr,
	606	.get_wptr = vce_v2_0_ring_get_wptr,
	607	.set_wptr = vce_v2_0_ring_set_wptr,
	608	.parse_cs = amdgpu_vce_ring_parse_cs,
	609	.emit_ib = amdgpu_vce_ring_emit_ib,
	610	.emit_fence = amdgpu_vce_ring_emit_fence,
a2e73f56 AD	611	.test_ring = amdgpu_vce_ring_test_ring,
a2e73f56 AD	612	.test_ib = amdgpu_vce_ring_test_ib,
edff0e28	613	.insert_nop = amdgpu_ring_insert_nop,
9e5d5309	614	.pad_ib = amdgpu_ring_generic_pad_ib,
ebff485e CK	615	.begin_use = amdgpu_vce_ring_begin_use,
ebff485e CK	616	.end_use = amdgpu_vce_ring_end_use,
a2e73f56 AD	617	};
	618
	619	static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
	620	{
	621	adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
	622	adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
	623	}
	624
	625	static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
	626	.set = vce_v2_0_set_interrupt_state,
	627	.process = vce_v2_0_process_interrupt,
	628	};
	629
	630	static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
	631	{
	632	adev->vce.irq.num_types = 1;
	633	adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
	634	};