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drm/amdgpu: clean up asic level reset for VI
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / vi.c
CommitLineData
aaa36a97
AD		 1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include "drmP.h"
27#include "amdgpu.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_ih.h"
30#include "amdgpu_uvd.h"
31#include "amdgpu_vce.h"
32#include "amdgpu_ucode.h"
33#include "atom.h"
d0dd7f0c 34#include "amd_pcie.h"
aaa36a97
AD		 35
36#include "gmc/gmc_8_1_d.h"
37#include "gmc/gmc_8_1_sh_mask.h"
38
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41
42#include "bif/bif_5_0_d.h"
43#include "bif/bif_5_0_sh_mask.h"
44
45#include "gca/gfx_8_0_d.h"
46#include "gca/gfx_8_0_sh_mask.h"
47
48#include "smu/smu_7_1_1_d.h"
49#include "smu/smu_7_1_1_sh_mask.h"
50
51#include "uvd/uvd_5_0_d.h"
52#include "uvd/uvd_5_0_sh_mask.h"
53
54#include "vce/vce_3_0_d.h"
55#include "vce/vce_3_0_sh_mask.h"
56
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
60#include "vid.h"
61#include "vi.h"
62#include "vi_dpm.h"
63#include "gmc_v8_0.h"
429c45de 64#include "gmc_v7_0.h"
aaa36a97
AD		 65#include "gfx_v8_0.h"
66#include "sdma_v2_4.h"
67#include "sdma_v3_0.h"
68#include "dce_v10_0.h"
69#include "dce_v11_0.h"
70#include "iceland_ih.h"
71#include "tonga_ih.h"
72#include "cz_ih.h"
73#include "uvd_v5_0.h"
74#include "uvd_v6_0.h"
75#include "vce_v3_0.h"
1f7371b2 76#include "amdgpu_powerplay.h"
aaa36a97
AD		 77
78/*
79 * Indirect registers accessor
80 */
81static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
82{
83 unsigned long flags;
84 u32 r;
85
86 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
87 WREG32(mmPCIE_INDEX, reg);
88 (void)RREG32(mmPCIE_INDEX);
89 r = RREG32(mmPCIE_DATA);
90 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
91 return r;
92}
93
94static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
95{
96 unsigned long flags;
97
98 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
99 WREG32(mmPCIE_INDEX, reg);
100 (void)RREG32(mmPCIE_INDEX);
101 WREG32(mmPCIE_DATA, v);
102 (void)RREG32(mmPCIE_DATA);
103 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
104}
105
106static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
107{
108 unsigned long flags;
109 u32 r;
110
111 spin_lock_irqsave(&adev->smc_idx_lock, flags);
112 WREG32(mmSMC_IND_INDEX_0, (reg));
113 r = RREG32(mmSMC_IND_DATA_0);
114 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
115 return r;
116}
117
118static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
119{
120 unsigned long flags;
121
122 spin_lock_irqsave(&adev->smc_idx_lock, flags);
123 WREG32(mmSMC_IND_INDEX_0, (reg));
124 WREG32(mmSMC_IND_DATA_0, (v));
125 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
126}
127
7b92cdbf
AD		 128/* smu_8_0_d.h */
129#define mmMP0PUB_IND_INDEX 0x180
130#define mmMP0PUB_IND_DATA 0x181
131
132static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
133{
134 unsigned long flags;
135 u32 r;
136
137 spin_lock_irqsave(&adev->smc_idx_lock, flags);
138 WREG32(mmMP0PUB_IND_INDEX, (reg));
139 r = RREG32(mmMP0PUB_IND_DATA);
140 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
141 return r;
142}
143
144static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
145{
146 unsigned long flags;
147
148 spin_lock_irqsave(&adev->smc_idx_lock, flags);
149 WREG32(mmMP0PUB_IND_INDEX, (reg));
150 WREG32(mmMP0PUB_IND_DATA, (v));
151 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
152}
153
aaa36a97
AD		 154static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
155{
156 unsigned long flags;
157 u32 r;
158
159 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
160 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
161 r = RREG32(mmUVD_CTX_DATA);
162 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
163 return r;
164}
165
166static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
167{
168 unsigned long flags;
169
170 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
171 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
172 WREG32(mmUVD_CTX_DATA, (v));
173 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
174}
175
176static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
177{
178 unsigned long flags;
179 u32 r;
180
181 spin_lock_irqsave(&adev->didt_idx_lock, flags);
182 WREG32(mmDIDT_IND_INDEX, (reg));
183 r = RREG32(mmDIDT_IND_DATA);
184 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
185 return r;
186}
187
188static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
189{
190 unsigned long flags;
191
192 spin_lock_irqsave(&adev->didt_idx_lock, flags);
193 WREG32(mmDIDT_IND_INDEX, (reg));
194 WREG32(mmDIDT_IND_DATA, (v));
195 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
196}
197
198static const u32 tonga_mgcg_cgcg_init[] =
199{
200 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
201 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
202 mmPCIE_DATA, 0x000f0000, 0x00000000,
203 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
204 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
aaa36a97
AD		 205 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
206 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
207};
208
48299f95
DZ		 209static const u32 fiji_mgcg_cgcg_init[] =
210{
211 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
212 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
213 mmPCIE_DATA, 0x000f0000, 0x00000000,
214 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
215 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
216 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
217 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
218};
219
aaa36a97
AD		 220static const u32 iceland_mgcg_cgcg_init[] =
221{
222 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
223 mmPCIE_DATA, 0x000f0000, 0x00000000,
224 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
225 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
226 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
227};
228
229static const u32 cz_mgcg_cgcg_init[] =
230{
231 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
232 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
233 mmPCIE_DATA, 0x000f0000, 0x00000000,
aaa36a97
AD		 234 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
235 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
236};
237
39bb0c92
SL		 238static const u32 stoney_mgcg_cgcg_init[] =
239{
240 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
241 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
242 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
243};
244
aaa36a97
AD		 245static void vi_init_golden_registers(struct amdgpu_device *adev)
246{
247 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
248 mutex_lock(&adev->grbm_idx_mutex);
249
250 switch (adev->asic_type) {
251 case CHIP_TOPAZ:
252 amdgpu_program_register_sequence(adev,
253 iceland_mgcg_cgcg_init,
254 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
255 break;
48299f95
DZ		 256 case CHIP_FIJI:
257 amdgpu_program_register_sequence(adev,
258 fiji_mgcg_cgcg_init,
259 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
260 break;
aaa36a97
AD		 261 case CHIP_TONGA:
262 amdgpu_program_register_sequence(adev,
263 tonga_mgcg_cgcg_init,
264 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
265 break;
266 case CHIP_CARRIZO:
267 amdgpu_program_register_sequence(adev,
268 cz_mgcg_cgcg_init,
269 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
270 break;
39bb0c92
SL		 271 case CHIP_STONEY:
272 amdgpu_program_register_sequence(adev,
273 stoney_mgcg_cgcg_init,
274 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
275 break;
aaa36a97
AD		 276 default:
277 break;
278 }
279 mutex_unlock(&adev->grbm_idx_mutex);
280}
281
282/**
283 * vi_get_xclk - get the xclk
284 *
285 * @adev: amdgpu_device pointer
286 *
287 * Returns the reference clock used by the gfx engine
288 * (VI).
289 */
290static u32 vi_get_xclk(struct amdgpu_device *adev)
291{
292 u32 reference_clock = adev->clock.spll.reference_freq;
293 u32 tmp;
294
2f7d10b3 295 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 296 return reference_clock;
297
298 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
299 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
300 return 1000;
301
302 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
303 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
304 return reference_clock / 4;
305
306 return reference_clock;
307}
308
309/**
310 * vi_srbm_select - select specific register instances
311 *
312 * @adev: amdgpu_device pointer
313 * @me: selected ME (micro engine)
314 * @pipe: pipe
315 * @queue: queue
316 * @vmid: VMID
317 *
318 * Switches the currently active registers instances. Some
319 * registers are instanced per VMID, others are instanced per
320 * me/pipe/queue combination.
321 */
322void vi_srbm_select(struct amdgpu_device *adev,
323 u32 me, u32 pipe, u32 queue, u32 vmid)
324{
325 u32 srbm_gfx_cntl = 0;
326 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
327 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
328 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
329 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
330 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
331}
332
333static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
334{
335 /* todo */
336}
337
338static bool vi_read_disabled_bios(struct amdgpu_device *adev)
339{
340 u32 bus_cntl;
341 u32 d1vga_control = 0;
342 u32 d2vga_control = 0;
343 u32 vga_render_control = 0;
344 u32 rom_cntl;
345 bool r;
346
347 bus_cntl = RREG32(mmBUS_CNTL);
348 if (adev->mode_info.num_crtc) {
349 d1vga_control = RREG32(mmD1VGA_CONTROL);
350 d2vga_control = RREG32(mmD2VGA_CONTROL);
351 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
352 }
353 rom_cntl = RREG32_SMC(ixROM_CNTL);
354
355 /* enable the rom */
356 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
357 if (adev->mode_info.num_crtc) {
358 /* Disable VGA mode */
359 WREG32(mmD1VGA_CONTROL,
360 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
361 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
362 WREG32(mmD2VGA_CONTROL,
363 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
364 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
365 WREG32(mmVGA_RENDER_CONTROL,
366 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
367 }
368 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
369
370 r = amdgpu_read_bios(adev);
371
372 /* restore regs */
373 WREG32(mmBUS_CNTL, bus_cntl);
374 if (adev->mode_info.num_crtc) {
375 WREG32(mmD1VGA_CONTROL, d1vga_control);
376 WREG32(mmD2VGA_CONTROL, d2vga_control);
377 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
378 }
379 WREG32_SMC(ixROM_CNTL, rom_cntl);
380 return r;
381}
95addb2a
AD		 382
383static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
384 u8 *bios, u32 length_bytes)
385{
386 u32 *dw_ptr;
387 unsigned long flags;
388 u32 i, length_dw;
389
390 if (bios == NULL)
391 return false;
392 if (length_bytes == 0)
393 return false;
394 /* APU vbios image is part of sbios image */
395 if (adev->flags & AMD_IS_APU)
396 return false;
397
398 dw_ptr = (u32 *)bios;
399 length_dw = ALIGN(length_bytes, 4) / 4;
400 /* take the smc lock since we are using the smc index */
401 spin_lock_irqsave(&adev->smc_idx_lock, flags);
402 /* set rom index to 0 */
403 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
404 WREG32(mmSMC_IND_DATA_0, 0);
405 /* set index to data for continous read */
406 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
407 for (i = 0; i < length_dw; i++)
408 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
409 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
410
411 return true;
412}
413
aaa36a97
AD		 414static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
415 {mmGB_MACROTILE_MODE7, true},
416};
417
418static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
419 {mmGB_TILE_MODE7, true},
420 {mmGB_TILE_MODE12, true},
421 {mmGB_TILE_MODE17, true},
422 {mmGB_TILE_MODE23, true},
423 {mmGB_MACROTILE_MODE7, true},
424};
425
426static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
427 {mmGRBM_STATUS, false},
c7890fea
MO		 428 {mmGRBM_STATUS2, false},
429 {mmGRBM_STATUS_SE0, false},
430 {mmGRBM_STATUS_SE1, false},
431 {mmGRBM_STATUS_SE2, false},
432 {mmGRBM_STATUS_SE3, false},
433 {mmSRBM_STATUS, false},
434 {mmSRBM_STATUS2, false},
435 {mmSRBM_STATUS3, false},
436 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
437 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
438 {mmCP_STAT, false},
439 {mmCP_STALLED_STAT1, false},
440 {mmCP_STALLED_STAT2, false},
441 {mmCP_STALLED_STAT3, false},
442 {mmCP_CPF_BUSY_STAT, false},
443 {mmCP_CPF_STALLED_STAT1, false},
444 {mmCP_CPF_STATUS, false},
445 {mmCP_CPC_BUSY_STAT, false},
446 {mmCP_CPC_STALLED_STAT1, false},
447 {mmCP_CPC_STATUS, false},
aaa36a97
AD		 448 {mmGB_ADDR_CONFIG, false},
449 {mmMC_ARB_RAMCFG, false},
450 {mmGB_TILE_MODE0, false},
451 {mmGB_TILE_MODE1, false},
452 {mmGB_TILE_MODE2, false},
453 {mmGB_TILE_MODE3, false},
454 {mmGB_TILE_MODE4, false},
455 {mmGB_TILE_MODE5, false},
456 {mmGB_TILE_MODE6, false},
457 {mmGB_TILE_MODE7, false},
458 {mmGB_TILE_MODE8, false},
459 {mmGB_TILE_MODE9, false},
460 {mmGB_TILE_MODE10, false},
461 {mmGB_TILE_MODE11, false},
462 {mmGB_TILE_MODE12, false},
463 {mmGB_TILE_MODE13, false},
464 {mmGB_TILE_MODE14, false},
465 {mmGB_TILE_MODE15, false},
466 {mmGB_TILE_MODE16, false},
467 {mmGB_TILE_MODE17, false},
468 {mmGB_TILE_MODE18, false},
469 {mmGB_TILE_MODE19, false},
470 {mmGB_TILE_MODE20, false},
471 {mmGB_TILE_MODE21, false},
472 {mmGB_TILE_MODE22, false},
473 {mmGB_TILE_MODE23, false},
474 {mmGB_TILE_MODE24, false},
475 {mmGB_TILE_MODE25, false},
476 {mmGB_TILE_MODE26, false},
477 {mmGB_TILE_MODE27, false},
478 {mmGB_TILE_MODE28, false},
479 {mmGB_TILE_MODE29, false},
480 {mmGB_TILE_MODE30, false},
481 {mmGB_TILE_MODE31, false},
482 {mmGB_MACROTILE_MODE0, false},
483 {mmGB_MACROTILE_MODE1, false},
484 {mmGB_MACROTILE_MODE2, false},
485 {mmGB_MACROTILE_MODE3, false},
486 {mmGB_MACROTILE_MODE4, false},
487 {mmGB_MACROTILE_MODE5, false},
488 {mmGB_MACROTILE_MODE6, false},
489 {mmGB_MACROTILE_MODE7, false},
490 {mmGB_MACROTILE_MODE8, false},
491 {mmGB_MACROTILE_MODE9, false},
492 {mmGB_MACROTILE_MODE10, false},
493 {mmGB_MACROTILE_MODE11, false},
494 {mmGB_MACROTILE_MODE12, false},
495 {mmGB_MACROTILE_MODE13, false},
496 {mmGB_MACROTILE_MODE14, false},
497 {mmGB_MACROTILE_MODE15, false},
498 {mmCC_RB_BACKEND_DISABLE, false, true},
499 {mmGC_USER_RB_BACKEND_DISABLE, false, true},
500 {mmGB_BACKEND_MAP, false, false},
501 {mmPA_SC_RASTER_CONFIG, false, true},
502 {mmPA_SC_RASTER_CONFIG_1, false, true},
503};
504
505static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
506 u32 sh_num, u32 reg_offset)
507{
508 uint32_t val;
509
510 mutex_lock(&adev->grbm_idx_mutex);
511 if (se_num != 0xffffffff || sh_num != 0xffffffff)
512 gfx_v8_0_select_se_sh(adev, se_num, sh_num);
513
514 val = RREG32(reg_offset);
515
516 if (se_num != 0xffffffff || sh_num != 0xffffffff)
517 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
518 mutex_unlock(&adev->grbm_idx_mutex);
519 return val;
520}
521
522static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
523 u32 sh_num, u32 reg_offset, u32 *value)
524{
525 struct amdgpu_allowed_register_entry *asic_register_table = NULL;
526 struct amdgpu_allowed_register_entry *asic_register_entry;
527 uint32_t size, i;
528
529 *value = 0;
530 switch (adev->asic_type) {
531 case CHIP_TOPAZ:
532 asic_register_table = tonga_allowed_read_registers;
533 size = ARRAY_SIZE(tonga_allowed_read_registers);
534 break;
48299f95 535 case CHIP_FIJI:
aaa36a97
AD		 536 case CHIP_TONGA:
537 case CHIP_CARRIZO:
39bb0c92 538 case CHIP_STONEY:
aaa36a97
AD		 539 asic_register_table = cz_allowed_read_registers;
540 size = ARRAY_SIZE(cz_allowed_read_registers);
541 break;
542 default:
543 return -EINVAL;
544 }
545
546 if (asic_register_table) {
547 for (i = 0; i < size; i++) {
548 asic_register_entry = asic_register_table + i;
549 if (reg_offset != asic_register_entry->reg_offset)
550 continue;
551 if (!asic_register_entry->untouched)
552 *value = asic_register_entry->grbm_indexed ?
553 vi_read_indexed_register(adev, se_num,
554 sh_num, reg_offset) :
555 RREG32(reg_offset);
556 return 0;
557 }
558 }
559
560 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
561 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
562 continue;
563
564 if (!vi_allowed_read_registers[i].untouched)
565 *value = vi_allowed_read_registers[i].grbm_indexed ?
566 vi_read_indexed_register(adev, se_num,
567 sh_num, reg_offset) :
568 RREG32(reg_offset);
569 return 0;
570 }
571 return -EINVAL;
572}
573
aaa36a97
AD		 574static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
575{
a2c5c698 576 u32 i;
aaa36a97
AD		 577
578 dev_info(adev->dev, "GPU pci config reset\n");
579
aaa36a97
AD		 580 /* disable BM */
581 pci_clear_master(adev->pdev);
582 /* reset */
583 amdgpu_pci_config_reset(adev);
584
585 udelay(100);
586
587 /* wait for asic to come out of reset */
588 for (i = 0; i < adev->usec_timeout; i++) {
589 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
590 break;
591 udelay(1);
592 }
593
594}
595
596static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
597{
598 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
599
600 if (hung)
601 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
602 else
603 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
604
605 WREG32(mmBIOS_SCRATCH_3, tmp);
606}
607
608/**
609 * vi_asic_reset - soft reset GPU
610 *
611 * @adev: amdgpu_device pointer
612 *
613 * Look up which blocks are hung and attempt
614 * to reset them.
615 * Returns 0 for success.
616 */
617static int vi_asic_reset(struct amdgpu_device *adev)
618{
a2c5c698 619 vi_set_bios_scratch_engine_hung(adev, true);
aaa36a97 620
a2c5c698 621 vi_gpu_pci_config_reset(adev);
aaa36a97 622
a2c5c698 623 vi_set_bios_scratch_engine_hung(adev, false);
aaa36a97
AD		 624
625 return 0;
626}
627
628static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
629 u32 cntl_reg, u32 status_reg)
630{
631 int r, i;
632 struct atom_clock_dividers dividers;
633 uint32_t tmp;
634
635 r = amdgpu_atombios_get_clock_dividers(adev,
636 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
637 clock, false, &dividers);
638 if (r)
639 return r;
640
641 tmp = RREG32_SMC(cntl_reg);
642 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
643 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
644 tmp |= dividers.post_divider;
645 WREG32_SMC(cntl_reg, tmp);
646
647 for (i = 0; i < 100; i++) {
648 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
649 break;
650 mdelay(10);
651 }
652 if (i == 100)
653 return -ETIMEDOUT;
654
655 return 0;
656}
657
658static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
659{
660 int r;
661
662 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
663 if (r)
664 return r;
665
666 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
667
668 return 0;
669}
670
671static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
672{
673 /* todo */
674
675 return 0;
676}
677
678static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
679{
e79d5c08
AD		 680 if (pci_is_root_bus(adev->pdev->bus))
681 return;
682
aaa36a97
AD		 683 if (amdgpu_pcie_gen2 == 0)
684 return;
685
2f7d10b3 686 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 687 return;
688
d0dd7f0c
AD		 689 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
690 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
aaa36a97
AD		 691 return;
692
693 /* todo */
694}
695
696static void vi_program_aspm(struct amdgpu_device *adev)
697{
698
699 if (amdgpu_aspm == 0)
700 return;
701
702 /* todo */
703}
704
705static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
706 bool enable)
707{
708 u32 tmp;
709
710 /* not necessary on CZ */
2f7d10b3 711 if (adev->flags & AMD_IS_APU)
aaa36a97
AD		 712 return;
713
714 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
715 if (enable)
716 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
717 else
718 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
719
720 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
721}
722
723/* topaz has no DCE, UVD, VCE */
724static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
725{
726 /* ORDER MATTERS! */
727 {
5fc3aeeb 728 .type = AMD_IP_BLOCK_TYPE_COMMON,
aaa36a97
AD		 729 .major = 2,
730 .minor = 0,
731 .rev = 0,
732 .funcs = &vi_common_ip_funcs,
733 },
734 {
5fc3aeeb 735 .type = AMD_IP_BLOCK_TYPE_GMC,
429c45de
KW		 736 .major = 7,
737 .minor = 4,
aaa36a97 738 .rev = 0,
429c45de 739 .funcs = &gmc_v7_0_ip_funcs,
aaa36a97
AD		 740 },
741 {
5fc3aeeb 742 .type = AMD_IP_BLOCK_TYPE_IH,
aaa36a97
AD		 743 .major = 2,
744 .minor = 4,
745 .rev = 0,
746 .funcs = &iceland_ih_ip_funcs,
747 },
748 {
5fc3aeeb 749 .type = AMD_IP_BLOCK_TYPE_SMC,
aaa36a97
AD		 750 .major = 7,
751 .minor = 1,
752 .rev = 0,
1f7371b2 753 .funcs = &amdgpu_pp_ip_funcs,
aaa36a97
AD		 754 },
755 {
5fc3aeeb 756 .type = AMD_IP_BLOCK_TYPE_GFX,
aaa36a97
AD		 757 .major = 8,
758 .minor = 0,
759 .rev = 0,
760 .funcs = &gfx_v8_0_ip_funcs,
761 },
762 {
5fc3aeeb 763 .type = AMD_IP_BLOCK_TYPE_SDMA,
aaa36a97
AD		 764 .major = 2,
765 .minor = 4,
766 .rev = 0,
767 .funcs = &sdma_v2_4_ip_funcs,
768 },
769};
770
771static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
772{
773 /* ORDER MATTERS! */
774 {
5fc3aeeb 775 .type = AMD_IP_BLOCK_TYPE_COMMON,
aaa36a97
AD		 776 .major = 2,
777 .minor = 0,
778 .rev = 0,
779 .funcs = &vi_common_ip_funcs,
780 },
781 {
5fc3aeeb 782 .type = AMD_IP_BLOCK_TYPE_GMC,
aaa36a97
AD		 783 .major = 8,
784 .minor = 0,
785 .rev = 0,
786 .funcs = &gmc_v8_0_ip_funcs,
787 },
788 {
5fc3aeeb 789 .type = AMD_IP_BLOCK_TYPE_IH,
aaa36a97
AD		 790 .major = 3,
791 .minor = 0,
792 .rev = 0,
793 .funcs = &tonga_ih_ip_funcs,
794 },
795 {
5fc3aeeb 796 .type = AMD_IP_BLOCK_TYPE_SMC,
aaa36a97
AD		 797 .major = 7,
798 .minor = 1,
799 .rev = 0,
1f7371b2 800 .funcs = &amdgpu_pp_ip_funcs,
aaa36a97
AD		 801 },
802 {
5fc3aeeb 803 .type = AMD_IP_BLOCK_TYPE_DCE,
aaa36a97
AD		 804 .major = 10,
805 .minor = 0,
806 .rev = 0,
807 .funcs = &dce_v10_0_ip_funcs,
808 },
809 {
5fc3aeeb 810 .type = AMD_IP_BLOCK_TYPE_GFX,
aaa36a97
AD		 811 .major = 8,
812 .minor = 0,
813 .rev = 0,
814 .funcs = &gfx_v8_0_ip_funcs,
815 },
816 {
5fc3aeeb 817 .type = AMD_IP_BLOCK_TYPE_SDMA,
aaa36a97
AD		 818 .major = 3,
819 .minor = 0,
820 .rev = 0,
821 .funcs = &sdma_v3_0_ip_funcs,
822 },
823 {
5fc3aeeb 824 .type = AMD_IP_BLOCK_TYPE_UVD,
aaa36a97
AD		 825 .major = 5,
826 .minor = 0,
827 .rev = 0,
828 .funcs = &uvd_v5_0_ip_funcs,
829 },
830 {
5fc3aeeb 831 .type = AMD_IP_BLOCK_TYPE_VCE,
aaa36a97
AD		 832 .major = 3,
833 .minor = 0,
834 .rev = 0,
835 .funcs = &vce_v3_0_ip_funcs,
836 },
837};
838
48299f95
DZ		 839static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
840{
841 /* ORDER MATTERS! */
842 {
843 .type = AMD_IP_BLOCK_TYPE_COMMON,
844 .major = 2,
845 .minor = 0,
846 .rev = 0,
847 .funcs = &vi_common_ip_funcs,
127a2628
DZ		 848 },
849 {
850 .type = AMD_IP_BLOCK_TYPE_GMC,
851 .major = 8,
852 .minor = 5,
853 .rev = 0,
854 .funcs = &gmc_v8_0_ip_funcs,
855 },
aa8a3b53
DZ		 856 {
857 .type = AMD_IP_BLOCK_TYPE_IH,
858 .major = 3,
859 .minor = 0,
860 .rev = 0,
861 .funcs = &tonga_ih_ip_funcs,
862 },
8e711e1a
DZ		 863 {
864 .type = AMD_IP_BLOCK_TYPE_SMC,
865 .major = 7,
866 .minor = 1,
867 .rev = 0,
899fa4c0 868 .funcs = &amdgpu_pp_ip_funcs,
8e711e1a 869 },
84390860
DZ		 870 {
871 .type = AMD_IP_BLOCK_TYPE_DCE,
872 .major = 10,
873 .minor = 1,
874 .rev = 0,
875 .funcs = &dce_v10_0_ip_funcs,
876 },
af15a2d5
DZ		 877 {
878 .type = AMD_IP_BLOCK_TYPE_GFX,
879 .major = 8,
880 .minor = 0,
881 .rev = 0,
882 .funcs = &gfx_v8_0_ip_funcs,
883 },
1a5bbb66
DZ		 884 {
885 .type = AMD_IP_BLOCK_TYPE_SDMA,
886 .major = 3,
887 .minor = 0,
888 .rev = 0,
889 .funcs = &sdma_v3_0_ip_funcs,
890 },
974ee3db
DZ		 891 {
892 .type = AMD_IP_BLOCK_TYPE_UVD,
893 .major = 6,
894 .minor = 0,
895 .rev = 0,
896 .funcs = &uvd_v6_0_ip_funcs,
897 },
188a9bcd
AD		 898 {
899 .type = AMD_IP_BLOCK_TYPE_VCE,
900 .major = 3,
901 .minor = 0,
902 .rev = 0,
903 .funcs = &vce_v3_0_ip_funcs,
904 },
48299f95
DZ		 905};
906
aaa36a97
AD		 907static const struct amdgpu_ip_block_version cz_ip_blocks[] =
908{
909 /* ORDER MATTERS! */
910 {
5fc3aeeb 911 .type = AMD_IP_BLOCK_TYPE_COMMON,
aaa36a97
AD		 912 .major = 2,
913 .minor = 0,
914 .rev = 0,
915 .funcs = &vi_common_ip_funcs,
916 },
917 {
5fc3aeeb 918 .type = AMD_IP_BLOCK_TYPE_GMC,
aaa36a97
AD		 919 .major = 8,
920 .minor = 0,
921 .rev = 0,
922 .funcs = &gmc_v8_0_ip_funcs,
923 },
924 {
5fc3aeeb 925 .type = AMD_IP_BLOCK_TYPE_IH,
aaa36a97
AD		 926 .major = 3,
927 .minor = 0,
928 .rev = 0,
929 .funcs = &cz_ih_ip_funcs,
930 },
931 {
5fc3aeeb 932 .type = AMD_IP_BLOCK_TYPE_SMC,
aaa36a97
AD		 933 .major = 8,
934 .minor = 0,
935 .rev = 0,
1f7371b2 936 .funcs = &amdgpu_pp_ip_funcs
aaa36a97
AD		 937 },
938 {
5fc3aeeb 939 .type = AMD_IP_BLOCK_TYPE_DCE,
aaa36a97
AD		 940 .major = 11,
941 .minor = 0,
942 .rev = 0,
943 .funcs = &dce_v11_0_ip_funcs,
944 },
945 {
5fc3aeeb 946 .type = AMD_IP_BLOCK_TYPE_GFX,
aaa36a97
AD		 947 .major = 8,
948 .minor = 0,
949 .rev = 0,
950 .funcs = &gfx_v8_0_ip_funcs,
951 },
952 {
5fc3aeeb 953 .type = AMD_IP_BLOCK_TYPE_SDMA,
aaa36a97
AD		 954 .major = 3,
955 .minor = 0,
956 .rev = 0,
957 .funcs = &sdma_v3_0_ip_funcs,
958 },
959 {
5fc3aeeb 960 .type = AMD_IP_BLOCK_TYPE_UVD,
aaa36a97
AD		 961 .major = 6,
962 .minor = 0,
963 .rev = 0,
964 .funcs = &uvd_v6_0_ip_funcs,
965 },
966 {
5fc3aeeb 967 .type = AMD_IP_BLOCK_TYPE_VCE,
aaa36a97
AD		 968 .major = 3,
969 .minor = 0,
970 .rev = 0,
971 .funcs = &vce_v3_0_ip_funcs,
972 },
973};
974
975int vi_set_ip_blocks(struct amdgpu_device *adev)
976{
977 switch (adev->asic_type) {
978 case CHIP_TOPAZ:
979 adev->ip_blocks = topaz_ip_blocks;
980 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
981 break;
48299f95
DZ		 982 case CHIP_FIJI:
983 adev->ip_blocks = fiji_ip_blocks;
984 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
985 break;
aaa36a97
AD		 986 case CHIP_TONGA:
987 adev->ip_blocks = tonga_ip_blocks;
988 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
989 break;
990 case CHIP_CARRIZO:
39bb0c92 991 case CHIP_STONEY:
aaa36a97
AD		 992 adev->ip_blocks = cz_ip_blocks;
993 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
994 break;
995 default:
996 /* FIXME: not supported yet */
997 return -EINVAL;
998 }
999
aaa36a97
AD		 1000 return 0;
1001}
1002
39bb0c92
SL		 1003#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1004#define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1005#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1006
aaa36a97
AD		 1007static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1008{
abdfb850 1009 if (adev->flags & AMD_IS_APU)
39bb0c92
SL		 1010 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1011 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
aaa36a97 1012 else
abdfb850
FC		 1013 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1014 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
aaa36a97
AD		 1015}
1016
1017static const struct amdgpu_asic_funcs vi_asic_funcs =
1018{
1019 .read_disabled_bios = &vi_read_disabled_bios,
95addb2a 1020 .read_bios_from_rom = &vi_read_bios_from_rom,
aaa36a97
AD		 1021 .read_register = &vi_read_register,
1022 .reset = &vi_asic_reset,
1023 .set_vga_state = &vi_vga_set_state,
1024 .get_xclk = &vi_get_xclk,
1025 .set_uvd_clocks = &vi_set_uvd_clocks,
1026 .set_vce_clocks = &vi_set_vce_clocks,
1027 .get_cu_info = &gfx_v8_0_get_cu_info,
1028 /* these should be moved to their own ip modules */
1029 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1030 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1031};
1032
5fc3aeeb 1033static int vi_common_early_init(void *handle)
aaa36a97
AD		 1034{
1035 bool smc_enabled = false;
5fc3aeeb 1036 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
aaa36a97 1037
2f7d10b3 1038 if (adev->flags & AMD_IS_APU) {
7b92cdbf
AD		 1039 adev->smc_rreg = &cz_smc_rreg;
1040 adev->smc_wreg = &cz_smc_wreg;
1041 } else {
1042 adev->smc_rreg = &vi_smc_rreg;
1043 adev->smc_wreg = &vi_smc_wreg;
1044 }
aaa36a97
AD		 1045 adev->pcie_rreg = &vi_pcie_rreg;
1046 adev->pcie_wreg = &vi_pcie_wreg;
1047 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1048 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1049 adev->didt_rreg = &vi_didt_rreg;
1050 adev->didt_wreg = &vi_didt_wreg;
1051
1052 adev->asic_funcs = &vi_asic_funcs;
1053
5fc3aeeb 1054 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1055 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
aaa36a97
AD		 1056 smc_enabled = true;
1057
1058 adev->rev_id = vi_get_rev_id(adev);
1059 adev->external_rev_id = 0xFF;
1060 switch (adev->asic_type) {
1061 case CHIP_TOPAZ:
1062 adev->has_uvd = false;
1063 adev->cg_flags = 0;
1064 adev->pg_flags = 0;
1065 adev->external_rev_id = 0x1;
aaa36a97 1066 break;
48299f95 1067 case CHIP_FIJI:
b6bc28ff 1068 adev->has_uvd = true;
6357b75a 1069 adev->cg_flags = 0;
b6bc28ff
FC		 1070 adev->pg_flags = 0;
1071 adev->external_rev_id = adev->rev_id + 0x3c;
1072 break;
aaa36a97
AD		 1073 case CHIP_TONGA:
1074 adev->has_uvd = true;
1075 adev->cg_flags = 0;
1076 adev->pg_flags = 0;
1077 adev->external_rev_id = adev->rev_id + 0x14;
aaa36a97
AD		 1078 break;
1079 case CHIP_CARRIZO:
39bb0c92 1080 case CHIP_STONEY:
aaa36a97
AD		 1081 adev->has_uvd = true;
1082 adev->cg_flags = 0;
1ee4478a
LL		 1083 /* Disable UVD pg */
1084 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
aaa36a97 1085 adev->external_rev_id = adev->rev_id + 0x1;
aaa36a97
AD		 1086 break;
1087 default:
1088 /* FIXME: not supported yet */
1089 return -EINVAL;
1090 }
1091
a3d08fa5
FC		 1092 if (amdgpu_smc_load_fw && smc_enabled)
1093 adev->firmware.smu_load = true;
1094
d0dd7f0c
AD		 1095 amdgpu_get_pcie_info(adev);
1096
aaa36a97
AD		 1097 return 0;
1098}
1099
5fc3aeeb 1100static int vi_common_sw_init(void *handle)
aaa36a97
AD		 1101{
1102 return 0;
1103}
1104
5fc3aeeb 1105static int vi_common_sw_fini(void *handle)
aaa36a97
AD		 1106{
1107 return 0;
1108}
1109
5fc3aeeb 1110static int vi_common_hw_init(void *handle)
aaa36a97 1111{
5fc3aeeb 1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113
aaa36a97
AD		 1114 /* move the golden regs per IP block */
1115 vi_init_golden_registers(adev);
1116 /* enable pcie gen2/3 link */
1117 vi_pcie_gen3_enable(adev);
1118 /* enable aspm */
1119 vi_program_aspm(adev);
1120 /* enable the doorbell aperture */
1121 vi_enable_doorbell_aperture(adev, true);
1122
1123 return 0;
1124}
1125
5fc3aeeb 1126static int vi_common_hw_fini(void *handle)
aaa36a97 1127{
5fc3aeeb 1128 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1129
aaa36a97
AD		 1130 /* enable the doorbell aperture */
1131 vi_enable_doorbell_aperture(adev, false);
1132
1133 return 0;
1134}
1135
5fc3aeeb 1136static int vi_common_suspend(void *handle)
aaa36a97 1137{
5fc3aeeb 1138 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139
aaa36a97
AD		 1140 return vi_common_hw_fini(adev);
1141}
1142
5fc3aeeb 1143static int vi_common_resume(void *handle)
aaa36a97 1144{
5fc3aeeb 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146
aaa36a97
AD		 1147 return vi_common_hw_init(adev);
1148}
1149
5fc3aeeb 1150static bool vi_common_is_idle(void *handle)
aaa36a97
AD		 1151{
1152 return true;
1153}
1154
5fc3aeeb 1155static int vi_common_wait_for_idle(void *handle)
aaa36a97
AD		 1156{
1157 return 0;
1158}
1159
5fc3aeeb 1160static void vi_common_print_status(void *handle)
aaa36a97 1161{
5fc3aeeb 1162 return;
aaa36a97
AD		 1163}
1164
5fc3aeeb 1165static int vi_common_soft_reset(void *handle)
aaa36a97 1166{
aaa36a97
AD		 1167 return 0;
1168}
1169
6cec2655
EH		 1170static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1171 bool enable)
1172{
1173 uint32_t temp, data;
1174
1175 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1176
1177 if (enable)
1178 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1179 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1180 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1181 else
1182 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1183 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1184 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1185
1186 if (temp != data)
1187 WREG32_PCIE(ixPCIE_CNTL2, data);
1188}
1189
1190static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1191 bool enable)
1192{
1193 uint32_t temp, data;
1194
1195 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1196
1197 if (enable)
1198 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1199 else
1200 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1201
1202 if (temp != data)
1203 WREG32(mmHDP_HOST_PATH_CNTL, data);
1204}
1205
1206static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
1207 bool enable)
1208{
1209 uint32_t temp, data;
1210
1211 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1212
1213 if (enable)
1214 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1215 else
1216 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1217
1218 if (temp != data)
1219 WREG32(mmHDP_MEM_POWER_LS, data);
1220}
1221
1222static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1223 bool enable)
1224{
1225 uint32_t temp, data;
1226
1227 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1228
1229 if (enable)
1230 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1231 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1232 else
1233 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1234 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1235
1236 if (temp != data)
1237 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1238}
1239
5fc3aeeb 1240static int vi_common_set_clockgating_state(void *handle,
1241 enum amd_clockgating_state state)
aaa36a97 1242{
6cec2655
EH		 1243 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244
1245 switch (adev->asic_type) {
1246 case CHIP_FIJI:
1247 fiji_update_bif_medium_grain_light_sleep(adev,
1248 state == AMD_CG_STATE_GATE ? true : false);
1249 fiji_update_hdp_medium_grain_clock_gating(adev,
1250 state == AMD_CG_STATE_GATE ? true : false);
1251 fiji_update_hdp_light_sleep(adev,
1252 state == AMD_CG_STATE_GATE ? true : false);
1253 fiji_update_rom_medium_grain_clock_gating(adev,
1254 state == AMD_CG_STATE_GATE ? true : false);
1255 break;
1256 default:
1257 break;
1258 }
aaa36a97
AD		 1259 return 0;
1260}
1261
5fc3aeeb 1262static int vi_common_set_powergating_state(void *handle,
1263 enum amd_powergating_state state)
aaa36a97
AD		 1264{
1265 return 0;
1266}
1267
5fc3aeeb 1268const struct amd_ip_funcs vi_common_ip_funcs = {
aaa36a97
AD		 1269 .early_init = vi_common_early_init,
1270 .late_init = NULL,
1271 .sw_init = vi_common_sw_init,
1272 .sw_fini = vi_common_sw_fini,
1273 .hw_init = vi_common_hw_init,
1274 .hw_fini = vi_common_hw_fini,
1275 .suspend = vi_common_suspend,
1276 .resume = vi_common_resume,
1277 .is_idle = vi_common_is_idle,
1278 .wait_for_idle = vi_common_wait_for_idle,
1279 .soft_reset = vi_common_soft_reset,
1280 .print_status = vi_common_print_status,
1281 .set_clockgating_state = vi_common_set_clockgating_state,
1282 .set_powergating_state = vi_common_set_powergating_state,
1283};
1284
Linux kernel - Deliverables
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