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Merge remote-tracking branch 'md/for-next'
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / polaris10_hwmgr.c
CommitLineData
a23eefa2
RZ		 1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
ae17c999 25#include <asm/div64.h>
a23eefa2
RZ		 26#include "linux/delay.h"
27#include "pp_acpi.h"
28#include "hwmgr.h"
2cc0c0b5
FC		 29#include "polaris10_hwmgr.h"
30#include "polaris10_powertune.h"
31#include "polaris10_dyn_defaults.h"
32#include "polaris10_smumgr.h"
a23eefa2
RZ		 33#include "pp_debug.h"
34#include "ppatomctrl.h"
35#include "atombios.h"
36#include "tonga_pptable.h"
37#include "pppcielanes.h"
38#include "amd_pcie_helpers.h"
39#include "hardwaremanager.h"
40#include "tonga_processpptables.h"
41#include "cgs_common.h"
42#include "smu74.h"
43#include "smu_ucode_xfer_vi.h"
44#include "smu74_discrete.h"
45#include "smu/smu_7_1_3_d.h"
46#include "smu/smu_7_1_3_sh_mask.h"
47#include "gmc/gmc_8_1_d.h"
48#include "gmc/gmc_8_1_sh_mask.h"
49#include "oss/oss_3_0_d.h"
50#include "gca/gfx_8_0_d.h"
51#include "bif/bif_5_0_d.h"
52#include "bif/bif_5_0_sh_mask.h"
53#include "gmc/gmc_8_1_d.h"
54#include "gmc/gmc_8_1_sh_mask.h"
55#include "bif/bif_5_0_d.h"
56#include "bif/bif_5_0_sh_mask.h"
57#include "dce/dce_10_0_d.h"
58#include "dce/dce_10_0_sh_mask.h"
59
2cc0c0b5
FC		 60#include "polaris10_thermal.h"
61#include "polaris10_clockpowergating.h"
eede5262 62
a23eefa2
RZ		 63#define MC_CG_ARB_FREQ_F0 0x0a
64#define MC_CG_ARB_FREQ_F1 0x0b
65#define MC_CG_ARB_FREQ_F2 0x0c
66#define MC_CG_ARB_FREQ_F3 0x0d
67
68#define MC_CG_SEQ_DRAMCONF_S0 0x05
69#define MC_CG_SEQ_DRAMCONF_S1 0x06
70#define MC_CG_SEQ_YCLK_SUSPEND 0x04
71#define MC_CG_SEQ_YCLK_RESUME 0x0a
72
73
74#define SMC_RAM_END 0x40000
75
76#define SMC_CG_IND_START 0xc0030000
77#define SMC_CG_IND_END 0xc0040000
78
79#define VOLTAGE_SCALE 4
80#define VOLTAGE_VID_OFFSET_SCALE1 625
81#define VOLTAGE_VID_OFFSET_SCALE2 100
82
83#define VDDC_VDDCI_DELTA 200
84
85#define MEM_FREQ_LOW_LATENCY 25000
86#define MEM_FREQ_HIGH_LATENCY 80000
87
88#define MEM_LATENCY_HIGH 45
89#define MEM_LATENCY_LOW 35
90#define MEM_LATENCY_ERR 0xFFFF
91
92#define MC_SEQ_MISC0_GDDR5_SHIFT 28
93#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
94#define MC_SEQ_MISC0_GDDR5_VALUE 5
95
96
97#define PCIE_BUS_CLK 10000
98#define TCLK (PCIE_BUS_CLK / 10)
99
a23eefa2
RZ		 100/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
101enum DPM_EVENT_SRC {
102 DPM_EVENT_SRC_ANALOG = 0,
103 DPM_EVENT_SRC_EXTERNAL = 1,
104 DPM_EVENT_SRC_DIGITAL = 2,
105 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
106 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
107};
108
909a0631 109static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
a23eefa2 110
2cc0c0b5 111struct polaris10_power_state *cast_phw_polaris10_power_state(
a23eefa2
RZ		 112 struct pp_hw_power_state *hw_ps)
113{
2cc0c0b5 114 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 115 "Invalid Powerstate Type!",
116 return NULL);
117
2cc0c0b5 118 return (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 119}
120
2cc0c0b5 121const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
a23eefa2
RZ		 122 const struct pp_hw_power_state *hw_ps)
123{
2cc0c0b5 124 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
a23eefa2
RZ		 125 "Invalid Powerstate Type!",
126 return NULL);
127
2cc0c0b5 128 return (const struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 129}
130
2cc0c0b5 131static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 132{
133 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
134 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
135 ? true : false;
136}
137
138/**
139 * Find the MC microcode version and store it in the HwMgr struct
140 *
141 * @param hwmgr the address of the powerplay hardware manager.
142 * @return always 0
143 */
144int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
145{
146 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
147
148 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
149
150 return 0;
151}
152
153uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
154{
155 uint32_t speedCntl = 0;
156
157 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
158 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
159 ixPCIE_LC_SPEED_CNTL);
160 return((uint16_t)PHM_GET_FIELD(speedCntl,
161 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
162}
163
164int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
165{
166 uint32_t link_width;
167
168 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
169 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
170 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
171
172 PP_ASSERT_WITH_CODE((7 >= link_width),
173 "Invalid PCIe lane width!", return 0);
174
175 return decode_pcie_lane_width(link_width);
176}
177
e85c7d66 178/**
179* Enable voltage control
180*
181* @param pHwMgr the address of the powerplay hardware manager.
182* @return always PP_Result_OK
183*/
2cc0c0b5 184int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
e85c7d66 185{
186 PP_ASSERT_WITH_CODE(
187 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
188 "Failed to enable voltage DPM during DPM Start Function!",
189 return 1;
190 );
191
192 return 0;
193}
a23eefa2
RZ		 194
195/**
196* Checks if we want to support voltage control
197*
198* @param hwmgr the address of the powerplay hardware manager.
199*/
2cc0c0b5 200static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
a23eefa2 201{
2cc0c0b5
FC		 202 const struct polaris10_hwmgr *data =
203 (const struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 204
2cc0c0b5 205 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
a23eefa2
RZ		 206}
207
208/**
209* Enable voltage control
210*
211* @param hwmgr the address of the powerplay hardware manager.
212* @return always 0
213*/
2cc0c0b5 214static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 215{
216 /* enable voltage control */
217 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
218 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
219
220 return 0;
221}
222
223/**
224* Create Voltage Tables.
225*
226* @param hwmgr the address of the powerplay hardware manager.
227* @return always 0
228*/
2cc0c0b5 229static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
a23eefa2 230{
2cc0c0b5 231 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 232 struct phm_ppt_v1_information *table_info =
233 (struct phm_ppt_v1_information *)hwmgr->pptable;
234 int result;
235
2cc0c0b5 236 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 237 result = atomctrl_get_voltage_table_v3(hwmgr,
238 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
239 &(data->mvdd_voltage_table));
240 PP_ASSERT_WITH_CODE((0 == result),
241 "Failed to retrieve MVDD table.",
242 return result);
2cc0c0b5 243 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 244 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
245 table_info->vdd_dep_on_mclk);
246 PP_ASSERT_WITH_CODE((0 == result),
247 "Failed to retrieve SVI2 MVDD table from dependancy table.",
248 return result;);
249 }
250
2cc0c0b5 251 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 252 result = atomctrl_get_voltage_table_v3(hwmgr,
253 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
254 &(data->vddci_voltage_table));
255 PP_ASSERT_WITH_CODE((0 == result),
256 "Failed to retrieve VDDCI table.",
257 return result);
2cc0c0b5 258 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 259 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
260 table_info->vdd_dep_on_mclk);
261 PP_ASSERT_WITH_CODE((0 == result),
262 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
263 return result);
264 }
265
2cc0c0b5 266 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 267 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
268 table_info->vddc_lookup_table);
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve SVI2 VDDC table from lookup table.",
271 return result);
272 }
273
274 PP_ASSERT_WITH_CODE(
275 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
276 "Too many voltage values for VDDC. Trimming to fit state table.",
277 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
278 &(data->vddc_voltage_table)));
279
280 PP_ASSERT_WITH_CODE(
281 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
282 "Too many voltage values for VDDCI. Trimming to fit state table.",
283 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
284 &(data->vddci_voltage_table)));
285
286 PP_ASSERT_WITH_CODE(
287 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
288 "Too many voltage values for MVDD. Trimming to fit state table.",
289 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
290 &(data->mvdd_voltage_table)));
291
292 return 0;
293}
294
295/**
296* Programs static screed detection parameters
297*
298* @param hwmgr the address of the powerplay hardware manager.
299* @return always 0
300*/
2cc0c0b5 301static int polaris10_program_static_screen_threshold_parameters(
a23eefa2
RZ		 302 struct pp_hwmgr *hwmgr)
303{
2cc0c0b5 304 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 305
306 /* Set static screen threshold unit */
307 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
308 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
309 data->static_screen_threshold_unit);
310 /* Set static screen threshold */
311 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
312 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
313 data->static_screen_threshold);
314
315 return 0;
316}
317
318/**
319* Setup display gap for glitch free memory clock switching.
320*
321* @param hwmgr the address of the powerplay hardware manager.
322* @return always 0
323*/
2cc0c0b5 324static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 325{
326 uint32_t display_gap =
327 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
328 ixCG_DISPLAY_GAP_CNTL);
329
330 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
331 DISP_GAP, DISPLAY_GAP_IGNORE);
332
333 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
334 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
335
336 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
337 ixCG_DISPLAY_GAP_CNTL, display_gap);
338
339 return 0;
340}
341
342/**
343* Programs activity state transition voting clients
344*
345* @param hwmgr the address of the powerplay hardware manager.
346* @return always 0
347*/
2cc0c0b5 348static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
a23eefa2 349{
2cc0c0b5 350 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 351
352 /* Clear reset for voting clients before enabling DPM */
353 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
354 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
355 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
356 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
357
358 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
359 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
360 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
361 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
362 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
363 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
364 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
365 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
366 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
367 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
368 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
369 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
370 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
371 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
374
375 return 0;
376}
377
c27371b8
EH		 378static int polaris10_clear_voting_clients(struct pp_hwmgr *hwmgr)
379{
380 /* Reset voting clients before disabling DPM */
381 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
382 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
383 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
384 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
385
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_0, 0);
388 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
389 ixCG_FREQ_TRAN_VOTING_1, 0);
390 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
391 ixCG_FREQ_TRAN_VOTING_2, 0);
392 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
393 ixCG_FREQ_TRAN_VOTING_3, 0);
394 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
395 ixCG_FREQ_TRAN_VOTING_4, 0);
396 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
397 ixCG_FREQ_TRAN_VOTING_5, 0);
398 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
399 ixCG_FREQ_TRAN_VOTING_6, 0);
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
401 ixCG_FREQ_TRAN_VOTING_7, 0);
402
403 return 0;
404}
405
a23eefa2
RZ		 406/**
407* Get the location of various tables inside the FW image.
408*
409* @param hwmgr the address of the powerplay hardware manager.
410* @return always 0
411*/
2cc0c0b5 412static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
a23eefa2 413{
2cc0c0b5
FC		 414 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
415 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
a23eefa2
RZ		 416 uint32_t tmp;
417 int result;
418 bool error = false;
419
2cc0c0b5 420 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 421 SMU7_FIRMWARE_HEADER_LOCATION +
422 offsetof(SMU74_Firmware_Header, DpmTable),
423 &tmp, data->sram_end);
424
425 if (0 == result)
426 data->dpm_table_start = tmp;
427
428 error |= (0 != result);
429
2cc0c0b5 430 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 431 SMU7_FIRMWARE_HEADER_LOCATION +
432 offsetof(SMU74_Firmware_Header, SoftRegisters),
433 &tmp, data->sram_end);
434
435 if (!result) {
436 data->soft_regs_start = tmp;
437 smu_data->soft_regs_start = tmp;
438 }
439
440 error |= (0 != result);
441
2cc0c0b5 442 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 443 SMU7_FIRMWARE_HEADER_LOCATION +
444 offsetof(SMU74_Firmware_Header, mcRegisterTable),
445 &tmp, data->sram_end);
446
447 if (!result)
448 data->mc_reg_table_start = tmp;
449
2cc0c0b5 450 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 451 SMU7_FIRMWARE_HEADER_LOCATION +
452 offsetof(SMU74_Firmware_Header, FanTable),
453 &tmp, data->sram_end);
454
455 if (!result)
456 data->fan_table_start = tmp;
457
458 error |= (0 != result);
459
2cc0c0b5 460 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 461 SMU7_FIRMWARE_HEADER_LOCATION +
462 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
463 &tmp, data->sram_end);
464
465 if (!result)
466 data->arb_table_start = tmp;
467
468 error |= (0 != result);
469
2cc0c0b5 470 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 471 SMU7_FIRMWARE_HEADER_LOCATION +
472 offsetof(SMU74_Firmware_Header, Version),
473 &tmp, data->sram_end);
474
475 if (!result)
476 hwmgr->microcode_version_info.SMC = tmp;
477
478 error |= (0 != result);
479
480 return error ? -1 : 0;
481}
482
483/* Copy one arb setting to another and then switch the active set.
484 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
485 */
2cc0c0b5 486static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 487 uint32_t arb_src, uint32_t arb_dest)
488{
489 uint32_t mc_arb_dram_timing;
490 uint32_t mc_arb_dram_timing2;
491 uint32_t burst_time;
492 uint32_t mc_cg_config;
493
494 switch (arb_src) {
495 case MC_CG_ARB_FREQ_F0:
496 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
497 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
498 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
499 break;
500 case MC_CG_ARB_FREQ_F1:
501 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
502 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
503 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
504 break;
505 default:
506 return -EINVAL;
507 }
508
509 switch (arb_dest) {
510 case MC_CG_ARB_FREQ_F0:
511 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
512 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
513 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
514 break;
515 case MC_CG_ARB_FREQ_F1:
516 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
517 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
518 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
519 break;
520 default:
521 return -EINVAL;
522 }
523
524 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
525 mc_cg_config |= 0x0000000F;
526 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
527 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
528
529 return 0;
530}
531
c27371b8
EH		 532static int polaris10_reset_to_default(struct pp_hwmgr *hwmgr)
533{
534 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
535}
536
a23eefa2
RZ		 537/**
538* Initial switch from ARB F0->F1
539*
540* @param hwmgr the address of the powerplay hardware manager.
541* @return always 0
542* This function is to be called from the SetPowerState table.
543*/
2cc0c0b5 544static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
a23eefa2 545{
2cc0c0b5 546 return polaris10_copy_and_switch_arb_sets(hwmgr,
a23eefa2
RZ		 547 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
548}
549
c27371b8
EH		 550static int polaris10_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
551{
552 uint32_t tmp;
553
554 tmp = (cgs_read_ind_register(hwmgr->device,
555 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
556 0x0000ff00) >> 8;
557
558 if (tmp == MC_CG_ARB_FREQ_F0)
559 return 0;
560
561 return polaris10_copy_and_switch_arb_sets(hwmgr,
562 tmp, MC_CG_ARB_FREQ_F0);
563}
564
2cc0c0b5 565static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
a23eefa2 566{
2cc0c0b5 567 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 568 struct phm_ppt_v1_information *table_info =
569 (struct phm_ppt_v1_information *)(hwmgr->pptable);
570 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
571 uint32_t i, max_entry;
572
573 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
574 data->use_pcie_power_saving_levels), "No pcie performance levels!",
575 return -EINVAL);
576
577 if (data->use_pcie_performance_levels &&
578 !data->use_pcie_power_saving_levels) {
579 data->pcie_gen_power_saving = data->pcie_gen_performance;
580 data->pcie_lane_power_saving = data->pcie_lane_performance;
581 } else if (!data->use_pcie_performance_levels &&
582 data->use_pcie_power_saving_levels) {
583 data->pcie_gen_performance = data->pcie_gen_power_saving;
584 data->pcie_lane_performance = data->pcie_lane_power_saving;
585 }
586
587 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
588 SMU74_MAX_LEVELS_LINK,
589 MAX_REGULAR_DPM_NUMBER);
590
591 if (pcie_table != NULL) {
592 /* max_entry is used to make sure we reserve one PCIE level
593 * for boot level (fix for A+A PSPP issue).
594 * If PCIE table from PPTable have ULV entry + 8 entries,
595 * then ignore the last entry.*/
596 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
597 SMU74_MAX_LEVELS_LINK : pcie_table->count;
598 for (i = 1; i < max_entry; i++) {
599 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
600 get_pcie_gen_support(data->pcie_gen_cap,
601 pcie_table->entries[i].gen_speed),
602 get_pcie_lane_support(data->pcie_lane_cap,
603 pcie_table->entries[i].lane_width));
604 }
605 data->dpm_table.pcie_speed_table.count = max_entry - 1;
e85c7d66 606
607 /* Setup BIF_SCLK levels */
608 for (i = 0; i < max_entry; i++)
609 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
a23eefa2
RZ		 610 } else {
611 /* Hardcode Pcie Table */
612 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
613 get_pcie_gen_support(data->pcie_gen_cap,
614 PP_Min_PCIEGen),
615 get_pcie_lane_support(data->pcie_lane_cap,
616 PP_Max_PCIELane));
617 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
618 get_pcie_gen_support(data->pcie_gen_cap,
619 PP_Min_PCIEGen),
620 get_pcie_lane_support(data->pcie_lane_cap,
621 PP_Max_PCIELane));
622 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
623 get_pcie_gen_support(data->pcie_gen_cap,
624 PP_Max_PCIEGen),
625 get_pcie_lane_support(data->pcie_lane_cap,
626 PP_Max_PCIELane));
627 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
628 get_pcie_gen_support(data->pcie_gen_cap,
629 PP_Max_PCIEGen),
630 get_pcie_lane_support(data->pcie_lane_cap,
631 PP_Max_PCIELane));
632 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
633 get_pcie_gen_support(data->pcie_gen_cap,
634 PP_Max_PCIEGen),
635 get_pcie_lane_support(data->pcie_lane_cap,
636 PP_Max_PCIELane));
637 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
638 get_pcie_gen_support(data->pcie_gen_cap,
639 PP_Max_PCIEGen),
640 get_pcie_lane_support(data->pcie_lane_cap,
641 PP_Max_PCIELane));
642
643 data->dpm_table.pcie_speed_table.count = 6;
644 }
645 /* Populate last level for boot PCIE level, but do not increment count. */
646 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
647 data->dpm_table.pcie_speed_table.count,
648 get_pcie_gen_support(data->pcie_gen_cap,
649 PP_Min_PCIEGen),
650 get_pcie_lane_support(data->pcie_lane_cap,
651 PP_Max_PCIELane));
652
653 return 0;
654}
655
656/*
657 * This function is to initalize all DPM state tables
658 * for SMU7 based on the dependency table.
659 * Dynamic state patching function will then trim these
660 * state tables to the allowed range based
661 * on the power policy or external client requests,
662 * such as UVD request, etc.
663 */
2cc0c0b5 664int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
a23eefa2 665{
2cc0c0b5 666 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 667 struct phm_ppt_v1_information *table_info =
668 (struct phm_ppt_v1_information *)(hwmgr->pptable);
669 uint32_t i;
670
671 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
672 table_info->vdd_dep_on_sclk;
673 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
674 table_info->vdd_dep_on_mclk;
675
676 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
677 "SCLK dependency table is missing. This table is mandatory",
678 return -EINVAL);
679 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
680 "SCLK dependency table has to have is missing."
681 "This table is mandatory",
682 return -EINVAL);
683
684 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
685 "MCLK dependency table is missing. This table is mandatory",
686 return -EINVAL);
687 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
688 "MCLK dependency table has to have is missing."
689 "This table is mandatory",
690 return -EINVAL);
691
692 /* clear the state table to reset everything to default */
693 phm_reset_single_dpm_table(
694 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
695 phm_reset_single_dpm_table(
696 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
697
698
699 /* Initialize Sclk DPM table based on allow Sclk values */
700 data->dpm_table.sclk_table.count = 0;
701 for (i = 0; i < dep_sclk_table->count; i++) {
702 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
703 dep_sclk_table->entries[i].clk) {
704
705 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
706 dep_sclk_table->entries[i].clk;
707
708 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
709 (i == 0) ? true : false;
710 data->dpm_table.sclk_table.count++;
711 }
712 }
713
714 /* Initialize Mclk DPM table based on allow Mclk values */
715 data->dpm_table.mclk_table.count = 0;
716 for (i = 0; i < dep_mclk_table->count; i++) {
717 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
718 [data->dpm_table.mclk_table.count - 1].value !=
719 dep_mclk_table->entries[i].clk) {
720 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
721 dep_mclk_table->entries[i].clk;
722 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
723 (i == 0) ? true : false;
724 data->dpm_table.mclk_table.count++;
725 }
726 }
727
728 /* setup PCIE gen speed levels */
2cc0c0b5 729 polaris10_setup_default_pcie_table(hwmgr);
a23eefa2
RZ		 730
731 /* save a copy of the default DPM table */
732 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
2cc0c0b5 733 sizeof(struct polaris10_dpm_table));
a23eefa2
RZ		 734
735 return 0;
736}
737
738uint8_t convert_to_vid(uint16_t vddc)
739{
740 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
741}
742
743/**
744 * Mvdd table preparation for SMC.
745 *
746 * @param *hwmgr The address of the hardware manager.
747 * @param *table The SMC DPM table structure to be populated.
748 * @return 0
749 */
2cc0c0b5 750static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 751 SMU74_Discrete_DpmTable *table)
752{
2cc0c0b5 753 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 754 uint32_t count, level;
755
2cc0c0b5 756 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
a23eefa2
RZ		 757 count = data->mvdd_voltage_table.count;
758 if (count > SMU_MAX_SMIO_LEVELS)
759 count = SMU_MAX_SMIO_LEVELS;
760 for (level = 0; level < count; level++) {
761 table->SmioTable2.Pattern[level].Voltage =
762 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
763 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
764 table->SmioTable2.Pattern[level].Smio =
765 (uint8_t) level;
766 table->Smio[level] |=
767 data->mvdd_voltage_table.entries[level].smio_low;
768 }
095d28c6 769 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
a23eefa2
RZ		 770
771 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
772 }
773
774 return 0;
775}
776
2cc0c0b5 777static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 778 struct SMU74_Discrete_DpmTable *table)
779{
780 uint32_t count, level;
2cc0c0b5 781 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 782
783 count = data->vddci_voltage_table.count;
784
2cc0c0b5 785 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 786 if (count > SMU_MAX_SMIO_LEVELS)
787 count = SMU_MAX_SMIO_LEVELS;
788 for (level = 0; level < count; ++level) {
789 table->SmioTable1.Pattern[level].Voltage =
790 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
791 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
792
793 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
794 }
795 }
796
797 table->SmioMask1 = data->vddci_voltage_table.mask_low;
798
799 return 0;
800}
801
802/**
803* Preparation of vddc and vddgfx CAC tables for SMC.
804*
805* @param hwmgr the address of the hardware manager
806* @param table the SMC DPM table structure to be populated
807* @return always 0
808*/
2cc0c0b5 809static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 810 struct SMU74_Discrete_DpmTable *table)
811{
812 uint32_t count;
813 uint8_t index;
2cc0c0b5 814 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 815 struct phm_ppt_v1_information *table_info =
816 (struct phm_ppt_v1_information *)(hwmgr->pptable);
817 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
818 table_info->vddc_lookup_table;
819 /* tables is already swapped, so in order to use the value from it,
820 * we need to swap it back.
821 * We are populating vddc CAC data to BapmVddc table
822 * in split and merged mode
823 */
824 for (count = 0; count < lookup_table->count; count++) {
825 index = phm_get_voltage_index(lookup_table,
826 data->vddc_voltage_table.entries[count].value);
827 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
828 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
829 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
830 }
831
832 return 0;
833}
834
835/**
836* Preparation of voltage tables for SMC.
837*
838* @param hwmgr the address of the hardware manager
839* @param table the SMC DPM table structure to be populated
840* @return always 0
841*/
842
2cc0c0b5 843int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 844 struct SMU74_Discrete_DpmTable *table)
845{
2cc0c0b5
FC		 846 polaris10_populate_smc_vddci_table(hwmgr, table);
847 polaris10_populate_smc_mvdd_table(hwmgr, table);
848 polaris10_populate_cac_table(hwmgr, table);
a23eefa2
RZ		 849
850 return 0;
851}
852
2cc0c0b5 853static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 854 struct SMU74_Discrete_Ulv *state)
855{
2cc0c0b5 856 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 857 struct phm_ppt_v1_information *table_info =
858 (struct phm_ppt_v1_information *)(hwmgr->pptable);
859
860 state->CcPwrDynRm = 0;
861 state->CcPwrDynRm1 = 0;
862
863 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
864 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
865 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
866
867 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
868
869 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
870 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
871 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
872
873 return 0;
874}
875
2cc0c0b5 876static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 877 struct SMU74_Discrete_DpmTable *table)
878{
2cc0c0b5 879 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
a23eefa2
RZ		 880}
881
2cc0c0b5 882static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 883 struct SMU74_Discrete_DpmTable *table)
884{
2cc0c0b5
FC		 885 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
886 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 887 int i;
888
889 /* Index (dpm_table->pcie_speed_table.count)
890 * is reserved for PCIE boot level. */
891 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
892 table->LinkLevel[i].PcieGenSpeed =
893 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
894 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
895 dpm_table->pcie_speed_table.dpm_levels[i].param1);
896 table->LinkLevel[i].EnabledForActivity = 1;
897 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
898 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
899 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
900 }
901
902 data->smc_state_table.LinkLevelCount =
903 (uint8_t)dpm_table->pcie_speed_table.count;
904 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
905 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
906
907 return 0;
908}
909
2cc0c0b5 910static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 911{
912 uint32_t reference_clock, tmp;
913 struct cgs_display_info info = {0};
914 struct cgs_mode_info mode_info;
915
916 info.mode_info = &mode_info;
917
918 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
919
920 if (tmp)
921 return TCLK;
922
923 cgs_get_active_displays_info(hwmgr->device, &info);
924 reference_clock = mode_info.ref_clock;
925
926 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
927
928 if (0 != tmp)
929 return reference_clock / 4;
930
931 return reference_clock;
932}
933
934/**
935* Calculates the SCLK dividers using the provided engine clock
936*
937* @param hwmgr the address of the hardware manager
938* @param clock the engine clock to use to populate the structure
939* @param sclk the SMC SCLK structure to be populated
940*/
2cc0c0b5 941static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 942 uint32_t clock, SMU_SclkSetting *sclk_setting)
943{
2cc0c0b5 944 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 945 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
946 struct pp_atomctrl_clock_dividers_ai dividers;
947
948 uint32_t ref_clock;
949 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
950 uint8_t i;
951 int result;
952 uint64_t temp;
953
954 sclk_setting->SclkFrequency = clock;
955 /* get the engine clock dividers for this clock value */
956 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
957 if (result == 0) {
958 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
959 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
960 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
961 sclk_setting->PllRange = dividers.ucSclkPllRange;
e85c7d66 962 sclk_setting->Sclk_slew_rate = 0x400;
963 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
964 sclk_setting->Pcc_down_slew_rate = 0xffff;
a23eefa2
RZ		 965 sclk_setting->SSc_En = dividers.ucSscEnable;
966 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
967 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
e85c7d66 968 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
a23eefa2
RZ		 969 return result;
970 }
971
2cc0c0b5 972 ref_clock = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 973
974 for (i = 0; i < NUM_SCLK_RANGE; i++) {
975 if (clock > data->range_table[i].trans_lower_frequency
976 && clock <= data->range_table[i].trans_upper_frequency) {
977 sclk_setting->PllRange = i;
978 break;
979 }
980 }
981
982 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
983 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
984 temp <<= 0x10;
ae17c999
SG		 985 do_div(temp, ref_clock);
986 sclk_setting->Fcw_frac = temp & 0xffff;
a23eefa2
RZ		 987
988 pcc_target_percent = 10; /* Hardcode 10% for now. */
989 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
990 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
991
992 ss_target_percent = 2; /* Hardcode 2% for now. */
993 sclk_setting->SSc_En = 0;
994 if (ss_target_percent) {
995 sclk_setting->SSc_En = 1;
996 ss_target_freq = clock - (clock * ss_target_percent / 100);
997 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
998 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
999 temp <<= 0x10;
ae17c999
SG		 1000 do_div(temp, ref_clock);
1001 sclk_setting->Fcw1_frac = temp & 0xffff;
a23eefa2
RZ		 1002 }
1003
1004 return 0;
1005}
1006
2cc0c0b5 1007static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1008 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1009 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1010{
1011 uint32_t i;
1012 uint16_t vddci;
2cc0c0b5 1013 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1014
1015 *voltage = *mvdd = 0;
1016
1017 /* clock - voltage dependency table is empty table */
1018 if (dep_table->count == 0)
1019 return -EINVAL;
1020
1021 for (i = 0; i < dep_table->count; i++) {
1022 /* find first sclk bigger than request */
1023 if (dep_table->entries[i].clk >= clock) {
1024 *voltage |= (dep_table->entries[i].vddc *
1025 VOLTAGE_SCALE) << VDDC_SHIFT;
2cc0c0b5 1026 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 1027 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1028 VOLTAGE_SCALE) << VDDCI_SHIFT;
1029 else if (dep_table->entries[i].vddci)
1030 *voltage |= (dep_table->entries[i].vddci *
1031 VOLTAGE_SCALE) << VDDCI_SHIFT;
1032 else {
1033 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1034 (dep_table->entries[i].vddc -
1035 (uint16_t)data->vddc_vddci_delta));
3ff21127 1036 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
a23eefa2
RZ		 1037 }
1038
2cc0c0b5 1039 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1040 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1041 VOLTAGE_SCALE;
1042 else if (dep_table->entries[i].mvdd)
1043 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1044 VOLTAGE_SCALE;
1045
1046 *voltage |= 1 << PHASES_SHIFT;
1047 return 0;
1048 }
1049 }
1050
1051 /* sclk is bigger than max sclk in the dependence table */
1052 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1053
2cc0c0b5 1054 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
a23eefa2
RZ		 1055 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1056 VOLTAGE_SCALE) << VDDCI_SHIFT;
1057 else if (dep_table->entries[i-1].vddci) {
1058 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1059 (dep_table->entries[i].vddc -
1060 (uint16_t)data->vddc_vddci_delta));
1061 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1062 }
1063
2cc0c0b5 1064 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
a23eefa2
RZ		 1065 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1066 else if (dep_table->entries[i].mvdd)
1067 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1068
1069 return 0;
1070}
1071
909a0631
NW		 1072static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1073{ {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1074 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1075 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1076 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1077 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1078 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1079 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1080 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
a23eefa2 1081
2cc0c0b5 1082static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 1083{
1084 uint32_t i, ref_clk;
2cc0c0b5 1085 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1086 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1087 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1088
2cc0c0b5 1089 ref_clk = polaris10_get_xclk(hwmgr);
a23eefa2
RZ		 1090
1091 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1092 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1093 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1094 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1095 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1096
1097 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1098 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1099
1100 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1101 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1102 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1103 }
1104 return;
1105 }
1106
1107 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1108
1109 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1110 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1111
1112 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1113 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1114 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1115
1116 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1117 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1118
1119 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1120 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1121 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1122 }
1123}
1124
1125/**
1126* Populates single SMC SCLK structure using the provided engine clock
1127*
1128* @param hwmgr the address of the hardware manager
1129* @param clock the engine clock to use to populate the structure
1130* @param sclk the SMC SCLK structure to be populated
1131*/
1132
2cc0c0b5 1133static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1134 uint32_t clock, uint16_t sclk_al_threshold,
1135 struct SMU74_Discrete_GraphicsLevel *level)
1136{
1137 int result, i, temp;
1138 /* PP_Clocks minClocks; */
1139 uint32_t mvdd;
2cc0c0b5 1140 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1141 struct phm_ppt_v1_information *table_info =
1142 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1143 SMU_SclkSetting curr_sclk_setting = { 0 };
1144
2cc0c0b5 1145 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
a23eefa2
RZ		 1146
1147 /* populate graphics levels */
2cc0c0b5 1148 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1149 table_info->vdd_dep_on_sclk, clock,
1150 &level->MinVoltage, &mvdd);
1151
1152 PP_ASSERT_WITH_CODE((0 == result),
1153 "can not find VDDC voltage value for "
1154 "VDDC engine clock dependency table",
1155 return result);
1156 level->ActivityLevel = sclk_al_threshold;
1157
1158 level->CcPwrDynRm = 0;
1159 level->CcPwrDynRm1 = 0;
1160 level->EnabledForActivity = 0;
1161 level->EnabledForThrottle = 1;
1162 level->UpHyst = 10;
1163 level->DownHyst = 0;
1164 level->VoltageDownHyst = 0;
1165 level->PowerThrottle = 0;
1166
1167 /*
1168 * TODO: get minimum clocks from dal configaration
1169 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1170 */
1171 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1172
1173 /* get level->DeepSleepDivId
1174 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1175 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1176 */
859b8b6a 1177 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
2cc0c0b5 1178 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
354ef928 1179 temp = clock >> i;
a23eefa2 1180
859b8b6a 1181 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
a23eefa2
RZ		 1182 break;
1183 }
1184
1185 level->DeepSleepDivId = i;
1186
1187 /* Default to slow, highest DPM level will be
1188 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1189 */
1190 if (data->update_up_hyst)
1191 level->UpHyst = (uint8_t)data->up_hyst;
1192 if (data->update_down_hyst)
1193 level->DownHyst = (uint8_t)data->down_hyst;
1194
1195 level->SclkSetting = curr_sclk_setting;
1196
1197 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1198 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1199 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1200 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1201 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1202 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1203 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1204 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
e85c7d66 1205 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1206 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1207 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1208 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1209 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
e85c7d66 1210 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
a23eefa2
RZ		 1211 return 0;
1212}
1213
1214/**
1215* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1216*
1217* @param hwmgr the address of the hardware manager
1218*/
2cc0c0b5 1219static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1220{
2cc0c0b5
FC		 1221 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1222 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1223 struct phm_ppt_v1_information *table_info =
1224 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1225 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1226 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1227 int result = 0;
1228 uint32_t array = data->dpm_table_start +
1229 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1230 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1231 SMU74_MAX_LEVELS_GRAPHICS;
1232 struct SMU74_Discrete_GraphicsLevel *levels =
1233 data->smc_state_table.GraphicsLevel;
1234 uint32_t i, max_entry;
1235 uint8_t hightest_pcie_level_enabled = 0,
1236 lowest_pcie_level_enabled = 0,
1237 mid_pcie_level_enabled = 0,
1238 count = 0;
1239
2cc0c0b5 1240 polaris10_get_sclk_range_table(hwmgr);
a23eefa2
RZ		 1241
1242 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1243
2cc0c0b5 1244 result = polaris10_populate_single_graphic_level(hwmgr,
a23eefa2
RZ		 1245 dpm_table->sclk_table.dpm_levels[i].value,
1246 (uint16_t)data->activity_target[i],
1247 &(data->smc_state_table.GraphicsLevel[i]));
1248 if (result)
1249 return result;
1250
1251 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1252 if (i > 1)
1253 levels[i].DeepSleepDivId = 0;
1254 }
5de95e55
RZ		 1255 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1256 PHM_PlatformCaps_SPLLShutdownSupport))
1257 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
a23eefa2
RZ		 1258
1259 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1260 data->smc_state_table.GraphicsDpmLevelCount =
1261 (uint8_t)dpm_table->sclk_table.count;
1262 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1263 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1264
1265
1266 if (pcie_table != NULL) {
1267 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1268 "There must be 1 or more PCIE levels defined in PPTable.",
1269 return -EINVAL);
1270 max_entry = pcie_entry_cnt - 1;
1271 for (i = 0; i < dpm_table->sclk_table.count; i++)
1272 levels[i].pcieDpmLevel =
1273 (uint8_t) ((i < max_entry) ? i : max_entry);
1274 } else {
1275 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1276 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1277 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1278 hightest_pcie_level_enabled++;
1279
1280 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1281 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1282 (1 << lowest_pcie_level_enabled)) == 0))
1283 lowest_pcie_level_enabled++;
1284
1285 while ((count < hightest_pcie_level_enabled) &&
1286 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1287 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1288 count++;
1289
1290 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1291 hightest_pcie_level_enabled ?
1292 (lowest_pcie_level_enabled + 1 + count) :
1293 hightest_pcie_level_enabled;
1294
1295 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1296 for (i = 2; i < dpm_table->sclk_table.count; i++)
1297 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1298
1299 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1300 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1301
1302 /* set pcieDpmLevel to mid_pcie_level_enabled */
1303 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1304 }
1305 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1306 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1307 (uint32_t)array_size, data->sram_end);
1308
1309 return result;
1310}
1311
2cc0c0b5 1312static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1313 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1314{
2cc0c0b5 1315 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1316 struct phm_ppt_v1_information *table_info =
1317 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1318 int result = 0;
1319 struct cgs_display_info info = {0, 0, NULL};
1320
1321 cgs_get_active_displays_info(hwmgr->device, &info);
1322
1323 if (table_info->vdd_dep_on_mclk) {
2cc0c0b5 1324 result = polaris10_get_dependency_volt_by_clk(hwmgr,
a23eefa2
RZ		 1325 table_info->vdd_dep_on_mclk, clock,
1326 &mem_level->MinVoltage, &mem_level->MinMvdd);
1327 PP_ASSERT_WITH_CODE((0 == result),
1328 "can not find MinVddc voltage value from memory "
1329 "VDDC voltage dependency table", return result);
1330 }
1331
1332 mem_level->MclkFrequency = clock;
a23eefa2
RZ		 1333 mem_level->EnabledForThrottle = 1;
1334 mem_level->EnabledForActivity = 0;
1335 mem_level->UpHyst = 0;
1336 mem_level->DownHyst = 100;
1337 mem_level->VoltageDownHyst = 0;
1338 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1339 mem_level->StutterEnable = false;
a23eefa2
RZ		 1340 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1341
1342 data->display_timing.num_existing_displays = info.display_count;
1343
1344 if ((data->mclk_stutter_mode_threshold) &&
1345 (clock <= data->mclk_stutter_mode_threshold) &&
1346 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1347 STUTTER_ENABLE) & 0x1))
1348 mem_level->StutterEnable = true;
1349
1350 if (!result) {
1351 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1352 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1353 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1354 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1355 }
1356 return result;
1357}
1358
1359/**
1360* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1361*
1362* @param hwmgr the address of the hardware manager
1363*/
2cc0c0b5 1364static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
a23eefa2 1365{
2cc0c0b5
FC		 1366 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1367 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2
RZ		 1368 int result;
1369 /* populate MCLK dpm table to SMU7 */
1370 uint32_t array = data->dpm_table_start +
1371 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1372 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1373 SMU74_MAX_LEVELS_MEMORY;
1374 struct SMU74_Discrete_MemoryLevel *levels =
1375 data->smc_state_table.MemoryLevel;
1376 uint32_t i;
1377
1378 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1379 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1380 "can not populate memory level as memory clock is zero",
1381 return -EINVAL);
2cc0c0b5 1382 result = polaris10_populate_single_memory_level(hwmgr,
a23eefa2
RZ		 1383 dpm_table->mclk_table.dpm_levels[i].value,
1384 &levels[i]);
b4c6f99e
RZ		 1385 if (i == dpm_table->mclk_table.count - 1) {
1386 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1387 levels[i].EnabledForActivity = 1;
1388 }
a23eefa2
RZ		 1389 if (result)
1390 return result;
1391 }
1392
880a076c 1393 /* In order to prevent MC activity from stutter mode to push DPM up,
a23eefa2 1394 * the UVD change complements this by putting the MCLK in
880a076c 1395 * a higher state by default such that we are not affected by
a23eefa2
RZ		 1396 * up threshold or and MCLK DPM latency.
1397 */
9a3c1b34 1398 levels[0].ActivityLevel = 0x1f;
a23eefa2
RZ		 1399 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1400
1401 data->smc_state_table.MemoryDpmLevelCount =
1402 (uint8_t)dpm_table->mclk_table.count;
1403 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1404 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
a23eefa2
RZ		 1405
1406 /* level count will send to smc once at init smc table and never change */
2cc0c0b5 1407 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
a23eefa2
RZ		 1408 (uint32_t)array_size, data->sram_end);
1409
1410 return result;
1411}
1412
1413/**
1414* Populates the SMC MVDD structure using the provided memory clock.
1415*
1416* @param hwmgr the address of the hardware manager
1417* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1418* @param voltage the SMC VOLTAGE structure to be populated
1419*/
2cc0c0b5 1420int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1421 uint32_t mclk, SMIO_Pattern *smio_pat)
1422{
2cc0c0b5 1423 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1424 struct phm_ppt_v1_information *table_info =
1425 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1426 uint32_t i = 0;
1427
2cc0c0b5 1428 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
a23eefa2
RZ		 1429 /* find mvdd value which clock is more than request */
1430 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1431 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1432 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1433 break;
1434 }
1435 }
1436 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1437 "MVDD Voltage is outside the supported range.",
1438 return -EINVAL);
1439 } else
1440 return -EINVAL;
1441
1442 return 0;
1443}
1444
2cc0c0b5 1445static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1446 SMU74_Discrete_DpmTable *table)
1447{
1448 int result = 0;
1449 uint32_t sclk_frequency;
2cc0c0b5 1450 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1451 struct phm_ppt_v1_information *table_info =
1452 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1453 SMIO_Pattern vol_level;
1454 uint32_t mvdd;
1455 uint16_t us_mvdd;
1456
1457 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1458
0636e0d6
RZ		 1459
1460 /* Get MinVoltage and Frequency from DPM0,
1461 * already converted to SMC_UL */
c0bcc4ec 1462 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
0636e0d6
RZ		 1463 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1464 table_info->vdd_dep_on_sclk,
1465 sclk_frequency,
1466 &table->ACPILevel.MinVoltage, &mvdd);
1467 PP_ASSERT_WITH_CODE((0 == result),
1468 "Cannot find ACPI VDDC voltage value "
1469 "in Clock Dependency Table",
1470 );
1471
a23eefa2 1472
2cc0c0b5 1473 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
a23eefa2
RZ		 1474 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1475
1476 table->ACPILevel.DeepSleepDivId = 0;
1477 table->ACPILevel.CcPwrDynRm = 0;
1478 table->ACPILevel.CcPwrDynRm1 = 0;
1479
1480 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1481 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1482 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1483 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1484
1485 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1486 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1487 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1488 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
e85c7d66 1489 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1490 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1491 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
a23eefa2
RZ		 1492 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1493 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
e85c7d66 1494 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
a23eefa2 1495
0636e0d6
RZ		 1496
1497 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
c0bcc4ec 1498 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
0636e0d6
RZ		 1499 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1500 table_info->vdd_dep_on_mclk,
1501 table->MemoryACPILevel.MclkFrequency,
1502 &table->MemoryACPILevel.MinVoltage, &mvdd);
1503 PP_ASSERT_WITH_CODE((0 == result),
1504 "Cannot find ACPI VDDCI voltage value "
1505 "in Clock Dependency Table",
1506 );
a23eefa2
RZ		 1507
1508 us_mvdd = 0;
2cc0c0b5 1509 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
a23eefa2
RZ		 1510 (data->mclk_dpm_key_disabled))
1511 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1512 else {
2cc0c0b5 1513 if (!polaris10_populate_mvdd_value(hwmgr,
a23eefa2
RZ		 1514 data->dpm_table.mclk_table.dpm_levels[0].value,
1515 &vol_level))
1516 us_mvdd = vol_level.Voltage;
1517 }
1518
2cc0c0b5 1519 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
a23eefa2
RZ		 1520 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1521 else
1522 table->MemoryACPILevel.MinMvdd = 0;
1523
1524 table->MemoryACPILevel.StutterEnable = false;
1525
1526 table->MemoryACPILevel.EnabledForThrottle = 0;
1527 table->MemoryACPILevel.EnabledForActivity = 0;
1528 table->MemoryACPILevel.UpHyst = 0;
1529 table->MemoryACPILevel.DownHyst = 100;
1530 table->MemoryACPILevel.VoltageDownHyst = 0;
1531 table->MemoryACPILevel.ActivityLevel =
1532 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1533
1534 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1535 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1536
1537 return result;
1538}
1539
2cc0c0b5 1540static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1541 SMU74_Discrete_DpmTable *table)
1542{
1543 int result = -EINVAL;
1544 uint8_t count;
1545 struct pp_atomctrl_clock_dividers_vi dividers;
1546 struct phm_ppt_v1_information *table_info =
1547 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1548 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1549 table_info->mm_dep_table;
2cc0c0b5 1550 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
0636e0d6 1551 uint32_t vddci;
a23eefa2
RZ		 1552
1553 table->VceLevelCount = (uint8_t)(mm_table->count);
1554 table->VceBootLevel = 0;
1555
1556 for (count = 0; count < table->VceLevelCount; count++) {
1557 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
681ed01c 1558 table->VceLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1559 table->VceLevel[count].MinVoltage |=
1560 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
0636e0d6
RZ		 1561
1562 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1563 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1564 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1565 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1566 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1567 else
1568 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1569
1570
a23eefa2 1571 table->VceLevel[count].MinVoltage |=
0636e0d6 1572 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
a23eefa2
RZ		 1573 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1574
1575 /*retrieve divider value for VBIOS */
1576 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1577 table->VceLevel[count].Frequency, &dividers);
1578 PP_ASSERT_WITH_CODE((0 == result),
1579 "can not find divide id for VCE engine clock",
1580 return result);
1581
1582 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1583
1584 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1585 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1586 }
1587 return result;
1588}
1589
2cc0c0b5 1590static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1591 SMU74_Discrete_DpmTable *table)
1592{
1593 int result = -EINVAL;
1594 uint8_t count;
1595 struct pp_atomctrl_clock_dividers_vi dividers;
1596 struct phm_ppt_v1_information *table_info =
1597 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1598 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1599 table_info->mm_dep_table;
2cc0c0b5 1600 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
0636e0d6 1601 uint32_t vddci;
a23eefa2
RZ		 1602
1603 table->SamuBootLevel = 0;
1604 table->SamuLevelCount = (uint8_t)(mm_table->count);
1605
1606 for (count = 0; count < table->SamuLevelCount; count++) {
1607 /* not sure whether we need evclk or not */
681ed01c 1608 table->SamuLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1609 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1610 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1611 VOLTAGE_SCALE) << VDDC_SHIFT;
0636e0d6
RZ		 1612
1613 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1614 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1615 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1616 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1617 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1618 else
1619 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1620
1621 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
a23eefa2
RZ		 1622 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1623
1624 /* retrieve divider value for VBIOS */
1625 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1626 table->SamuLevel[count].Frequency, &dividers);
1627 PP_ASSERT_WITH_CODE((0 == result),
1628 "can not find divide id for samu clock", return result);
1629
1630 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1631
1632 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1633 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1634 }
1635 return result;
1636}
1637
2cc0c0b5 1638static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1639 int32_t eng_clock, int32_t mem_clock,
1640 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1641{
1642 uint32_t dram_timing;
1643 uint32_t dram_timing2;
1644 uint32_t burst_time;
1645 int result;
1646
1647 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1648 eng_clock, mem_clock);
1649 PP_ASSERT_WITH_CODE(result == 0,
1650 "Error calling VBIOS to set DRAM_TIMING.", return result);
1651
1652 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1653 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1654 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1655
1656
1657 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1658 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1659 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1660
1661 return 0;
1662}
1663
2cc0c0b5 1664static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 1665{
2cc0c0b5 1666 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1667 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1668 uint32_t i, j;
1669 int result = 0;
1670
1671 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1672 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2cc0c0b5 1673 result = polaris10_populate_memory_timing_parameters(hwmgr,
a23eefa2
RZ		 1674 data->dpm_table.sclk_table.dpm_levels[i].value,
1675 data->dpm_table.mclk_table.dpm_levels[j].value,
1676 &arb_regs.entries[i][j]);
1677 if (result == 0)
1678 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1679 if (result != 0)
1680 return result;
1681 }
1682 }
1683
2cc0c0b5 1684 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 1685 hwmgr->smumgr,
1686 data->arb_table_start,
1687 (uint8_t *)&arb_regs,
1688 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1689 data->sram_end);
1690 return result;
1691}
1692
2cc0c0b5 1693static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1694 struct SMU74_Discrete_DpmTable *table)
1695{
1696 int result = -EINVAL;
1697 uint8_t count;
1698 struct pp_atomctrl_clock_dividers_vi dividers;
1699 struct phm_ppt_v1_information *table_info =
1700 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1701 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1702 table_info->mm_dep_table;
2cc0c0b5 1703 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
0636e0d6 1704 uint32_t vddci;
a23eefa2
RZ		 1705
1706 table->UvdLevelCount = (uint8_t)(mm_table->count);
1707 table->UvdBootLevel = 0;
1708
1709 for (count = 0; count < table->UvdLevelCount; count++) {
681ed01c 1710 table->UvdLevel[count].MinVoltage = 0;
a23eefa2
RZ		 1711 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1712 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1713 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1714 VOLTAGE_SCALE) << VDDC_SHIFT;
0636e0d6
RZ		 1715
1716 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1717 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1718 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1719 else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1720 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1721 else
1722 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1723
1724 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
a23eefa2
RZ		 1725 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1726
1727 /* retrieve divider value for VBIOS */
1728 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1729 table->UvdLevel[count].VclkFrequency, &dividers);
1730 PP_ASSERT_WITH_CODE((0 == result),
1731 "can not find divide id for Vclk clock", return result);
1732
1733 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1734
1735 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1736 table->UvdLevel[count].DclkFrequency, &dividers);
1737 PP_ASSERT_WITH_CODE((0 == result),
1738 "can not find divide id for Dclk clock", return result);
1739
1740 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1741
1742 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1743 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1744 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
a23eefa2 1745 }
0636e0d6 1746
a23eefa2
RZ		 1747 return result;
1748}
1749
2cc0c0b5 1750static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1751 struct SMU74_Discrete_DpmTable *table)
1752{
1753 int result = 0;
2cc0c0b5 1754 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1755
1756 table->GraphicsBootLevel = 0;
1757 table->MemoryBootLevel = 0;
1758
1759 /* find boot level from dpm table */
1760 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1761 data->vbios_boot_state.sclk_bootup_value,
1762 (uint32_t *)&(table->GraphicsBootLevel));
1763
1764 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1765 data->vbios_boot_state.mclk_bootup_value,
1766 (uint32_t *)&(table->MemoryBootLevel));
1767
1768 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1769 VOLTAGE_SCALE;
1770 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1771 VOLTAGE_SCALE;
1772 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1773 VOLTAGE_SCALE;
1774
1775 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1776 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1777 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1778
1779 return 0;
1780}
1781
1782
2cc0c0b5 1783static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
a23eefa2 1784{
2cc0c0b5 1785 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1786 struct phm_ppt_v1_information *table_info =
1787 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1788 uint8_t count, level;
1789
1790 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1791
1792 for (level = 0; level < count; level++) {
1793 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1794 data->vbios_boot_state.sclk_bootup_value) {
1795 data->smc_state_table.GraphicsBootLevel = level;
1796 break;
1797 }
1798 }
1799
1800 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1801 for (level = 0; level < count; level++) {
1802 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1803 data->vbios_boot_state.mclk_bootup_value) {
1804 data->smc_state_table.MemoryBootLevel = level;
1805 break;
1806 }
1807 }
1808
1809 return 0;
1810}
1811
2cc0c0b5 1812static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
a23eefa2 1813{
270d0136 1814 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
2cc0c0b5 1815 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
037d6dfa 1816 uint8_t i, stretch_amount, volt_offset = 0;
a23eefa2
RZ		 1817 struct phm_ppt_v1_information *table_info =
1818 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1819 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1820 table_info->vdd_dep_on_sclk;
1821
1822 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1823
1824 /* Read SMU_Eefuse to read and calculate RO and determine
1825 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1826 */
1827 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
270d0136 1828 ixSMU_EFUSE_0 + (67 * 4));
a23eefa2
RZ		 1829 efuse &= 0xFF000000;
1830 efuse = efuse >> 24;
a23eefa2 1831
270d0136
RZ		 1832 if (hwmgr->chip_id == CHIP_POLARIS10) {
1833 min = 1000;
1834 max = 2300;
1835 } else {
1836 min = 1100;
1837 max = 2100;
1838 }
a23eefa2 1839
270d0136 1840 ro = efuse * (max -min)/255 + min;
a23eefa2
RZ		 1841
1842 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1843 for (i = 0; i < sclk_table->count; i++) {
1844 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1845 sclk_table->entries[i].cks_enable << i;
0812a945 1846 if (hwmgr->chip_id == CHIP_POLARIS10) {
ab6bad05 1847 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
0812a945 1848 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
ab6bad05
RZ		 1849 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1850 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
0812a945 1851 } else {
ab6bad05
RZ		 1852 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
1853 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1854 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1855 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
0812a945 1856 }
270d0136 1857
a23eefa2
RZ		 1858 if (volt_without_cks >= volt_with_cks)
1859 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
ab6bad05 1860 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
270d0136 1861
a23eefa2
RZ		 1862 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1863 }
1864
83a7af6d 1865 data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
a23eefa2 1866 /* Populate CKS Lookup Table */
037d6dfa
MB		 1867 if (stretch_amount != 1 && stretch_amount != 2 && stretch_amount != 3 &&
1868 stretch_amount != 4 && stretch_amount != 5) {
a23eefa2
RZ		 1869 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1870 PHM_PlatformCaps_ClockStretcher);
1871 PP_ASSERT_WITH_CODE(false,
1872 "Stretch Amount in PPTable not supported\n",
1873 return -EINVAL);
1874 }
1875
a23eefa2
RZ		 1876 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1877 value &= 0xFFFFFFFE;
1878 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1879
1880 return 0;
1881}
1882
1883/**
1884* Populates the SMC VRConfig field in DPM table.
1885*
1886* @param hwmgr the address of the hardware manager
1887* @param table the SMC DPM table structure to be populated
1888* @return always 0
1889*/
2cc0c0b5 1890static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 1891 struct SMU74_Discrete_DpmTable *table)
1892{
2cc0c0b5 1893 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 1894 uint16_t config;
1895
1896 config = VR_MERGED_WITH_VDDC;
1897 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1898
1899 /* Set Vddc Voltage Controller */
2cc0c0b5 1900 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
a23eefa2
RZ		 1901 config = VR_SVI2_PLANE_1;
1902 table->VRConfig |= config;
1903 } else {
1904 PP_ASSERT_WITH_CODE(false,
1905 "VDDC should be on SVI2 control in merged mode!",
1906 );
1907 }
1908 /* Set Vddci Voltage Controller */
2cc0c0b5 1909 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
a23eefa2
RZ		 1910 config = VR_SVI2_PLANE_2; /* only in merged mode */
1911 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2cc0c0b5 1912 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
a23eefa2
RZ		 1913 config = VR_SMIO_PATTERN_1;
1914 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1915 } else {
1916 config = VR_STATIC_VOLTAGE;
1917 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1918 }
1919 /* Set Mvdd Voltage Controller */
2cc0c0b5 1920 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
a23eefa2
RZ		 1921 config = VR_SVI2_PLANE_2;
1922 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
696b2d73
RZ		 1923 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
1924 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
a23eefa2
RZ		 1925 } else {
1926 config = VR_STATIC_VOLTAGE;
1927 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1928 }
1929
1930 return 0;
1931}
1932
432c3a3c
RZ		 1933
1934int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1935{
1936 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1937 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1938 int result = 0;
1939 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1940 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1941 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1942 uint32_t tmp, i;
1943 struct pp_smumgr *smumgr = hwmgr->smumgr;
1944 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1945
1946 struct phm_ppt_v1_information *table_info =
1947 (struct phm_ppt_v1_information *)hwmgr->pptable;
1948 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1949 table_info->vdd_dep_on_sclk;
1950
1951
1952 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1953 return result;
1954
1955 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1956
1957 if (0 == result) {
1958 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1959 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1960 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1961 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1962 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1963 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1964 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1965 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1966 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1967 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1968 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1969 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1970 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1971 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1972 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1973 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1974 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1975 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1976 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1977 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1978 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1979 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1980 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1981 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1982
1983 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1984 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1985 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1986 }
1987
1988 result = polaris10_read_smc_sram_dword(smumgr,
1989 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1990 &tmp, data->sram_end);
1991
1992 polaris10_copy_bytes_to_smc(smumgr,
1993 tmp,
1994 (uint8_t *)&AVFS_meanNsigma,
1995 sizeof(AVFS_meanNsigma_t),
1996 data->sram_end);
1997
1998 result = polaris10_read_smc_sram_dword(smumgr,
1999 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
2000 &tmp, data->sram_end);
2001 polaris10_copy_bytes_to_smc(smumgr,
2002 tmp,
2003 (uint8_t *)&AVFS_SclkOffset,
2004 sizeof(AVFS_Sclk_Offset_t),
2005 data->sram_end);
2006
2007 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2008 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2009 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2010 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2011 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2012 }
2013 return result;
2014}
2015
2016
a23eefa2
RZ		 2017/**
2018* Initializes the SMC table and uploads it
2019*
2020* @param hwmgr the address of the powerplay hardware manager.
2021* @return always 0
2022*/
2cc0c0b5 2023static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2024{
2025 int result;
2cc0c0b5 2026 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2027 struct phm_ppt_v1_information *table_info =
2028 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2029 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2cc0c0b5 2030 const struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 2031 uint8_t i;
2032 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
e85c7d66 2033 pp_atomctrl_clock_dividers_vi dividers;
a23eefa2 2034
2cc0c0b5 2035 result = polaris10_setup_default_dpm_tables(hwmgr);
a23eefa2
RZ		 2036 PP_ASSERT_WITH_CODE(0 == result,
2037 "Failed to setup default DPM tables!", return result);
2038
2cc0c0b5
FC		 2039 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2040 polaris10_populate_smc_voltage_tables(hwmgr, table);
a23eefa2 2041
681ed01c 2042 table->SystemFlags = 0;
a23eefa2
RZ		 2043 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2044 PHM_PlatformCaps_AutomaticDCTransition))
2045 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2046
2047 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2048 PHM_PlatformCaps_StepVddc))
2049 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2050
2051 if (data->is_memory_gddr5)
2052 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2053
2054 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2cc0c0b5 2055 result = polaris10_populate_ulv_state(hwmgr, table);
a23eefa2
RZ		 2056 PP_ASSERT_WITH_CODE(0 == result,
2057 "Failed to initialize ULV state!", return result);
2058 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2cc0c0b5 2059 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
a23eefa2
RZ		 2060 }
2061
2cc0c0b5 2062 result = polaris10_populate_smc_link_level(hwmgr, table);
a23eefa2
RZ		 2063 PP_ASSERT_WITH_CODE(0 == result,
2064 "Failed to initialize Link Level!", return result);
2065
2cc0c0b5 2066 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 2067 PP_ASSERT_WITH_CODE(0 == result,
2068 "Failed to initialize Graphics Level!", return result);
2069
2cc0c0b5 2070 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 2071 PP_ASSERT_WITH_CODE(0 == result,
2072 "Failed to initialize Memory Level!", return result);
2073
2cc0c0b5 2074 result = polaris10_populate_smc_acpi_level(hwmgr, table);
a23eefa2
RZ		 2075 PP_ASSERT_WITH_CODE(0 == result,
2076 "Failed to initialize ACPI Level!", return result);
2077
2cc0c0b5 2078 result = polaris10_populate_smc_vce_level(hwmgr, table);
a23eefa2
RZ		 2079 PP_ASSERT_WITH_CODE(0 == result,
2080 "Failed to initialize VCE Level!", return result);
2081
2cc0c0b5 2082 result = polaris10_populate_smc_samu_level(hwmgr, table);
a23eefa2
RZ		 2083 PP_ASSERT_WITH_CODE(0 == result,
2084 "Failed to initialize SAMU Level!", return result);
2085
2086 /* Since only the initial state is completely set up at this point
2087 * (the other states are just copies of the boot state) we only
2088 * need to populate the ARB settings for the initial state.
2089 */
2cc0c0b5 2090 result = polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 2091 PP_ASSERT_WITH_CODE(0 == result,
2092 "Failed to Write ARB settings for the initial state.", return result);
2093
2cc0c0b5 2094 result = polaris10_populate_smc_uvd_level(hwmgr, table);
a23eefa2
RZ		 2095 PP_ASSERT_WITH_CODE(0 == result,
2096 "Failed to initialize UVD Level!", return result);
2097
2cc0c0b5 2098 result = polaris10_populate_smc_boot_level(hwmgr, table);
a23eefa2
RZ		 2099 PP_ASSERT_WITH_CODE(0 == result,
2100 "Failed to initialize Boot Level!", return result);
2101
2cc0c0b5 2102 result = polaris10_populate_smc_initailial_state(hwmgr);
a23eefa2
RZ		 2103 PP_ASSERT_WITH_CODE(0 == result,
2104 "Failed to initialize Boot State!", return result);
2105
2cc0c0b5 2106 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
a23eefa2
RZ		 2107 PP_ASSERT_WITH_CODE(0 == result,
2108 "Failed to populate BAPM Parameters!", return result);
2109
2110 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2111 PHM_PlatformCaps_ClockStretcher)) {
2cc0c0b5 2112 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
a23eefa2
RZ		 2113 PP_ASSERT_WITH_CODE(0 == result,
2114 "Failed to populate Clock Stretcher Data Table!",
2115 return result);
2116 }
432c3a3c
RZ		 2117
2118 result = polaris10_populate_avfs_parameters(hwmgr);
2119 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2120
9ab9cf05 2121 table->CurrSclkPllRange = 0xff;
a23eefa2
RZ		 2122 table->GraphicsVoltageChangeEnable = 1;
2123 table->GraphicsThermThrottleEnable = 1;
2124 table->GraphicsInterval = 1;
2125 table->VoltageInterval = 1;
2126 table->ThermalInterval = 1;
2127 table->TemperatureLimitHigh =
2128 table_info->cac_dtp_table->usTargetOperatingTemp *
2cc0c0b5 2129 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2130 table->TemperatureLimitLow =
2131 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2cc0c0b5 2132 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
a23eefa2
RZ		 2133 table->MemoryVoltageChangeEnable = 1;
2134 table->MemoryInterval = 1;
2135 table->VoltageResponseTime = 0;
2136 table->PhaseResponseTime = 0;
2137 table->MemoryThermThrottleEnable = 1;
2138 table->PCIeBootLinkLevel = 0;
2139 table->PCIeGenInterval = 1;
681ed01c 2140 table->VRConfig = 0;
a23eefa2 2141
2cc0c0b5 2142 result = polaris10_populate_vr_config(hwmgr, table);
a23eefa2
RZ		 2143 PP_ASSERT_WITH_CODE(0 == result,
2144 "Failed to populate VRConfig setting!", return result);
2145
2146 table->ThermGpio = 17;
2147 table->SclkStepSize = 0x4000;
2148
2149 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2150 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2151 } else {
2cc0c0b5 2152 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2153 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2154 PHM_PlatformCaps_RegulatorHot);
2155 }
2156
2157 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2158 &gpio_pin)) {
2159 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2160 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2161 PHM_PlatformCaps_AutomaticDCTransition);
2162 } else {
2cc0c0b5 2163 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
a23eefa2
RZ		 2164 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2165 PHM_PlatformCaps_AutomaticDCTransition);
2166 }
2167
2168 /* Thermal Output GPIO */
2169 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2170 &gpio_pin)) {
2171 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2172 PHM_PlatformCaps_ThermalOutGPIO);
2173
2174 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2175
2176 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2177 * since VBIOS will program this register to set 'inactive state',
2178 * driver can then determine 'active state' from this and
2179 * program SMU with correct polarity
2180 */
2181 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2182 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2183 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2184
2185 /* if required, combine VRHot/PCC with thermal out GPIO */
2186 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2187 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2188 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2189 } else {
2190 table->ThermOutGpio = 17;
2191 table->ThermOutPolarity = 1;
2192 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2193 }
2194
e85c7d66 2195 /* Populate BIF_SCLK levels into SMC DPM table */
2196 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2197 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2198 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2199
2200 if (i == 0)
2201 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2202 else
2203 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2204 }
2205
a23eefa2
RZ		 2206 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2207 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2208
2209 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2210 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2211 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2212 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2213 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
9ab9cf05 2214 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
a23eefa2
RZ		 2215 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2216 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2217 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2218 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2219
2220 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2cc0c0b5 2221 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
a23eefa2
RZ		 2222 data->dpm_table_start +
2223 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2224 (uint8_t *)&(table->SystemFlags),
2225 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2226 data->sram_end);
2227 PP_ASSERT_WITH_CODE(0 == result,
2228 "Failed to upload dpm data to SMC memory!", return result);
2229
2230 return 0;
2231}
2232
2233/**
2234* Initialize the ARB DRAM timing table's index field.
2235*
2236* @param hwmgr the address of the powerplay hardware manager.
2237* @return always 0
2238*/
2cc0c0b5 2239static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
a23eefa2 2240{
2cc0c0b5 2241 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2242 uint32_t tmp;
2243 int result;
2244
2245 /* This is a read-modify-write on the first byte of the ARB table.
2246 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2247 * is the field 'current'.
2248 * This solution is ugly, but we never write the whole table only
2249 * individual fields in it.
2250 * In reality this field should not be in that structure
2251 * but in a soft register.
2252 */
2cc0c0b5 2253 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2254 data->arb_table_start, &tmp, data->sram_end);
2255
2256 if (result)
2257 return result;
2258
2259 tmp &= 0x00FFFFFF;
2260 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2261
2cc0c0b5 2262 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
a23eefa2
RZ		 2263 data->arb_table_start, tmp, data->sram_end);
2264}
2265
2cc0c0b5 2266static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2267{
2268 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2269 PHM_PlatformCaps_RegulatorHot))
2270 return smum_send_msg_to_smc(hwmgr->smumgr,
2271 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2272
2273 return 0;
2274}
2275
2cc0c0b5 2276static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2277{
2278 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2279 SCLK_PWRMGT_OFF, 0);
2280 return 0;
2281}
2282
2cc0c0b5 2283static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
a23eefa2 2284{
2cc0c0b5
FC		 2285 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2286 struct polaris10_ulv_parm *ulv = &(data->ulv);
a23eefa2
RZ		 2287
2288 if (ulv->ulv_supported)
2289 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2290
2291 return 0;
2292}
2293
c27371b8
EH		 2294static int polaris10_disable_ulv(struct pp_hwmgr *hwmgr)
2295{
2296 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2297 struct polaris10_ulv_parm *ulv = &(data->ulv);
2298
2299 if (ulv->ulv_supported)
2300 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
2301
2302 return 0;
2303}
2304
2cc0c0b5 2305static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2306{
2307 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2308 PHM_PlatformCaps_SclkDeepSleep)) {
2309 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2310 PP_ASSERT_WITH_CODE(false,
2311 "Attempt to enable Master Deep Sleep switch failed!",
2312 return -1);
2313 } else {
2314 if (smum_send_msg_to_smc(hwmgr->smumgr,
2315 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2316 PP_ASSERT_WITH_CODE(false,
2317 "Attempt to disable Master Deep Sleep switch failed!",
2318 return -1);
2319 }
2320 }
2321
2322 return 0;
2323}
2324
c27371b8
EH		 2325static int polaris10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2326{
2327 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2328 PHM_PlatformCaps_SclkDeepSleep)) {
2329 if (smum_send_msg_to_smc(hwmgr->smumgr,
2330 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2331 PP_ASSERT_WITH_CODE(false,
2332 "Attempt to disable Master Deep Sleep switch failed!",
2333 return -1);
2334 }
2335 }
2336
2337 return 0;
2338}
2339
2cc0c0b5 2340static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2341{
2cc0c0b5 2342 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
40787ef2
RZ		 2343 uint32_t soft_register_value = 0;
2344 uint32_t handshake_disables_offset = data->soft_regs_start
2345 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
a23eefa2
RZ		 2346
2347 /* enable SCLK dpm */
2348 if (!data->sclk_dpm_key_disabled)
2349 PP_ASSERT_WITH_CODE(
2350 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2351 "Failed to enable SCLK DPM during DPM Start Function!",
2352 return -1);
2353
2354 /* enable MCLK dpm */
2355 if (0 == data->mclk_dpm_key_disabled) {
40787ef2
RZ		 2356/* Disable UVD - SMU handshake for MCLK. */
2357 soft_register_value = cgs_read_ind_register(hwmgr->device,
2358 CGS_IND_REG__SMC, handshake_disables_offset);
2359 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2360 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2361 handshake_disables_offset, soft_register_value);
a23eefa2
RZ		 2362
2363 PP_ASSERT_WITH_CODE(
2364 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2365 PPSMC_MSG_MCLKDPM_Enable)),
2366 "Failed to enable MCLK DPM during DPM Start Function!",
2367 return -1);
2368
a23eefa2
RZ		 2369 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2370
2371 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2373 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2374 udelay(10);
2375 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2377 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2378 }
2379
2380 return 0;
2381}
2382
2cc0c0b5 2383static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 2384{
2cc0c0b5 2385 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2386
2387 /*enable general power management */
2388
2389 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2390 GLOBAL_PWRMGT_EN, 1);
2391
2392 /* enable sclk deep sleep */
2393
2394 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2395 DYNAMIC_PM_EN, 1);
2396
2397 /* prepare for PCIE DPM */
2398
2399 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2400 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2401 VoltageChangeTimeout), 0x1000);
2402 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2403 SWRST_COMMAND_1, RESETLC, 0x0);
e85c7d66 2404/*
a23eefa2
RZ		 2405 PP_ASSERT_WITH_CODE(
2406 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2407 PPSMC_MSG_Voltage_Cntl_Enable)),
2408 "Failed to enable voltage DPM during DPM Start Function!",
2409 return -1);
e85c7d66 2410*/
a23eefa2 2411
2cc0c0b5 2412 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
a23eefa2
RZ		 2413 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2414 return -1;
2415 }
2416
2417 /* enable PCIE dpm */
2418 if (0 == data->pcie_dpm_key_disabled) {
2419 PP_ASSERT_WITH_CODE(
2420 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2421 PPSMC_MSG_PCIeDPM_Enable)),
2422 "Failed to enable pcie DPM during DPM Start Function!",
2423 return -1);
2424 }
2425
c8c67448
EH		 2426 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2427 PHM_PlatformCaps_Falcon_QuickTransition)) {
2428 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2429 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2430 "Failed to enable AC DC GPIO Interrupt!",
2431 );
2432 }
a23eefa2
RZ		 2433
2434 return 0;
2435}
2436
c27371b8
EH		 2437static int polaris10_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2438{
2439 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2440
2441 /* disable SCLK dpm */
2442 if (!data->sclk_dpm_key_disabled)
2443 PP_ASSERT_WITH_CODE(
2444 (smum_send_msg_to_smc(hwmgr->smumgr,
2445 PPSMC_MSG_DPM_Disable) == 0),
2446 "Failed to disable SCLK DPM!",
2447 return -1);
2448
2449 /* disable MCLK dpm */
2450 if (!data->mclk_dpm_key_disabled) {
2451 PP_ASSERT_WITH_CODE(
2452 (smum_send_msg_to_smc(hwmgr->smumgr,
2453 PPSMC_MSG_MCLKDPM_Disable) == 0),
2454 "Failed to disable MCLK DPM!",
2455 return -1);
2456 }
2457
2458 return 0;
2459}
2460
2461static int polaris10_stop_dpm(struct pp_hwmgr *hwmgr)
2462{
2463 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2464
2465 /* disable general power management */
2466 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2467 GLOBAL_PWRMGT_EN, 0);
2468 /* disable sclk deep sleep */
2469 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2470 DYNAMIC_PM_EN, 0);
2471
2472 /* disable PCIE dpm */
2473 if (!data->pcie_dpm_key_disabled) {
2474 PP_ASSERT_WITH_CODE(
2475 (smum_send_msg_to_smc(hwmgr->smumgr,
2476 PPSMC_MSG_PCIeDPM_Disable) == 0),
2477 "Failed to disable pcie DPM during DPM Stop Function!",
2478 return -1);
2479 }
2480
2481 if (polaris10_disable_sclk_mclk_dpm(hwmgr)) {
2482 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
2483 return -1;
2484 }
2485
2486 return 0;
2487}
2488
2cc0c0b5 2489static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
a23eefa2
RZ		 2490{
2491 bool protection;
2492 enum DPM_EVENT_SRC src;
2493
2494 switch (sources) {
2495 default:
2496 printk(KERN_ERR "Unknown throttling event sources.");
2497 /* fall through */
2498 case 0:
2499 protection = false;
2500 /* src is unused */
2501 break;
2502 case (1 << PHM_AutoThrottleSource_Thermal):
2503 protection = true;
2504 src = DPM_EVENT_SRC_DIGITAL;
2505 break;
2506 case (1 << PHM_AutoThrottleSource_External):
2507 protection = true;
2508 src = DPM_EVENT_SRC_EXTERNAL;
2509 break;
2510 case (1 << PHM_AutoThrottleSource_External) |
2511 (1 << PHM_AutoThrottleSource_Thermal):
2512 protection = true;
2513 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2514 break;
2515 }
2516 /* Order matters - don't enable thermal protection for the wrong source. */
2517 if (protection) {
2518 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2519 DPM_EVENT_SRC, src);
2520 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2521 THERMAL_PROTECTION_DIS,
f0911de8 2522 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
a23eefa2
RZ		 2523 PHM_PlatformCaps_ThermalController));
2524 } else
2525 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2526 THERMAL_PROTECTION_DIS, 1);
2527}
2528
2cc0c0b5 2529static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 2530 PHM_AutoThrottleSource source)
2531{
2cc0c0b5 2532 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2533
2534 if (!(data->active_auto_throttle_sources & (1 << source))) {
2535 data->active_auto_throttle_sources |= 1 << source;
2cc0c0b5 2536 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
a23eefa2
RZ		 2537 }
2538 return 0;
2539}
2540
2cc0c0b5 2541static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
a23eefa2 2542{
2cc0c0b5 2543 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
a23eefa2
RZ		 2544}
2545
c27371b8
EH		 2546static int polaris10_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2547 PHM_AutoThrottleSource source)
2548{
2549 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2550
2551 if (data->active_auto_throttle_sources & (1 << source)) {
2552 data->active_auto_throttle_sources &= ~(1 << source);
2553 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2554 }
2555 return 0;
2556}
2557
2558static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2559{
2560 return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2561}
2562
2cc0c0b5 2563int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
a23eefa2 2564{
2cc0c0b5 2565 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 2566 data->pcie_performance_request = true;
2567
2568 return 0;
2569}
2570
2cc0c0b5 2571int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2572{
2573 int tmp_result, result = 0;
2cc0c0b5 2574 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
a23eefa2
RZ		 2575 PP_ASSERT_WITH_CODE(result == 0,
2576 "DPM is already running right now, no need to enable DPM!",
2577 return 0);
2578
2cc0c0b5
FC		 2579 if (polaris10_voltage_control(hwmgr)) {
2580 tmp_result = polaris10_enable_voltage_control(hwmgr);
a23eefa2
RZ		 2581 PP_ASSERT_WITH_CODE(tmp_result == 0,
2582 "Failed to enable voltage control!",
2583 result = tmp_result);
2584
2cc0c0b5 2585 tmp_result = polaris10_construct_voltage_tables(hwmgr);
a23eefa2
RZ		 2586 PP_ASSERT_WITH_CODE((0 == tmp_result),
2587 "Failed to contruct voltage tables!",
2588 result = tmp_result);
2589 }
2590
2591 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2592 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2593 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2594 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2595
2596 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2597 PHM_PlatformCaps_ThermalController))
2598 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2599 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2600
2cc0c0b5 2601 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
a23eefa2
RZ		 2602 PP_ASSERT_WITH_CODE((0 == tmp_result),
2603 "Failed to program static screen threshold parameters!",
2604 result = tmp_result);
2605
2cc0c0b5 2606 tmp_result = polaris10_enable_display_gap(hwmgr);
a23eefa2
RZ		 2607 PP_ASSERT_WITH_CODE((0 == tmp_result),
2608 "Failed to enable display gap!", result = tmp_result);
2609
2cc0c0b5 2610 tmp_result = polaris10_program_voting_clients(hwmgr);
a23eefa2
RZ		 2611 PP_ASSERT_WITH_CODE((0 == tmp_result),
2612 "Failed to program voting clients!", result = tmp_result);
2613
2cc0c0b5 2614 tmp_result = polaris10_process_firmware_header(hwmgr);
a23eefa2
RZ		 2615 PP_ASSERT_WITH_CODE((0 == tmp_result),
2616 "Failed to process firmware header!", result = tmp_result);
2617
2cc0c0b5 2618 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
a23eefa2
RZ		 2619 PP_ASSERT_WITH_CODE((0 == tmp_result),
2620 "Failed to initialize switch from ArbF0 to F1!",
2621 result = tmp_result);
2622
2cc0c0b5 2623 tmp_result = polaris10_init_smc_table(hwmgr);
a23eefa2
RZ		 2624 PP_ASSERT_WITH_CODE((0 == tmp_result),
2625 "Failed to initialize SMC table!", result = tmp_result);
2626
2cc0c0b5 2627 tmp_result = polaris10_init_arb_table_index(hwmgr);
a23eefa2
RZ		 2628 PP_ASSERT_WITH_CODE((0 == tmp_result),
2629 "Failed to initialize ARB table index!", result = tmp_result);
2630
2cc0c0b5 2631 tmp_result = polaris10_populate_pm_fuses(hwmgr);
a23eefa2
RZ		 2632 PP_ASSERT_WITH_CODE((0 == tmp_result),
2633 "Failed to populate PM fuses!", result = tmp_result);
2634
2cc0c0b5 2635 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
a23eefa2
RZ		 2636 PP_ASSERT_WITH_CODE((0 == tmp_result),
2637 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2638
83a7af6d
RZ		 2639 smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay);
2640
2cc0c0b5 2641 tmp_result = polaris10_enable_sclk_control(hwmgr);
a23eefa2
RZ		 2642 PP_ASSERT_WITH_CODE((0 == tmp_result),
2643 "Failed to enable SCLK control!", result = tmp_result);
2644
2cc0c0b5 2645 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
e85c7d66 2646 PP_ASSERT_WITH_CODE((0 == tmp_result),
2647 "Failed to enable voltage control!", result = tmp_result);
2648
2cc0c0b5 2649 tmp_result = polaris10_enable_ulv(hwmgr);
a23eefa2
RZ		 2650 PP_ASSERT_WITH_CODE((0 == tmp_result),
2651 "Failed to enable ULV!", result = tmp_result);
2652
2cc0c0b5 2653 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
a23eefa2
RZ		 2654 PP_ASSERT_WITH_CODE((0 == tmp_result),
2655 "Failed to enable deep sleep master switch!", result = tmp_result);
2656
36e6b912
RZ		 2657 tmp_result = polaris10_enable_didt_config(hwmgr);
2658 PP_ASSERT_WITH_CODE((tmp_result == 0),
2659 "Failed to enable deep sleep master switch!", result = tmp_result);
2660
2cc0c0b5 2661 tmp_result = polaris10_start_dpm(hwmgr);
a23eefa2
RZ		 2662 PP_ASSERT_WITH_CODE((0 == tmp_result),
2663 "Failed to start DPM!", result = tmp_result);
2664
2cc0c0b5 2665 tmp_result = polaris10_enable_smc_cac(hwmgr);
a23eefa2
RZ		 2666 PP_ASSERT_WITH_CODE((0 == tmp_result),
2667 "Failed to enable SMC CAC!", result = tmp_result);
2668
2cc0c0b5 2669 tmp_result = polaris10_enable_power_containment(hwmgr);
a23eefa2
RZ		 2670 PP_ASSERT_WITH_CODE((0 == tmp_result),
2671 "Failed to enable power containment!", result = tmp_result);
2672
2cc0c0b5 2673 tmp_result = polaris10_power_control_set_level(hwmgr);
a23eefa2
RZ		 2674 PP_ASSERT_WITH_CODE((0 == tmp_result),
2675 "Failed to power control set level!", result = tmp_result);
2676
2cc0c0b5 2677 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
a23eefa2
RZ		 2678 PP_ASSERT_WITH_CODE((0 == tmp_result),
2679 "Failed to enable thermal auto throttle!", result = tmp_result);
2680
2cc0c0b5 2681 tmp_result = polaris10_pcie_performance_request(hwmgr);
a23eefa2 2682 PP_ASSERT_WITH_CODE((0 == tmp_result),
5f88567c 2683 "pcie performance request failed!", result = tmp_result);
a23eefa2
RZ		 2684
2685 return result;
2686}
2687
2cc0c0b5 2688int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
a23eefa2 2689{
c27371b8 2690 int tmp_result, result = 0;
a23eefa2 2691
c27371b8
EH		 2692 tmp_result = (polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2693 PP_ASSERT_WITH_CODE(tmp_result == 0,
2694 "DPM is not running right now, no need to disable DPM!",
2695 return 0);
2696
2697 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2698 PHM_PlatformCaps_ThermalController))
2699 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2700 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
2701
2702 tmp_result = polaris10_disable_power_containment(hwmgr);
2703 PP_ASSERT_WITH_CODE((tmp_result == 0),
2704 "Failed to disable power containment!", result = tmp_result);
2705
2706 tmp_result = polaris10_disable_smc_cac(hwmgr);
2707 PP_ASSERT_WITH_CODE((tmp_result == 0),
2708 "Failed to disable SMC CAC!", result = tmp_result);
2709
2710 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2711 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
2712 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2713 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
2714
2715 tmp_result = polaris10_disable_thermal_auto_throttle(hwmgr);
2716 PP_ASSERT_WITH_CODE((tmp_result == 0),
2717 "Failed to disable thermal auto throttle!", result = tmp_result);
2718
2719 tmp_result = polaris10_stop_dpm(hwmgr);
2720 PP_ASSERT_WITH_CODE((tmp_result == 0),
2721 "Failed to stop DPM!", result = tmp_result);
2722
2723 tmp_result = polaris10_disable_deep_sleep_master_switch(hwmgr);
2724 PP_ASSERT_WITH_CODE((tmp_result == 0),
2725 "Failed to disable deep sleep master switch!", result = tmp_result);
2726
2727 tmp_result = polaris10_disable_ulv(hwmgr);
2728 PP_ASSERT_WITH_CODE((tmp_result == 0),
2729 "Failed to disable ULV!", result = tmp_result);
2730
2731 tmp_result = polaris10_clear_voting_clients(hwmgr);
2732 PP_ASSERT_WITH_CODE((tmp_result == 0),
2733 "Failed to clear voting clients!", result = tmp_result);
2734
2735 tmp_result = polaris10_reset_to_default(hwmgr);
2736 PP_ASSERT_WITH_CODE((tmp_result == 0),
2737 "Failed to reset to default!", result = tmp_result);
2738
2739 tmp_result = polaris10_force_switch_to_arbf0(hwmgr);
2740 PP_ASSERT_WITH_CODE((tmp_result == 0),
2741 "Failed to force to switch arbf0!", result = tmp_result);
2742
2743 return result;
a23eefa2
RZ		 2744}
2745
2cc0c0b5 2746int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2747{
2748
2749 return 0;
2750}
2751
2cc0c0b5 2752int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2753{
2754 return phm_hwmgr_backend_fini(hwmgr);
2755}
2756
2cc0c0b5 2757int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
a23eefa2 2758{
2cc0c0b5 2759 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 2760
f0911de8
RZ		 2761 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2762 PHM_PlatformCaps_DynamicPatchPowerState);
2763
2cc0c0b5 2764 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2765 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2766 PHM_PlatformCaps_EnableMVDDControl);
2767
2cc0c0b5 2768 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
a23eefa2
RZ		 2769 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2770 PHM_PlatformCaps_ControlVDDCI);
2771
2772 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2773 PHM_PlatformCaps_TablelessHardwareInterface);
2774
2775 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2776 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2777
2778 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2779 PHM_PlatformCaps_DynamicPowerManagement);
2780
f0911de8
RZ		 2781 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2782 PHM_PlatformCaps_UnTabledHardwareInterface);
2783
a23eefa2
RZ		 2784 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2785 PHM_PlatformCaps_TablelessHardwareInterface);
2786
2787 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2788 PHM_PlatformCaps_SMC);
2789
2790 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2791 PHM_PlatformCaps_NonABMSupportInPPLib);
2792
2793 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2794 PHM_PlatformCaps_DynamicUVDState);
2795
a23eefa2 2796 /* power tune caps Assume disabled */
36e6b912 2797 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
a23eefa2 2798 PHM_PlatformCaps_SQRamping);
36e6b912 2799 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
a23eefa2 2800 PHM_PlatformCaps_DBRamping);
36e6b912 2801 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
a23eefa2 2802 PHM_PlatformCaps_TDRamping);
36e6b912 2803 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
a23eefa2
RZ		 2804 PHM_PlatformCaps_TCPRamping);
2805
f0911de8
RZ		 2806 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2807 PHM_PlatformCaps_CAC);
2808
2809 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2810 PHM_PlatformCaps_RegulatorHot);
2811
2812 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2813 PHM_PlatformCaps_AutomaticDCTransition);
2814
2815 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2816 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2817
2818 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2819 PHM_PlatformCaps_FanSpeedInTableIsRPM);
919e334d 2820
5de95e55
RZ		 2821 if (hwmgr->chip_id == CHIP_POLARIS11)
2822 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2823 PHM_PlatformCaps_SPLLShutdownSupport);
a23eefa2
RZ		 2824 return 0;
2825}
2826
2cc0c0b5 2827static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
a23eefa2 2828{
2cc0c0b5 2829 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 2830
2cc0c0b5 2831 polaris10_initialize_power_tune_defaults(hwmgr);
a23eefa2
RZ		 2832
2833 data->pcie_gen_performance.max = PP_PCIEGen1;
2834 data->pcie_gen_performance.min = PP_PCIEGen3;
2835 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2836 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2837 data->pcie_lane_performance.max = 0;
2838 data->pcie_lane_performance.min = 16;
2839 data->pcie_lane_power_saving.max = 0;
2840 data->pcie_lane_power_saving.min = 16;
2841}
2842
2843/**
2844* Get Leakage VDDC based on leakage ID.
2845*
2846* @param hwmgr the address of the powerplay hardware manager.
2847* @return always 0
2848*/
2cc0c0b5 2849static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
a23eefa2 2850{
2cc0c0b5 2851 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 2852 uint16_t vv_id;
e5eb3717 2853 uint32_t vddc = 0;
a23eefa2
RZ		 2854 uint16_t i, j;
2855 uint32_t sclk = 0;
2856 struct phm_ppt_v1_information *table_info =
2857 (struct phm_ppt_v1_information *)hwmgr->pptable;
2858 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2859 table_info->vdd_dep_on_sclk;
2860 int result;
2861
2cc0c0b5 2862 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
a23eefa2
RZ		 2863 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2864 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2865 table_info->vddc_lookup_table, vv_id, &sclk)) {
2866 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2867 PHM_PlatformCaps_ClockStretcher)) {
2868 for (j = 1; j < sclk_table->count; j++) {
2869 if (sclk_table->entries[j].clk == sclk &&
2870 sclk_table->entries[j].cks_enable == 0) {
2871 sclk += 5000;
2872 break;
2873 }
2874 }
2875 }
2876
b1814a1d
RZ		 2877 if (atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2878 VOLTAGE_TYPE_VDDC,
2879 sclk, vv_id, &vddc) != 0) {
2880 printk(KERN_WARNING "failed to retrieving EVV voltage!\n");
2881 continue;
2882 }
a23eefa2 2883
a94cbfc3
RZ		 2884 /* need to make sure vddc is less than 2V or else, it could burn the ASIC.
2885 * real voltage level in unit of 0.01mV */
e5eb3717 2886 PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0),
a23eefa2
RZ		 2887 "Invalid VDDC value", result = -EINVAL;);
2888
2889 /* the voltage should not be zero nor equal to leakage ID */
2890 if (vddc != 0 && vddc != vv_id) {
2891 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2892 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2893 data->vddc_leakage.count++;
2894 }
2895 }
2896 }
2897
2898 return 0;
2899}
2900
2901/**
2902 * Change virtual leakage voltage to actual value.
2903 *
2904 * @param hwmgr the address of the powerplay hardware manager.
2905 * @param pointer to changing voltage
2906 * @param pointer to leakage table
2907 */
2cc0c0b5
FC		 2908static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2909 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2910{
2911 uint32_t index;
2912
2913 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2914 for (index = 0; index < leakage_table->count; index++) {
2915 /* if this voltage matches a leakage voltage ID */
2916 /* patch with actual leakage voltage */
2917 if (leakage_table->leakage_id[index] == *voltage) {
2918 *voltage = leakage_table->actual_voltage[index];
2919 break;
2920 }
2921 }
2922
2923 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2924 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2925}
2926
2927/**
2928* Patch voltage lookup table by EVV leakages.
2929*
2930* @param hwmgr the address of the powerplay hardware manager.
2931* @param pointer to voltage lookup table
2932* @param pointer to leakage table
2933* @return always 0
2934*/
2cc0c0b5 2935static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
a23eefa2 2936 phm_ppt_v1_voltage_lookup_table *lookup_table,
2cc0c0b5 2937 struct polaris10_leakage_voltage *leakage_table)
a23eefa2
RZ		 2938{
2939 uint32_t i;
2940
2941 for (i = 0; i < lookup_table->count; i++)
2cc0c0b5 2942 polaris10_patch_with_vdd_leakage(hwmgr,
a23eefa2
RZ		 2943 &lookup_table->entries[i].us_vdd, leakage_table);
2944
2945 return 0;
2946}
2947
2cc0c0b5
FC		 2948static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2949 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
a23eefa2
RZ		 2950 uint16_t *vddc)
2951{
2952 struct phm_ppt_v1_information *table_info =
2953 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2cc0c0b5 2954 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
a23eefa2
RZ		 2955 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2956 table_info->max_clock_voltage_on_dc.vddc;
2957 return 0;
2958}
2959
2cc0c0b5 2960static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
a23eefa2
RZ		 2961 struct pp_hwmgr *hwmgr)
2962{
2963 uint8_t entryId;
2964 uint8_t voltageId;
2965 struct phm_ppt_v1_information *table_info =
2966 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2967
2968 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2969 table_info->vdd_dep_on_sclk;
2970 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2971 table_info->vdd_dep_on_mclk;
2972 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2973 table_info->mm_dep_table;
2974
2975 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2976 voltageId = sclk_table->entries[entryId].vddInd;
2977 sclk_table->entries[entryId].vddc =
2978 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2979 }
2980
2981 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2982 voltageId = mclk_table->entries[entryId].vddInd;
2983 mclk_table->entries[entryId].vddc =
2984 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2985 }
2986
2987 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2988 voltageId = mm_table->entries[entryId].vddcInd;
2989 mm_table->entries[entryId].vddc =
2990 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2991 }
2992
2993 return 0;
2994
2995}
2996
2cc0c0b5 2997static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 2998{
2999 /* Need to determine if we need calculated voltage. */
3000 return 0;
3001}
3002
2cc0c0b5 3003static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 3004{
3005 /* Need to determine if we need calculated voltage from mm table. */
3006 return 0;
3007}
3008
2cc0c0b5 3009static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3010 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
3011{
3012 uint32_t table_size, i, j;
3013 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3014 table_size = lookup_table->count;
3015
3016 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3017 "Lookup table is empty", return -EINVAL);
3018
3019 /* Sorting voltages */
3020 for (i = 0; i < table_size - 1; i++) {
3021 for (j = i + 1; j > 0; j--) {
3022 if (lookup_table->entries[j].us_vdd <
3023 lookup_table->entries[j - 1].us_vdd) {
3024 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
3025 lookup_table->entries[j - 1] = lookup_table->entries[j];
3026 lookup_table->entries[j] = tmp_voltage_lookup_record;
3027 }
3028 }
3029 }
3030
3031 return 0;
3032}
3033
2cc0c0b5 3034static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 3035{
3036 int result = 0;
3037 int tmp_result;
2cc0c0b5 3038 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3039 struct phm_ppt_v1_information *table_info =
3040 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3041
2cc0c0b5 3042 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
a23eefa2
RZ		 3043 table_info->vddc_lookup_table, &(data->vddc_leakage));
3044 if (tmp_result)
3045 result = tmp_result;
3046
2cc0c0b5 3047 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
a23eefa2
RZ		 3048 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
3049 if (tmp_result)
3050 result = tmp_result;
3051
2cc0c0b5 3052 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
a23eefa2
RZ		 3053 if (tmp_result)
3054 result = tmp_result;
3055
2cc0c0b5 3056 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
a23eefa2
RZ		 3057 if (tmp_result)
3058 result = tmp_result;
3059
2cc0c0b5 3060 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
a23eefa2
RZ		 3061 if (tmp_result)
3062 result = tmp_result;
3063
2cc0c0b5 3064 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
a23eefa2
RZ		 3065 if (tmp_result)
3066 result = tmp_result;
3067
3068 return result;
3069}
3070
2cc0c0b5 3071static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 3072{
3073 struct phm_ppt_v1_information *table_info =
3074 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3075
3076 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3077 table_info->vdd_dep_on_sclk;
3078 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3079 table_info->vdd_dep_on_mclk;
3080
3081 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
edf600da 3082 "VDD dependency on SCLK table is missing. \
a23eefa2
RZ		 3083 This table is mandatory", return -EINVAL);
3084 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
edf600da 3085 "VDD dependency on SCLK table has to have is missing. \
a23eefa2
RZ		 3086 This table is mandatory", return -EINVAL);
3087
3088 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
edf600da 3089 "VDD dependency on MCLK table is missing. \
a23eefa2
RZ		 3090 This table is mandatory", return -EINVAL);
3091 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3092 "VDD dependency on MCLK table has to have is missing. \
3093 This table is mandatory", return -EINVAL);
3094
3095 table_info->max_clock_voltage_on_ac.sclk =
3096 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3097 table_info->max_clock_voltage_on_ac.mclk =
3098 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3099 table_info->max_clock_voltage_on_ac.vddc =
3100 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3101 table_info->max_clock_voltage_on_ac.vddci =
3102 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3103
f0911de8
RZ		 3104 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
3105 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
3106 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
3107 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
3108
a23eefa2
RZ		 3109 return 0;
3110}
3111
3a8bd717
RZ		 3112int polaris10_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
3113{
3114 struct phm_ppt_v1_information *table_info =
3115 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3116 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3117 table_info->vdd_dep_on_mclk;
3118 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
3119 table_info->vddc_lookup_table;
3120 uint32_t i;
3121
6391b6ab
RZ		 3122 if (hwmgr->chip_id == CHIP_POLARIS10 && hwmgr->hw_revision == 0xC7 &&
3123 ((hwmgr->sub_sys_id == 0xb37 && hwmgr->sub_vendor_id == 0x1002) ||
3124 (hwmgr->sub_sys_id == 0x4a8 && hwmgr->sub_vendor_id == 0x1043) ||
3125 (hwmgr->sub_sys_id == 0x9480 && hwmgr->sub_vendor_id == 0x1682))) {
3a8bd717
RZ		 3126 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
3127 return 0;
3128
3129 for (i = 0; i < lookup_table->count; i++) {
3130 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) {
3131 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i;
3132 return 0;
3133 }
3134 }
3135 }
3136 return 0;
3137}
3138
3139
2cc0c0b5 3140int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
a23eefa2 3141{
76ad42c1 3142 struct polaris10_hwmgr *data;
a23eefa2
RZ		 3143 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3144 uint32_t temp_reg;
3145 int result;
f0911de8
RZ		 3146 struct phm_ppt_v1_information *table_info =
3147 (struct phm_ppt_v1_information *)(hwmgr->pptable);
a23eefa2 3148
76ad42c1
EH		 3149 data = kzalloc(sizeof(struct polaris10_hwmgr), GFP_KERNEL);
3150 if (data == NULL)
3151 return -ENOMEM;
3152
3153 hwmgr->backend = data;
3154
a23eefa2
RZ		 3155 data->dll_default_on = false;
3156 data->sram_end = SMC_RAM_END;
7d367c2a 3157 data->mclk_dpm0_activity_target = 0xa;
a23eefa2 3158 data->disable_dpm_mask = 0xFF;
2cc0c0b5
FC		 3159 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3160 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3161 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3162 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3163 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3164 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3165 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3166 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3167 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3168 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3169
3170 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3171 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3172 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3173 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3174 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3175 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3176 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3177 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
a23eefa2
RZ		 3178
3179 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3180
2cc0c0b5 3181 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
a23eefa2
RZ		 3182
3183 /* need to set voltage control types before EVV patching */
2cc0c0b5
FC		 3184 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3185 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3186 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
a23eefa2 3187
919e334d
RZ		 3188 data->enable_tdc_limit_feature = true;
3189 data->enable_pkg_pwr_tracking_feature = true;
a2fb4934 3190 data->force_pcie_gen = PP_PCIEGenInvalid;
9a3c1b34 3191 data->mclk_stutter_mode_threshold = 40000;
919e334d 3192
a23eefa2
RZ		 3193 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3194 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 3195 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2 3196
a23eefa2
RZ		 3197 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3198 PHM_PlatformCaps_EnableMVDDControl)) {
3199 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3200 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 3201 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 3202 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3203 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2cc0c0b5 3204 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 3205 }
3206
3207 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3208 PHM_PlatformCaps_ControlVDDCI)) {
3209 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3210 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2cc0c0b5 3211 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
a23eefa2
RZ		 3212 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3213 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2cc0c0b5 3214 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
a23eefa2
RZ		 3215 }
3216
270d0136
RZ		 3217 if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3218 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3219 PHM_PlatformCaps_ClockStretcher);
3220
2cc0c0b5 3221 polaris10_set_features_platform_caps(hwmgr);
a23eefa2 3222
3a8bd717 3223 polaris10_patch_voltage_workaround(hwmgr);
2cc0c0b5 3224 polaris10_init_dpm_defaults(hwmgr);
a23eefa2
RZ		 3225
3226 /* Get leakage voltage based on leakage ID. */
2cc0c0b5 3227 result = polaris10_get_evv_voltages(hwmgr);
a23eefa2
RZ		 3228
3229 if (result) {
3230 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
3231 return -1;
3232 }
3233
2cc0c0b5
FC		 3234 polaris10_complete_dependency_tables(hwmgr);
3235 polaris10_set_private_data_based_on_pptable(hwmgr);
a23eefa2
RZ		 3236
3237 /* Initalize Dynamic State Adjustment Rule Settings */
3238 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3239
3240 if (0 == result) {
3241 struct cgs_system_info sys_info = {0};
3242
ed5121a3 3243 data->is_tlu_enabled = false;
a23eefa2
RZ		 3244
3245 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
2cc0c0b5 3246 POLARIS10_MAX_HARDWARE_POWERLEVELS;
a23eefa2
RZ		 3247 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3248 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
f0911de8 3249
a23eefa2
RZ		 3250
3251 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3252 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3253 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3254 case 0:
3255 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3256 break;
3257 case 1:
3258 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3259 break;
3260 case 2:
3261 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3262 break;
3263 case 3:
3264 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3265 break;
3266 case 4:
3267 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3268 break;
3269 default:
3270 PP_ASSERT_WITH_CODE(0,
3271 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3272 );
3273 break;
3274 }
3275 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3276 }
3277
f0911de8
RZ		 3278 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3279 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3280 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3281 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3282
3283 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3284 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3285
3286 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3287
3288 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3289
3290 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3291 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3292
3293 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3294
3295 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3296 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3297
3298 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3299 table_info->cac_dtp_table->usOperatingTempStep = 1;
3300 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3301
3302 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3303 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3304
3305 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3306 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3307
3308 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3309 table_info->cac_dtp_table->usOperatingTempMinLimit;
3310
3311 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3312 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3313
3314 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3315 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3316
3317 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3318 table_info->cac_dtp_table->usOperatingTempStep;
3319
3320 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3321 table_info->cac_dtp_table->usTargetOperatingTemp;
3322 }
3323
a23eefa2
RZ		 3324 sys_info.size = sizeof(struct cgs_system_info);
3325 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3326 result = cgs_query_system_info(hwmgr->device, &sys_info);
3327 if (result)
d1371f8c 3328 data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
a23eefa2
RZ		 3329 else
3330 data->pcie_gen_cap = (uint32_t)sys_info.value;
3331 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3332 data->pcie_spc_cap = 20;
3333 sys_info.size = sizeof(struct cgs_system_info);
3334 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3335 result = cgs_query_system_info(hwmgr->device, &sys_info);
3336 if (result)
d1371f8c 3337 data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
a23eefa2
RZ		 3338 else
3339 data->pcie_lane_cap = (uint32_t)sys_info.value;
f0911de8
RZ		 3340
3341 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3342/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3343 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3344 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
a23eefa2
RZ		 3345 } else {
3346 /* Ignore return value in here, we are cleaning up a mess. */
2cc0c0b5 3347 polaris10_hwmgr_backend_fini(hwmgr);
a23eefa2
RZ		 3348 }
3349
3350 return 0;
3351}
3352
2cc0c0b5 3353static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
a23eefa2 3354{
2cc0c0b5 3355 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3356 uint32_t level, tmp;
3357
3358 if (!data->pcie_dpm_key_disabled) {
3359 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3360 level = 0;
3361 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3362 while (tmp >>= 1)
3363 level++;
3364
3365 if (level)
3366 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3367 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3368 }
3369 }
3370
3371 if (!data->sclk_dpm_key_disabled) {
3372 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3373 level = 0;
3374 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3375 while (tmp >>= 1)
3376 level++;
3377
3378 if (level)
3379 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3380 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3381 (1 << level));
3382 }
3383 }
3384
3385 if (!data->mclk_dpm_key_disabled) {
3386 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3387 level = 0;
3388 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3389 while (tmp >>= 1)
3390 level++;
3391
3392 if (level)
3393 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3394 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3395 (1 << level));
3396 }
3397 }
3398
3399 return 0;
3400}
3401
2cc0c0b5 3402static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
a23eefa2 3403{
2cc0c0b5 3404 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3405
3406 phm_apply_dal_min_voltage_request(hwmgr);
3407
3408 if (!data->sclk_dpm_key_disabled) {
3409 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3410 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3411 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3412 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3413 }
3414
3415 if (!data->mclk_dpm_key_disabled) {
3416 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3417 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3418 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3419 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3420 }
3421
3422 return 0;
3423}
3424
2cc0c0b5 3425static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
a23eefa2 3426{
2cc0c0b5 3427 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 3428
2cc0c0b5 3429 if (!polaris10_is_dpm_running(hwmgr))
a23eefa2
RZ		 3430 return -EINVAL;
3431
3432 if (!data->pcie_dpm_key_disabled) {
3433 smum_send_msg_to_smc(hwmgr->smumgr,
3434 PPSMC_MSG_PCIeDPM_UnForceLevel);
3435 }
3436
2cc0c0b5 3437 return polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 3438}
3439
2cc0c0b5 3440static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
a23eefa2 3441{
2cc0c0b5
FC		 3442 struct polaris10_hwmgr *data =
3443 (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3444 uint32_t level;
3445
3446 if (!data->sclk_dpm_key_disabled)
3447 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3448 level = phm_get_lowest_enabled_level(hwmgr,
3449 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3450 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3451 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3452 (1 << level));
3453
3454 }
2043f43e 3455
a23eefa2
RZ		 3456 if (!data->mclk_dpm_key_disabled) {
3457 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3458 level = phm_get_lowest_enabled_level(hwmgr,
3459 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3460 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3461 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3462 (1 << level));
3463 }
3464 }
2043f43e 3465
a23eefa2
RZ		 3466 if (!data->pcie_dpm_key_disabled) {
3467 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3468 level = phm_get_lowest_enabled_level(hwmgr,
3469 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3470 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3471 PPSMC_MSG_PCIeDPM_ForceLevel,
3472 (level));
3473 }
3474 }
3475
3476 return 0;
3477
3478}
2cc0c0b5 3479static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3480 enum amd_dpm_forced_level level)
3481{
3482 int ret = 0;
3483
3484 switch (level) {
3485 case AMD_DPM_FORCED_LEVEL_HIGH:
2cc0c0b5 3486 ret = polaris10_force_dpm_highest(hwmgr);
a23eefa2
RZ		 3487 if (ret)
3488 return ret;
3489 break;
3490 case AMD_DPM_FORCED_LEVEL_LOW:
2cc0c0b5 3491 ret = polaris10_force_dpm_lowest(hwmgr);
a23eefa2
RZ		 3492 if (ret)
3493 return ret;
3494 break;
3495 case AMD_DPM_FORCED_LEVEL_AUTO:
2cc0c0b5 3496 ret = polaris10_unforce_dpm_levels(hwmgr);
a23eefa2
RZ		 3497 if (ret)
3498 return ret;
3499 break;
3500 default:
3501 break;
3502 }
3503
3504 hwmgr->dpm_level = level;
3505
3506 return ret;
3507}
3508
2cc0c0b5 3509static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
a23eefa2 3510{
2cc0c0b5 3511 return sizeof(struct polaris10_power_state);
a23eefa2
RZ		 3512}
3513
3514
2cc0c0b5 3515static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3516 struct pp_power_state *request_ps,
3517 const struct pp_power_state *current_ps)
3518{
3519
2cc0c0b5
FC		 3520 struct polaris10_power_state *polaris10_ps =
3521 cast_phw_polaris10_power_state(&request_ps->hardware);
a23eefa2
RZ		 3522 uint32_t sclk;
3523 uint32_t mclk;
3524 struct PP_Clocks minimum_clocks = {0};
3525 bool disable_mclk_switching;
3526 bool disable_mclk_switching_for_frame_lock;
3527 struct cgs_display_info info = {0};
3528 const struct phm_clock_and_voltage_limits *max_limits;
3529 uint32_t i;
2cc0c0b5 3530 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3531 struct phm_ppt_v1_information *table_info =
3532 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3533 int32_t count;
3534 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3535
3536 data->battery_state = (PP_StateUILabel_Battery ==
3537 request_ps->classification.ui_label);
3538
2cc0c0b5 3539 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
a23eefa2
RZ		 3540 "VI should always have 2 performance levels",
3541 );
3542
3543 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3544 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3545 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3546
3547 /* Cap clock DPM tables at DC MAX if it is in DC. */
3548 if (PP_PowerSource_DC == hwmgr->power_source) {
2cc0c0b5
FC		 3549 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3550 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3551 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3552 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3553 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
a23eefa2
RZ		 3554 }
3555 }
3556
2cc0c0b5
FC		 3557 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3558 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
a23eefa2
RZ		 3559
3560 cgs_get_active_displays_info(hwmgr->device, &info);
3561
3562 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3563
3564 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3565
3566 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3567 PHM_PlatformCaps_StablePState)) {
3568 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3569 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3570
3571 for (count = table_info->vdd_dep_on_sclk->count - 1;
3572 count >= 0; count--) {
3573 if (stable_pstate_sclk >=
3574 table_info->vdd_dep_on_sclk->entries[count].clk) {
3575 stable_pstate_sclk =
3576 table_info->vdd_dep_on_sclk->entries[count].clk;
3577 break;
3578 }
3579 }
3580
3581 if (count < 0)
3582 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3583
3584 stable_pstate_mclk = max_limits->mclk;
3585
3586 minimum_clocks.engineClock = stable_pstate_sclk;
3587 minimum_clocks.memoryClock = stable_pstate_mclk;
3588 }
3589
3590 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3591 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3592
3593 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3594 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3595
2cc0c0b5 3596 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
a23eefa2
RZ		 3597
3598 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3599 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3600 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3601 "Overdrive sclk exceeds limit",
3602 hwmgr->gfx_arbiter.sclk_over_drive =
3603 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3604
3605 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
2cc0c0b5 3606 polaris10_ps->performance_levels[1].engine_clock =
a23eefa2
RZ		 3607 hwmgr->gfx_arbiter.sclk_over_drive;
3608 }
3609
3610 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3611 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3612 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3613 "Overdrive mclk exceeds limit",
3614 hwmgr->gfx_arbiter.mclk_over_drive =
3615 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3616
3617 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
2cc0c0b5 3618 polaris10_ps->performance_levels[1].memory_clock =
a23eefa2
RZ		 3619 hwmgr->gfx_arbiter.mclk_over_drive;
3620 }
3621
3622 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3623 hwmgr->platform_descriptor.platformCaps,
3624 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3625
36e6b912 3626
a23eefa2
RZ		 3627 disable_mclk_switching = (1 < info.display_count) ||
3628 disable_mclk_switching_for_frame_lock;
3629
2cc0c0b5
FC		 3630 sclk = polaris10_ps->performance_levels[0].engine_clock;
3631 mclk = polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3632
3633 if (disable_mclk_switching)
2cc0c0b5
FC		 3634 mclk = polaris10_ps->performance_levels
3635 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 3636
3637 if (sclk < minimum_clocks.engineClock)
3638 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3639 max_limits->sclk : minimum_clocks.engineClock;
3640
3641 if (mclk < minimum_clocks.memoryClock)
3642 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3643 max_limits->mclk : minimum_clocks.memoryClock;
3644
2cc0c0b5
FC		 3645 polaris10_ps->performance_levels[0].engine_clock = sclk;
3646 polaris10_ps->performance_levels[0].memory_clock = mclk;
a23eefa2 3647
2cc0c0b5
FC		 3648 polaris10_ps->performance_levels[1].engine_clock =
3649 (polaris10_ps->performance_levels[1].engine_clock >=
3650 polaris10_ps->performance_levels[0].engine_clock) ?
3651 polaris10_ps->performance_levels[1].engine_clock :
3652 polaris10_ps->performance_levels[0].engine_clock;
a23eefa2
RZ		 3653
3654 if (disable_mclk_switching) {
2cc0c0b5
FC		 3655 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3656 mclk = polaris10_ps->performance_levels[1].memory_clock;
a23eefa2 3657
2cc0c0b5
FC		 3658 polaris10_ps->performance_levels[0].memory_clock = mclk;
3659 polaris10_ps->performance_levels[1].memory_clock = mclk;
a23eefa2 3660 } else {
2cc0c0b5
FC		 3661 if (polaris10_ps->performance_levels[1].memory_clock <
3662 polaris10_ps->performance_levels[0].memory_clock)
3663 polaris10_ps->performance_levels[1].memory_clock =
3664 polaris10_ps->performance_levels[0].memory_clock;
a23eefa2
RZ		 3665 }
3666
3667 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3668 PHM_PlatformCaps_StablePState)) {
2cc0c0b5
FC		 3669 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3670 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3671 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3672 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3673 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
a23eefa2
RZ		 3674 }
3675 }
3676 return 0;
3677}
3678
3679
2cc0c0b5 3680static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3681{
3682 struct pp_power_state *ps;
2cc0c0b5 3683 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3684
3685 if (hwmgr == NULL)
3686 return -EINVAL;
3687
3688 ps = hwmgr->request_ps;
3689
3690 if (ps == NULL)
3691 return -EINVAL;
3692
2cc0c0b5 3693 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3694
3695 if (low)
2cc0c0b5 3696 return polaris10_ps->performance_levels[0].memory_clock;
a23eefa2 3697 else
2cc0c0b5
FC		 3698 return polaris10_ps->performance_levels
3699 [polaris10_ps->performance_level_count-1].memory_clock;
a23eefa2
RZ		 3700}
3701
2cc0c0b5 3702static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
a23eefa2
RZ		 3703{
3704 struct pp_power_state *ps;
2cc0c0b5 3705 struct polaris10_power_state *polaris10_ps;
a23eefa2
RZ		 3706
3707 if (hwmgr == NULL)
3708 return -EINVAL;
3709
3710 ps = hwmgr->request_ps;
3711
3712 if (ps == NULL)
3713 return -EINVAL;
3714
2cc0c0b5 3715 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
a23eefa2
RZ		 3716
3717 if (low)
2cc0c0b5 3718 return polaris10_ps->performance_levels[0].engine_clock;
a23eefa2 3719 else
2cc0c0b5
FC		 3720 return polaris10_ps->performance_levels
3721 [polaris10_ps->performance_level_count-1].engine_clock;
a23eefa2
RZ		 3722}
3723
2cc0c0b5 3724static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3725 struct pp_hw_power_state *hw_ps)
3726{
2cc0c0b5
FC		 3727 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3728 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
a23eefa2
RZ		 3729 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3730 uint16_t size;
3731 uint8_t frev, crev;
3732 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3733
3734 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3735 * We assume here that fw_info is unchanged if this call fails.
3736 */
3737 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3738 hwmgr->device, index,
3739 &size, &frev, &crev);
3740 if (!fw_info)
3741 /* During a test, there is no firmware info table. */
3742 return 0;
3743
3744 /* Patch the state. */
3745 data->vbios_boot_state.sclk_bootup_value =
3746 le32_to_cpu(fw_info->ulDefaultEngineClock);
3747 data->vbios_boot_state.mclk_bootup_value =
3748 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3749 data->vbios_boot_state.mvdd_bootup_value =
3750 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3751 data->vbios_boot_state.vddc_bootup_value =
3752 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3753 data->vbios_boot_state.vddci_bootup_value =
3754 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3755 data->vbios_boot_state.pcie_gen_bootup_value =
3756 phm_get_current_pcie_speed(hwmgr);
3757
3758 data->vbios_boot_state.pcie_lane_bootup_value =
3759 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3760
3761 /* set boot power state */
3762 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3763 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3764 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3765 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3766
3767 return 0;
3768}
3769
2cc0c0b5 3770static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3771 void *state, struct pp_power_state *power_state,
3772 void *pp_table, uint32_t classification_flag)
3773{
2cc0c0b5
FC		 3774 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3775 struct polaris10_power_state *polaris10_power_state =
3776 (struct polaris10_power_state *)(&(power_state->hardware));
3777 struct polaris10_performance_level *performance_level;
a23eefa2
RZ		 3778 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3779 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3780 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3ff21127
RZ		 3781 PPTable_Generic_SubTable_Header *sclk_dep_table =
3782 (PPTable_Generic_SubTable_Header *)
a23eefa2
RZ		 3783 (((unsigned long)powerplay_table) +
3784 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3ff21127 3785
a23eefa2
RZ		 3786 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3787 (ATOM_Tonga_MCLK_Dependency_Table *)
3788 (((unsigned long)powerplay_table) +
3789 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3790
3791 /* The following fields are not initialized here: id orderedList allStatesList */
3792 power_state->classification.ui_label =
3793 (le16_to_cpu(state_entry->usClassification) &
3794 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3795 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3796 power_state->classification.flags = classification_flag;
3797 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3798
3799 power_state->classification.temporary_state = false;
3800 power_state->classification.to_be_deleted = false;
3801
3802 power_state->validation.disallowOnDC =
3803 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3804 ATOM_Tonga_DISALLOW_ON_DC));
3805
3806 power_state->pcie.lanes = 0;
3807
3808 power_state->display.disableFrameModulation = false;
3809 power_state->display.limitRefreshrate = false;
3810 power_state->display.enableVariBright =
3811 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3812 ATOM_Tonga_ENABLE_VARIBRIGHT));
3813
3814 power_state->validation.supportedPowerLevels = 0;
3815 power_state->uvd_clocks.VCLK = 0;
3816 power_state->uvd_clocks.DCLK = 0;
3817 power_state->temperatures.min = 0;
3818 power_state->temperatures.max = 0;
3819
2cc0c0b5
FC		 3820 performance_level = &(polaris10_power_state->performance_levels
3821 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3822
3823 PP_ASSERT_WITH_CODE(
2cc0c0b5 3824 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
a23eefa2
RZ		 3825 "Performance levels exceeds SMC limit!",
3826 return -1);
3827
3828 PP_ASSERT_WITH_CODE(
2cc0c0b5 3829 (polaris10_power_state->performance_level_count <=
a23eefa2
RZ		 3830 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3831 "Performance levels exceeds Driver limit!",
3832 return -1);
3833
3834 /* Performance levels are arranged from low to high. */
3835 performance_level->memory_clock = mclk_dep_table->entries
3836 [state_entry->ucMemoryClockIndexLow].ulMclk;
3ff21127
RZ		 3837 if (sclk_dep_table->ucRevId == 0)
3838 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3839 [state_entry->ucEngineClockIndexLow].ulSclk;
3840 else if (sclk_dep_table->ucRevId == 1)
3841 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
a23eefa2
RZ		 3842 [state_entry->ucEngineClockIndexLow].ulSclk;
3843 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3844 state_entry->ucPCIEGenLow);
3845 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3846 state_entry->ucPCIELaneHigh);
3847
2cc0c0b5
FC		 3848 performance_level = &(polaris10_power_state->performance_levels
3849 [polaris10_power_state->performance_level_count++]);
a23eefa2
RZ		 3850 performance_level->memory_clock = mclk_dep_table->entries
3851 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3ff21127
RZ		 3852
3853 if (sclk_dep_table->ucRevId == 0)
3854 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3855 [state_entry->ucEngineClockIndexHigh].ulSclk;
3856 else if (sclk_dep_table->ucRevId == 1)
3857 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
a23eefa2 3858 [state_entry->ucEngineClockIndexHigh].ulSclk;
3ff21127 3859
a23eefa2
RZ		 3860 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3861 state_entry->ucPCIEGenHigh);
3862 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3863 state_entry->ucPCIELaneHigh);
3864
3865 return 0;
3866}
3867
2cc0c0b5 3868static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 3869 unsigned long entry_index, struct pp_power_state *state)
3870{
3871 int result;
2cc0c0b5
FC		 3872 struct polaris10_power_state *ps;
3873 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3874 struct phm_ppt_v1_information *table_info =
3875 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3876 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3877 table_info->vdd_dep_on_mclk;
3878
3879 state->hardware.magic = PHM_VIslands_Magic;
3880
2cc0c0b5 3881 ps = (struct polaris10_power_state *)(&state->hardware);
a23eefa2
RZ		 3882
3883 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
2cc0c0b5 3884 polaris10_get_pp_table_entry_callback_func);
a23eefa2
RZ		 3885
3886 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3887 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3888 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3889 */
3890 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3891 if (dep_mclk_table->entries[0].clk !=
3892 data->vbios_boot_state.mclk_bootup_value)
3893 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3894 "does not match VBIOS boot MCLK level");
3895 if (dep_mclk_table->entries[0].vddci !=
3896 data->vbios_boot_state.vddci_bootup_value)
3897 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3898 "does not match VBIOS boot VDDCI level");
3899 }
3900
3901 /* set DC compatible flag if this state supports DC */
3902 if (!state->validation.disallowOnDC)
3903 ps->dc_compatible = true;
3904
3905 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3906 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3907
3908 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3909 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3910
3911 if (!result) {
3912 uint32_t i;
3913
3914 switch (state->classification.ui_label) {
3915 case PP_StateUILabel_Performance:
3916 data->use_pcie_performance_levels = true;
a23eefa2
RZ		 3917 for (i = 0; i < ps->performance_level_count; i++) {
3918 if (data->pcie_gen_performance.max <
3919 ps->performance_levels[i].pcie_gen)
3920 data->pcie_gen_performance.max =
3921 ps->performance_levels[i].pcie_gen;
3922
3923 if (data->pcie_gen_performance.min >
3924 ps->performance_levels[i].pcie_gen)
3925 data->pcie_gen_performance.min =
3926 ps->performance_levels[i].pcie_gen;
3927
3928 if (data->pcie_lane_performance.max <
3929 ps->performance_levels[i].pcie_lane)
3930 data->pcie_lane_performance.max =
3931 ps->performance_levels[i].pcie_lane;
a23eefa2
RZ		 3932 if (data->pcie_lane_performance.min >
3933 ps->performance_levels[i].pcie_lane)
3934 data->pcie_lane_performance.min =
3935 ps->performance_levels[i].pcie_lane;
3936 }
3937 break;
3938 case PP_StateUILabel_Battery:
3939 data->use_pcie_power_saving_levels = true;
3940
3941 for (i = 0; i < ps->performance_level_count; i++) {
3942 if (data->pcie_gen_power_saving.max <
3943 ps->performance_levels[i].pcie_gen)
3944 data->pcie_gen_power_saving.max =
3945 ps->performance_levels[i].pcie_gen;
3946
3947 if (data->pcie_gen_power_saving.min >
3948 ps->performance_levels[i].pcie_gen)
3949 data->pcie_gen_power_saving.min =
3950 ps->performance_levels[i].pcie_gen;
3951
3952 if (data->pcie_lane_power_saving.max <
3953 ps->performance_levels[i].pcie_lane)
3954 data->pcie_lane_power_saving.max =
3955 ps->performance_levels[i].pcie_lane;
3956
3957 if (data->pcie_lane_power_saving.min >
3958 ps->performance_levels[i].pcie_lane)
3959 data->pcie_lane_power_saving.min =
3960 ps->performance_levels[i].pcie_lane;
3961 }
3962 break;
3963 default:
3964 break;
3965 }
3966 }
3967 return 0;
3968}
3969
3970static void
2cc0c0b5 3971polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
a23eefa2 3972{
b2d96143
RZ		 3973 uint32_t sclk, mclk, activity_percent;
3974 uint32_t offset;
3975 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 3976
3977 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3978
3979 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3980
3981 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3982
3983 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3984 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3985 mclk / 100, sclk / 100);
b2d96143
RZ		 3986
3987 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3988 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3989 activity_percent += 0x80;
3990 activity_percent >>= 8;
3991
3992 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3993
3994 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3995
3996 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
a23eefa2
RZ		 3997}
3998
2cc0c0b5 3999static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4000{
4001 const struct phm_set_power_state_input *states =
4002 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4003 const struct polaris10_power_state *polaris10_ps =
4004 cast_const_phw_polaris10_power_state(states->pnew_state);
4005 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4006 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4007 uint32_t sclk = polaris10_ps->performance_levels
4008 [polaris10_ps->performance_level_count - 1].engine_clock;
4009 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4010 uint32_t mclk = polaris10_ps->performance_levels
4011 [polaris10_ps->performance_level_count - 1].memory_clock;
a23eefa2
RZ		 4012 struct PP_Clocks min_clocks = {0};
4013 uint32_t i;
4014 struct cgs_display_info info = {0};
4015
4016 data->need_update_smu7_dpm_table = 0;
4017
4018 for (i = 0; i < sclk_table->count; i++) {
4019 if (sclk == sclk_table->dpm_levels[i].value)
4020 break;
4021 }
4022
4023 if (i >= sclk_table->count)
4024 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4025 else {
4026 /* TODO: Check SCLK in DAL's minimum clocks
4027 * in case DeepSleep divider update is required.
4028 */
2cc0c0b5
FC		 4029 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
4030 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4031 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 4032 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4033 }
4034
4035 for (i = 0; i < mclk_table->count; i++) {
4036 if (mclk == mclk_table->dpm_levels[i].value)
4037 break;
4038 }
4039
4040 if (i >= mclk_table->count)
4041 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4042
4043 cgs_get_active_displays_info(hwmgr->device, &info);
4044
4045 if (data->display_timing.num_existing_displays != info.display_count)
4046 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4047
4048 return 0;
4049}
4050
2cc0c0b5
FC		 4051static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4052 const struct polaris10_power_state *polaris10_ps)
a23eefa2
RZ		 4053{
4054 uint32_t i;
4055 uint32_t sclk, max_sclk = 0;
2cc0c0b5
FC		 4056 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4057 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
a23eefa2 4058
2cc0c0b5
FC		 4059 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
4060 sclk = polaris10_ps->performance_levels[i].engine_clock;
a23eefa2
RZ		 4061 if (max_sclk < sclk)
4062 max_sclk = sclk;
4063 }
4064
4065 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4066 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4067 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4068 dpm_table->pcie_speed_table.dpm_levels
4069 [dpm_table->pcie_speed_table.count - 1].value :
4070 dpm_table->pcie_speed_table.dpm_levels[i].value);
4071 }
4072
4073 return 0;
4074}
4075
2cc0c0b5 4076static int polaris10_request_link_speed_change_before_state_change(
a23eefa2
RZ		 4077 struct pp_hwmgr *hwmgr, const void *input)
4078{
4079 const struct phm_set_power_state_input *states =
4080 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4081 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4082 const struct polaris10_power_state *polaris10_nps =
4083 cast_const_phw_polaris10_power_state(states->pnew_state);
4084 const struct polaris10_power_state *polaris10_cps =
4085 cast_const_phw_polaris10_power_state(states->pcurrent_state);
a23eefa2 4086
2cc0c0b5 4087 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
a23eefa2
RZ		 4088 uint16_t current_link_speed;
4089
4090 if (data->force_pcie_gen == PP_PCIEGenInvalid)
2cc0c0b5 4091 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
a23eefa2
RZ		 4092 else
4093 current_link_speed = data->force_pcie_gen;
4094
4095 data->force_pcie_gen = PP_PCIEGenInvalid;
4096 data->pspp_notify_required = false;
4097
4098 if (target_link_speed > current_link_speed) {
4099 switch (target_link_speed) {
4100 case PP_PCIEGen3:
4101 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4102 break;
4103 data->force_pcie_gen = PP_PCIEGen2;
4104 if (current_link_speed == PP_PCIEGen2)
4105 break;
4106 case PP_PCIEGen2:
4107 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4108 break;
4109 default:
4110 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
4111 break;
4112 }
4113 } else {
4114 if (target_link_speed < current_link_speed)
4115 data->pspp_notify_required = true;
4116 }
4117
4118 return 0;
4119}
4120
2cc0c0b5 4121static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 4122{
2cc0c0b5 4123 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4124
4125 if (0 == data->need_update_smu7_dpm_table)
4126 return 0;
4127
4128 if ((0 == data->sclk_dpm_key_disabled) &&
4129 (data->need_update_smu7_dpm_table &
4130 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4ba27f9b
EC		 4131 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4132 "Trying to freeze SCLK DPM when DPM is disabled",
a23eefa2
RZ		 4133 );
4134 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4135 PPSMC_MSG_SCLKDPM_FreezeLevel),
4136 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4137 return -1);
4138 }
4139
4140 if ((0 == data->mclk_dpm_key_disabled) &&
4141 (data->need_update_smu7_dpm_table &
4142 DPMTABLE_OD_UPDATE_MCLK)) {
4ba27f9b
EC		 4143 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4144 "Trying to freeze MCLK DPM when DPM is disabled",
a23eefa2
RZ		 4145 );
4146 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4147 PPSMC_MSG_MCLKDPM_FreezeLevel),
4148 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4149 return -1);
4150 }
4151
4152 return 0;
4153}
4154
2cc0c0b5 4155static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
a23eefa2
RZ		 4156 struct pp_hwmgr *hwmgr, const void *input)
4157{
4158 int result = 0;
4159 const struct phm_set_power_state_input *states =
4160 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4161 const struct polaris10_power_state *polaris10_ps =
4162 cast_const_phw_polaris10_power_state(states->pnew_state);
4163 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4164 uint32_t sclk = polaris10_ps->performance_levels
4165 [polaris10_ps->performance_level_count - 1].engine_clock;
4166 uint32_t mclk = polaris10_ps->performance_levels
4167 [polaris10_ps->performance_level_count - 1].memory_clock;
4168 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4169
4170 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
a23eefa2
RZ		 4171 uint32_t dpm_count, clock_percent;
4172 uint32_t i;
4173
4174 if (0 == data->need_update_smu7_dpm_table)
4175 return 0;
4176
4177 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4178 dpm_table->sclk_table.dpm_levels
4179 [dpm_table->sclk_table.count - 1].value = sclk;
4180
4181 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4182 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4183 /* Need to do calculation based on the golden DPM table
4184 * as the Heatmap GPU Clock axis is also based on the default values
4185 */
4186 PP_ASSERT_WITH_CODE(
4187 (golden_dpm_table->sclk_table.dpm_levels
4188 [golden_dpm_table->sclk_table.count - 1].value != 0),
4189 "Divide by 0!",
4190 return -1);
4191 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4192
4193 for (i = dpm_count; i > 1; i--) {
4194 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4195 clock_percent =
4196 ((sclk
4197 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4198 ) * 100)
4199 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4200
4201 dpm_table->sclk_table.dpm_levels[i].value =
4202 golden_dpm_table->sclk_table.dpm_levels[i].value +
4203 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4204 clock_percent)/100;
4205
4206 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4207 clock_percent =
4208 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4209 - sclk) * 100)
4210 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4211
4212 dpm_table->sclk_table.dpm_levels[i].value =
4213 golden_dpm_table->sclk_table.dpm_levels[i].value -
4214 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4215 clock_percent) / 100;
4216 } else
4217 dpm_table->sclk_table.dpm_levels[i].value =
4218 golden_dpm_table->sclk_table.dpm_levels[i].value;
4219 }
4220 }
4221 }
4222
4223 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4224 dpm_table->mclk_table.dpm_levels
4225 [dpm_table->mclk_table.count - 1].value = mclk;
4226
4227 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4228 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4229
4230 PP_ASSERT_WITH_CODE(
4231 (golden_dpm_table->mclk_table.dpm_levels
4232 [golden_dpm_table->mclk_table.count-1].value != 0),
4233 "Divide by 0!",
4234 return -1);
4235 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4236 for (i = dpm_count; i > 1; i--) {
4237 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4238 clock_percent = ((mclk -
4239 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4240 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4241
4242 dpm_table->mclk_table.dpm_levels[i].value =
4243 golden_dpm_table->mclk_table.dpm_levels[i].value +
4244 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4245 clock_percent) / 100;
4246
4247 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4248 clock_percent = (
4249 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4250 * 100)
4251 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4252
4253 dpm_table->mclk_table.dpm_levels[i].value =
4254 golden_dpm_table->mclk_table.dpm_levels[i].value -
4255 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4256 clock_percent) / 100;
4257 } else
4258 dpm_table->mclk_table.dpm_levels[i].value =
4259 golden_dpm_table->mclk_table.dpm_levels[i].value;
4260 }
4261 }
4262 }
4263
4264 if (data->need_update_smu7_dpm_table &
4265 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
2cc0c0b5 4266 result = polaris10_populate_all_graphic_levels(hwmgr);
a23eefa2
RZ		 4267 PP_ASSERT_WITH_CODE((0 == result),
4268 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4269 return result);
4270 }
4271
4272 if (data->need_update_smu7_dpm_table &
4273 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4274 /*populate MCLK dpm table to SMU7 */
2cc0c0b5 4275 result = polaris10_populate_all_memory_levels(hwmgr);
a23eefa2
RZ		 4276 PP_ASSERT_WITH_CODE((0 == result),
4277 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4278 return result);
4279 }
4280
4281 return result;
4282}
4283
2cc0c0b5
FC		 4284static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4285 struct polaris10_single_dpm_table *dpm_table,
a23eefa2
RZ		 4286 uint32_t low_limit, uint32_t high_limit)
4287{
4288 uint32_t i;
a23eefa2
RZ		 4289
4290 for (i = 0; i < dpm_table->count; i++) {
4291 if ((dpm_table->dpm_levels[i].value < low_limit)
4292 || (dpm_table->dpm_levels[i].value > high_limit))
4293 dpm_table->dpm_levels[i].enabled = false;
a23eefa2
RZ		 4294 else
4295 dpm_table->dpm_levels[i].enabled = true;
4296 }
4297
4298 return 0;
4299}
4300
2cc0c0b5
FC		 4301static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4302 const struct polaris10_power_state *polaris10_ps)
a23eefa2 4303{
2cc0c0b5 4304 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4305 uint32_t high_limit_count;
4306
2cc0c0b5 4307 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
a23eefa2
RZ		 4308 "power state did not have any performance level",
4309 return -1);
4310
2cc0c0b5 4311 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
a23eefa2 4312
2cc0c0b5 4313 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4314 &(data->dpm_table.sclk_table),
2cc0c0b5
FC		 4315 polaris10_ps->performance_levels[0].engine_clock,
4316 polaris10_ps->performance_levels[high_limit_count].engine_clock);
a23eefa2 4317
2cc0c0b5 4318 polaris10_trim_single_dpm_states(hwmgr,
a23eefa2 4319 &(data->dpm_table.mclk_table),
2cc0c0b5
FC		 4320 polaris10_ps->performance_levels[0].memory_clock,
4321 polaris10_ps->performance_levels[high_limit_count].memory_clock);
a23eefa2 4322
538f1ef3 4323 return 0;
a23eefa2
RZ		 4324}
4325
2cc0c0b5 4326static int polaris10_generate_dpm_level_enable_mask(
a23eefa2
RZ		 4327 struct pp_hwmgr *hwmgr, const void *input)
4328{
4329 int result;
4330 const struct phm_set_power_state_input *states =
4331 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4332 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4333 const struct polaris10_power_state *polaris10_ps =
4334 cast_const_phw_polaris10_power_state(states->pnew_state);
a23eefa2 4335
2cc0c0b5 4336 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
a23eefa2
RZ		 4337 if (result)
4338 return result;
4339
4340 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4341 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4342 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4343 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4344 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4345 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4346
4347 return 0;
4348}
4349
2cc0c0b5 4350int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
a23eefa2
RZ		 4351{
4352 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
92c6d645
EH		 4353 PPSMC_MSG_UVDDPM_Enable :
4354 PPSMC_MSG_UVDDPM_Disable);
4355}
4356
2cc0c0b5 4357int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4358{
4359 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
a23eefa2
RZ		 4360 PPSMC_MSG_VCEDPM_Enable :
4361 PPSMC_MSG_VCEDPM_Disable);
4362}
4363
2cc0c0b5 4364int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
92c6d645
EH		 4365{
4366 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4367 PPSMC_MSG_SAMUDPM_Enable :
4368 PPSMC_MSG_SAMUDPM_Disable);
4369}
4370
2cc0c0b5 4371int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4372{
2cc0c0b5 4373 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645
EH		 4374 uint32_t mm_boot_level_offset, mm_boot_level_value;
4375 struct phm_ppt_v1_information *table_info =
4376 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4377
4378 if (!bgate) {
4379 data->smc_state_table.UvdBootLevel = 0;
4380 if (table_info->mm_dep_table->count > 0)
4381 data->smc_state_table.UvdBootLevel =
4382 (uint8_t) (table_info->mm_dep_table->count - 1);
4383 mm_boot_level_offset = data->dpm_table_start +
4384 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4385 mm_boot_level_offset /= 4;
4386 mm_boot_level_offset *= 4;
4387 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4388 CGS_IND_REG__SMC, mm_boot_level_offset);
4389 mm_boot_level_value &= 0x00FFFFFF;
4390 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4391 cgs_write_ind_register(hwmgr->device,
4392 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4393
4394 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4395 PHM_PlatformCaps_UVDDPM) ||
4396 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4397 PHM_PlatformCaps_StablePState))
4398 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4399 PPSMC_MSG_UVDDPM_SetEnabledMask,
4400 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4401 }
4402
2cc0c0b5 4403 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
92c6d645
EH		 4404}
4405
990c70ad 4406int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
a23eefa2 4407{
2cc0c0b5 4408 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4409 uint32_t mm_boot_level_offset, mm_boot_level_value;
4410 struct phm_ppt_v1_information *table_info =
4411 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4412
990c70ad
RZ		 4413 if (!bgate) {
4414 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4415 PHM_PlatformCaps_StablePState))
4416 data->smc_state_table.VceBootLevel =
a23eefa2 4417 (uint8_t) (table_info->mm_dep_table->count - 1);
990c70ad
RZ		 4418 else
4419 data->smc_state_table.VceBootLevel = 0;
a23eefa2
RZ		 4420
4421 mm_boot_level_offset = data->dpm_table_start +
4422 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4423 mm_boot_level_offset /= 4;
4424 mm_boot_level_offset *= 4;
4425 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4426 CGS_IND_REG__SMC, mm_boot_level_offset);
4427 mm_boot_level_value &= 0xFF00FFFF;
4428 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4429 cgs_write_ind_register(hwmgr->device,
4430 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4431
990c70ad 4432 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
a23eefa2
RZ		 4433 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4434 PPSMC_MSG_VCEDPM_SetEnabledMask,
4435 (uint32_t)1 << data->smc_state_table.VceBootLevel);
a23eefa2
RZ		 4436 }
4437
990c70ad
RZ		 4438 polaris10_enable_disable_vce_dpm(hwmgr, !bgate);
4439
a23eefa2
RZ		 4440 return 0;
4441}
4442
2cc0c0b5 4443int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
92c6d645 4444{
2cc0c0b5 4445 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
92c6d645 4446 uint32_t mm_boot_level_offset, mm_boot_level_value;
92c6d645
EH		 4447
4448 if (!bgate) {
871fd840 4449 data->smc_state_table.SamuBootLevel = 0;
92c6d645
EH		 4450 mm_boot_level_offset = data->dpm_table_start +
4451 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4452 mm_boot_level_offset /= 4;
4453 mm_boot_level_offset *= 4;
4454 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4455 CGS_IND_REG__SMC, mm_boot_level_offset);
4456 mm_boot_level_value &= 0xFFFFFF00;
4457 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4458 cgs_write_ind_register(hwmgr->device,
4459 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4460
4461 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4462 PHM_PlatformCaps_StablePState))
4463 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4464 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4465 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4466 }
4467
2cc0c0b5 4468 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
92c6d645
EH		 4469}
4470
2cc0c0b5 4471static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4472{
2cc0c0b5 4473 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4474
4475 int result = 0;
4476 uint32_t low_sclk_interrupt_threshold = 0;
4477
4478 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4479 PHM_PlatformCaps_SclkThrottleLowNotification)
4480 && (hwmgr->gfx_arbiter.sclk_threshold !=
4481 data->low_sclk_interrupt_threshold)) {
4482 data->low_sclk_interrupt_threshold =
4483 hwmgr->gfx_arbiter.sclk_threshold;
4484 low_sclk_interrupt_threshold =
4485 data->low_sclk_interrupt_threshold;
4486
4487 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4488
2cc0c0b5 4489 result = polaris10_copy_bytes_to_smc(
a23eefa2
RZ		 4490 hwmgr->smumgr,
4491 data->dpm_table_start +
4492 offsetof(SMU74_Discrete_DpmTable,
4493 LowSclkInterruptThreshold),
4494 (uint8_t *)&low_sclk_interrupt_threshold,
4495 sizeof(uint32_t),
4496 data->sram_end);
4497 }
4498
4499 return result;
4500}
4501
2cc0c0b5 4502static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
a23eefa2 4503{
2cc0c0b5 4504 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4505
4506 if (data->need_update_smu7_dpm_table &
4507 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2cc0c0b5 4508 return polaris10_program_memory_timing_parameters(hwmgr);
a23eefa2
RZ		 4509
4510 return 0;
4511}
4512
2cc0c0b5 4513static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
a23eefa2 4514{
2cc0c0b5 4515 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4516
4517 if (0 == data->need_update_smu7_dpm_table)
4518 return 0;
4519
4520 if ((0 == data->sclk_dpm_key_disabled) &&
4521 (data->need_update_smu7_dpm_table &
4522 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4523
4ba27f9b
EC		 4524 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4525 "Trying to Unfreeze SCLK DPM when DPM is disabled",
a23eefa2
RZ		 4526 );
4527 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4528 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4529 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4530 return -1);
4531 }
4532
4533 if ((0 == data->mclk_dpm_key_disabled) &&
4534 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4535
4ba27f9b
EC		 4536 PP_ASSERT_WITH_CODE(polaris10_is_dpm_running(hwmgr),
4537 "Trying to Unfreeze MCLK DPM when DPM is disabled",
a23eefa2
RZ		 4538 );
4539 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4540 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4541 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4542 return -1);
4543 }
4544
4545 data->need_update_smu7_dpm_table = 0;
4546
4547 return 0;
4548}
4549
2cc0c0b5 4550static int polaris10_notify_link_speed_change_after_state_change(
a23eefa2
RZ		 4551 struct pp_hwmgr *hwmgr, const void *input)
4552{
4553 const struct phm_set_power_state_input *states =
4554 (const struct phm_set_power_state_input *)input;
2cc0c0b5
FC		 4555 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4556 const struct polaris10_power_state *polaris10_ps =
4557 cast_const_phw_polaris10_power_state(states->pnew_state);
4558 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
a23eefa2
RZ		 4559 uint8_t request;
4560
4561 if (data->pspp_notify_required) {
4562 if (target_link_speed == PP_PCIEGen3)
4563 request = PCIE_PERF_REQ_GEN3;
4564 else if (target_link_speed == PP_PCIEGen2)
4565 request = PCIE_PERF_REQ_GEN2;
4566 else
4567 request = PCIE_PERF_REQ_GEN1;
4568
4569 if (request == PCIE_PERF_REQ_GEN1 &&
4570 phm_get_current_pcie_speed(hwmgr) > 0)
4571 return 0;
4572
4573 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4574 if (PP_PCIEGen2 == target_link_speed)
4575 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4576 else
4577 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4578 }
4579 }
4580
4581 return 0;
4582}
4583
83a7af6d
RZ		 4584static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr)
4585{
4586 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4587
4588 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4589 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2);
4590 return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL;
4591}
4592
36e6b912
RZ		 4593
4594
2cc0c0b5 4595static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
a23eefa2
RZ		 4596{
4597 int tmp_result, result = 0;
2cc0c0b5 4598 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2 4599
2cc0c0b5 4600 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
a23eefa2
RZ		 4601 PP_ASSERT_WITH_CODE((0 == tmp_result),
4602 "Failed to find DPM states clocks in DPM table!",
4603 result = tmp_result);
4604
4605 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4606 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4607 tmp_result =
2cc0c0b5 4608 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
a23eefa2
RZ		 4609 PP_ASSERT_WITH_CODE((0 == tmp_result),
4610 "Failed to request link speed change before state change!",
4611 result = tmp_result);
4612 }
4613
2cc0c0b5 4614 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4615 PP_ASSERT_WITH_CODE((0 == tmp_result),
4616 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4617
2cc0c0b5 4618 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
a23eefa2
RZ		 4619 PP_ASSERT_WITH_CODE((0 == tmp_result),
4620 "Failed to populate and upload SCLK MCLK DPM levels!",
4621 result = tmp_result);
4622
2cc0c0b5 4623 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
a23eefa2
RZ		 4624 PP_ASSERT_WITH_CODE((0 == tmp_result),
4625 "Failed to generate DPM level enabled mask!",
4626 result = tmp_result);
4627
2cc0c0b5 4628 tmp_result = polaris10_update_sclk_threshold(hwmgr);
a23eefa2
RZ		 4629 PP_ASSERT_WITH_CODE((0 == tmp_result),
4630 "Failed to update SCLK threshold!",
4631 result = tmp_result);
4632
2cc0c0b5 4633 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
a23eefa2
RZ		 4634 PP_ASSERT_WITH_CODE((0 == tmp_result),
4635 "Failed to program memory timing parameters!",
4636 result = tmp_result);
4637
83a7af6d
RZ		 4638 tmp_result = polaris10_notify_smc_display(hwmgr);
4639 PP_ASSERT_WITH_CODE((0 == tmp_result),
4640 "Failed to notify smc display settings!",
4641 result = tmp_result);
4642
2cc0c0b5 4643 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
a23eefa2
RZ		 4644 PP_ASSERT_WITH_CODE((0 == tmp_result),
4645 "Failed to unfreeze SCLK MCLK DPM!",
4646 result = tmp_result);
4647
2cc0c0b5 4648 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
a23eefa2
RZ		 4649 PP_ASSERT_WITH_CODE((0 == tmp_result),
4650 "Failed to upload DPM level enabled mask!",
4651 result = tmp_result);
4652
4653 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4654 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4655 tmp_result =
2cc0c0b5 4656 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
a23eefa2
RZ		 4657 PP_ASSERT_WITH_CODE((0 == tmp_result),
4658 "Failed to notify link speed change after state change!",
4659 result = tmp_result);
4660 }
4661 data->apply_optimized_settings = false;
4662 return result;
4663}
4664
2cc0c0b5 4665static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
a23eefa2 4666{
eede5262
EH		 4667 hwmgr->thermal_controller.
4668 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
a23eefa2 4669
eede5262 4670 if (phm_is_hw_access_blocked(hwmgr))
a23eefa2 4671 return 0;
eede5262
EH		 4672
4673 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4674 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
a23eefa2
RZ		 4675}
4676
83a7af6d 4677
2cc0c0b5 4678int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
a23eefa2
RZ		 4679{
4680 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4681
4682 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4683}
4684
2cc0c0b5 4685int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4686{
4687 uint32_t num_active_displays = 0;
4688 struct cgs_display_info info = {0};
4689 info.mode_info = NULL;
4690
4691 cgs_get_active_displays_info(hwmgr->device, &info);
4692
4693 num_active_displays = info.display_count;
4694
4695 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
2cc0c0b5 4696 polaris10_notify_smc_display_change(hwmgr, false);
a23eefa2 4697
36e6b912 4698
a23eefa2
RZ		 4699 return 0;
4700}
4701
4702/**
4703* Programs the display gap
4704*
4705* @param hwmgr the address of the powerplay hardware manager.
4706* @return always OK
4707*/
2cc0c0b5 4708int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
a23eefa2 4709{
2cc0c0b5 4710 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4711 uint32_t num_active_displays = 0;
4712 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4713 uint32_t display_gap2;
4714 uint32_t pre_vbi_time_in_us;
4715 uint32_t frame_time_in_us;
4716 uint32_t ref_clock;
4717 uint32_t refresh_rate = 0;
4718 struct cgs_display_info info = {0};
4719 struct cgs_mode_info mode_info;
4720
4721 info.mode_info = &mode_info;
4722
4723 cgs_get_active_displays_info(hwmgr->device, &info);
4724 num_active_displays = info.display_count;
4725
4726 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4727 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4728
4729 ref_clock = mode_info.ref_clock;
4730 refresh_rate = mode_info.refresh_rate;
4731
4732 if (0 == refresh_rate)
4733 refresh_rate = 60;
4734
4735 frame_time_in_us = 1000000 / refresh_rate;
4736
4737 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
83a7af6d
RZ		 4738 data->frame_time_x2 = frame_time_in_us * 2 / 100;
4739
a23eefa2
RZ		 4740 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4741
4742 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4743
4744 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4745
4746 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4747
36e6b912 4748
a23eefa2
RZ		 4749 return 0;
4750}
4751
4752
2cc0c0b5 4753int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
a23eefa2 4754{
2cc0c0b5 4755 return polaris10_program_display_gap(hwmgr);
a23eefa2
RZ		 4756}
4757
4758/**
4759* Set maximum target operating fan output RPM
4760*
4761* @param hwmgr: the address of the powerplay hardware manager.
4762* @param usMaxFanRpm: max operating fan RPM value.
4763* @return The response that came from the SMC.
4764*/
2cc0c0b5 4765static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
a23eefa2 4766{
eede5262
EH		 4767 hwmgr->thermal_controller.
4768 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4769
4770 if (phm_is_hw_access_blocked(hwmgr))
4771 return 0;
4772
4773 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4774 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
a23eefa2
RZ		 4775}
4776
2cc0c0b5 4777int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
a23eefa2
RZ		 4778 const void *thermal_interrupt_info)
4779{
4780 return 0;
4781}
4782
2cc0c0b5 4783bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
a23eefa2 4784{
2cc0c0b5 4785 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4786 bool is_update_required = false;
4787 struct cgs_display_info info = {0, 0, NULL};
4788
4789 cgs_get_active_displays_info(hwmgr->device, &info);
4790
4791 if (data->display_timing.num_existing_displays != info.display_count)
4792 is_update_required = true;
4793/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4794 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4795 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
2cc0c0b5
FC		 4796 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4797 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4798 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
a23eefa2
RZ		 4799 is_update_required = true;
4800*/
4801 return is_update_required;
4802}
4803
2cc0c0b5
FC		 4804static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4805 const struct polaris10_performance_level *pl2)
a23eefa2
RZ		 4806{
4807 return ((pl1->memory_clock == pl2->memory_clock) &&
4808 (pl1->engine_clock == pl2->engine_clock) &&
4809 (pl1->pcie_gen == pl2->pcie_gen) &&
4810 (pl1->pcie_lane == pl2->pcie_lane));
4811}
4812
2cc0c0b5 4813int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
a23eefa2 4814{
2cc0c0b5
FC		 4815 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4816 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
a23eefa2
RZ		 4817 int i;
4818
4819 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4820 return -EINVAL;
4821
4822 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4823 if (psa->performance_level_count != psb->performance_level_count) {
4824 *equal = false;
4825 return 0;
4826 }
4827
4828 for (i = 0; i < psa->performance_level_count; i++) {
2cc0c0b5 4829 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
a23eefa2
RZ		 4830 /* If we have found even one performance level pair that is different the states are different. */
4831 *equal = false;
4832 return 0;
4833 }
4834 }
4835
4836 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4837 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4838 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4839 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4840
4841 return 0;
4842}
4843
2cc0c0b5 4844int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
a23eefa2 4845{
2cc0c0b5 4846 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4847
4848 uint32_t vbios_version;
4849
4850 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4851
4852 phm_get_mc_microcode_version(hwmgr);
4853 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4854 /* Full version of MC ucode has already been loaded. */
4855 if (vbios_version == 0) {
4856 data->need_long_memory_training = false;
4857 return 0;
4858 }
4859
83a7af6d 4860 data->need_long_memory_training = false;
a23eefa2
RZ		 4861
4862/*
edf600da 4863 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
a23eefa2
RZ		 4864 pfd = &tonga_mcmeFirmware;
4865 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
2cc0c0b5 4866 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
a23eefa2
RZ		 4867 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4868 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4869*/
4870 return 0;
4871}
4872
4873/**
4874 * Read clock related registers.
4875 *
4876 * @param hwmgr the address of the powerplay hardware manager.
4877 * @return always 0
4878 */
2cc0c0b5 4879static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
a23eefa2 4880{
2cc0c0b5 4881 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4882
4883 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4884 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4885 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4886
4887 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4888 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4889 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4890
4891 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4892 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4893 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4894
4895 return 0;
4896}
4897
4898/**
4899 * Find out if memory is GDDR5.
4900 *
4901 * @param hwmgr the address of the powerplay hardware manager.
4902 * @return always 0
4903 */
2cc0c0b5 4904static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
a23eefa2 4905{
2cc0c0b5 4906 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4907 uint32_t temp;
4908
4909 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4910
4911 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4912 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4913 MC_SEQ_MISC0_GDDR5_SHIFT));
4914
4915 return 0;
4916}
4917
4918/**
4919 * Enables Dynamic Power Management by SMC
4920 *
4921 * @param hwmgr the address of the powerplay hardware manager.
4922 * @return always 0
4923 */
2cc0c0b5 4924static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4925{
4926 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4927 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4928
4929 return 0;
4930}
4931
4932/**
4933 * Initialize PowerGating States for different engines
4934 *
4935 * @param hwmgr the address of the powerplay hardware manager.
4936 * @return always 0
4937 */
2cc0c0b5 4938static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
a23eefa2 4939{
2cc0c0b5 4940 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4941
4942 data->uvd_power_gated = false;
4943 data->vce_power_gated = false;
4944 data->samu_power_gated = false;
4945
4946 return 0;
4947}
4948
2cc0c0b5 4949static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
a23eefa2 4950{
2cc0c0b5 4951 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
a23eefa2
RZ		 4952 data->low_sclk_interrupt_threshold = 0;
4953
4954 return 0;
4955}
4956
2cc0c0b5 4957int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
a23eefa2
RZ		 4958{
4959 int tmp_result, result = 0;
4960
2cc0c0b5 4961 polaris10_upload_mc_firmware(hwmgr);
a23eefa2 4962
2cc0c0b5 4963 tmp_result = polaris10_read_clock_registers(hwmgr);
a23eefa2
RZ		 4964 PP_ASSERT_WITH_CODE((0 == tmp_result),
4965 "Failed to read clock registers!", result = tmp_result);
4966
2cc0c0b5 4967 tmp_result = polaris10_get_memory_type(hwmgr);
a23eefa2
RZ		 4968 PP_ASSERT_WITH_CODE((0 == tmp_result),
4969 "Failed to get memory type!", result = tmp_result);
4970
2cc0c0b5 4971 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
a23eefa2
RZ		 4972 PP_ASSERT_WITH_CODE((0 == tmp_result),
4973 "Failed to enable ACPI power management!", result = tmp_result);
4974
2cc0c0b5 4975 tmp_result = polaris10_init_power_gate_state(hwmgr);
a23eefa2
RZ		 4976 PP_ASSERT_WITH_CODE((0 == tmp_result),
4977 "Failed to init power gate state!", result = tmp_result);
4978
4979 tmp_result = phm_get_mc_microcode_version(hwmgr);
4980 PP_ASSERT_WITH_CODE((0 == tmp_result),
4981 "Failed to get MC microcode version!", result = tmp_result);
4982
2cc0c0b5 4983 tmp_result = polaris10_init_sclk_threshold(hwmgr);
a23eefa2
RZ		 4984 PP_ASSERT_WITH_CODE((0 == tmp_result),
4985 "Failed to init sclk threshold!", result = tmp_result);
4986
4987 return result;
4988}
4989
2cc0c0b5 4990static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
5632708f 4991 enum pp_clock_type type, uint32_t mask)
2cc0c0b5
FC		 4992{
4993 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4994
4995 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4996 return -EINVAL;
4997
4998 switch (type) {
4999 case PP_SCLK:
5000 if (!data->sclk_dpm_key_disabled)
5001 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5002 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5632708f 5003 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
2cc0c0b5
FC		 5004 break;
5005 case PP_MCLK:
5006 if (!data->mclk_dpm_key_disabled)
5007 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5008 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5632708f 5009 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
2cc0c0b5
FC		 5010 break;
5011 case PP_PCIE:
5632708f
EH		 5012 {
5013 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5014 uint32_t level = 0;
5015
5016 while (tmp >>= 1)
5017 level++;
5018
2cc0c0b5
FC		 5019 if (!data->pcie_dpm_key_disabled)
5020 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5021 PPSMC_MSG_PCIeDPM_ForceLevel,
5632708f 5022 level);
2cc0c0b5 5023 break;
5632708f 5024 }
2cc0c0b5
FC		 5025 default:
5026 break;
5027 }
5028
5029 return 0;
5030}
5031
5032static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
5033{
5034 uint32_t speedCntl = 0;
5035
5036 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
5037 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
5038 ixPCIE_LC_SPEED_CNTL);
5039 return((uint16_t)PHM_GET_FIELD(speedCntl,
5040 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
5041}
5042
5043static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
5044 enum pp_clock_type type, char *buf)
5045{
5046 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5047 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5048 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5049 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5050 int i, now, size = 0;
5051 uint32_t clock, pcie_speed;
5052
5053 switch (type) {
5054 case PP_SCLK:
5055 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5056 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5057
5058 for (i = 0; i < sclk_table->count; i++) {
5059 if (clock > sclk_table->dpm_levels[i].value)
5060 continue;
5061 break;
5062 }
5063 now = i;
5064
5065 for (i = 0; i < sclk_table->count; i++)
5066 size += sprintf(buf + size, "%d: %uMhz %s\n",
5067 i, sclk_table->dpm_levels[i].value / 100,
5068 (i == now) ? "*" : "");
5069 break;
5070 case PP_MCLK:
5071 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5072 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5073
5074 for (i = 0; i < mclk_table->count; i++) {
5075 if (clock > mclk_table->dpm_levels[i].value)
5076 continue;
5077 break;
5078 }
5079 now = i;
5080
5081 for (i = 0; i < mclk_table->count; i++)
5082 size += sprintf(buf + size, "%d: %uMhz %s\n",
5083 i, mclk_table->dpm_levels[i].value / 100,
5084 (i == now) ? "*" : "");
5085 break;
5086 case PP_PCIE:
5087 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
5088 for (i = 0; i < pcie_table->count; i++) {
5089 if (pcie_speed != pcie_table->dpm_levels[i].value)
5090 continue;
5091 break;
5092 }
5093 now = i;
5094
5095 for (i = 0; i < pcie_table->count; i++)
5096 size += sprintf(buf + size, "%d: %s %s\n", i,
5097 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5098 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5099 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5100 (i == now) ? "*" : "");
5101 break;
5102 default:
5103 break;
5104 }
5105 return size;
5106}
5107
9e26bbb3
RZ		 5108static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5109{
5110 if (mode) {
5111 /* stop auto-manage */
5112 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5113 PHM_PlatformCaps_MicrocodeFanControl))
5114 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
5115 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
5116 } else
5117 /* restart auto-manage */
5118 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5119
5120 return 0;
5121}
5122
5123static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5124{
5125 if (hwmgr->fan_ctrl_is_in_default_mode)
5126 return hwmgr->fan_ctrl_default_mode;
5127 else
5128 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5129 CG_FDO_CTRL2, FDO_PWM_MODE);
5130}
5131
09a04264
EH		 5132static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
5133{
5134 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5135 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5136 struct polaris10_single_dpm_table *golden_sclk_table =
5137 &(data->golden_dpm_table.sclk_table);
5138 int value;
5139
5140 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5141 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5142 100 /
5143 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5144
5145 return value;
5146}
5147
5148static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5149{
5150 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5151 struct polaris10_single_dpm_table *golden_sclk_table =
5152 &(data->golden_dpm_table.sclk_table);
5153 struct pp_power_state *ps;
5154 struct polaris10_power_state *polaris10_ps;
5155
5156 if (value > 20)
5157 value = 20;
5158
5159 ps = hwmgr->request_ps;
5160
5161 if (ps == NULL)
5162 return -EINVAL;
5163
5164 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5165
5166 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
5167 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5168 value / 100 +
5169 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5170
5171 return 0;
5172}
5173
0c9e2005
EH		 5174static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr)
5175{
5176 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5177 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5178 struct polaris10_single_dpm_table *golden_mclk_table =
5179 &(data->golden_dpm_table.mclk_table);
5180 int value;
5181
5182 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5183 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5184 100 /
5185 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5186
5187 return value;
5188}
5189
5190static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5191{
5192 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5193 struct polaris10_single_dpm_table *golden_mclk_table =
5194 &(data->golden_dpm_table.mclk_table);
5195 struct pp_power_state *ps;
5196 struct polaris10_power_state *polaris10_ps;
5197
5198 if (value > 20)
5199 value = 20;
5200
5201 ps = hwmgr->request_ps;
5202
5203 if (ps == NULL)
5204 return -EINVAL;
5205
5206 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5207
5208 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock =
5209 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5210 value / 100 +
5211 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5212
5213 return 0;
5214}
2cc0c0b5
FC		 5215static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5216 .backend_init = &polaris10_hwmgr_backend_init,
5217 .backend_fini = &polaris10_hwmgr_backend_fini,
5218 .asic_setup = &polaris10_setup_asic_task,
5219 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5220 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5221 .force_dpm_level = &polaris10_force_dpm_level,
5222 .power_state_set = polaris10_set_power_state_tasks,
5223 .get_power_state_size = polaris10_get_power_state_size,
5224 .get_mclk = polaris10_dpm_get_mclk,
5225 .get_sclk = polaris10_dpm_get_sclk,
5226 .patch_boot_state = polaris10_dpm_patch_boot_state,
5227 .get_pp_table_entry = polaris10_get_pp_table_entry,
a23eefa2 5228 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
2cc0c0b5
FC		 5229 .print_current_perforce_level = polaris10_print_current_perforce_level,
5230 .powerdown_uvd = polaris10_phm_powerdown_uvd,
5231 .powergate_uvd = polaris10_phm_powergate_uvd,
5232 .powergate_vce = polaris10_phm_powergate_vce,
5233 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5234 .update_clock_gatings = polaris10_phm_update_clock_gatings,
5235 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5236 .display_config_changed = polaris10_display_configuration_changed_task,
5237 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5238 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5239 .get_temperature = polaris10_thermal_get_temperature,
5240 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5241 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5242 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5243 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5244 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5245 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5246 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5247 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5248 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5249 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5250 .check_states_equal = polaris10_check_states_equal,
9e26bbb3
RZ		 5251 .set_fan_control_mode = polaris10_set_fan_control_mode,
5252 .get_fan_control_mode = polaris10_get_fan_control_mode,
2cc0c0b5
FC		 5253 .force_clock_level = polaris10_force_clock_level,
5254 .print_clock_levels = polaris10_print_clock_levels,
5255 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
09a04264
EH		 5256 .get_sclk_od = polaris10_get_sclk_od,
5257 .set_sclk_od = polaris10_set_sclk_od,
0c9e2005
EH		 5258 .get_mclk_od = polaris10_get_mclk_od,
5259 .set_mclk_od = polaris10_set_mclk_od,
a23eefa2
RZ		 5260};
5261
2cc0c0b5 5262int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
a23eefa2 5263{
2cc0c0b5 5264 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
a23eefa2 5265 hwmgr->pptable_func = &tonga_pptable_funcs;
2cc0c0b5 5266 pp_polaris10_thermal_initialize(hwmgr);
a23eefa2
RZ		 5267
5268 return 0;
5269}
Linux kernel - Deliverables
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