[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / inc / amd_powerplay.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _AMD_POWERPLAY_H_
#define _AMD_POWERPLAY_H_

#include <linux/seq_file.h>
#include <linux/types.h>
#include <linux/errno.h>
#include "amd_shared.h"
#include "cgs_common.h"


enum amd_pp_event {
	AMD_PP_EVENT_INITIALIZE = 0,
	AMD_PP_EVENT_UNINITIALIZE,
	AMD_PP_EVENT_POWER_SOURCE_CHANGE,
	AMD_PP_EVENT_SUSPEND,
	AMD_PP_EVENT_RESUME,
	AMD_PP_EVENT_ENTER_REST_STATE,
	AMD_PP_EVENT_EXIT_REST_STATE,
	AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
	AMD_PP_EVENT_THERMAL_NOTIFICATION,
	AMD_PP_EVENT_VBIOS_NOTIFICATION,
	AMD_PP_EVENT_ENTER_THERMAL_STATE,
	AMD_PP_EVENT_EXIT_THERMAL_STATE,
	AMD_PP_EVENT_ENTER_FORCED_STATE,
	AMD_PP_EVENT_EXIT_FORCED_STATE,
	AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
	AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
	AMD_PP_EVENT_ENTER_SCREEN_SAVER,
	AMD_PP_EVENT_EXIT_SCREEN_SAVER,
	AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
	AMD_PP_EVENT_VPU_RECOVERY_END,
	AMD_PP_EVENT_ENABLE_POWER_PLAY,
	AMD_PP_EVENT_DISABLE_POWER_PLAY,
	AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
	AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
	AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
	AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
	AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
	AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
	AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
	AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
	AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
	AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
	AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
	AMD_PP_EVENT_ENABLE_CGPG,
	AMD_PP_EVENT_DISABLE_CGPG,
	AMD_PP_EVENT_ENTER_TEXT_MODE,
	AMD_PP_EVENT_EXIT_TEXT_MODE,
	AMD_PP_EVENT_VIDEO_START,
	AMD_PP_EVENT_VIDEO_STOP,
	AMD_PP_EVENT_ENABLE_USER_STATE,
	AMD_PP_EVENT_DISABLE_USER_STATE,
	AMD_PP_EVENT_READJUST_POWER_STATE,
	AMD_PP_EVENT_START_INACTIVITY,
	AMD_PP_EVENT_STOP_INACTIVITY,
	AMD_PP_EVENT_LINKED_ADAPTERS_READY,
	AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
	AMD_PP_EVENT_COMPLETE_INIT,
	AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
	AMD_PP_EVENT_BACKLIGHT_CHANGED,
	AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
	AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
	AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
	AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
	AMD_PP_EVENT_SCREEN_ON,
	AMD_PP_EVENT_SCREEN_OFF,
	AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
	AMD_PP_EVENT_ENTER_ULP_STATE,
	AMD_PP_EVENT_EXIT_ULP_STATE,
	AMD_PP_EVENT_REGISTER_IP_STATE,
	AMD_PP_EVENT_UNREGISTER_IP_STATE,
	AMD_PP_EVENT_ENTER_MGPU_MODE,
	AMD_PP_EVENT_EXIT_MGPU_MODE,
	AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
	AMD_PP_EVENT_PRE_SUSPEND,
	AMD_PP_EVENT_PRE_RESUME,
	AMD_PP_EVENT_ENTER_BACOS,
	AMD_PP_EVENT_EXIT_BACOS,
	AMD_PP_EVENT_RESUME_BACO,
	AMD_PP_EVENT_RESET_BACO,
	AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
	AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
	AMD_PP_EVENT_START_COMPUTE_APPLICATION,
	AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
	AMD_PP_EVENT_REDUCE_POWER_LIMIT,
	AMD_PP_EVENT_ENTER_FRAME_LOCK,
	AMD_PP_EVENT_EXIT_FRAME_LOOCK,
	AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
	AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
	AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
	AMD_PP_EVENT_HIBERNATE,
	AMD_PP_EVENT_CONNECTED_STANDBY,
	AMD_PP_EVENT_ENTER_SELF_REFRESH,
	AMD_PP_EVENT_EXIT_SELF_REFRESH,
	AMD_PP_EVENT_START_AVFS_BTC,
	AMD_PP_EVENT_MAX
};

enum amd_dpm_forced_level {
	AMD_DPM_FORCED_LEVEL_AUTO = 0,
	AMD_DPM_FORCED_LEVEL_LOW = 1,
	AMD_DPM_FORCED_LEVEL_HIGH = 2,
	AMD_DPM_FORCED_LEVEL_MANUAL = 3,
};

struct amd_pp_init {
	struct cgs_device *device;
	uint32_t chip_family;
	uint32_t chip_id;
	uint32_t rev_id;
	uint16_t sub_sys_id;
	uint16_t sub_vendor_id;
};

enum amd_pp_display_config_type{
	AMD_PP_DisplayConfigType_None = 0,
	AMD_PP_DisplayConfigType_DP54 ,
	AMD_PP_DisplayConfigType_DP432 ,
	AMD_PP_DisplayConfigType_DP324 ,
	AMD_PP_DisplayConfigType_DP27,
	AMD_PP_DisplayConfigType_DP243,
	AMD_PP_DisplayConfigType_DP216,
	AMD_PP_DisplayConfigType_DP162,
	AMD_PP_DisplayConfigType_HDMI6G ,
	AMD_PP_DisplayConfigType_HDMI297 ,
	AMD_PP_DisplayConfigType_HDMI162,
	AMD_PP_DisplayConfigType_LVDS,
	AMD_PP_DisplayConfigType_DVI,
	AMD_PP_DisplayConfigType_WIRELESS,
	AMD_PP_DisplayConfigType_VGA
};

struct single_display_configuration
{
	uint32_t controller_index;
	uint32_t controller_id;
	uint32_t signal_type;
	uint32_t display_state;
	/* phy id for the primary internal transmitter */
	uint8_t primary_transmitter_phyi_d;
	/* bitmap with the active lanes */
	uint8_t primary_transmitter_active_lanemap;
	/* phy id for the secondary internal transmitter (for dual-link dvi) */
	uint8_t secondary_transmitter_phy_id;
	/* bitmap with the active lanes */
	uint8_t secondary_transmitter_active_lanemap;
	/* misc phy settings for SMU. */
	uint32_t config_flags;
	uint32_t display_type;
	uint32_t view_resolution_cx;
	uint32_t view_resolution_cy;
	enum amd_pp_display_config_type displayconfigtype;
	uint32_t vertical_refresh; /* for active display */
};

#define MAX_NUM_DISPLAY 32

struct amd_pp_display_configuration {
	bool nb_pstate_switch_disable;/* controls NB PState switch */
	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
	bool cpu_pstate_disable;
	uint32_t cpu_pstate_separation_time;

	uint32_t num_display;  /* total number of display*/
	uint32_t num_path_including_non_display;
	uint32_t crossfire_display_index;
	uint32_t min_mem_set_clock;
	uint32_t min_core_set_clock;
	/* unit 10KHz x bit*/
	uint32_t min_bus_bandwidth;
	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
	uint32_t min_core_set_clock_in_sr;

	struct single_display_configuration displays[MAX_NUM_DISPLAY];

	uint32_t vrefresh; /* for active display*/

	uint32_t min_vblank_time; /* for active display*/
	bool multi_monitor_in_sync;
	/* Controller Index of primary display - used in MCLK SMC switching hang
	 * SW Workaround*/
	uint32_t crtc_index;
	/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
	uint32_t line_time_in_us;
	bool invalid_vblank_time;

	uint32_t display_clk;
	/*
	 * for given display configuration if multimonitormnsync == false then
	 * Memory clock DPMS with this latency or below is allowed, DPMS with
	 * higher latency not allowed.
	 */
	uint32_t dce_tolerable_mclk_in_active_latency;
};

struct amd_pp_simple_clock_info {
	uint32_t	engine_max_clock;
	uint32_t	memory_max_clock;
	uint32_t	level;
};

enum PP_DAL_POWERLEVEL {
	PP_DAL_POWERLEVEL_INVALID = 0,
	PP_DAL_POWERLEVEL_ULTRALOW,
	PP_DAL_POWERLEVEL_LOW,
	PP_DAL_POWERLEVEL_NOMINAL,
	PP_DAL_POWERLEVEL_PERFORMANCE,

	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
};

struct amd_pp_clock_info {
	uint32_t min_engine_clock;
	uint32_t max_engine_clock;
	uint32_t min_memory_clock;
	uint32_t max_memory_clock;
	uint32_t min_bus_bandwidth;
	uint32_t max_bus_bandwidth;
	uint32_t max_engine_clock_in_sr;
	uint32_t min_engine_clock_in_sr;
	enum PP_DAL_POWERLEVEL max_clocks_state;
};

enum amd_pp_clock_type {
	amd_pp_disp_clock = 1,
	amd_pp_sys_clock,
	amd_pp_mem_clock
};

#define MAX_NUM_CLOCKS 16

struct amd_pp_clocks {
	uint32_t count;
	uint32_t clock[MAX_NUM_CLOCKS];
};


enum {
	PP_GROUP_UNKNOWN = 0,
	PP_GROUP_GFX = 1,
	PP_GROUP_SYS,
	PP_GROUP_MAX
};

enum pp_clock_type {
	PP_SCLK,
	PP_MCLK,
	PP_PCIE,
};

struct pp_states_info {
	uint32_t nums;
	uint32_t states[16];
};

#define PP_GROUP_MASK        0xF0000000
#define PP_GROUP_SHIFT       28

#define PP_BLOCK_MASK        0x0FFFFF00
#define PP_BLOCK_SHIFT       8

#define PP_BLOCK_GFX_CG         0x01
#define PP_BLOCK_GFX_MG         0x02
#define PP_BLOCK_GFX_3D         0x04
#define PP_BLOCK_GFX_RLC        0x08
#define PP_BLOCK_GFX_CP         0x10
#define PP_BLOCK_SYS_BIF        0x01
#define PP_BLOCK_SYS_MC         0x02
#define PP_BLOCK_SYS_ROM        0x04
#define PP_BLOCK_SYS_DRM        0x08
#define PP_BLOCK_SYS_HDP        0x10
#define PP_BLOCK_SYS_SDMA       0x20

#define PP_STATE_MASK           0x0000000F
#define PP_STATE_SHIFT          0
#define PP_STATE_SUPPORT_MASK   0x000000F0
#define PP_STATE_SUPPORT_SHIFT  0

#define PP_STATE_CG             0x01
#define PP_STATE_LS             0x02
#define PP_STATE_DS             0x04
#define PP_STATE_SD             0x08
#define PP_STATE_SUPPORT_CG     0x10
#define PP_STATE_SUPPORT_LS     0x20
#define PP_STATE_SUPPORT_DS     0x40
#define PP_STATE_SUPPORT_SD     0x80

#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
								block << PP_BLOCK_SHIFT |\
								support << PP_STATE_SUPPORT_SHIFT |\
								state << PP_STATE_SHIFT)

struct amd_powerplay_funcs {
	int (*get_temperature)(void *handle);
	int (*load_firmware)(void *handle);
	int (*wait_for_fw_loading_complete)(void *handle);
	int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
	enum amd_pm_state_type (*get_current_power_state)(void *handle);
	int (*get_sclk)(void *handle, bool low);
	int (*get_mclk)(void *handle, bool low);
	int (*powergate_vce)(void *handle, bool gate);
	int (*powergate_uvd)(void *handle, bool gate);
	int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
				   void *input, void *output);
	void (*print_current_performance_level)(void *handle,
						      struct seq_file *m);
	int (*set_fan_control_mode)(void *handle, uint32_t mode);
	int (*get_fan_control_mode)(void *handle);
	int (*set_fan_speed_percent)(void *handle, uint32_t percent);
	int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
	int (*get_pp_table)(void *handle, char **table);
	int (*set_pp_table)(void *handle, const char *buf, size_t size);
	int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
	int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
	int (*get_sclk_od)(void *handle);
	int (*set_sclk_od)(void *handle, uint32_t value);
	int (*get_mclk_od)(void *handle);
	int (*set_mclk_od)(void *handle, uint32_t value);
};

struct amd_powerplay {
	void *pp_handle;
	const struct amd_ip_funcs *ip_funcs;
	const struct amd_powerplay_funcs *pp_funcs;
};

int amd_powerplay_init(struct amd_pp_init *pp_init,
		       struct amd_powerplay *amd_pp);

int amd_powerplay_fini(void *handle);

int amd_powerplay_reset(void *handle);

int amd_powerplay_display_configuration_change(void *handle,
		const struct amd_pp_display_configuration *input);

int amd_powerplay_get_display_power_level(void *handle,
		struct amd_pp_simple_clock_info *output);

int amd_powerplay_get_current_clocks(void *handle,
		struct amd_pp_clock_info *output);

int amd_powerplay_get_clock_by_type(void *handle,
		enum amd_pp_clock_type type,
		struct amd_pp_clocks *clocks);

int amd_powerplay_get_display_mode_validation_clocks(void *handle,
		struct amd_pp_simple_clock_info *output);

#endif /* _AMD_POWERPLAY_H_ */
Commit	Line	Data
1f7371b2 AD	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef _AMD_POWERPLAY_H_
	24	#define _AMD_POWERPLAY_H_
	25
	26	#include <linux/seq_file.h>
	27	#include <linux/types.h>
fd3e14ff	28	#include <linux/errno.h>
1f7371b2 AD	29	#include "amd_shared.h"
	30	#include "cgs_common.h"
	31
e273b041	32
1f7371b2 AD	33	enum amd_pp_event {
	34	AMD_PP_EVENT_INITIALIZE = 0,
	35	AMD_PP_EVENT_UNINITIALIZE,
	36	AMD_PP_EVENT_POWER_SOURCE_CHANGE,
	37	AMD_PP_EVENT_SUSPEND,
	38	AMD_PP_EVENT_RESUME,
	39	AMD_PP_EVENT_ENTER_REST_STATE,
	40	AMD_PP_EVENT_EXIT_REST_STATE,
	41	AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
	42	AMD_PP_EVENT_THERMAL_NOTIFICATION,
	43	AMD_PP_EVENT_VBIOS_NOTIFICATION,
	44	AMD_PP_EVENT_ENTER_THERMAL_STATE,
	45	AMD_PP_EVENT_EXIT_THERMAL_STATE,
	46	AMD_PP_EVENT_ENTER_FORCED_STATE,
	47	AMD_PP_EVENT_EXIT_FORCED_STATE,
	48	AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
	49	AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
	50	AMD_PP_EVENT_ENTER_SCREEN_SAVER,
	51	AMD_PP_EVENT_EXIT_SCREEN_SAVER,
	52	AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
	53	AMD_PP_EVENT_VPU_RECOVERY_END,
	54	AMD_PP_EVENT_ENABLE_POWER_PLAY,
	55	AMD_PP_EVENT_DISABLE_POWER_PLAY,
	56	AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
	57	AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
	58	AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
	59	AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
	60	AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
	61	AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
	62	AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
	63	AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
	64	AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
	65	AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
	66	AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
	67	AMD_PP_EVENT_ENABLE_CGPG,
	68	AMD_PP_EVENT_DISABLE_CGPG,
	69	AMD_PP_EVENT_ENTER_TEXT_MODE,
	70	AMD_PP_EVENT_EXIT_TEXT_MODE,
	71	AMD_PP_EVENT_VIDEO_START,
	72	AMD_PP_EVENT_VIDEO_STOP,
	73	AMD_PP_EVENT_ENABLE_USER_STATE,
	74	AMD_PP_EVENT_DISABLE_USER_STATE,
	75	AMD_PP_EVENT_READJUST_POWER_STATE,
	76	AMD_PP_EVENT_START_INACTIVITY,
	77	AMD_PP_EVENT_STOP_INACTIVITY,
	78	AMD_PP_EVENT_LINKED_ADAPTERS_READY,
	79	AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
	80	AMD_PP_EVENT_COMPLETE_INIT,
	81	AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
	82	AMD_PP_EVENT_BACKLIGHT_CHANGED,
	83	AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
	84	AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
	85	AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	86	AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
	87	AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
	88	AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
	89	AMD_PP_EVENT_SCREEN_ON,
	90	AMD_PP_EVENT_SCREEN_OFF,
	91	AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
	92	AMD_PP_EVENT_ENTER_ULP_STATE,
	93	AMD_PP_EVENT_EXIT_ULP_STATE,
	94	AMD_PP_EVENT_REGISTER_IP_STATE,
	95	AMD_PP_EVENT_UNREGISTER_IP_STATE,
	96	AMD_PP_EVENT_ENTER_MGPU_MODE,
97	AMD_PP_EVENT_EXIT_MGPU_MODE,
98	AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
99	AMD_PP_EVENT_PRE_SUSPEND,
100	AMD_PP_EVENT_PRE_RESUME,
101	AMD_PP_EVENT_ENTER_BACOS,
102	AMD_PP_EVENT_EXIT_BACOS,
103	AMD_PP_EVENT_RESUME_BACO,
104	AMD_PP_EVENT_RESET_BACO,
105	AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
106	AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
107	AMD_PP_EVENT_START_COMPUTE_APPLICATION,
108	AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
109	AMD_PP_EVENT_REDUCE_POWER_LIMIT,
110	AMD_PP_EVENT_ENTER_FRAME_LOCK,
111	AMD_PP_EVENT_EXIT_FRAME_LOOCK,
112	AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
113	AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
114	AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
115	AMD_PP_EVENT_HIBERNATE,
116	AMD_PP_EVENT_CONNECTED_STANDBY,
117	AMD_PP_EVENT_ENTER_SELF_REFRESH,
118	AMD_PP_EVENT_EXIT_SELF_REFRESH,
119	AMD_PP_EVENT_START_AVFS_BTC,
120	AMD_PP_EVENT_MAX
121	};
122
123	enum amd_dpm_forced_level {
124	AMD_DPM_FORCED_LEVEL_AUTO = 0,
125	AMD_DPM_FORCED_LEVEL_LOW = 1,
126	AMD_DPM_FORCED_LEVEL_HIGH = 2,
f3898ea1	127	AMD_DPM_FORCED_LEVEL_MANUAL = 3,
1f7371b2 AD	128	};
	129
	130	struct amd_pp_init {
	131	struct cgs_device *device;
	132	uint32_t chip_family;
	133	uint32_t chip_id;
	134	uint32_t rev_id;
93bdacd1 RZ	135	uint16_t sub_sys_id;
93bdacd1 RZ	136	uint16_t sub_vendor_id;
1f7371b2	137	};
af223dfa	138
14f63411 EY	139	enum amd_pp_display_config_type{
	140	AMD_PP_DisplayConfigType_None = 0,
	141	AMD_PP_DisplayConfigType_DP54 ,
	142	AMD_PP_DisplayConfigType_DP432 ,
	143	AMD_PP_DisplayConfigType_DP324 ,
	144	AMD_PP_DisplayConfigType_DP27,
	145	AMD_PP_DisplayConfigType_DP243,
	146	AMD_PP_DisplayConfigType_DP216,
	147	AMD_PP_DisplayConfigType_DP162,
	148	AMD_PP_DisplayConfigType_HDMI6G ,
	149	AMD_PP_DisplayConfigType_HDMI297 ,
	150	AMD_PP_DisplayConfigType_HDMI162,
	151	AMD_PP_DisplayConfigType_LVDS,
	152	AMD_PP_DisplayConfigType_DVI,
	153	AMD_PP_DisplayConfigType_WIRELESS,
	154	AMD_PP_DisplayConfigType_VGA
	155	};
	156
	157	struct single_display_configuration
	158	{
	159	uint32_t controller_index;
	160	uint32_t controller_id;
	161	uint32_t signal_type;
	162	uint32_t display_state;
	163	/* phy id for the primary internal transmitter */
	164	uint8_t primary_transmitter_phyi_d;
	165	/* bitmap with the active lanes */
	166	uint8_t primary_transmitter_active_lanemap;
	167	/* phy id for the secondary internal transmitter (for dual-link dvi) */
	168	uint8_t secondary_transmitter_phy_id;
	169	/* bitmap with the active lanes */
	170	uint8_t secondary_transmitter_active_lanemap;
	171	/* misc phy settings for SMU. */
	172	uint32_t config_flags;
	173	uint32_t display_type;
	174	uint32_t view_resolution_cx;
	175	uint32_t view_resolution_cy;
	176	enum amd_pp_display_config_type displayconfigtype;
	177	uint32_t vertical_refresh; /* for active display */
	178	};
	179
	180	#define MAX_NUM_DISPLAY 32
1f7371b2	181
7fb72a1f RZ	182	struct amd_pp_display_configuration {
	183	bool nb_pstate_switch_disable;/* controls NB PState switch */
	184	bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
	185	bool cpu_pstate_disable;
	186	uint32_t cpu_pstate_separation_time;
14f63411 EY	187
	188	uint32_t num_display; /* total number of display*/
	189	uint32_t num_path_including_non_display;
	190	uint32_t crossfire_display_index;
	191	uint32_t min_mem_set_clock;
	192	uint32_t min_core_set_clock;
	193	/* unit 10KHz x bit*/
	194	uint32_t min_bus_bandwidth;
	195	/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
	196	uint32_t min_core_set_clock_in_sr;
	197
	198	struct single_display_configuration displays[MAX_NUM_DISPLAY];
	199
	200	uint32_t vrefresh; /* for active display*/
	201
	202	uint32_t min_vblank_time; /* for active display*/
	203	bool multi_monitor_in_sync;
	204	/* Controller Index of primary display - used in MCLK SMC switching hang
	205	* SW Workaround*/
	206	uint32_t crtc_index;
	207	/* htotal1000/pixelclk - used in MCLK SMC switching hang SW Workaround/
	208	uint32_t line_time_in_us;
	209	bool invalid_vblank_time;
	210
	211	uint32_t display_clk;
	212	/*
	213	* for given display configuration if multimonitormnsync == false then
	214	* Memory clock DPMS with this latency or below is allowed, DPMS with
	215	* higher latency not allowed.
	216	*/
	217	uint32_t dce_tolerable_mclk_in_active_latency;
7fb72a1f RZ	218	};
7fb72a1f RZ	219
47329134	220	struct amd_pp_simple_clock_info {
c4dd206b VP	221	uint32_t engine_max_clock;
	222	uint32_t memory_max_clock;
	223	uint32_t level;
	224	};
	225
e273b041 RZ	226	enum PP_DAL_POWERLEVEL {
	227	PP_DAL_POWERLEVEL_INVALID = 0,
	228	PP_DAL_POWERLEVEL_ULTRALOW,
	229	PP_DAL_POWERLEVEL_LOW,
	230	PP_DAL_POWERLEVEL_NOMINAL,
	231	PP_DAL_POWERLEVEL_PERFORMANCE,
	232
	233	PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
	234	PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
	235	PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
	236	PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
	237	PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
	238	PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
	239	PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
	240	PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
	241	};
	242
	243	struct amd_pp_clock_info {
	244	uint32_t min_engine_clock;
	245	uint32_t max_engine_clock;
	246	uint32_t min_memory_clock;
	247	uint32_t max_memory_clock;
	248	uint32_t min_bus_bandwidth;
	249	uint32_t max_bus_bandwidth;
	250	uint32_t max_engine_clock_in_sr;
	251	uint32_t min_engine_clock_in_sr;
	252	enum PP_DAL_POWERLEVEL max_clocks_state;
	253	};
	254
	255	enum amd_pp_clock_type {
	256	amd_pp_disp_clock = 1,
	257	amd_pp_sys_clock,
	258	amd_pp_mem_clock
	259	};
	260
	261	#define MAX_NUM_CLOCKS 16
	262
	263	struct amd_pp_clocks {
	264	uint32_t count;
	265	uint32_t clock[MAX_NUM_CLOCKS];
	266	};
	267
	268
3cec76f9 RZ	269	enum {
	270	PP_GROUP_UNKNOWN = 0,
	271	PP_GROUP_GFX = 1,
	272	PP_GROUP_SYS,
	273	PP_GROUP_MAX
	274	};
	275
f3898ea1 EH	276	enum pp_clock_type {
	277	PP_SCLK,
	278	PP_MCLK,
	279	PP_PCIE,
	280	};
	281
	282	struct pp_states_info {
	283	uint32_t nums;
	284	uint32_t states[16];
	285	};
	286
3cec76f9 RZ	287	#define PP_GROUP_MASK 0xF0000000
	288	#define PP_GROUP_SHIFT 28
	289
	290	#define PP_BLOCK_MASK 0x0FFFFF00
	291	#define PP_BLOCK_SHIFT 8
	292
	293	#define PP_BLOCK_GFX_CG 0x01
	294	#define PP_BLOCK_GFX_MG 0x02
03e3905f EH	295	#define PP_BLOCK_GFX_3D 0x04
	296	#define PP_BLOCK_GFX_RLC 0x08
	297	#define PP_BLOCK_GFX_CP 0x10
3cec76f9 RZ	298	#define PP_BLOCK_SYS_BIF 0x01
	299	#define PP_BLOCK_SYS_MC 0x02
	300	#define PP_BLOCK_SYS_ROM 0x04
	301	#define PP_BLOCK_SYS_DRM 0x08
	302	#define PP_BLOCK_SYS_HDP 0x10
	303	#define PP_BLOCK_SYS_SDMA 0x20
	304
	305	#define PP_STATE_MASK 0x0000000F
	306	#define PP_STATE_SHIFT 0
	307	#define PP_STATE_SUPPORT_MASK 0x000000F0
	308	#define PP_STATE_SUPPORT_SHIFT 0
	309
	310	#define PP_STATE_CG 0x01
	311	#define PP_STATE_LS 0x02
	312	#define PP_STATE_DS 0x04
	313	#define PP_STATE_SD 0x08
	314	#define PP_STATE_SUPPORT_CG 0x10
	315	#define PP_STATE_SUPPORT_LS 0x20
	316	#define PP_STATE_SUPPORT_DS 0x40
	317	#define PP_STATE_SUPPORT_SD 0x80
	318
	319	#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT \|\
	320	block << PP_BLOCK_SHIFT \|\
	321	support << PP_STATE_SUPPORT_SHIFT \|\
	322	state << PP_STATE_SHIFT)
	323
1f7371b2 AD	324	struct amd_powerplay_funcs {
	325	int (get_temperature)(void handle);
	326	int (load_firmware)(void handle);
	327	int (wait_for_fw_loading_complete)(void handle);
	328	int (force_performance_level)(void handle, enum amd_dpm_forced_level level);
	329	enum amd_dpm_forced_level (get_performance_level)(void handle);
	330	enum amd_pm_state_type (get_current_power_state)(void handle);
	331	int (get_sclk)(void handle, bool low);
	332	int (get_mclk)(void handle, bool low);
	333	int (powergate_vce)(void handle, bool gate);
	334	int (powergate_uvd)(void handle, bool gate);
	335	int (dispatch_tasks)(void handle, enum amd_pp_event event_id,
	336	void input, void output);
	337	void (print_current_performance_level)(void handle,
	338	struct seq_file *m);
cac9a199 RZ	339	int (set_fan_control_mode)(void handle, uint32_t mode);
	340	int (get_fan_control_mode)(void handle);
	341	int (set_fan_speed_percent)(void handle, uint32_t percent);
	342	int (get_fan_speed_percent)(void handle, uint32_t *speed);
f3898ea1 EH	343	int (get_pp_num_states)(void handle, struct pp_states_info *data);
	344	int (get_pp_table)(void handle, char **table);
	345	int (set_pp_table)(void handle, const char *buf, size_t size);
5632708f	346	int (force_clock_level)(void handle, enum pp_clock_type type, uint32_t mask);
f3898ea1	347	int (print_clock_levels)(void handle, enum pp_clock_type type, char *buf);
428bafa8 EH	348	int (get_sclk_od)(void handle);
428bafa8 EH	349	int (set_sclk_od)(void handle, uint32_t value);
f2bdc05f EH	350	int (get_mclk_od)(void handle);
f2bdc05f EH	351	int (set_mclk_od)(void handle, uint32_t value);
1f7371b2 AD	352	};
	353
	354	struct amd_powerplay {
	355	void *pp_handle;
	356	const struct amd_ip_funcs *ip_funcs;
	357	const struct amd_powerplay_funcs *pp_funcs;
	358	};
	359
	360	int amd_powerplay_init(struct amd_pp_init *pp_init,
	361	struct amd_powerplay *amd_pp);
155f1127	362
1f7371b2 AD	363	int amd_powerplay_fini(void *handle);
1f7371b2 AD	364
4dcf9e6f EH	365	int amd_powerplay_reset(void *handle);
4dcf9e6f EH	366
155f1127 DR	367	int amd_powerplay_display_configuration_change(void *handle,
155f1127 DR	368	const struct amd_pp_display_configuration *input);
7fb72a1f	369
1c9a9082	370	int amd_powerplay_get_display_power_level(void *handle,
47329134	371	struct amd_pp_simple_clock_info *output);
c4dd206b	372
155f1127 DR	373	int amd_powerplay_get_current_clocks(void *handle,
155f1127 DR	374	struct amd_pp_clock_info *output);
e273b041	375
155f1127 DR	376	int amd_powerplay_get_clock_by_type(void *handle,
	377	enum amd_pp_clock_type type,
	378	struct amd_pp_clocks *clocks);
e273b041	379
155f1127 DR	380	int amd_powerplay_get_display_mode_validation_clocks(void *handle,
155f1127 DR	381	struct amd_pp_simple_clock_info *output);
c4dd206b	382
1f7371b2	383	#endif /* _AMD_POWERPLAY_H_ */