[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / inc / hardwaremanager.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _HARDWARE_MANAGER_H_
#define _HARDWARE_MANAGER_H_


struct pp_hwmgr;
struct pp_hw_power_state;
struct pp_power_state;
enum amd_dpm_forced_level;
struct PP_TemperatureRange;


struct phm_fan_speed_info {
	uint32_t min_percent;
	uint32_t max_percent;
	uint32_t min_rpm;
	uint32_t max_rpm;
	bool supports_percent_read;
	bool supports_percent_write;
	bool supports_rpm_read;
	bool supports_rpm_write;
};

/* Automatic Power State Throttling */
enum PHM_AutoThrottleSource
{
    PHM_AutoThrottleSource_Thermal,
    PHM_AutoThrottleSource_External
};

typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;

enum phm_platform_caps {
	PHM_PlatformCaps_AtomBiosPpV1 = 0,
	PHM_PlatformCaps_PowerPlaySupport,
	PHM_PlatformCaps_ACOverdriveSupport,
	PHM_PlatformCaps_BacklightSupport,
	PHM_PlatformCaps_ThermalController,
	PHM_PlatformCaps_BiosPowerSourceControl,
	PHM_PlatformCaps_DisableVoltageTransition,
	PHM_PlatformCaps_DisableEngineTransition,
	PHM_PlatformCaps_DisableMemoryTransition,
	PHM_PlatformCaps_DynamicPowerManagement,
	PHM_PlatformCaps_EnableASPML0s,
	PHM_PlatformCaps_EnableASPML1,
	PHM_PlatformCaps_OD5inACSupport,
	PHM_PlatformCaps_OD5inDCSupport,
	PHM_PlatformCaps_SoftStateOD5,
	PHM_PlatformCaps_NoOD5Support,
	PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
	PHM_PlatformCaps_ActivityReporting,
	PHM_PlatformCaps_EnableBackbias,
	PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
	PHM_PlatformCaps_ShowPowerBudgetWarning,
	PHM_PlatformCaps_PowerBudgetWaiverAvailable,
	PHM_PlatformCaps_GFXClockGatingSupport,
	PHM_PlatformCaps_MMClockGatingSupport,
	PHM_PlatformCaps_AutomaticDCTransition,
	PHM_PlatformCaps_GeminiPrimary,
	PHM_PlatformCaps_MemorySpreadSpectrumSupport,
	PHM_PlatformCaps_EngineSpreadSpectrumSupport,
	PHM_PlatformCaps_StepVddc,
	PHM_PlatformCaps_DynamicPCIEGen2Support,
	PHM_PlatformCaps_SMC,
	PHM_PlatformCaps_FaultyInternalThermalReading,          /* Internal thermal controller reports faulty temperature value when DAC2 is active */
	PHM_PlatformCaps_EnableVoltageControl,                  /* indicates voltage can be controlled */
	PHM_PlatformCaps_EnableSideportControl,                 /* indicates Sideport can be controlled */
	PHM_PlatformCaps_VideoPlaybackEEUNotification,          /* indicates EEU notification of video start/stop is required */
	PHM_PlatformCaps_TurnOffPll_ASPML1,                     /* PCIE Turn Off PLL in ASPM L1 */
	PHM_PlatformCaps_EnableHTLinkControl,                   /* indicates HT Link can be controlled by ACPI or CLMC overrided/automated mode. */
	PHM_PlatformCaps_PerformanceStateOnly,                  /* indicates only performance power state to be used on current system. */
	PHM_PlatformCaps_ExclusiveModeAlwaysHigh,               /* In Exclusive (3D) mode always stay in High state. */
	PHM_PlatformCaps_DisableMGClockGating,                  /* to disable Medium Grain Clock Gating or not */
	PHM_PlatformCaps_DisableMGCGTSSM,                       /* TO disable Medium Grain Clock Gating Shader Complex control */
	PHM_PlatformCaps_UVDAlwaysHigh,                         /* In UVD mode always stay in High state */
	PHM_PlatformCaps_DisablePowerGating,                    /* to disable power gating */
	PHM_PlatformCaps_CustomThermalPolicy,                   /* indicates only performance power state to be used on current system. */
	PHM_PlatformCaps_StayInBootState,                       /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
	PHM_PlatformCaps_SMCAllowSeparateSWThermalState,        /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
	PHM_PlatformCaps_MultiUVDStateSupport,                  /* Powerplay state table supports multi UVD states. */
	PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,             /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
	PHM_PlatformCaps_EnableMCUHTLinkControl,                /* Enable HT link control by MCU */
	PHM_PlatformCaps_ABM,                                   /* ABM support.*/
	PHM_PlatformCaps_KongThermalPolicy,                     /* A thermal policy specific for Kong */
	PHM_PlatformCaps_SwitchVDDNB,                           /* if the users want to switch VDDNB */
	PHM_PlatformCaps_ULPS,                                  /* support ULPS mode either through ACPI state or ULPS state */
	PHM_PlatformCaps_NativeULPS,                            /* hardware capable of ULPS state (other than through the ACPI state) */
	PHM_PlatformCaps_EnableMVDDControl,                     /* indicates that memory voltage can be controlled */
	PHM_PlatformCaps_ControlVDDCI,                          /* Control VDDCI separately from VDDC. */
	PHM_PlatformCaps_DisableDCODT,                          /* indicates if DC ODT apply or not */
	PHM_PlatformCaps_DynamicACTiming,                       /* if the SMC dynamically re-programs MC SEQ register values */
	PHM_PlatformCaps_EnableThermalIntByGPIO,                /* enable throttle control through GPIO */
	PHM_PlatformCaps_BootStateOnAlert,                      /* Go to boot state on alerts, e.g. on an AC->DC transition. */
	PHM_PlatformCaps_DontWaitForVBlankOnAlert,              /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
	PHM_PlatformCaps_Force3DClockSupport,                   /* indicates if the platform supports force 3D clock. */
	PHM_PlatformCaps_MicrocodeFanControl,                   /* Fan is controlled by the SMC microcode. */
	PHM_PlatformCaps_AdjustUVDPriorityForSP,
	PHM_PlatformCaps_DisableLightSleep,                     /* Light sleep for evergreen family. */
	PHM_PlatformCaps_DisableMCLS,                           /* MC Light sleep */
	PHM_PlatformCaps_RegulatorHot,                          /* Enable throttling on 'regulator hot' events. */
	PHM_PlatformCaps_BACO,                                  /* Support Bus Alive Chip Off mode */
	PHM_PlatformCaps_DisableDPM,                            /* Disable DPM, supported from Llano */
	PHM_PlatformCaps_DynamicM3Arbiter,                      /* support dynamically change m3 arbitor parameters */
	PHM_PlatformCaps_SclkDeepSleep,                         /* support sclk deep sleep */
	PHM_PlatformCaps_DynamicPatchPowerState,                /* this ASIC supports to patch power state dynamically */
	PHM_PlatformCaps_ThermalAutoThrottling,                 /* enabling auto thermal throttling, */
	PHM_PlatformCaps_SumoThermalPolicy,                     /* A thermal policy specific for Sumo */
	PHM_PlatformCaps_PCIEPerformanceRequest,                /* support to change RC voltage */
	PHM_PlatformCaps_BLControlledByGPU,                     /* support varibright */
	PHM_PlatformCaps_PowerContainment,                      /* support DPM2 power containment (AKA TDP clamping) */
	PHM_PlatformCaps_SQRamping,                             /* support DPM2 SQ power throttle */
	PHM_PlatformCaps_CAC,                                   /* support Capacitance * Activity power estimation */
	PHM_PlatformCaps_NIChipsets,                            /* Northern Island and beyond chipsets */
	PHM_PlatformCaps_TrinityChipsets,                       /* Trinity chipset */
	PHM_PlatformCaps_EvergreenChipsets,                     /* Evergreen family chipset */
	PHM_PlatformCaps_PowerControl,                          /* Cayman and beyond chipsets */
	PHM_PlatformCaps_DisableLSClockGating,                  /* to disable Light Sleep control for HDP memories */
	PHM_PlatformCaps_BoostState,                            /* this ASIC supports boost state */
	PHM_PlatformCaps_UserMaxClockForMultiDisplays,          /* indicates if max memory clock is used for all status when multiple displays are connected */
	PHM_PlatformCaps_RegWriteDelay,                         /* indicates if back to back reg write delay is required */
	PHM_PlatformCaps_NonABMSupportInPPLib,                  /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
	PHM_PlatformCaps_GFXDynamicMGPowerGating,               /* Enable Dynamic MG PowerGating on Trinity */
	PHM_PlatformCaps_DisableSMUUVDHandshake,                /* Disable SMU UVD Handshake */
	PHM_PlatformCaps_DTE,                                   /* Support Digital Temperature Estimation */
	PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,            /* This is for the feature requested by David B., and Tonny W.*/
	PHM_PlatformCaps_UVDPowerGating,                        /* enable UVD power gating, supported from Llano */
	PHM_PlatformCaps_UVDDynamicPowerGating,                 /* enable UVD Dynamic power gating, supported from UVD5 */
	PHM_PlatformCaps_VCEPowerGating,                        /* Enable VCE power gating, supported for TN and later ASICs */
	PHM_PlatformCaps_SamuPowerGating,                       /* Enable SAMU power gating, supported for KV and later ASICs */
	PHM_PlatformCaps_UVDDPM,                                /* UVD clock DPM */
	PHM_PlatformCaps_VCEDPM,                                /* VCE clock DPM */
	PHM_PlatformCaps_SamuDPM,                               /* SAMU clock DPM */
	PHM_PlatformCaps_AcpDPM,                                /* ACP clock DPM */
	PHM_PlatformCaps_SclkDeepSleepAboveLow,                 /* Enable SCLK Deep Sleep on all DPM states */
	PHM_PlatformCaps_DynamicUVDState,                       /* Dynamic UVD State */
	PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
	PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,            /* Set UVD Clk With Dummy Back End */
	PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,            /* Set VCE Clk With Dummy Back End */
	PHM_PlatformCaps_WantACPClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
	PHM_PlatformCaps_OD6inACSupport,                        /* indicates that the ASIC/back end supports OD6 */
	PHM_PlatformCaps_OD6inDCSupport,                        /* indicates that the ASIC/back end supports OD6 in DC */
	PHM_PlatformCaps_EnablePlatformPowerManagement,         /* indicates that Platform Power Management feature is supported */
	PHM_PlatformCaps_SurpriseRemoval,                       /* indicates that surprise removal feature is requested */
	PHM_PlatformCaps_NewCACVoltage,                         /* indicates new CAC voltage table support */
	PHM_PlatformCaps_DBRamping,                             /* for dI/dT feature */
	PHM_PlatformCaps_TDRamping,                             /* for dI/dT feature */
	PHM_PlatformCaps_TCPRamping,                            /* for dI/dT feature */
	PHM_PlatformCaps_EnableSMU7ThermalManagement,           /* SMC will manage thermal events */
	PHM_PlatformCaps_FPS,                                   /* FPS support */
	PHM_PlatformCaps_ACP,                                   /* ACP support */
	PHM_PlatformCaps_SclkThrottleLowNotification,           /* SCLK Throttle Low Notification */
	PHM_PlatformCaps_XDMAEnabled,                           /* XDMA engine is enabled */
	PHM_PlatformCaps_UseDummyBackEnd,                       /* use dummy back end */
	PHM_PlatformCaps_EnableDFSBypass,                       /* Enable DFS bypass */
	PHM_PlatformCaps_VddNBDirectRequest,
	PHM_PlatformCaps_PauseMMSessions,
	PHM_PlatformCaps_UnTabledHardwareInterface,             /* Tableless/direct call hardware interface for CI and newer ASICs */
	PHM_PlatformCaps_SMU7,                                  /* indicates that vpuRecoveryBegin without SMU shutdown */
	PHM_PlatformCaps_RevertGPIO5Polarity,                   /* indicates revert GPIO5 plarity table support */
	PHM_PlatformCaps_Thermal2GPIO17,                        /* indicates thermal2GPIO17 table support */
	PHM_PlatformCaps_ThermalOutGPIO,                        /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
	PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,      /* Disable memory clock switch during Framelock */
	PHM_PlatformCaps_VRHotGPIOConfigurable,                 /* indicates VR_HOT GPIO configurable */
	PHM_PlatformCaps_TempInversion,                         /* enable Temp Inversion feature */
	PHM_PlatformCaps_IOIC3,
	PHM_PlatformCaps_ConnectedStandby,
	PHM_PlatformCaps_EVV,
	PHM_PlatformCaps_EnableLongIdleBACOSupport,
	PHM_PlatformCaps_CombinePCCWithThermalSignal,
	PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
	PHM_PlatformCaps_StablePState,
	PHM_PlatformCaps_OD6PlusinACSupport,
	PHM_PlatformCaps_OD6PlusinDCSupport,
	PHM_PlatformCaps_ODThermalLimitUnlock,
	PHM_PlatformCaps_ReducePowerLimit,
	PHM_PlatformCaps_ODFuzzyFanControlSupport,
	PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
	PHM_PlatformCaps_ControlVDDGFX,
	PHM_PlatformCaps_BBBSupported,
	PHM_PlatformCaps_DisableVoltageIsland,
	PHM_PlatformCaps_FanSpeedInTableIsRPM,
	PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
	PHM_PlatformCaps_IcelandULPSSWWorkAround,
	PHM_PlatformCaps_FPSEnhancement,
	PHM_PlatformCaps_LoadPostProductionFirmware,
	PHM_PlatformCaps_VpuRecoveryInProgress,
	PHM_PlatformCaps_Falcon_QuickTransition,
	PHM_PlatformCaps_AVFS,
	PHM_PlatformCaps_ClockStretcher,
	PHM_PlatformCaps_TablelessHardwareInterface,
	PHM_PlatformCaps_EnableDriverEVV,
	PHM_PlatformCaps_Max
};

#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)

/* Number of uint32_t entries used by CAPS table */
#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
	((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))

struct pp_hw_descriptor {
	uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
};

enum PHM_PerformanceLevelDesignation {
	PHM_PerformanceLevelDesignation_Activity,
	PHM_PerformanceLevelDesignation_PowerContainment
};

typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;

struct PHM_PerformanceLevel {
    uint32_t    coreClock;
    uint32_t    memory_clock;
    uint32_t  vddc;
    uint32_t  vddci;
    uint32_t    nonLocalMemoryFreq;
    uint32_t nonLocalMemoryWidth;
};

typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;

/* Function for setting a platform cap */
static inline void phm_cap_set(uint32_t *caps,
			enum phm_platform_caps c)
{
	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
			     (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
}

static inline void phm_cap_unset(uint32_t *caps,
			enum phm_platform_caps c)
{
	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
}

static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
{
	return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
		  (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
}

#define PP_PCIEGenInvalid  0xffff
enum PP_PCIEGen {
    PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
    PP_PCIEGen2,                    /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
    PP_PCIEGen3                     /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
};

typedef enum PP_PCIEGen PP_PCIEGen;

#define PP_Min_PCIEGen     PP_PCIEGen1
#define PP_Max_PCIEGen     PP_PCIEGen3
#define PP_Min_PCIELane    1
#define PP_Max_PCIELane    32

enum phm_clock_Type {
	PHM_DispClock = 1,
	PHM_SClock,
	PHM_MemClock
};

#define MAX_NUM_CLOCKS 16

struct PP_Clocks {
	uint32_t engineClock;
	uint32_t memoryClock;
	uint32_t BusBandwidth;
	uint32_t engineClockInSR;
};

struct pp_clock_info {
	uint32_t min_mem_clk;
	uint32_t max_mem_clk;
	uint32_t min_eng_clk;
	uint32_t max_eng_clk;
	uint32_t min_bus_bandwidth;
	uint32_t max_bus_bandwidth;
};

struct phm_platform_descriptor {
	uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
	uint32_t vbiosInterruptId;
	struct PP_Clocks overdriveLimit;
	struct PP_Clocks clockStep;
	uint32_t hardwareActivityPerformanceLevels;
	uint32_t minimumClocksReductionPercentage;
	uint32_t minOverdriveVDDC;
	uint32_t maxOverdriveVDDC;
	uint32_t overdriveVDDCStep;
	uint32_t hardwarePerformanceLevels;
	uint16_t powerBudget;
	uint32_t TDPLimit;
	uint32_t nearTDPLimit;
	uint32_t nearTDPLimitAdjusted;
	uint32_t SQRampingThreshold;
	uint32_t CACLeakage;
	uint16_t TDPODLimit;
	uint32_t TDPAdjustment;
	bool TDPAdjustmentPolarity;
	uint16_t LoadLineSlope;
	uint32_t  VidMinLimit;
	uint32_t  VidMaxLimit;
	uint32_t  VidStep;
	uint32_t  VidAdjustment;
	bool VidAdjustmentPolarity;
};

struct phm_clocks {
	uint32_t num_of_entries;
	uint32_t clock[MAX_NUM_CLOCKS];
};

extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
		    const struct pp_hw_power_state *pcurrent_state,
		 const struct pp_hw_power_state *pnew_power_state);

extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				   struct pp_power_state *adjusted_ps,
			     const struct pp_power_state *current_ps);

extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);

extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
				 const struct pp_hw_power_state *pstate1,
				 const struct pp_hw_power_state *pstate2,
				 bool *equal);

extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
		const struct amd_pp_display_configuration *display_config);

extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
		struct amd_pp_simple_clock_info *info);

extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);

extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);

extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
				PHM_PerformanceLevelDesignation designation, uint32_t index,
				PHM_PerformanceLevel *level);

extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
			struct pp_clock_info *pclock_info,
			PHM_PerformanceLevelDesignation designation);

extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);

extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);

extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);

#endif /* _HARDWARE_MANAGER_H_ */
Commit	Line	Data
3bace359 JZ	1	/*
	2	* Copyright 2015 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef _HARDWARE_MANAGER_H_
	24	#define _HARDWARE_MANAGER_H_
	25
28a18bab RZ	26
28a18bab RZ	27
3bace359	28	struct pp_hwmgr;
28a18bab RZ	29	struct pp_hw_power_state;
	30	struct pp_power_state;
	31	enum amd_dpm_forced_level;
fba4eef5 RZ	32	struct PP_TemperatureRange;
fba4eef5 RZ	33
e273b041	34
fba4eef5 RZ	35	struct phm_fan_speed_info {
	36	uint32_t min_percent;
	37	uint32_t max_percent;
	38	uint32_t min_rpm;
	39	uint32_t max_rpm;
	40	bool supports_percent_read;
	41	bool supports_percent_write;
	42	bool supports_rpm_read;
	43	bool supports_rpm_write;
	44	};
3bace359 JZ	45
	46	/* Automatic Power State Throttling */
	47	enum PHM_AutoThrottleSource
	48	{
	49	PHM_AutoThrottleSource_Thermal,
	50	PHM_AutoThrottleSource_External
	51	};
	52
	53	typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
	54
	55	enum phm_platform_caps {
	56	PHM_PlatformCaps_AtomBiosPpV1 = 0,
	57	PHM_PlatformCaps_PowerPlaySupport,
	58	PHM_PlatformCaps_ACOverdriveSupport,
	59	PHM_PlatformCaps_BacklightSupport,
	60	PHM_PlatformCaps_ThermalController,
	61	PHM_PlatformCaps_BiosPowerSourceControl,
	62	PHM_PlatformCaps_DisableVoltageTransition,
	63	PHM_PlatformCaps_DisableEngineTransition,
	64	PHM_PlatformCaps_DisableMemoryTransition,
	65	PHM_PlatformCaps_DynamicPowerManagement,
	66	PHM_PlatformCaps_EnableASPML0s,
	67	PHM_PlatformCaps_EnableASPML1,
	68	PHM_PlatformCaps_OD5inACSupport,
	69	PHM_PlatformCaps_OD5inDCSupport,
	70	PHM_PlatformCaps_SoftStateOD5,
	71	PHM_PlatformCaps_NoOD5Support,
	72	PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
	73	PHM_PlatformCaps_ActivityReporting,
	74	PHM_PlatformCaps_EnableBackbias,
	75	PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
	76	PHM_PlatformCaps_ShowPowerBudgetWarning,
	77	PHM_PlatformCaps_PowerBudgetWaiverAvailable,
	78	PHM_PlatformCaps_GFXClockGatingSupport,
	79	PHM_PlatformCaps_MMClockGatingSupport,
	80	PHM_PlatformCaps_AutomaticDCTransition,
	81	PHM_PlatformCaps_GeminiPrimary,
	82	PHM_PlatformCaps_MemorySpreadSpectrumSupport,
	83	PHM_PlatformCaps_EngineSpreadSpectrumSupport,
	84	PHM_PlatformCaps_StepVddc,
	85	PHM_PlatformCaps_DynamicPCIEGen2Support,
	86	PHM_PlatformCaps_SMC,
	87	PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */
	88	PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */
	89	PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */
	90	PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */
	91	PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */
	92	PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overrided/automated mode. */
	93	PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */
	94	PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */
	95	PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */
	96	PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */
	97	PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */
	98	PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
	99	PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */
	100	PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
	101	PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
	102	PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */
	103	PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
	104	PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */
	105	PHM_PlatformCaps_ABM, /* ABM support.*/
	106	PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */
	107	PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */
	108	PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */
109	PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */
110	PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */
111	PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */
112	PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */
113	PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */
114	PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */
115	PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
116	PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
117	PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */
118	PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */
119	PHM_PlatformCaps_AdjustUVDPriorityForSP,
120	PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */
121	PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */
122	PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */
123	PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */
124	PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */
125	PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */
126	PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */
127	PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */
128	PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */
129	PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */
130	PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */
131	PHM_PlatformCaps_BLControlledByGPU, /* support varibright */
132	PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */
133	PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */
134	PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */
135	PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */
136	PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */
137	PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */
138	PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */
139	PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */
140	PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */
141	PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */
142	PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */
143	PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
144	PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */
145	PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */
146	PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */
147	PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/
148	PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */
149	PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */
150	PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */
151	PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */
152	PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */
153	PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */
154	PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */
155	PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */
156	PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */
157	PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */
158	PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
159	PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */
160	PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */
161	PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
162	PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */
163	PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */
164	PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */
165	PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */
166	PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */
167	PHM_PlatformCaps_DBRamping, /* for dI/dT feature */
168	PHM_PlatformCaps_TDRamping, /* for dI/dT feature */
169	PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */
170	PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */
171	PHM_PlatformCaps_FPS, /* FPS support */
172	PHM_PlatformCaps_ACP, /* ACP support */
173	PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */
174	PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */
175	PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */
176	PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */
177	PHM_PlatformCaps_VddNBDirectRequest,
178	PHM_PlatformCaps_PauseMMSessions,
179	PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */
180	PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */
181	PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */
182	PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */
183	PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
184	PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */
185	PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */
186	PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */
187	PHM_PlatformCaps_IOIC3,
188	PHM_PlatformCaps_ConnectedStandby,
189	PHM_PlatformCaps_EVV,
190	PHM_PlatformCaps_EnableLongIdleBACOSupport,
191	PHM_PlatformCaps_CombinePCCWithThermalSignal,
192	PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
193	PHM_PlatformCaps_StablePState,
194	PHM_PlatformCaps_OD6PlusinACSupport,
195	PHM_PlatformCaps_OD6PlusinDCSupport,
196	PHM_PlatformCaps_ODThermalLimitUnlock,
197	PHM_PlatformCaps_ReducePowerLimit,
198	PHM_PlatformCaps_ODFuzzyFanControlSupport,
199	PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
200	PHM_PlatformCaps_ControlVDDGFX,
201	PHM_PlatformCaps_BBBSupported,
202	PHM_PlatformCaps_DisableVoltageIsland,
203	PHM_PlatformCaps_FanSpeedInTableIsRPM,
204	PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
205	PHM_PlatformCaps_IcelandULPSSWWorkAround,
206	PHM_PlatformCaps_FPSEnhancement,
207	PHM_PlatformCaps_LoadPostProductionFirmware,
208	PHM_PlatformCaps_VpuRecoveryInProgress,
209	PHM_PlatformCaps_Falcon_QuickTransition,
210	PHM_PlatformCaps_AVFS,
211	PHM_PlatformCaps_ClockStretcher,
212	PHM_PlatformCaps_TablelessHardwareInterface,
213	PHM_PlatformCaps_EnableDriverEVV,
214	PHM_PlatformCaps_Max
215	};
216
217	#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
218
219	/* Number of uint32_t entries used by CAPS table */
220	#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
221	((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
222
223	struct pp_hw_descriptor {
224	uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
225	};
226
28a18bab RZ	227	enum PHM_PerformanceLevelDesignation {
	228	PHM_PerformanceLevelDesignation_Activity,
	229	PHM_PerformanceLevelDesignation_PowerContainment
	230	};
	231
	232	typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
	233
	234	struct PHM_PerformanceLevel {
c82baa28	235	uint32_t coreClock;
	236	uint32_t memory_clock;
	237	uint32_t vddc;
	238	uint32_t vddci;
	239	uint32_t nonLocalMemoryFreq;
	240	uint32_t nonLocalMemoryWidth;
28a18bab RZ	241	};
	242
	243	typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
	244
3bace359 JZ	245	/* Function for setting a platform cap */
	246	static inline void phm_cap_set(uint32_t *caps,
	247	enum phm_platform_caps c)
	248	{
	249	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] \|= (1UL <<
	250	(c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
	251	}
	252
	253	static inline void phm_cap_unset(uint32_t *caps,
	254	enum phm_platform_caps c)
	255	{
	256	caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
	257	}
	258
	259	static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
	260	{
	261	return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
	262	(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
	263	}
	264
28a18bab RZ	265	#define PP_PCIEGenInvalid 0xffff
28a18bab RZ	266	enum PP_PCIEGen {
c82baa28	267	PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
	268	PP_PCIEGen2, /PCIE 2.0 - Transfer rate of 5.0 GT/s /
	269	PP_PCIEGen3 /PCIE 3.0 - Transfer rate of 8.0 GT/s /
28a18bab RZ	270	};
	271
	272	typedef enum PP_PCIEGen PP_PCIEGen;
	273
	274	#define PP_Min_PCIEGen PP_PCIEGen1
	275	#define PP_Max_PCIEGen PP_PCIEGen3
	276	#define PP_Min_PCIELane 1
	277	#define PP_Max_PCIELane 32
	278
3bace359 JZ	279	enum phm_clock_Type {
	280	PHM_DispClock = 1,
	281	PHM_SClock,
	282	PHM_MemClock
	283	};
	284
	285	#define MAX_NUM_CLOCKS 16
	286
	287	struct PP_Clocks {
	288	uint32_t engineClock;
	289	uint32_t memoryClock;
	290	uint32_t BusBandwidth;
	291	uint32_t engineClockInSR;
	292	};
	293
e273b041 RZ	294	struct pp_clock_info {
	295	uint32_t min_mem_clk;
	296	uint32_t max_mem_clk;
	297	uint32_t min_eng_clk;
	298	uint32_t max_eng_clk;
	299	uint32_t min_bus_bandwidth;
	300	uint32_t max_bus_bandwidth;
	301	};
	302
3bace359 JZ	303	struct phm_platform_descriptor {
	304	uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
	305	uint32_t vbiosInterruptId;
	306	struct PP_Clocks overdriveLimit;
	307	struct PP_Clocks clockStep;
	308	uint32_t hardwareActivityPerformanceLevels;
	309	uint32_t minimumClocksReductionPercentage;
	310	uint32_t minOverdriveVDDC;
	311	uint32_t maxOverdriveVDDC;
	312	uint32_t overdriveVDDCStep;
	313	uint32_t hardwarePerformanceLevels;
	314	uint16_t powerBudget;
	315	uint32_t TDPLimit;
	316	uint32_t nearTDPLimit;
	317	uint32_t nearTDPLimitAdjusted;
	318	uint32_t SQRampingThreshold;
	319	uint32_t CACLeakage;
	320	uint16_t TDPODLimit;
	321	uint32_t TDPAdjustment;
	322	bool TDPAdjustmentPolarity;
	323	uint16_t LoadLineSlope;
	324	uint32_t VidMinLimit;
	325	uint32_t VidMaxLimit;
	326	uint32_t VidStep;
	327	uint32_t VidAdjustment;
	328	bool VidAdjustmentPolarity;
	329	};
	330
	331	struct phm_clocks {
	332	uint32_t num_of_entries;
	333	uint32_t clock[MAX_NUM_CLOCKS];
	334	};
09b4c872	335
28a18bab RZ	336	extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
	337	extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
	338	extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
	339	extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
3bace359 JZ	340	extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
	341	extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
	342	extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
28a18bab RZ	343	extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
	344	extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
	345	extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
	346	const struct pp_hw_power_state *pcurrent_state,
	347	const struct pp_hw_power_state *pnew_power_state);
	348
	349	extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
	350	struct pp_power_state *adjusted_ps,
	351	const struct pp_power_state *current_ps);
	352
	353	extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
6f3bf747 RZ	354	extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
6f3bf747 RZ	355	extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
fba4eef5 RZ	356	extern int phm_register_thermal_interrupt(struct pp_hwmgr hwmgr, const void info);
	357	extern int phm_start_thermal_controller(struct pp_hwmgr hwmgr, struct PP_TemperatureRange temperature_range);
	358	extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
09b4c872 RZ	359	extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
	360
	361	extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
	362	const struct pp_hw_power_state *pstate1,
	363	const struct pp_hw_power_state *pstate2,
	364	bool *equal);
	365
7fb72a1f	366	extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
c4dd206b VP	367	const struct amd_pp_display_configuration *display_config);
	368
	369	extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
47329134	370	struct amd_pp_simple_clock_info *info);
7fb72a1f	371
73afe621 RZ	372	extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
73afe621 RZ	373
e1d32e60 RZ	374	extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
e1d32e60 RZ	375
e273b041 RZ	376	extern int phm_get_performance_level(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state,
	377	PHM_PerformanceLevelDesignation designation, uint32_t index,
	378	PHM_PerformanceLevel *level);
	379
	380	extern int phm_get_clock_info(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state,
	381	struct pp_clock_info *pclock_info,
	382	PHM_PerformanceLevelDesignation designation);
	383
	384	extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr hwmgr, const struct pp_hw_power_state state, struct pp_clock_info *clock_info);
	385
	386	extern int phm_get_clock_by_type(struct pp_hwmgr hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks clocks);
	387
	388	extern int phm_get_max_high_clocks(struct pp_hwmgr hwmgr, struct amd_pp_simple_clock_info clocks);
	389
3bace359	390	#endif /* _HARDWARE_MANAGER_H_ */
fba4eef5	391