[deliverable/linux.git] / drivers / gpu / drm / arc / arcpgu_crtc.c

/*
 * ARC PGU DRM driver.
 *
 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_plane_helper.h>
#include <linux/clk.h>
#include <linux/platform_data/simplefb.h>

#include "arcpgu.h"
#include "arcpgu_regs.h"

#define ENCODE_PGU_XY(x, y)	((((x) - 1) << 16) | ((y) - 1))

static struct simplefb_format supported_formats[] = {
	{ "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
	{ "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
};

static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	uint32_t pixel_format = crtc->primary->state->fb->pixel_format;
	struct simplefb_format *format = NULL;
	int i;

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
		if (supported_formats[i].fourcc == pixel_format)
			format = &supported_formats[i];
	}

	if (WARN_ON(!format))
		return;

	if (format->fourcc == DRM_FORMAT_RGB888)
		arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
			      arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
					   ARCPGU_MODE_RGB888_MASK);

}

static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
	.destroy = drm_crtc_cleanup,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = drm_atomic_helper_crtc_reset,
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
};

static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	struct drm_display_mode *m = &crtc->state->adjusted_mode;
	u32 val;

	arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
		      ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));

	arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
		      ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
				    m->crtc_hsync_end - m->crtc_hdisplay));

	arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
		      ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
				    m->crtc_vsync_end - m->crtc_vdisplay));

	arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
		      ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
				    m->crtc_vblank_end - m->crtc_vblank_start));

	val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);

	if (m->flags & DRM_MODE_FLAG_PVSYNC)
		val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
	else
		val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);

	if (m->flags & DRM_MODE_FLAG_PHSYNC)
		val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
	else
		val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);

	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
	arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
	arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);

	arc_pgu_set_pxl_fmt(crtc);

	clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
}

static void arc_pgu_crtc_enable(struct drm_crtc *crtc)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);

	clk_prepare_enable(arcpgu->clk);
	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
		      arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
		      ARCPGU_CTRL_ENABLE_MASK);
}

static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);

	if (!crtc->primary->fb)
		return;

	clk_disable_unprepare(arcpgu->clk);
	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
			      arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
			      ~ARCPGU_CTRL_ENABLE_MASK);
}

static int arc_pgu_crtc_atomic_check(struct drm_crtc *crtc,
				     struct drm_crtc_state *state)
{
	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	struct drm_display_mode *mode = &state->adjusted_mode;
	long rate, clk_rate = mode->clock * 1000;

	rate = clk_round_rate(arcpgu->clk, clk_rate);
	if (rate != clk_rate)
		return -EINVAL;

	return 0;
}

static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
				      struct drm_crtc_state *state)
{
	struct drm_pending_vblank_event *event = crtc->state->event;

	if (event) {
		crtc->state->event = NULL;

		spin_lock_irq(&crtc->dev->event_lock);
		drm_crtc_send_vblank_event(crtc, event);
		spin_unlock_irq(&crtc->dev->event_lock);
	}
}

static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
	.mode_set	= drm_helper_crtc_mode_set,
	.mode_set_base	= drm_helper_crtc_mode_set_base,
	.mode_set_nofb	= arc_pgu_crtc_mode_set_nofb,
	.enable		= arc_pgu_crtc_enable,
	.disable	= arc_pgu_crtc_disable,
	.prepare	= arc_pgu_crtc_disable,
	.commit		= arc_pgu_crtc_enable,
	.atomic_check	= arc_pgu_crtc_atomic_check,
	.atomic_begin	= arc_pgu_crtc_atomic_begin,
};

static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
					struct drm_plane_state *state)
{
	struct arcpgu_drm_private *arcpgu;
	struct drm_gem_cma_object *gem;

	if (!plane->state->crtc || !plane->state->fb)
		return;

	arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
	gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
	arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
}

static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
	.atomic_update = arc_pgu_plane_atomic_update,
};

static void arc_pgu_plane_destroy(struct drm_plane *plane)
{
	drm_plane_helper_disable(plane);
	drm_plane_cleanup(plane);
}

static const struct drm_plane_funcs arc_pgu_plane_funcs = {
	.update_plane		= drm_atomic_helper_update_plane,
	.disable_plane		= drm_atomic_helper_disable_plane,
	.destroy		= arc_pgu_plane_destroy,
	.reset			= drm_atomic_helper_plane_reset,
	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	.atomic_destroy_state	= drm_atomic_helper_plane_destroy_state,
};

static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
{
	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	struct drm_plane *plane = NULL;
	u32 formats[ARRAY_SIZE(supported_formats)], i;
	int ret;

	plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
	if (!plane)
		return ERR_PTR(-ENOMEM);

	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
		formats[i] = supported_formats[i].fourcc;

	ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
				       formats, ARRAY_SIZE(formats),
				       DRM_PLANE_TYPE_PRIMARY, NULL);
	if (ret)
		return ERR_PTR(ret);

	drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
	arcpgu->plane = plane;

	return plane;
}

int arc_pgu_setup_crtc(struct drm_device *drm)
{
	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	struct drm_plane *primary;
	int ret;

	primary = arc_pgu_plane_init(drm);
	if (IS_ERR(primary))
		return PTR_ERR(primary);

	ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
					&arc_pgu_crtc_funcs, NULL);
	if (ret) {
		arc_pgu_plane_destroy(primary);
		return ret;
	}

	drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
	return 0;
}
Commit	Line	Data
51dacf20 CP	1	/*
	2	* ARC PGU DRM driver.
	3	*
	4	* Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#include <drm/drm_atomic_helper.h>
	18	#include <drm/drm_crtc_helper.h>
	19	#include <drm/drm_fb_cma_helper.h>
	20	#include <drm/drm_gem_cma_helper.h>
	21	#include <drm/drm_plane_helper.h>
	22	#include <linux/clk.h>
	23	#include <linux/platform_data/simplefb.h>
	24
	25	#include "arcpgu.h"
	26	#include "arcpgu_regs.h"
	27
	28	#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) \| ((y) - 1))
	29
	30	static struct simplefb_format supported_formats[] = {
	31	{ "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
	32	{ "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
	33	};
	34
	35	static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
	36	{
	37	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
	38	uint32_t pixel_format = crtc->primary->state->fb->pixel_format;
	39	struct simplefb_format *format = NULL;
	40	int i;
	41
	42	for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
	43	if (supported_formats[i].fourcc == pixel_format)
	44	format = &supported_formats[i];
	45	}
	46
	47	if (WARN_ON(!format))
	48	return;
	49
	50	if (format->fourcc == DRM_FORMAT_RGB888)
	51	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
	52	arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) \|
	53	ARCPGU_MODE_RGB888_MASK);
	54
	55	}
	56
	57	static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
	58	.destroy = drm_crtc_cleanup,
	59	.set_config = drm_atomic_helper_set_config,
	60	.page_flip = drm_atomic_helper_page_flip,
	61	.reset = drm_atomic_helper_crtc_reset,
	62	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	63	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	64	};
65
66	static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
67	{
68	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
69	struct drm_display_mode *m = &crtc->state->adjusted_mode;
70	u32 val;
71
72	arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
73	ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
74
75	arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
76	ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
77	m->crtc_hsync_end - m->crtc_hdisplay));
78
79	arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
80	ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
81	m->crtc_vsync_end - m->crtc_vdisplay));
82
83	arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
84	ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
85	m->crtc_vblank_end - m->crtc_vblank_start));
86
87	val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
88
89	if (m->flags & DRM_MODE_FLAG_PVSYNC)
90	val \|= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
91	else
92	val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
93
94	if (m->flags & DRM_MODE_FLAG_PHSYNC)
95	val \|= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
96	else
97	val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
98
99	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
100	arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
101	arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
102
103	arc_pgu_set_pxl_fmt(crtc);
104
105	clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
106	}
107
108	static void arc_pgu_crtc_enable(struct drm_crtc *crtc)
109	{
110	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
111
112	clk_prepare_enable(arcpgu->clk);
113	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
114	arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) \|
115	ARCPGU_CTRL_ENABLE_MASK);
116	}
117
118	static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
119	{
120	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
121
122	if (!crtc->primary->fb)
123	return;
124
125	clk_disable_unprepare(arcpgu->clk);
126	arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
127	arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
128	~ARCPGU_CTRL_ENABLE_MASK);
129	}
130
131	static int arc_pgu_crtc_atomic_check(struct drm_crtc *crtc,
132	struct drm_crtc_state *state)
133	{
134	struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
135	struct drm_display_mode *mode = &state->adjusted_mode;
136	long rate, clk_rate = mode->clock * 1000;
137
138	rate = clk_round_rate(arcpgu->clk, clk_rate);
139	if (rate != clk_rate)
140	return -EINVAL;
141
142	return 0;
143	}
144
145	static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
146	struct drm_crtc_state *state)
147	{
84d9a4a2	148	struct drm_pending_vblank_event *event = crtc->state->event;
51dacf20	149
84d9a4a2	150	if (event) {
51dacf20	151	crtc->state->event = NULL;
51dacf20	152
84d9a4a2 DV	153	spin_lock_irq(&crtc->dev->event_lock);
	154	drm_crtc_send_vblank_event(crtc, event);
	155	spin_unlock_irq(&crtc->dev->event_lock);
51dacf20 CP	156	}
	157	}
	158
	159	static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
	160	.mode_set = drm_helper_crtc_mode_set,
	161	.mode_set_base = drm_helper_crtc_mode_set_base,
	162	.mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
	163	.enable = arc_pgu_crtc_enable,
	164	.disable = arc_pgu_crtc_disable,
	165	.prepare = arc_pgu_crtc_disable,
	166	.commit = arc_pgu_crtc_enable,
	167	.atomic_check = arc_pgu_crtc_atomic_check,
	168	.atomic_begin = arc_pgu_crtc_atomic_begin,
	169	};
	170
	171	static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
	172	struct drm_plane_state *state)
	173	{
	174	struct arcpgu_drm_private *arcpgu;
	175	struct drm_gem_cma_object *gem;
	176
	177	if (!plane->state->crtc \|\| !plane->state->fb)
	178	return;
	179
	180	arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
	181	gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
	182	arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
	183	}
	184
	185	static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
51dacf20 CP	186	.atomic_update = arc_pgu_plane_atomic_update,
	187	};
	188
	189	static void arc_pgu_plane_destroy(struct drm_plane *plane)
	190	{
	191	drm_plane_helper_disable(plane);
	192	drm_plane_cleanup(plane);
	193	}
	194
	195	static const struct drm_plane_funcs arc_pgu_plane_funcs = {
	196	.update_plane = drm_atomic_helper_update_plane,
	197	.disable_plane = drm_atomic_helper_disable_plane,
	198	.destroy = arc_pgu_plane_destroy,
	199	.reset = drm_atomic_helper_plane_reset,
	200	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
	201	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
	202	};
	203
	204	static struct drm_plane arc_pgu_plane_init(struct drm_device drm)
	205	{
	206	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	207	struct drm_plane *plane = NULL;
	208	u32 formats[ARRAY_SIZE(supported_formats)], i;
	209	int ret;
	210
	211	plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
	212	if (!plane)
	213	return ERR_PTR(-ENOMEM);
	214
	215	for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
	216	formats[i] = supported_formats[i].fourcc;
	217
	218	ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
	219	formats, ARRAY_SIZE(formats),
	220	DRM_PLANE_TYPE_PRIMARY, NULL);
	221	if (ret)
	222	return ERR_PTR(ret);
	223
	224	drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
	225	arcpgu->plane = plane;
	226
	227	return plane;
	228	}
	229
	230	int arc_pgu_setup_crtc(struct drm_device *drm)
	231	{
	232	struct arcpgu_drm_private *arcpgu = drm->dev_private;
	233	struct drm_plane *primary;
	234	int ret;
	235
	236	primary = arc_pgu_plane_init(drm);
	237	if (IS_ERR(primary))
	238	return PTR_ERR(primary);
	239
	240	ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
	241	&arc_pgu_crtc_funcs, NULL);
	242	if (ret) {
	243	arc_pgu_plane_destroy(primary);
	244	return ret;
	245	}
	246
	247	drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
	248	return 0;
	249	}