projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/etnaviv: add further minor features and varyings count
[deliverable/linux.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
CommitLineData
a8c21a54
T		 1/*
2 * Copyright (C) 2015 Etnaviv Project
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/component.h>
18#include <linux/fence.h>
19#include <linux/moduleparam.h>
20#include <linux/of_device.h>
21#include "etnaviv_dump.h"
22#include "etnaviv_gpu.h"
23#include "etnaviv_gem.h"
24#include "etnaviv_mmu.h"
25#include "etnaviv_iommu.h"
26#include "etnaviv_iommu_v2.h"
27#include "common.xml.h"
28#include "state.xml.h"
29#include "state_hi.xml.h"
30#include "cmdstream.xml.h"
31
32static const struct platform_device_id gpu_ids[] = {
33 { .name = "etnaviv-gpu,2d" },
34 { },
35};
36
37static bool etnaviv_dump_core = true;
38module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
39
40/*
41 * Driver functions:
42 */
43
44int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
45{
46 switch (param) {
47 case ETNAVIV_PARAM_GPU_MODEL:
48 *value = gpu->identity.model;
49 break;
50
51 case ETNAVIV_PARAM_GPU_REVISION:
52 *value = gpu->identity.revision;
53 break;
54
55 case ETNAVIV_PARAM_GPU_FEATURES_0:
56 *value = gpu->identity.features;
57 break;
58
59 case ETNAVIV_PARAM_GPU_FEATURES_1:
60 *value = gpu->identity.minor_features0;
61 break;
62
63 case ETNAVIV_PARAM_GPU_FEATURES_2:
64 *value = gpu->identity.minor_features1;
65 break;
66
67 case ETNAVIV_PARAM_GPU_FEATURES_3:
68 *value = gpu->identity.minor_features2;
69 break;
70
71 case ETNAVIV_PARAM_GPU_FEATURES_4:
72 *value = gpu->identity.minor_features3;
73 break;
74
602eb489
RK		 75 case ETNAVIV_PARAM_GPU_FEATURES_5:
76 *value = gpu->identity.minor_features4;
77 break;
78
79 case ETNAVIV_PARAM_GPU_FEATURES_6:
80 *value = gpu->identity.minor_features5;
81 break;
82
a8c21a54
T		 83 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
84 *value = gpu->identity.stream_count;
85 break;
86
87 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
88 *value = gpu->identity.register_max;
89 break;
90
91 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
92 *value = gpu->identity.thread_count;
93 break;
94
95 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
96 *value = gpu->identity.vertex_cache_size;
97 break;
98
99 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
100 *value = gpu->identity.shader_core_count;
101 break;
102
103 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
104 *value = gpu->identity.pixel_pipes;
105 break;
106
107 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
108 *value = gpu->identity.vertex_output_buffer_size;
109 break;
110
111 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
112 *value = gpu->identity.buffer_size;
113 break;
114
115 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
116 *value = gpu->identity.instruction_count;
117 break;
118
119 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
120 *value = gpu->identity.num_constants;
121 break;
122
602eb489
RK		 123 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
124 *value = gpu->identity.varyings_count;
125 break;
126
a8c21a54
T		 127 default:
128 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
129 return -EINVAL;
130 }
131
132 return 0;
133}
134
472f79dc
RK		 135
136#define etnaviv_is_model_rev(gpu, mod, rev) \
137 ((gpu)->identity.model == chipModel_##mod && \
138 (gpu)->identity.revision == rev)
52f36ba1
RK		 139#define etnaviv_field(val, field) \
140 (((val) & field##__MASK) >> field##__SHIFT)
141
a8c21a54
T		 142static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
143{
144 if (gpu->identity.minor_features0 &
145 chipMinorFeatures0_MORE_MINOR_FEATURES) {
602eb489
RK		 146 u32 specs[4];
147 unsigned int streams;
a8c21a54
T		 148
149 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
150 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
602eb489
RK		 151 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
152 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
a8c21a54 153
52f36ba1
RK		 154 gpu->identity.stream_count = etnaviv_field(specs[0],
155 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
156 gpu->identity.register_max = etnaviv_field(specs[0],
157 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
158 gpu->identity.thread_count = etnaviv_field(specs[0],
159 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
160 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
161 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
162 gpu->identity.shader_core_count = etnaviv_field(specs[0],
163 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
164 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
165 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
a8c21a54 166 gpu->identity.vertex_output_buffer_size =
52f36ba1
RK		 167 etnaviv_field(specs[0],
168 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
169
170 gpu->identity.buffer_size = etnaviv_field(specs[1],
171 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
172 gpu->identity.instruction_count = etnaviv_field(specs[1],
173 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
174 gpu->identity.num_constants = etnaviv_field(specs[1],
175 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
602eb489
RK		 176
177 gpu->identity.varyings_count = etnaviv_field(specs[2],
178 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
179
180 /* This overrides the value from older register if non-zero */
181 streams = etnaviv_field(specs[3],
182 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
183 if (streams)
184 gpu->identity.stream_count = streams;
a8c21a54
T		 185 }
186
187 /* Fill in the stream count if not specified */
188 if (gpu->identity.stream_count == 0) {
189 if (gpu->identity.model >= 0x1000)
190 gpu->identity.stream_count = 4;
191 else
192 gpu->identity.stream_count = 1;
193 }
194
195 /* Convert the register max value */
196 if (gpu->identity.register_max)
197 gpu->identity.register_max = 1 << gpu->identity.register_max;
507f8991 198 else if (gpu->identity.model == chipModel_GC400)
a8c21a54
T		 199 gpu->identity.register_max = 32;
200 else
201 gpu->identity.register_max = 64;
202
203 /* Convert thread count */
204 if (gpu->identity.thread_count)
205 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
507f8991 206 else if (gpu->identity.model == chipModel_GC400)
a8c21a54 207 gpu->identity.thread_count = 64;
507f8991
RK		 208 else if (gpu->identity.model == chipModel_GC500 ||
209 gpu->identity.model == chipModel_GC530)
a8c21a54
T		 210 gpu->identity.thread_count = 128;
211 else
212 gpu->identity.thread_count = 256;
213
214 if (gpu->identity.vertex_cache_size == 0)
215 gpu->identity.vertex_cache_size = 8;
216
217 if (gpu->identity.shader_core_count == 0) {
218 if (gpu->identity.model >= 0x1000)
219 gpu->identity.shader_core_count = 2;
220 else
221 gpu->identity.shader_core_count = 1;
222 }
223
224 if (gpu->identity.pixel_pipes == 0)
225 gpu->identity.pixel_pipes = 1;
226
227 /* Convert virtex buffer size */
228 if (gpu->identity.vertex_output_buffer_size) {
229 gpu->identity.vertex_output_buffer_size =
230 1 << gpu->identity.vertex_output_buffer_size;
507f8991 231 } else if (gpu->identity.model == chipModel_GC400) {
a8c21a54
T		 232 if (gpu->identity.revision < 0x4000)
233 gpu->identity.vertex_output_buffer_size = 512;
234 else if (gpu->identity.revision < 0x4200)
235 gpu->identity.vertex_output_buffer_size = 256;
236 else
237 gpu->identity.vertex_output_buffer_size = 128;
238 } else {
239 gpu->identity.vertex_output_buffer_size = 512;
240 }
241
242 switch (gpu->identity.instruction_count) {
243 case 0:
472f79dc 244 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
507f8991 245 gpu->identity.model == chipModel_GC880)
a8c21a54
T		 246 gpu->identity.instruction_count = 512;
247 else
248 gpu->identity.instruction_count = 256;
249 break;
250
251 case 1:
252 gpu->identity.instruction_count = 1024;
253 break;
254
255 case 2:
256 gpu->identity.instruction_count = 2048;
257 break;
258
259 default:
260 gpu->identity.instruction_count = 256;
261 break;
262 }
263
264 if (gpu->identity.num_constants == 0)
265 gpu->identity.num_constants = 168;
602eb489
RK		 266
267 if (gpu->identity.varyings_count == 0) {
268 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
269 gpu->identity.varyings_count = 12;
270 else
271 gpu->identity.varyings_count = 8;
272 }
273
274 /*
275 * For some cores, two varyings are consumed for position, so the
276 * maximum varying count needs to be reduced by one.
277 */
278 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
279 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
280 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
281 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
282 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
283 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
284 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
285 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
286 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
287 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
288 etnaviv_is_model_rev(gpu, GC880, 0x5106))
289 gpu->identity.varyings_count -= 1;
a8c21a54
T		 290}
291
292static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
293{
294 u32 chipIdentity;
295
296 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
297
298 /* Special case for older graphic cores. */
52f36ba1 299 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
507f8991 300 gpu->identity.model = chipModel_GC500;
52f36ba1
RK		 301 gpu->identity.revision = etnaviv_field(chipIdentity,
302 VIVS_HI_CHIP_IDENTITY_REVISION);
a8c21a54
T		 303 } else {
304
305 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
306 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
307
308 /*
309 * !!!! HACK ALERT !!!!
310 * Because people change device IDs without letting software
311 * know about it - here is the hack to make it all look the
312 * same. Only for GC400 family.
313 */
314 if ((gpu->identity.model & 0xff00) == 0x0400 &&
507f8991 315 gpu->identity.model != chipModel_GC420) {
a8c21a54
T		 316 gpu->identity.model = gpu->identity.model & 0x0400;
317 }
318
319 /* Another special case */
472f79dc 320 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
a8c21a54
T		 321 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
322 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
323
324 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
325 /*
326 * This IP has an ECO; put the correct
327 * revision in it.
328 */
329 gpu->identity.revision = 0x1051;
330 }
331 }
332 }
333
334 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
335 gpu->identity.model, gpu->identity.revision);
336
337 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
338
339 /* Disable fast clear on GC700. */
507f8991 340 if (gpu->identity.model == chipModel_GC700)
a8c21a54
T		 341 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
342
507f8991
RK		 343 if ((gpu->identity.model == chipModel_GC500 &&
344 gpu->identity.revision < 2) ||
345 (gpu->identity.model == chipModel_GC300 &&
346 gpu->identity.revision < 0x2000)) {
a8c21a54
T		 347
348 /*
349 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
350 * registers.
351 */
352 gpu->identity.minor_features0 = 0;
353 gpu->identity.minor_features1 = 0;
354 gpu->identity.minor_features2 = 0;
355 gpu->identity.minor_features3 = 0;
602eb489
RK		 356 gpu->identity.minor_features4 = 0;
357 gpu->identity.minor_features5 = 0;
a8c21a54
T		 358 } else
359 gpu->identity.minor_features0 =
360 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
361
362 if (gpu->identity.minor_features0 &
363 chipMinorFeatures0_MORE_MINOR_FEATURES) {
364 gpu->identity.minor_features1 =
365 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
366 gpu->identity.minor_features2 =
367 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
368 gpu->identity.minor_features3 =
369 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
602eb489
RK		 370 gpu->identity.minor_features4 =
371 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
372 gpu->identity.minor_features5 =
373 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
a8c21a54
T		 374 }
375
376 /* GC600 idle register reports zero bits where modules aren't present */
377 if (gpu->identity.model == chipModel_GC600) {
378 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
379 VIVS_HI_IDLE_STATE_RA |
380 VIVS_HI_IDLE_STATE_SE |
381 VIVS_HI_IDLE_STATE_PA |
382 VIVS_HI_IDLE_STATE_SH |
383 VIVS_HI_IDLE_STATE_PE |
384 VIVS_HI_IDLE_STATE_DE |
385 VIVS_HI_IDLE_STATE_FE;
386 } else {
387 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
388 }
389
390 etnaviv_hw_specs(gpu);
391}
392
393static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
394{
395 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
396 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
397 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
398}
399
400static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
401{
402 u32 control, idle;
403 unsigned long timeout;
404 bool failed = true;
405
406 /* TODO
407 *
408 * - clock gating
409 * - puls eater
410 * - what about VG?
411 */
412
413 /* We hope that the GPU resets in under one second */
414 timeout = jiffies + msecs_to_jiffies(1000);
415
416 while (time_is_after_jiffies(timeout)) {
417 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
418 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
419
420 /* enable clock */
421 etnaviv_gpu_load_clock(gpu, control);
422
423 /* Wait for stable clock. Vivante's code waited for 1ms */
424 usleep_range(1000, 10000);
425
426 /* isolate the GPU. */
427 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
428 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
429
430 /* set soft reset. */
431 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
432 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
433
434 /* wait for reset. */
435 msleep(1);
436
437 /* reset soft reset bit. */
438 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
439 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
440
441 /* reset GPU isolation. */
442 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
443 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
444
445 /* read idle register. */
446 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
447
448 /* try reseting again if FE it not idle */
449 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
450 dev_dbg(gpu->dev, "FE is not idle\n");
451 continue;
452 }
453
454 /* read reset register. */
455 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
456
457 /* is the GPU idle? */
458 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
459 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
460 dev_dbg(gpu->dev, "GPU is not idle\n");
461 continue;
462 }
463
464 failed = false;
465 break;
466 }
467
468 if (failed) {
469 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
470 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
471
472 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
473 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
474 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
475 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
476
477 return -EBUSY;
478 }
479
480 /* We rely on the GPU running, so program the clock */
481 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
482 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
483
484 /* enable clock */
485 etnaviv_gpu_load_clock(gpu, control);
486
487 return 0;
488}
489
490static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
491{
492 u16 prefetch;
493
472f79dc
RK		 494 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
495 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
496 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
a8c21a54
T		 497 u32 mc_memory_debug;
498
499 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
500
501 if (gpu->identity.revision == 0x5007)
502 mc_memory_debug |= 0x0c;
503 else
504 mc_memory_debug |= 0x08;
505
506 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
507 }
508
509 /*
510 * Update GPU AXI cache atttribute to "cacheable, no allocate".
511 * This is necessary to prevent the iMX6 SoC locking up.
512 */
513 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
514 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
515 VIVS_HI_AXI_CONFIG_ARCACHE(2));
516
517 /* GC2000 rev 5108 needs a special bus config */
472f79dc 518 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
a8c21a54
T		 519 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
520 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
521 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
522 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
523 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
524 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
525 }
526
527 /* set base addresses */
528 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
529 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
530 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
531 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
532 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
533
534 /* setup the MMU page table pointers */
535 etnaviv_iommu_domain_restore(gpu, gpu->mmu->domain);
536
537 /* Start command processor */
538 prefetch = etnaviv_buffer_init(gpu);
539
540 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
541 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS,
542 gpu->buffer->paddr - gpu->memory_base);
543 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
544 VIVS_FE_COMMAND_CONTROL_ENABLE |
545 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
546}
547
548int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
549{
550 int ret, i;
551 struct iommu_domain *iommu;
552 enum etnaviv_iommu_version version;
553 bool mmuv2;
554
555 ret = pm_runtime_get_sync(gpu->dev);
556 if (ret < 0)
557 return ret;
558
559 etnaviv_hw_identify(gpu);
560
561 if (gpu->identity.model == 0) {
562 dev_err(gpu->dev, "Unknown GPU model\n");
f6427760
RK		 563 ret = -ENXIO;
564 goto fail;
a8c21a54
T		 565 }
566
b98c6688
RK		 567 /* Exclude VG cores with FE2.0 */
568 if (gpu->identity.features & chipFeatures_PIPE_VG &&
569 gpu->identity.features & chipFeatures_FE20) {
570 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
571 ret = -ENXIO;
572 goto fail;
573 }
574
a8c21a54
T		 575 ret = etnaviv_hw_reset(gpu);
576 if (ret)
577 goto fail;
578
579 /* Setup IOMMU.. eventually we will (I think) do this once per context
580 * and have separate page tables per context. For now, to keep things
581 * simple and to get something working, just use a single address space:
582 */
583 mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION;
584 dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2);
585
586 if (!mmuv2) {
587 iommu = etnaviv_iommu_domain_alloc(gpu);
588 version = ETNAVIV_IOMMU_V1;
589 } else {
590 iommu = etnaviv_iommu_v2_domain_alloc(gpu);
591 version = ETNAVIV_IOMMU_V2;
592 }
593
594 if (!iommu) {
595 ret = -ENOMEM;
596 goto fail;
597 }
598
599 /* TODO: we will leak here memory - fix it! */
600
601 gpu->mmu = etnaviv_iommu_new(gpu, iommu, version);
602 if (!gpu->mmu) {
603 ret = -ENOMEM;
604 goto fail;
605 }
606
607 /* Create buffer: */
608 gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
609 if (!gpu->buffer) {
610 ret = -ENOMEM;
611 dev_err(gpu->dev, "could not create command buffer\n");
612 goto fail;
613 }
614 if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
615 ret = -EINVAL;
616 dev_err(gpu->dev,
617 "command buffer outside valid memory window\n");
618 goto free_buffer;
619 }
620
621 /* Setup event management */
622 spin_lock_init(&gpu->event_spinlock);
623 init_completion(&gpu->event_free);
624 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
625 gpu->event[i].used = false;
626 complete(&gpu->event_free);
627 }
628
629 /* Now program the hardware */
630 mutex_lock(&gpu->lock);
631 etnaviv_gpu_hw_init(gpu);
632 mutex_unlock(&gpu->lock);
633
634 pm_runtime_mark_last_busy(gpu->dev);
635 pm_runtime_put_autosuspend(gpu->dev);
636
637 return 0;
638
639free_buffer:
640 etnaviv_gpu_cmdbuf_free(gpu->buffer);
641 gpu->buffer = NULL;
642fail:
643 pm_runtime_mark_last_busy(gpu->dev);
644 pm_runtime_put_autosuspend(gpu->dev);
645
646 return ret;
647}
648
649#ifdef CONFIG_DEBUG_FS
650struct dma_debug {
651 u32 address[2];
652 u32 state[2];
653};
654
655static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
656{
657 u32 i;
658
659 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
660 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
661
662 for (i = 0; i < 500; i++) {
663 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
664 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
665
666 if (debug->address[0] != debug->address[1])
667 break;
668
669 if (debug->state[0] != debug->state[1])
670 break;
671 }
672}
673
674int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
675{
676 struct dma_debug debug;
677 u32 dma_lo, dma_hi, axi, idle;
678 int ret;
679
680 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
681
682 ret = pm_runtime_get_sync(gpu->dev);
683 if (ret < 0)
684 return ret;
685
686 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
687 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
688 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
689 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
690
691 verify_dma(gpu, &debug);
692
693 seq_puts(m, "\tfeatures\n");
694 seq_printf(m, "\t minor_features0: 0x%08x\n",
695 gpu->identity.minor_features0);
696 seq_printf(m, "\t minor_features1: 0x%08x\n",
697 gpu->identity.minor_features1);
698 seq_printf(m, "\t minor_features2: 0x%08x\n",
699 gpu->identity.minor_features2);
700 seq_printf(m, "\t minor_features3: 0x%08x\n",
701 gpu->identity.minor_features3);
602eb489
RK		 702 seq_printf(m, "\t minor_features4: 0x%08x\n",
703 gpu->identity.minor_features4);
704 seq_printf(m, "\t minor_features5: 0x%08x\n",
705 gpu->identity.minor_features5);
a8c21a54
T		 706
707 seq_puts(m, "\tspecs\n");
708 seq_printf(m, "\t stream_count: %d\n",
709 gpu->identity.stream_count);
710 seq_printf(m, "\t register_max: %d\n",
711 gpu->identity.register_max);
712 seq_printf(m, "\t thread_count: %d\n",
713 gpu->identity.thread_count);
714 seq_printf(m, "\t vertex_cache_size: %d\n",
715 gpu->identity.vertex_cache_size);
716 seq_printf(m, "\t shader_core_count: %d\n",
717 gpu->identity.shader_core_count);
718 seq_printf(m, "\t pixel_pipes: %d\n",
719 gpu->identity.pixel_pipes);
720 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
721 gpu->identity.vertex_output_buffer_size);
722 seq_printf(m, "\t buffer_size: %d\n",
723 gpu->identity.buffer_size);
724 seq_printf(m, "\t instruction_count: %d\n",
725 gpu->identity.instruction_count);
726 seq_printf(m, "\t num_constants: %d\n",
727 gpu->identity.num_constants);
602eb489
RK		 728 seq_printf(m, "\t varyings_count: %d\n",
729 gpu->identity.varyings_count);
a8c21a54
T		 730
731 seq_printf(m, "\taxi: 0x%08x\n", axi);
732 seq_printf(m, "\tidle: 0x%08x\n", idle);
733 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
734 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
735 seq_puts(m, "\t FE is not idle\n");
736 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
737 seq_puts(m, "\t DE is not idle\n");
738 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
739 seq_puts(m, "\t PE is not idle\n");
740 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
741 seq_puts(m, "\t SH is not idle\n");
742 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
743 seq_puts(m, "\t PA is not idle\n");
744 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
745 seq_puts(m, "\t SE is not idle\n");
746 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
747 seq_puts(m, "\t RA is not idle\n");
748 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
749 seq_puts(m, "\t TX is not idle\n");
750 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
751 seq_puts(m, "\t VG is not idle\n");
752 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
753 seq_puts(m, "\t IM is not idle\n");
754 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
755 seq_puts(m, "\t FP is not idle\n");
756 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
757 seq_puts(m, "\t TS is not idle\n");
758 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
759 seq_puts(m, "\t AXI low power mode\n");
760
761 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
762 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
763 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
764 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
765
766 seq_puts(m, "\tMC\n");
767 seq_printf(m, "\t read0: 0x%08x\n", read0);
768 seq_printf(m, "\t read1: 0x%08x\n", read1);
769 seq_printf(m, "\t write: 0x%08x\n", write);
770 }
771
772 seq_puts(m, "\tDMA ");
773
774 if (debug.address[0] == debug.address[1] &&
775 debug.state[0] == debug.state[1]) {
776 seq_puts(m, "seems to be stuck\n");
777 } else if (debug.address[0] == debug.address[1]) {
778 seq_puts(m, "adress is constant\n");
779 } else {
780 seq_puts(m, "is runing\n");
781 }
782
783 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
784 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
785 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
786 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
787 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
788 dma_lo, dma_hi);
789
790 ret = 0;
791
792 pm_runtime_mark_last_busy(gpu->dev);
793 pm_runtime_put_autosuspend(gpu->dev);
794
795 return ret;
796}
797#endif
798
799/*
800 * Power Management:
801 */
802static int enable_clk(struct etnaviv_gpu *gpu)
803{
804 if (gpu->clk_core)
805 clk_prepare_enable(gpu->clk_core);
806 if (gpu->clk_shader)
807 clk_prepare_enable(gpu->clk_shader);
808
809 return 0;
810}
811
812static int disable_clk(struct etnaviv_gpu *gpu)
813{
814 if (gpu->clk_core)
815 clk_disable_unprepare(gpu->clk_core);
816 if (gpu->clk_shader)
817 clk_disable_unprepare(gpu->clk_shader);
818
819 return 0;
820}
821
822static int enable_axi(struct etnaviv_gpu *gpu)
823{
824 if (gpu->clk_bus)
825 clk_prepare_enable(gpu->clk_bus);
826
827 return 0;
828}
829
830static int disable_axi(struct etnaviv_gpu *gpu)
831{
832 if (gpu->clk_bus)
833 clk_disable_unprepare(gpu->clk_bus);
834
835 return 0;
836}
837
838/*
839 * Hangcheck detection for locked gpu:
840 */
841static void recover_worker(struct work_struct *work)
842{
843 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
844 recover_work);
845 unsigned long flags;
846 unsigned int i;
847
848 dev_err(gpu->dev, "hangcheck recover!\n");
849
850 if (pm_runtime_get_sync(gpu->dev) < 0)
851 return;
852
853 mutex_lock(&gpu->lock);
854
855 /* Only catch the first event, or when manually re-armed */
856 if (etnaviv_dump_core) {
857 etnaviv_core_dump(gpu);
858 etnaviv_dump_core = false;
859 }
860
861 etnaviv_hw_reset(gpu);
862
863 /* complete all events, the GPU won't do it after the reset */
864 spin_lock_irqsave(&gpu->event_spinlock, flags);
865 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
866 if (!gpu->event[i].used)
867 continue;
868 fence_signal(gpu->event[i].fence);
869 gpu->event[i].fence = NULL;
870 gpu->event[i].used = false;
871 complete(&gpu->event_free);
872 /*
873 * Decrement the PM count for each stuck event. This is safe
874 * even in atomic context as we use ASYNC RPM here.
875 */
876 pm_runtime_put_autosuspend(gpu->dev);
877 }
878 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
879 gpu->completed_fence = gpu->active_fence;
880
881 etnaviv_gpu_hw_init(gpu);
882 gpu->switch_context = true;
883
884 mutex_unlock(&gpu->lock);
885 pm_runtime_mark_last_busy(gpu->dev);
886 pm_runtime_put_autosuspend(gpu->dev);
887
888 /* Retire the buffer objects in a work */
889 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
890}
891
892static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
893{
894 DBG("%s", dev_name(gpu->dev));
895 mod_timer(&gpu->hangcheck_timer,
896 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
897}
898
899static void hangcheck_handler(unsigned long data)
900{
901 struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
902 u32 fence = gpu->completed_fence;
903 bool progress = false;
904
905 if (fence != gpu->hangcheck_fence) {
906 gpu->hangcheck_fence = fence;
907 progress = true;
908 }
909
910 if (!progress) {
911 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
912 int change = dma_addr - gpu->hangcheck_dma_addr;
913
914 if (change < 0 || change > 16) {
915 gpu->hangcheck_dma_addr = dma_addr;
916 progress = true;
917 }
918 }
919
920 if (!progress && fence_after(gpu->active_fence, fence)) {
921 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
922 dev_err(gpu->dev, " completed fence: %u\n", fence);
923 dev_err(gpu->dev, " active fence: %u\n",
924 gpu->active_fence);
925 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
926 }
927
928 /* if still more pending work, reset the hangcheck timer: */
929 if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
930 hangcheck_timer_reset(gpu);
931}
932
933static void hangcheck_disable(struct etnaviv_gpu *gpu)
934{
935 del_timer_sync(&gpu->hangcheck_timer);
936 cancel_work_sync(&gpu->recover_work);
937}
938
939/* fence object management */
940struct etnaviv_fence {
941 struct etnaviv_gpu *gpu;
942 struct fence base;
943};
944
945static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence)
946{
947 return container_of(fence, struct etnaviv_fence, base);
948}
949
950static const char *etnaviv_fence_get_driver_name(struct fence *fence)
951{
952 return "etnaviv";
953}
954
955static const char *etnaviv_fence_get_timeline_name(struct fence *fence)
956{
957 struct etnaviv_fence *f = to_etnaviv_fence(fence);
958
959 return dev_name(f->gpu->dev);
960}
961
962static bool etnaviv_fence_enable_signaling(struct fence *fence)
963{
964 return true;
965}
966
967static bool etnaviv_fence_signaled(struct fence *fence)
968{
969 struct etnaviv_fence *f = to_etnaviv_fence(fence);
970
971 return fence_completed(f->gpu, f->base.seqno);
972}
973
974static void etnaviv_fence_release(struct fence *fence)
975{
976 struct etnaviv_fence *f = to_etnaviv_fence(fence);
977
978 kfree_rcu(f, base.rcu);
979}
980
981static const struct fence_ops etnaviv_fence_ops = {
982 .get_driver_name = etnaviv_fence_get_driver_name,
983 .get_timeline_name = etnaviv_fence_get_timeline_name,
984 .enable_signaling = etnaviv_fence_enable_signaling,
985 .signaled = etnaviv_fence_signaled,
986 .wait = fence_default_wait,
987 .release = etnaviv_fence_release,
988};
989
990static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
991{
992 struct etnaviv_fence *f;
993
994 f = kzalloc(sizeof(*f), GFP_KERNEL);
995 if (!f)
996 return NULL;
997
998 f->gpu = gpu;
999
1000 fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1001 gpu->fence_context, ++gpu->next_fence);
1002
1003 return &f->base;
1004}
1005
1006int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1007 unsigned int context, bool exclusive)
1008{
1009 struct reservation_object *robj = etnaviv_obj->resv;
1010 struct reservation_object_list *fobj;
1011 struct fence *fence;
1012 int i, ret;
1013
1014 if (!exclusive) {
1015 ret = reservation_object_reserve_shared(robj);
1016 if (ret)
1017 return ret;
1018 }
1019
1020 /*
1021 * If we have any shared fences, then the exclusive fence
1022 * should be ignored as it will already have been signalled.
1023 */
1024 fobj = reservation_object_get_list(robj);
1025 if (!fobj || fobj->shared_count == 0) {
1026 /* Wait on any existing exclusive fence which isn't our own */
1027 fence = reservation_object_get_excl(robj);
1028 if (fence && fence->context != context) {
1029 ret = fence_wait(fence, true);
1030 if (ret)
1031 return ret;
1032 }
1033 }
1034
1035 if (!exclusive || !fobj)
1036 return 0;
1037
1038 for (i = 0; i < fobj->shared_count; i++) {
1039 fence = rcu_dereference_protected(fobj->shared[i],
1040 reservation_object_held(robj));
1041 if (fence->context != context) {
1042 ret = fence_wait(fence, true);
1043 if (ret)
1044 return ret;
1045 }
1046 }
1047
1048 return 0;
1049}
1050
1051/*
1052 * event management:
1053 */
1054
1055static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1056{
1057 unsigned long ret, flags;
1058 unsigned int i, event = ~0U;
1059
1060 ret = wait_for_completion_timeout(&gpu->event_free,
1061 msecs_to_jiffies(10 * 10000));
1062 if (!ret)
1063 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1064
1065 spin_lock_irqsave(&gpu->event_spinlock, flags);
1066
1067 /* find first free event */
1068 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1069 if (gpu->event[i].used == false) {
1070 gpu->event[i].used = true;
1071 event = i;
1072 break;
1073 }
1074 }
1075
1076 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1077
1078 return event;
1079}
1080
1081static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1082{
1083 unsigned long flags;
1084
1085 spin_lock_irqsave(&gpu->event_spinlock, flags);
1086
1087 if (gpu->event[event].used == false) {
1088 dev_warn(gpu->dev, "event %u is already marked as free",
1089 event);
1090 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1091 } else {
1092 gpu->event[event].used = false;
1093 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1094
1095 complete(&gpu->event_free);
1096 }
1097}
1098
1099/*
1100 * Cmdstream submission/retirement:
1101 */
1102
1103struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1104 size_t nr_bos)
1105{
1106 struct etnaviv_cmdbuf *cmdbuf;
1107 size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo[0]),
1108 sizeof(*cmdbuf));
1109
1110 cmdbuf = kzalloc(sz, GFP_KERNEL);
1111 if (!cmdbuf)
1112 return NULL;
1113
1114 cmdbuf->vaddr = dma_alloc_writecombine(gpu->dev, size, &cmdbuf->paddr,
1115 GFP_KERNEL);
1116 if (!cmdbuf->vaddr) {
1117 kfree(cmdbuf);
1118 return NULL;
1119 }
1120
1121 cmdbuf->gpu = gpu;
1122 cmdbuf->size = size;
1123
1124 return cmdbuf;
1125}
1126
1127void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1128{
1129 dma_free_writecombine(cmdbuf->gpu->dev, cmdbuf->size,
1130 cmdbuf->vaddr, cmdbuf->paddr);
1131 kfree(cmdbuf);
1132}
1133
1134static void retire_worker(struct work_struct *work)
1135{
1136 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1137 retire_work);
1138 u32 fence = gpu->completed_fence;
1139 struct etnaviv_cmdbuf *cmdbuf, *tmp;
1140 unsigned int i;
1141
1142 mutex_lock(&gpu->lock);
1143 list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1144 if (!fence_is_signaled(cmdbuf->fence))
1145 break;
1146
1147 list_del(&cmdbuf->node);
1148 fence_put(cmdbuf->fence);
1149
1150 for (i = 0; i < cmdbuf->nr_bos; i++) {
1151 struct etnaviv_gem_object *etnaviv_obj = cmdbuf->bo[i];
1152
1153 atomic_dec(&etnaviv_obj->gpu_active);
1154 /* drop the refcount taken in etnaviv_gpu_submit */
1155 etnaviv_gem_put_iova(gpu, &etnaviv_obj->base);
1156 }
1157
1158 etnaviv_gpu_cmdbuf_free(cmdbuf);
1159 }
1160
1161 gpu->retired_fence = fence;
1162
1163 mutex_unlock(&gpu->lock);
1164
1165 wake_up_all(&gpu->fence_event);
1166}
1167
1168int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1169 u32 fence, struct timespec *timeout)
1170{
1171 int ret;
1172
1173 if (fence_after(fence, gpu->next_fence)) {
1174 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1175 fence, gpu->next_fence);
1176 return -EINVAL;
1177 }
1178
1179 if (!timeout) {
1180 /* No timeout was requested: just test for completion */
1181 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1182 } else {
1183 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1184
1185 ret = wait_event_interruptible_timeout(gpu->fence_event,
1186 fence_completed(gpu, fence),
1187 remaining);
1188 if (ret == 0) {
1189 DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1190 fence, gpu->retired_fence,
1191 gpu->completed_fence);
1192 ret = -ETIMEDOUT;
1193 } else if (ret != -ERESTARTSYS) {
1194 ret = 0;
1195 }
1196 }
1197
1198 return ret;
1199}
1200
1201/*
1202 * Wait for an object to become inactive. This, on it's own, is not race
1203 * free: the object is moved by the retire worker off the active list, and
1204 * then the iova is put. Moreover, the object could be re-submitted just
1205 * after we notice that it's become inactive.
1206 *
1207 * Although the retirement happens under the gpu lock, we don't want to hold
1208 * that lock in this function while waiting.
1209 */
1210int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1211 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1212{
1213 unsigned long remaining;
1214 long ret;
1215
1216 if (!timeout)
1217 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1218
1219 remaining = etnaviv_timeout_to_jiffies(timeout);
1220
1221 ret = wait_event_interruptible_timeout(gpu->fence_event,
1222 !is_active(etnaviv_obj),
1223 remaining);
1224 if (ret > 0) {
1225 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1226
1227 /* Synchronise with the retire worker */
1228 flush_workqueue(priv->wq);
1229 return 0;
1230 } else if (ret == -ERESTARTSYS) {
1231 return -ERESTARTSYS;
1232 } else {
1233 return -ETIMEDOUT;
1234 }
1235}
1236
1237int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1238{
1239 return pm_runtime_get_sync(gpu->dev);
1240}
1241
1242void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1243{
1244 pm_runtime_mark_last_busy(gpu->dev);
1245 pm_runtime_put_autosuspend(gpu->dev);
1246}
1247
1248/* add bo's to gpu's ring, and kick gpu: */
1249int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1250 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1251{
1252 struct fence *fence;
1253 unsigned int event, i;
1254 int ret;
1255
1256 ret = etnaviv_gpu_pm_get_sync(gpu);
1257 if (ret < 0)
1258 return ret;
1259
1260 mutex_lock(&gpu->lock);
1261
1262 /*
1263 * TODO
1264 *
1265 * - flush
1266 * - data endian
1267 * - prefetch
1268 *
1269 */
1270
1271 event = event_alloc(gpu);
1272 if (unlikely(event == ~0U)) {
1273 DRM_ERROR("no free event\n");
1274 ret = -EBUSY;
1275 goto out_unlock;
1276 }
1277
1278 fence = etnaviv_gpu_fence_alloc(gpu);
1279 if (!fence) {
1280 event_free(gpu, event);
1281 ret = -ENOMEM;
1282 goto out_unlock;
1283 }
1284
1285 gpu->event[event].fence = fence;
1286 submit->fence = fence->seqno;
1287 gpu->active_fence = submit->fence;
1288
1289 if (gpu->lastctx != cmdbuf->ctx) {
1290 gpu->mmu->need_flush = true;
1291 gpu->switch_context = true;
1292 gpu->lastctx = cmdbuf->ctx;
1293 }
1294
1295 etnaviv_buffer_queue(gpu, event, cmdbuf);
1296
1297 cmdbuf->fence = fence;
1298 list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1299
1300 /* We're committed to adding this command buffer, hold a PM reference */
1301 pm_runtime_get_noresume(gpu->dev);
1302
1303 for (i = 0; i < submit->nr_bos; i++) {
1304 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1305 u32 iova;
1306
1307 /* Each cmdbuf takes a refcount on the iova */
1308 etnaviv_gem_get_iova(gpu, &etnaviv_obj->base, &iova);
1309 cmdbuf->bo[i] = etnaviv_obj;
1310 atomic_inc(&etnaviv_obj->gpu_active);
1311
1312 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1313 reservation_object_add_excl_fence(etnaviv_obj->resv,
1314 fence);
1315 else
1316 reservation_object_add_shared_fence(etnaviv_obj->resv,
1317 fence);
1318 }
1319 cmdbuf->nr_bos = submit->nr_bos;
1320 hangcheck_timer_reset(gpu);
1321 ret = 0;
1322
1323out_unlock:
1324 mutex_unlock(&gpu->lock);
1325
1326 etnaviv_gpu_pm_put(gpu);
1327
1328 return ret;
1329}
1330
1331/*
1332 * Init/Cleanup:
1333 */
1334static irqreturn_t irq_handler(int irq, void *data)
1335{
1336 struct etnaviv_gpu *gpu = data;
1337 irqreturn_t ret = IRQ_NONE;
1338
1339 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1340
1341 if (intr != 0) {
1342 int event;
1343
1344 pm_runtime_mark_last_busy(gpu->dev);
1345
1346 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1347
1348 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1349 dev_err(gpu->dev, "AXI bus error\n");
1350 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1351 }
1352
1353 while ((event = ffs(intr)) != 0) {
1354 struct fence *fence;
1355
1356 event -= 1;
1357
1358 intr &= ~(1 << event);
1359
1360 dev_dbg(gpu->dev, "event %u\n", event);
1361
1362 fence = gpu->event[event].fence;
1363 gpu->event[event].fence = NULL;
1364 fence_signal(fence);
1365
1366 /*
1367 * Events can be processed out of order. Eg,
1368 * - allocate and queue event 0
1369 * - allocate event 1
1370 * - event 0 completes, we process it
1371 * - allocate and queue event 0
1372 * - event 1 and event 0 complete
1373 * we can end up processing event 0 first, then 1.
1374 */
1375 if (fence_after(fence->seqno, gpu->completed_fence))
1376 gpu->completed_fence = fence->seqno;
1377
1378 event_free(gpu, event);
1379
1380 /*
1381 * We need to balance the runtime PM count caused by
1382 * each submission. Upon submission, we increment
1383 * the runtime PM counter, and allocate one event.
1384 * So here, we put the runtime PM count for each
1385 * completed event.
1386 */
1387 pm_runtime_put_autosuspend(gpu->dev);
1388 }
1389
1390 /* Retire the buffer objects in a work */
1391 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1392
1393 ret = IRQ_HANDLED;
1394 }
1395
1396 return ret;
1397}
1398
1399static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1400{
1401 int ret;
1402
1403 ret = enable_clk(gpu);
1404 if (ret)
1405 return ret;
1406
1407 ret = enable_axi(gpu);
1408 if (ret) {
1409 disable_clk(gpu);
1410 return ret;
1411 }
1412
1413 return 0;
1414}
1415
1416static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1417{
1418 int ret;
1419
1420 ret = disable_axi(gpu);
1421 if (ret)
1422 return ret;
1423
1424 ret = disable_clk(gpu);
1425 if (ret)
1426 return ret;
1427
1428 return 0;
1429}
1430
1431static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1432{
1433 if (gpu->buffer) {
1434 unsigned long timeout;
1435
1436 /* Replace the last WAIT with END */
1437 etnaviv_buffer_end(gpu);
1438
1439 /*
1440 * We know that only the FE is busy here, this should
1441 * happen quickly (as the WAIT is only 200 cycles). If
1442 * we fail, just warn and continue.
1443 */
1444 timeout = jiffies + msecs_to_jiffies(100);
1445 do {
1446 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1447
1448 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1449 break;
1450
1451 if (time_is_before_jiffies(timeout)) {
1452 dev_warn(gpu->dev,
1453 "timed out waiting for idle: idle=0x%x\n",
1454 idle);
1455 break;
1456 }
1457
1458 udelay(5);
1459 } while (1);
1460 }
1461
1462 return etnaviv_gpu_clk_disable(gpu);
1463}
1464
1465#ifdef CONFIG_PM
1466static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1467{
1468 u32 clock;
1469 int ret;
1470
1471 ret = mutex_lock_killable(&gpu->lock);
1472 if (ret)
1473 return ret;
1474
1475 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1476 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1477
1478 etnaviv_gpu_load_clock(gpu, clock);
1479 etnaviv_gpu_hw_init(gpu);
1480
1481 gpu->switch_context = true;
1482
1483 mutex_unlock(&gpu->lock);
1484
1485 return 0;
1486}
1487#endif
1488
1489static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1490 void *data)
1491{
1492 struct drm_device *drm = data;
1493 struct etnaviv_drm_private *priv = drm->dev_private;
1494 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1495 int ret;
1496
1497#ifdef CONFIG_PM
1498 ret = pm_runtime_get_sync(gpu->dev);
1499#else
1500 ret = etnaviv_gpu_clk_enable(gpu);
1501#endif
1502 if (ret < 0)
1503 return ret;
1504
1505 gpu->drm = drm;
1506 gpu->fence_context = fence_context_alloc(1);
1507 spin_lock_init(&gpu->fence_spinlock);
1508
1509 INIT_LIST_HEAD(&gpu->active_cmd_list);
1510 INIT_WORK(&gpu->retire_work, retire_worker);
1511 INIT_WORK(&gpu->recover_work, recover_worker);
1512 init_waitqueue_head(&gpu->fence_event);
1513
1514 setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
1515 (unsigned long)gpu);
1516
1517 priv->gpu[priv->num_gpus++] = gpu;
1518
1519 pm_runtime_mark_last_busy(gpu->dev);
1520 pm_runtime_put_autosuspend(gpu->dev);
1521
1522 return 0;
1523}
1524
1525static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1526 void *data)
1527{
1528 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1529
1530 DBG("%s", dev_name(gpu->dev));
1531
1532 hangcheck_disable(gpu);
1533
1534#ifdef CONFIG_PM
1535 pm_runtime_get_sync(gpu->dev);
1536 pm_runtime_put_sync_suspend(gpu->dev);
1537#else
1538 etnaviv_gpu_hw_suspend(gpu);
1539#endif
1540
1541 if (gpu->buffer) {
1542 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1543 gpu->buffer = NULL;
1544 }
1545
1546 if (gpu->mmu) {
1547 etnaviv_iommu_destroy(gpu->mmu);
1548 gpu->mmu = NULL;
1549 }
1550
1551 gpu->drm = NULL;
1552}
1553
1554static const struct component_ops gpu_ops = {
1555 .bind = etnaviv_gpu_bind,
1556 .unbind = etnaviv_gpu_unbind,
1557};
1558
1559static const struct of_device_id etnaviv_gpu_match[] = {
1560 {
1561 .compatible = "vivante,gc"
1562 },
1563 { /* sentinel */ }
1564};
1565
1566static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1567{
1568 struct device *dev = &pdev->dev;
1569 struct etnaviv_gpu *gpu;
1570 int err = 0;
1571
1572 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1573 if (!gpu)
1574 return -ENOMEM;
1575
1576 gpu->dev = &pdev->dev;
1577 mutex_init(&gpu->lock);
1578
1579 /*
1580 * Set the GPU base address to the start of physical memory. This
1581 * ensures that if we have up to 2GB, the v1 MMU can address the
1582 * highest memory. This is important as command buffers may be
1583 * allocated outside of this limit.
1584 */
1585 gpu->memory_base = PHYS_OFFSET;
1586
1587 /* Map registers: */
1588 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1589 if (IS_ERR(gpu->mmio))
1590 return PTR_ERR(gpu->mmio);
1591
1592 /* Get Interrupt: */
1593 gpu->irq = platform_get_irq(pdev, 0);
1594 if (gpu->irq < 0) {
1595 err = gpu->irq;
1596 dev_err(dev, "failed to get irq: %d\n", err);
1597 goto fail;
1598 }
1599
1600 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1601 dev_name(gpu->dev), gpu);
1602 if (err) {
1603 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1604 goto fail;
1605 }
1606
1607 /* Get Clocks: */
1608 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1609 DBG("clk_bus: %p", gpu->clk_bus);
1610 if (IS_ERR(gpu->clk_bus))
1611 gpu->clk_bus = NULL;
1612
1613 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1614 DBG("clk_core: %p", gpu->clk_core);
1615 if (IS_ERR(gpu->clk_core))
1616 gpu->clk_core = NULL;
1617
1618 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1619 DBG("clk_shader: %p", gpu->clk_shader);
1620 if (IS_ERR(gpu->clk_shader))
1621 gpu->clk_shader = NULL;
1622
1623 /* TODO: figure out max mapped size */
1624 dev_set_drvdata(dev, gpu);
1625
1626 /*
1627 * We treat the device as initially suspended. The runtime PM
1628 * autosuspend delay is rather arbitary: no measurements have
1629 * yet been performed to determine an appropriate value.
1630 */
1631 pm_runtime_use_autosuspend(gpu->dev);
1632 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1633 pm_runtime_enable(gpu->dev);
1634
1635 err = component_add(&pdev->dev, &gpu_ops);
1636 if (err < 0) {
1637 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1638 goto fail;
1639 }
1640
1641 return 0;
1642
1643fail:
1644 return err;
1645}
1646
1647static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1648{
1649 component_del(&pdev->dev, &gpu_ops);
1650 pm_runtime_disable(&pdev->dev);
1651 return 0;
1652}
1653
1654#ifdef CONFIG_PM
1655static int etnaviv_gpu_rpm_suspend(struct device *dev)
1656{
1657 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1658 u32 idle, mask;
1659
1660 /* If we have outstanding fences, we're not idle */
1661 if (gpu->completed_fence != gpu->active_fence)
1662 return -EBUSY;
1663
1664 /* Check whether the hardware (except FE) is idle */
1665 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1666 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1667 if (idle != mask)
1668 return -EBUSY;
1669
1670 return etnaviv_gpu_hw_suspend(gpu);
1671}
1672
1673static int etnaviv_gpu_rpm_resume(struct device *dev)
1674{
1675 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1676 int ret;
1677
1678 ret = etnaviv_gpu_clk_enable(gpu);
1679 if (ret)
1680 return ret;
1681
1682 /* Re-initialise the basic hardware state */
1683 if (gpu->drm && gpu->buffer) {
1684 ret = etnaviv_gpu_hw_resume(gpu);
1685 if (ret) {
1686 etnaviv_gpu_clk_disable(gpu);
1687 return ret;
1688 }
1689 }
1690
1691 return 0;
1692}
1693#endif
1694
1695static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1696 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1697 NULL)
1698};
1699
1700struct platform_driver etnaviv_gpu_driver = {
1701 .driver = {
1702 .name = "etnaviv-gpu",
1703 .owner = THIS_MODULE,
1704 .pm = &etnaviv_gpu_pm_ops,
1705 .of_match_table = etnaviv_gpu_match,
1706 },
1707 .probe = etnaviv_gpu_platform_probe,
1708 .remove = etnaviv_gpu_platform_remove,
1709 .id_table = gpu_ids,
1710};
Linux kernel - Deliverables
This page took 0.096415 seconds and 5 git commands to generate.