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Merge branches 'acpi-soc', 'acpi-misc', 'acpi-pci' and 'device-properties'
[deliverable/linux.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
CommitLineData
a8c21a54
T		 1/*
2 * Copyright (C) 2015 Etnaviv Project
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/component.h>
18#include <linux/fence.h>
19#include <linux/moduleparam.h>
20#include <linux/of_device.h>
21#include "etnaviv_dump.h"
22#include "etnaviv_gpu.h"
23#include "etnaviv_gem.h"
24#include "etnaviv_mmu.h"
25#include "etnaviv_iommu.h"
26#include "etnaviv_iommu_v2.h"
27#include "common.xml.h"
28#include "state.xml.h"
29#include "state_hi.xml.h"
30#include "cmdstream.xml.h"
31
32static const struct platform_device_id gpu_ids[] = {
33 { .name = "etnaviv-gpu,2d" },
34 { },
35};
36
37static bool etnaviv_dump_core = true;
38module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
39
40/*
41 * Driver functions:
42 */
43
44int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
45{
46 switch (param) {
47 case ETNAVIV_PARAM_GPU_MODEL:
48 *value = gpu->identity.model;
49 break;
50
51 case ETNAVIV_PARAM_GPU_REVISION:
52 *value = gpu->identity.revision;
53 break;
54
55 case ETNAVIV_PARAM_GPU_FEATURES_0:
56 *value = gpu->identity.features;
57 break;
58
59 case ETNAVIV_PARAM_GPU_FEATURES_1:
60 *value = gpu->identity.minor_features0;
61 break;
62
63 case ETNAVIV_PARAM_GPU_FEATURES_2:
64 *value = gpu->identity.minor_features1;
65 break;
66
67 case ETNAVIV_PARAM_GPU_FEATURES_3:
68 *value = gpu->identity.minor_features2;
69 break;
70
71 case ETNAVIV_PARAM_GPU_FEATURES_4:
72 *value = gpu->identity.minor_features3;
73 break;
74
602eb489
RK		 75 case ETNAVIV_PARAM_GPU_FEATURES_5:
76 *value = gpu->identity.minor_features4;
77 break;
78
79 case ETNAVIV_PARAM_GPU_FEATURES_6:
80 *value = gpu->identity.minor_features5;
81 break;
82
a8c21a54
T		 83 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
84 *value = gpu->identity.stream_count;
85 break;
86
87 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
88 *value = gpu->identity.register_max;
89 break;
90
91 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
92 *value = gpu->identity.thread_count;
93 break;
94
95 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
96 *value = gpu->identity.vertex_cache_size;
97 break;
98
99 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
100 *value = gpu->identity.shader_core_count;
101 break;
102
103 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
104 *value = gpu->identity.pixel_pipes;
105 break;
106
107 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
108 *value = gpu->identity.vertex_output_buffer_size;
109 break;
110
111 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
112 *value = gpu->identity.buffer_size;
113 break;
114
115 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
116 *value = gpu->identity.instruction_count;
117 break;
118
119 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
120 *value = gpu->identity.num_constants;
121 break;
122
602eb489
RK		 123 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
124 *value = gpu->identity.varyings_count;
125 break;
126
a8c21a54
T		 127 default:
128 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
129 return -EINVAL;
130 }
131
132 return 0;
133}
134
472f79dc
RK		 135
136#define etnaviv_is_model_rev(gpu, mod, rev) \
137 ((gpu)->identity.model == chipModel_##mod && \
138 (gpu)->identity.revision == rev)
52f36ba1
RK		 139#define etnaviv_field(val, field) \
140 (((val) & field##__MASK) >> field##__SHIFT)
141
a8c21a54
T		 142static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
143{
144 if (gpu->identity.minor_features0 &
145 chipMinorFeatures0_MORE_MINOR_FEATURES) {
602eb489
RK		 146 u32 specs[4];
147 unsigned int streams;
a8c21a54
T		 148
149 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
150 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
602eb489
RK		 151 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
152 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
a8c21a54 153
52f36ba1
RK		 154 gpu->identity.stream_count = etnaviv_field(specs[0],
155 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
156 gpu->identity.register_max = etnaviv_field(specs[0],
157 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
158 gpu->identity.thread_count = etnaviv_field(specs[0],
159 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
160 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
161 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
162 gpu->identity.shader_core_count = etnaviv_field(specs[0],
163 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
164 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
165 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
a8c21a54 166 gpu->identity.vertex_output_buffer_size =
52f36ba1
RK		 167 etnaviv_field(specs[0],
168 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
169
170 gpu->identity.buffer_size = etnaviv_field(specs[1],
171 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
172 gpu->identity.instruction_count = etnaviv_field(specs[1],
173 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
174 gpu->identity.num_constants = etnaviv_field(specs[1],
175 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
602eb489
RK		 176
177 gpu->identity.varyings_count = etnaviv_field(specs[2],
178 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
179
180 /* This overrides the value from older register if non-zero */
181 streams = etnaviv_field(specs[3],
182 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
183 if (streams)
184 gpu->identity.stream_count = streams;
a8c21a54
T		 185 }
186
187 /* Fill in the stream count if not specified */
188 if (gpu->identity.stream_count == 0) {
189 if (gpu->identity.model >= 0x1000)
190 gpu->identity.stream_count = 4;
191 else
192 gpu->identity.stream_count = 1;
193 }
194
195 /* Convert the register max value */
196 if (gpu->identity.register_max)
197 gpu->identity.register_max = 1 << gpu->identity.register_max;
507f8991 198 else if (gpu->identity.model == chipModel_GC400)
a8c21a54
T		 199 gpu->identity.register_max = 32;
200 else
201 gpu->identity.register_max = 64;
202
203 /* Convert thread count */
204 if (gpu->identity.thread_count)
205 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
507f8991 206 else if (gpu->identity.model == chipModel_GC400)
a8c21a54 207 gpu->identity.thread_count = 64;
507f8991
RK		 208 else if (gpu->identity.model == chipModel_GC500 ||
209 gpu->identity.model == chipModel_GC530)
a8c21a54
T		 210 gpu->identity.thread_count = 128;
211 else
212 gpu->identity.thread_count = 256;
213
214 if (gpu->identity.vertex_cache_size == 0)
215 gpu->identity.vertex_cache_size = 8;
216
217 if (gpu->identity.shader_core_count == 0) {
218 if (gpu->identity.model >= 0x1000)
219 gpu->identity.shader_core_count = 2;
220 else
221 gpu->identity.shader_core_count = 1;
222 }
223
224 if (gpu->identity.pixel_pipes == 0)
225 gpu->identity.pixel_pipes = 1;
226
227 /* Convert virtex buffer size */
228 if (gpu->identity.vertex_output_buffer_size) {
229 gpu->identity.vertex_output_buffer_size =
230 1 << gpu->identity.vertex_output_buffer_size;
507f8991 231 } else if (gpu->identity.model == chipModel_GC400) {
a8c21a54
T		 232 if (gpu->identity.revision < 0x4000)
233 gpu->identity.vertex_output_buffer_size = 512;
234 else if (gpu->identity.revision < 0x4200)
235 gpu->identity.vertex_output_buffer_size = 256;
236 else
237 gpu->identity.vertex_output_buffer_size = 128;
238 } else {
239 gpu->identity.vertex_output_buffer_size = 512;
240 }
241
242 switch (gpu->identity.instruction_count) {
243 case 0:
472f79dc 244 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
507f8991 245 gpu->identity.model == chipModel_GC880)
a8c21a54
T		 246 gpu->identity.instruction_count = 512;
247 else
248 gpu->identity.instruction_count = 256;
249 break;
250
251 case 1:
252 gpu->identity.instruction_count = 1024;
253 break;
254
255 case 2:
256 gpu->identity.instruction_count = 2048;
257 break;
258
259 default:
260 gpu->identity.instruction_count = 256;
261 break;
262 }
263
264 if (gpu->identity.num_constants == 0)
265 gpu->identity.num_constants = 168;
602eb489
RK		 266
267 if (gpu->identity.varyings_count == 0) {
268 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
269 gpu->identity.varyings_count = 12;
270 else
271 gpu->identity.varyings_count = 8;
272 }
273
274 /*
275 * For some cores, two varyings are consumed for position, so the
276 * maximum varying count needs to be reduced by one.
277 */
278 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
279 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
280 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
281 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
282 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
283 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
284 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
285 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
286 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
287 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
288 etnaviv_is_model_rev(gpu, GC880, 0x5106))
289 gpu->identity.varyings_count -= 1;
a8c21a54
T		 290}
291
292static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
293{
294 u32 chipIdentity;
295
296 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
297
298 /* Special case for older graphic cores. */
52f36ba1 299 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
507f8991 300 gpu->identity.model = chipModel_GC500;
52f36ba1
RK		 301 gpu->identity.revision = etnaviv_field(chipIdentity,
302 VIVS_HI_CHIP_IDENTITY_REVISION);
a8c21a54
T		 303 } else {
304
305 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
306 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
307
308 /*
309 * !!!! HACK ALERT !!!!
310 * Because people change device IDs without letting software
311 * know about it - here is the hack to make it all look the
312 * same. Only for GC400 family.
313 */
314 if ((gpu->identity.model & 0xff00) == 0x0400 &&
507f8991 315 gpu->identity.model != chipModel_GC420) {
a8c21a54
T		 316 gpu->identity.model = gpu->identity.model & 0x0400;
317 }
318
319 /* Another special case */
472f79dc 320 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
a8c21a54
T		 321 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
322 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
323
324 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
325 /*
326 * This IP has an ECO; put the correct
327 * revision in it.
328 */
329 gpu->identity.revision = 0x1051;
330 }
331 }
332 }
333
334 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
335 gpu->identity.model, gpu->identity.revision);
336
337 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
338
339 /* Disable fast clear on GC700. */
507f8991 340 if (gpu->identity.model == chipModel_GC700)
a8c21a54
T		 341 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
342
507f8991
RK		 343 if ((gpu->identity.model == chipModel_GC500 &&
344 gpu->identity.revision < 2) ||
345 (gpu->identity.model == chipModel_GC300 &&
346 gpu->identity.revision < 0x2000)) {
a8c21a54
T		 347
348 /*
349 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
350 * registers.
351 */
352 gpu->identity.minor_features0 = 0;
353 gpu->identity.minor_features1 = 0;
354 gpu->identity.minor_features2 = 0;
355 gpu->identity.minor_features3 = 0;
602eb489
RK		 356 gpu->identity.minor_features4 = 0;
357 gpu->identity.minor_features5 = 0;
a8c21a54
T		 358 } else
359 gpu->identity.minor_features0 =
360 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
361
362 if (gpu->identity.minor_features0 &
363 chipMinorFeatures0_MORE_MINOR_FEATURES) {
364 gpu->identity.minor_features1 =
365 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
366 gpu->identity.minor_features2 =
367 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
368 gpu->identity.minor_features3 =
369 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
602eb489
RK		 370 gpu->identity.minor_features4 =
371 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
372 gpu->identity.minor_features5 =
373 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
a8c21a54
T		 374 }
375
376 /* GC600 idle register reports zero bits where modules aren't present */
377 if (gpu->identity.model == chipModel_GC600) {
378 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
379 VIVS_HI_IDLE_STATE_RA |
380 VIVS_HI_IDLE_STATE_SE |
381 VIVS_HI_IDLE_STATE_PA |
382 VIVS_HI_IDLE_STATE_SH |
383 VIVS_HI_IDLE_STATE_PE |
384 VIVS_HI_IDLE_STATE_DE |
385 VIVS_HI_IDLE_STATE_FE;
386 } else {
387 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
388 }
389
390 etnaviv_hw_specs(gpu);
391}
392
393static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
394{
395 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
396 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
397 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
398}
399
400static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
401{
402 u32 control, idle;
403 unsigned long timeout;
404 bool failed = true;
405
406 /* TODO
407 *
408 * - clock gating
409 * - puls eater
410 * - what about VG?
411 */
412
413 /* We hope that the GPU resets in under one second */
414 timeout = jiffies + msecs_to_jiffies(1000);
415
416 while (time_is_after_jiffies(timeout)) {
417 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
418 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
419
420 /* enable clock */
421 etnaviv_gpu_load_clock(gpu, control);
422
423 /* Wait for stable clock. Vivante's code waited for 1ms */
424 usleep_range(1000, 10000);
425
426 /* isolate the GPU. */
427 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
428 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
429
430 /* set soft reset. */
431 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
432 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
433
434 /* wait for reset. */
435 msleep(1);
436
437 /* reset soft reset bit. */
438 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
439 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
440
441 /* reset GPU isolation. */
442 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
443 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
444
445 /* read idle register. */
446 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
447
448 /* try reseting again if FE it not idle */
449 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
450 dev_dbg(gpu->dev, "FE is not idle\n");
451 continue;
452 }
453
454 /* read reset register. */
455 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
456
457 /* is the GPU idle? */
458 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
459 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
460 dev_dbg(gpu->dev, "GPU is not idle\n");
461 continue;
462 }
463
464 failed = false;
465 break;
466 }
467
468 if (failed) {
469 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
470 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
471
472 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
473 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
474 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
475 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
476
477 return -EBUSY;
478 }
479
480 /* We rely on the GPU running, so program the clock */
481 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
482 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
483
484 /* enable clock */
485 etnaviv_gpu_load_clock(gpu, control);
486
487 return 0;
488}
489
490static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
491{
492 u16 prefetch;
493
472f79dc
RK		 494 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
495 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
496 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
a8c21a54
T		 497 u32 mc_memory_debug;
498
499 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
500
501 if (gpu->identity.revision == 0x5007)
502 mc_memory_debug |= 0x0c;
503 else
504 mc_memory_debug |= 0x08;
505
506 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
507 }
508
509 /*
510 * Update GPU AXI cache atttribute to "cacheable, no allocate".
511 * This is necessary to prevent the iMX6 SoC locking up.
512 */
513 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
514 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
515 VIVS_HI_AXI_CONFIG_ARCACHE(2));
516
517 /* GC2000 rev 5108 needs a special bus config */
472f79dc 518 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
a8c21a54
T		 519 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
520 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
521 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
522 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
523 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
524 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
525 }
526
527 /* set base addresses */
528 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
529 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
530 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
531 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
532 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
533
534 /* setup the MMU page table pointers */
535 etnaviv_iommu_domain_restore(gpu, gpu->mmu->domain);
536
537 /* Start command processor */
538 prefetch = etnaviv_buffer_init(gpu);
539
540 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
541 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS,
542 gpu->buffer->paddr - gpu->memory_base);
543 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
544 VIVS_FE_COMMAND_CONTROL_ENABLE |
545 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
546}
547
548int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
549{
550 int ret, i;
551 struct iommu_domain *iommu;
552 enum etnaviv_iommu_version version;
553 bool mmuv2;
554
555 ret = pm_runtime_get_sync(gpu->dev);
556 if (ret < 0)
557 return ret;
558
559 etnaviv_hw_identify(gpu);
560
561 if (gpu->identity.model == 0) {
562 dev_err(gpu->dev, "Unknown GPU model\n");
f6427760
RK		 563 ret = -ENXIO;
564 goto fail;
a8c21a54
T		 565 }
566
b98c6688
RK		 567 /* Exclude VG cores with FE2.0 */
568 if (gpu->identity.features & chipFeatures_PIPE_VG &&
569 gpu->identity.features & chipFeatures_FE20) {
570 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
571 ret = -ENXIO;
572 goto fail;
573 }
574
a8c21a54
T		 575 ret = etnaviv_hw_reset(gpu);
576 if (ret)
577 goto fail;
578
579 /* Setup IOMMU.. eventually we will (I think) do this once per context
580 * and have separate page tables per context. For now, to keep things
581 * simple and to get something working, just use a single address space:
582 */
583 mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION;
584 dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2);
585
586 if (!mmuv2) {
587 iommu = etnaviv_iommu_domain_alloc(gpu);
588 version = ETNAVIV_IOMMU_V1;
589 } else {
590 iommu = etnaviv_iommu_v2_domain_alloc(gpu);
591 version = ETNAVIV_IOMMU_V2;
592 }
593
594 if (!iommu) {
595 ret = -ENOMEM;
596 goto fail;
597 }
598
a8c21a54
T		 599 gpu->mmu = etnaviv_iommu_new(gpu, iommu, version);
600 if (!gpu->mmu) {
45d16a6d 601 iommu_domain_free(iommu);
a8c21a54
T		 602 ret = -ENOMEM;
603 goto fail;
604 }
605
606 /* Create buffer: */
607 gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
608 if (!gpu->buffer) {
609 ret = -ENOMEM;
610 dev_err(gpu->dev, "could not create command buffer\n");
45d16a6d 611 goto destroy_iommu;
a8c21a54
T		 612 }
613 if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
614 ret = -EINVAL;
615 dev_err(gpu->dev,
616 "command buffer outside valid memory window\n");
617 goto free_buffer;
618 }
619
620 /* Setup event management */
621 spin_lock_init(&gpu->event_spinlock);
622 init_completion(&gpu->event_free);
623 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
624 gpu->event[i].used = false;
625 complete(&gpu->event_free);
626 }
627
628 /* Now program the hardware */
629 mutex_lock(&gpu->lock);
630 etnaviv_gpu_hw_init(gpu);
631 mutex_unlock(&gpu->lock);
632
633 pm_runtime_mark_last_busy(gpu->dev);
634 pm_runtime_put_autosuspend(gpu->dev);
635
636 return 0;
637
638free_buffer:
639 etnaviv_gpu_cmdbuf_free(gpu->buffer);
640 gpu->buffer = NULL;
45d16a6d
LS		 641destroy_iommu:
642 etnaviv_iommu_destroy(gpu->mmu);
643 gpu->mmu = NULL;
a8c21a54
T		 644fail:
645 pm_runtime_mark_last_busy(gpu->dev);
646 pm_runtime_put_autosuspend(gpu->dev);
647
648 return ret;
649}
650
651#ifdef CONFIG_DEBUG_FS
652struct dma_debug {
653 u32 address[2];
654 u32 state[2];
655};
656
657static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
658{
659 u32 i;
660
661 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
662 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
663
664 for (i = 0; i < 500; i++) {
665 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
666 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
667
668 if (debug->address[0] != debug->address[1])
669 break;
670
671 if (debug->state[0] != debug->state[1])
672 break;
673 }
674}
675
676int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
677{
678 struct dma_debug debug;
679 u32 dma_lo, dma_hi, axi, idle;
680 int ret;
681
682 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
683
684 ret = pm_runtime_get_sync(gpu->dev);
685 if (ret < 0)
686 return ret;
687
688 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
689 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
690 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
691 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
692
693 verify_dma(gpu, &debug);
694
695 seq_puts(m, "\tfeatures\n");
696 seq_printf(m, "\t minor_features0: 0x%08x\n",
697 gpu->identity.minor_features0);
698 seq_printf(m, "\t minor_features1: 0x%08x\n",
699 gpu->identity.minor_features1);
700 seq_printf(m, "\t minor_features2: 0x%08x\n",
701 gpu->identity.minor_features2);
702 seq_printf(m, "\t minor_features3: 0x%08x\n",
703 gpu->identity.minor_features3);
602eb489
RK		 704 seq_printf(m, "\t minor_features4: 0x%08x\n",
705 gpu->identity.minor_features4);
706 seq_printf(m, "\t minor_features5: 0x%08x\n",
707 gpu->identity.minor_features5);
a8c21a54
T		 708
709 seq_puts(m, "\tspecs\n");
710 seq_printf(m, "\t stream_count: %d\n",
711 gpu->identity.stream_count);
712 seq_printf(m, "\t register_max: %d\n",
713 gpu->identity.register_max);
714 seq_printf(m, "\t thread_count: %d\n",
715 gpu->identity.thread_count);
716 seq_printf(m, "\t vertex_cache_size: %d\n",
717 gpu->identity.vertex_cache_size);
718 seq_printf(m, "\t shader_core_count: %d\n",
719 gpu->identity.shader_core_count);
720 seq_printf(m, "\t pixel_pipes: %d\n",
721 gpu->identity.pixel_pipes);
722 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
723 gpu->identity.vertex_output_buffer_size);
724 seq_printf(m, "\t buffer_size: %d\n",
725 gpu->identity.buffer_size);
726 seq_printf(m, "\t instruction_count: %d\n",
727 gpu->identity.instruction_count);
728 seq_printf(m, "\t num_constants: %d\n",
729 gpu->identity.num_constants);
602eb489
RK		 730 seq_printf(m, "\t varyings_count: %d\n",
731 gpu->identity.varyings_count);
a8c21a54
T		 732
733 seq_printf(m, "\taxi: 0x%08x\n", axi);
734 seq_printf(m, "\tidle: 0x%08x\n", idle);
735 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
736 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
737 seq_puts(m, "\t FE is not idle\n");
738 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
739 seq_puts(m, "\t DE is not idle\n");
740 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
741 seq_puts(m, "\t PE is not idle\n");
742 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
743 seq_puts(m, "\t SH is not idle\n");
744 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
745 seq_puts(m, "\t PA is not idle\n");
746 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
747 seq_puts(m, "\t SE is not idle\n");
748 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
749 seq_puts(m, "\t RA is not idle\n");
750 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
751 seq_puts(m, "\t TX is not idle\n");
752 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
753 seq_puts(m, "\t VG is not idle\n");
754 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
755 seq_puts(m, "\t IM is not idle\n");
756 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
757 seq_puts(m, "\t FP is not idle\n");
758 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
759 seq_puts(m, "\t TS is not idle\n");
760 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
761 seq_puts(m, "\t AXI low power mode\n");
762
763 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
764 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
765 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
766 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
767
768 seq_puts(m, "\tMC\n");
769 seq_printf(m, "\t read0: 0x%08x\n", read0);
770 seq_printf(m, "\t read1: 0x%08x\n", read1);
771 seq_printf(m, "\t write: 0x%08x\n", write);
772 }
773
774 seq_puts(m, "\tDMA ");
775
776 if (debug.address[0] == debug.address[1] &&
777 debug.state[0] == debug.state[1]) {
778 seq_puts(m, "seems to be stuck\n");
779 } else if (debug.address[0] == debug.address[1]) {
780 seq_puts(m, "adress is constant\n");
781 } else {
782 seq_puts(m, "is runing\n");
783 }
784
785 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
786 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
787 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
788 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
789 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
790 dma_lo, dma_hi);
791
792 ret = 0;
793
794 pm_runtime_mark_last_busy(gpu->dev);
795 pm_runtime_put_autosuspend(gpu->dev);
796
797 return ret;
798}
799#endif
800
801/*
802 * Power Management:
803 */
804static int enable_clk(struct etnaviv_gpu *gpu)
805{
806 if (gpu->clk_core)
807 clk_prepare_enable(gpu->clk_core);
808 if (gpu->clk_shader)
809 clk_prepare_enable(gpu->clk_shader);
810
811 return 0;
812}
813
814static int disable_clk(struct etnaviv_gpu *gpu)
815{
816 if (gpu->clk_core)
817 clk_disable_unprepare(gpu->clk_core);
818 if (gpu->clk_shader)
819 clk_disable_unprepare(gpu->clk_shader);
820
821 return 0;
822}
823
824static int enable_axi(struct etnaviv_gpu *gpu)
825{
826 if (gpu->clk_bus)
827 clk_prepare_enable(gpu->clk_bus);
828
829 return 0;
830}
831
832static int disable_axi(struct etnaviv_gpu *gpu)
833{
834 if (gpu->clk_bus)
835 clk_disable_unprepare(gpu->clk_bus);
836
837 return 0;
838}
839
840/*
841 * Hangcheck detection for locked gpu:
842 */
843static void recover_worker(struct work_struct *work)
844{
845 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
846 recover_work);
847 unsigned long flags;
848 unsigned int i;
849
850 dev_err(gpu->dev, "hangcheck recover!\n");
851
852 if (pm_runtime_get_sync(gpu->dev) < 0)
853 return;
854
855 mutex_lock(&gpu->lock);
856
857 /* Only catch the first event, or when manually re-armed */
858 if (etnaviv_dump_core) {
859 etnaviv_core_dump(gpu);
860 etnaviv_dump_core = false;
861 }
862
863 etnaviv_hw_reset(gpu);
864
865 /* complete all events, the GPU won't do it after the reset */
866 spin_lock_irqsave(&gpu->event_spinlock, flags);
867 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
868 if (!gpu->event[i].used)
869 continue;
870 fence_signal(gpu->event[i].fence);
871 gpu->event[i].fence = NULL;
872 gpu->event[i].used = false;
873 complete(&gpu->event_free);
874 /*
875 * Decrement the PM count for each stuck event. This is safe
876 * even in atomic context as we use ASYNC RPM here.
877 */
878 pm_runtime_put_autosuspend(gpu->dev);
879 }
880 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
881 gpu->completed_fence = gpu->active_fence;
882
883 etnaviv_gpu_hw_init(gpu);
884 gpu->switch_context = true;
885
886 mutex_unlock(&gpu->lock);
887 pm_runtime_mark_last_busy(gpu->dev);
888 pm_runtime_put_autosuspend(gpu->dev);
889
890 /* Retire the buffer objects in a work */
891 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
892}
893
894static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
895{
896 DBG("%s", dev_name(gpu->dev));
897 mod_timer(&gpu->hangcheck_timer,
898 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
899}
900
901static void hangcheck_handler(unsigned long data)
902{
903 struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
904 u32 fence = gpu->completed_fence;
905 bool progress = false;
906
907 if (fence != gpu->hangcheck_fence) {
908 gpu->hangcheck_fence = fence;
909 progress = true;
910 }
911
912 if (!progress) {
913 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
914 int change = dma_addr - gpu->hangcheck_dma_addr;
915
916 if (change < 0 || change > 16) {
917 gpu->hangcheck_dma_addr = dma_addr;
918 progress = true;
919 }
920 }
921
922 if (!progress && fence_after(gpu->active_fence, fence)) {
923 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
924 dev_err(gpu->dev, " completed fence: %u\n", fence);
925 dev_err(gpu->dev, " active fence: %u\n",
926 gpu->active_fence);
927 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
928 }
929
930 /* if still more pending work, reset the hangcheck timer: */
931 if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
932 hangcheck_timer_reset(gpu);
933}
934
935static void hangcheck_disable(struct etnaviv_gpu *gpu)
936{
937 del_timer_sync(&gpu->hangcheck_timer);
938 cancel_work_sync(&gpu->recover_work);
939}
940
941/* fence object management */
942struct etnaviv_fence {
943 struct etnaviv_gpu *gpu;
944 struct fence base;
945};
946
947static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence)
948{
949 return container_of(fence, struct etnaviv_fence, base);
950}
951
952static const char *etnaviv_fence_get_driver_name(struct fence *fence)
953{
954 return "etnaviv";
955}
956
957static const char *etnaviv_fence_get_timeline_name(struct fence *fence)
958{
959 struct etnaviv_fence *f = to_etnaviv_fence(fence);
960
961 return dev_name(f->gpu->dev);
962}
963
964static bool etnaviv_fence_enable_signaling(struct fence *fence)
965{
966 return true;
967}
968
969static bool etnaviv_fence_signaled(struct fence *fence)
970{
971 struct etnaviv_fence *f = to_etnaviv_fence(fence);
972
973 return fence_completed(f->gpu, f->base.seqno);
974}
975
976static void etnaviv_fence_release(struct fence *fence)
977{
978 struct etnaviv_fence *f = to_etnaviv_fence(fence);
979
980 kfree_rcu(f, base.rcu);
981}
982
983static const struct fence_ops etnaviv_fence_ops = {
984 .get_driver_name = etnaviv_fence_get_driver_name,
985 .get_timeline_name = etnaviv_fence_get_timeline_name,
986 .enable_signaling = etnaviv_fence_enable_signaling,
987 .signaled = etnaviv_fence_signaled,
988 .wait = fence_default_wait,
989 .release = etnaviv_fence_release,
990};
991
992static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
993{
994 struct etnaviv_fence *f;
995
996 f = kzalloc(sizeof(*f), GFP_KERNEL);
997 if (!f)
998 return NULL;
999
1000 f->gpu = gpu;
1001
1002 fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1003 gpu->fence_context, ++gpu->next_fence);
1004
1005 return &f->base;
1006}
1007
1008int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1009 unsigned int context, bool exclusive)
1010{
1011 struct reservation_object *robj = etnaviv_obj->resv;
1012 struct reservation_object_list *fobj;
1013 struct fence *fence;
1014 int i, ret;
1015
1016 if (!exclusive) {
1017 ret = reservation_object_reserve_shared(robj);
1018 if (ret)
1019 return ret;
1020 }
1021
1022 /*
1023 * If we have any shared fences, then the exclusive fence
1024 * should be ignored as it will already have been signalled.
1025 */
1026 fobj = reservation_object_get_list(robj);
1027 if (!fobj || fobj->shared_count == 0) {
1028 /* Wait on any existing exclusive fence which isn't our own */
1029 fence = reservation_object_get_excl(robj);
1030 if (fence && fence->context != context) {
1031 ret = fence_wait(fence, true);
1032 if (ret)
1033 return ret;
1034 }
1035 }
1036
1037 if (!exclusive || !fobj)
1038 return 0;
1039
1040 for (i = 0; i < fobj->shared_count; i++) {
1041 fence = rcu_dereference_protected(fobj->shared[i],
1042 reservation_object_held(robj));
1043 if (fence->context != context) {
1044 ret = fence_wait(fence, true);
1045 if (ret)
1046 return ret;
1047 }
1048 }
1049
1050 return 0;
1051}
1052
1053/*
1054 * event management:
1055 */
1056
1057static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1058{
1059 unsigned long ret, flags;
1060 unsigned int i, event = ~0U;
1061
1062 ret = wait_for_completion_timeout(&gpu->event_free,
1063 msecs_to_jiffies(10 * 10000));
1064 if (!ret)
1065 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1066
1067 spin_lock_irqsave(&gpu->event_spinlock, flags);
1068
1069 /* find first free event */
1070 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1071 if (gpu->event[i].used == false) {
1072 gpu->event[i].used = true;
1073 event = i;
1074 break;
1075 }
1076 }
1077
1078 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1079
1080 return event;
1081}
1082
1083static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1084{
1085 unsigned long flags;
1086
1087 spin_lock_irqsave(&gpu->event_spinlock, flags);
1088
1089 if (gpu->event[event].used == false) {
1090 dev_warn(gpu->dev, "event %u is already marked as free",
1091 event);
1092 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1093 } else {
1094 gpu->event[event].used = false;
1095 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1096
1097 complete(&gpu->event_free);
1098 }
1099}
1100
1101/*
1102 * Cmdstream submission/retirement:
1103 */
1104
1105struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1106 size_t nr_bos)
1107{
1108 struct etnaviv_cmdbuf *cmdbuf;
1109 size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo[0]),
1110 sizeof(*cmdbuf));
1111
1112 cmdbuf = kzalloc(sz, GFP_KERNEL);
1113 if (!cmdbuf)
1114 return NULL;
1115
f6e45661
LR		 1116 cmdbuf->vaddr = dma_alloc_wc(gpu->dev, size, &cmdbuf->paddr,
1117 GFP_KERNEL);
a8c21a54
T		 1118 if (!cmdbuf->vaddr) {
1119 kfree(cmdbuf);
1120 return NULL;
1121 }
1122
1123 cmdbuf->gpu = gpu;
1124 cmdbuf->size = size;
1125
1126 return cmdbuf;
1127}
1128
1129void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1130{
f6e45661
LR		 1131 dma_free_wc(cmdbuf->gpu->dev, cmdbuf->size, cmdbuf->vaddr,
1132 cmdbuf->paddr);
a8c21a54
T		 1133 kfree(cmdbuf);
1134}
1135
1136static void retire_worker(struct work_struct *work)
1137{
1138 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1139 retire_work);
1140 u32 fence = gpu->completed_fence;
1141 struct etnaviv_cmdbuf *cmdbuf, *tmp;
1142 unsigned int i;
1143
1144 mutex_lock(&gpu->lock);
1145 list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1146 if (!fence_is_signaled(cmdbuf->fence))
1147 break;
1148
1149 list_del(&cmdbuf->node);
1150 fence_put(cmdbuf->fence);
1151
1152 for (i = 0; i < cmdbuf->nr_bos; i++) {
1153 struct etnaviv_gem_object *etnaviv_obj = cmdbuf->bo[i];
1154
1155 atomic_dec(&etnaviv_obj->gpu_active);
1156 /* drop the refcount taken in etnaviv_gpu_submit */
1157 etnaviv_gem_put_iova(gpu, &etnaviv_obj->base);
1158 }
1159
1160 etnaviv_gpu_cmdbuf_free(cmdbuf);
1161 }
1162
1163 gpu->retired_fence = fence;
1164
1165 mutex_unlock(&gpu->lock);
1166
1167 wake_up_all(&gpu->fence_event);
1168}
1169
1170int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1171 u32 fence, struct timespec *timeout)
1172{
1173 int ret;
1174
1175 if (fence_after(fence, gpu->next_fence)) {
1176 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1177 fence, gpu->next_fence);
1178 return -EINVAL;
1179 }
1180
1181 if (!timeout) {
1182 /* No timeout was requested: just test for completion */
1183 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1184 } else {
1185 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1186
1187 ret = wait_event_interruptible_timeout(gpu->fence_event,
1188 fence_completed(gpu, fence),
1189 remaining);
1190 if (ret == 0) {
1191 DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1192 fence, gpu->retired_fence,
1193 gpu->completed_fence);
1194 ret = -ETIMEDOUT;
1195 } else if (ret != -ERESTARTSYS) {
1196 ret = 0;
1197 }
1198 }
1199
1200 return ret;
1201}
1202
1203/*
1204 * Wait for an object to become inactive. This, on it's own, is not race
1205 * free: the object is moved by the retire worker off the active list, and
1206 * then the iova is put. Moreover, the object could be re-submitted just
1207 * after we notice that it's become inactive.
1208 *
1209 * Although the retirement happens under the gpu lock, we don't want to hold
1210 * that lock in this function while waiting.
1211 */
1212int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1213 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1214{
1215 unsigned long remaining;
1216 long ret;
1217
1218 if (!timeout)
1219 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1220
1221 remaining = etnaviv_timeout_to_jiffies(timeout);
1222
1223 ret = wait_event_interruptible_timeout(gpu->fence_event,
1224 !is_active(etnaviv_obj),
1225 remaining);
1226 if (ret > 0) {
1227 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1228
1229 /* Synchronise with the retire worker */
1230 flush_workqueue(priv->wq);
1231 return 0;
1232 } else if (ret == -ERESTARTSYS) {
1233 return -ERESTARTSYS;
1234 } else {
1235 return -ETIMEDOUT;
1236 }
1237}
1238
1239int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1240{
1241 return pm_runtime_get_sync(gpu->dev);
1242}
1243
1244void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1245{
1246 pm_runtime_mark_last_busy(gpu->dev);
1247 pm_runtime_put_autosuspend(gpu->dev);
1248}
1249
1250/* add bo's to gpu's ring, and kick gpu: */
1251int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1252 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1253{
1254 struct fence *fence;
1255 unsigned int event, i;
1256 int ret;
1257
1258 ret = etnaviv_gpu_pm_get_sync(gpu);
1259 if (ret < 0)
1260 return ret;
1261
1262 mutex_lock(&gpu->lock);
1263
1264 /*
1265 * TODO
1266 *
1267 * - flush
1268 * - data endian
1269 * - prefetch
1270 *
1271 */
1272
1273 event = event_alloc(gpu);
1274 if (unlikely(event == ~0U)) {
1275 DRM_ERROR("no free event\n");
1276 ret = -EBUSY;
1277 goto out_unlock;
1278 }
1279
1280 fence = etnaviv_gpu_fence_alloc(gpu);
1281 if (!fence) {
1282 event_free(gpu, event);
1283 ret = -ENOMEM;
1284 goto out_unlock;
1285 }
1286
1287 gpu->event[event].fence = fence;
1288 submit->fence = fence->seqno;
1289 gpu->active_fence = submit->fence;
1290
1291 if (gpu->lastctx != cmdbuf->ctx) {
1292 gpu->mmu->need_flush = true;
1293 gpu->switch_context = true;
1294 gpu->lastctx = cmdbuf->ctx;
1295 }
1296
1297 etnaviv_buffer_queue(gpu, event, cmdbuf);
1298
1299 cmdbuf->fence = fence;
1300 list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1301
1302 /* We're committed to adding this command buffer, hold a PM reference */
1303 pm_runtime_get_noresume(gpu->dev);
1304
1305 for (i = 0; i < submit->nr_bos; i++) {
1306 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1307 u32 iova;
1308
1309 /* Each cmdbuf takes a refcount on the iova */
1310 etnaviv_gem_get_iova(gpu, &etnaviv_obj->base, &iova);
1311 cmdbuf->bo[i] = etnaviv_obj;
1312 atomic_inc(&etnaviv_obj->gpu_active);
1313
1314 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1315 reservation_object_add_excl_fence(etnaviv_obj->resv,
1316 fence);
1317 else
1318 reservation_object_add_shared_fence(etnaviv_obj->resv,
1319 fence);
1320 }
1321 cmdbuf->nr_bos = submit->nr_bos;
1322 hangcheck_timer_reset(gpu);
1323 ret = 0;
1324
1325out_unlock:
1326 mutex_unlock(&gpu->lock);
1327
1328 etnaviv_gpu_pm_put(gpu);
1329
1330 return ret;
1331}
1332
1333/*
1334 * Init/Cleanup:
1335 */
1336static irqreturn_t irq_handler(int irq, void *data)
1337{
1338 struct etnaviv_gpu *gpu = data;
1339 irqreturn_t ret = IRQ_NONE;
1340
1341 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1342
1343 if (intr != 0) {
1344 int event;
1345
1346 pm_runtime_mark_last_busy(gpu->dev);
1347
1348 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1349
1350 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1351 dev_err(gpu->dev, "AXI bus error\n");
1352 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1353 }
1354
1355 while ((event = ffs(intr)) != 0) {
1356 struct fence *fence;
1357
1358 event -= 1;
1359
1360 intr &= ~(1 << event);
1361
1362 dev_dbg(gpu->dev, "event %u\n", event);
1363
1364 fence = gpu->event[event].fence;
1365 gpu->event[event].fence = NULL;
1366 fence_signal(fence);
1367
1368 /*
1369 * Events can be processed out of order. Eg,
1370 * - allocate and queue event 0
1371 * - allocate event 1
1372 * - event 0 completes, we process it
1373 * - allocate and queue event 0
1374 * - event 1 and event 0 complete
1375 * we can end up processing event 0 first, then 1.
1376 */
1377 if (fence_after(fence->seqno, gpu->completed_fence))
1378 gpu->completed_fence = fence->seqno;
1379
1380 event_free(gpu, event);
1381
1382 /*
1383 * We need to balance the runtime PM count caused by
1384 * each submission. Upon submission, we increment
1385 * the runtime PM counter, and allocate one event.
1386 * So here, we put the runtime PM count for each
1387 * completed event.
1388 */
1389 pm_runtime_put_autosuspend(gpu->dev);
1390 }
1391
1392 /* Retire the buffer objects in a work */
1393 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1394
1395 ret = IRQ_HANDLED;
1396 }
1397
1398 return ret;
1399}
1400
1401static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1402{
1403 int ret;
1404
1405 ret = enable_clk(gpu);
1406 if (ret)
1407 return ret;
1408
1409 ret = enable_axi(gpu);
1410 if (ret) {
1411 disable_clk(gpu);
1412 return ret;
1413 }
1414
1415 return 0;
1416}
1417
1418static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1419{
1420 int ret;
1421
1422 ret = disable_axi(gpu);
1423 if (ret)
1424 return ret;
1425
1426 ret = disable_clk(gpu);
1427 if (ret)
1428 return ret;
1429
1430 return 0;
1431}
1432
1433static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1434{
1435 if (gpu->buffer) {
1436 unsigned long timeout;
1437
1438 /* Replace the last WAIT with END */
1439 etnaviv_buffer_end(gpu);
1440
1441 /*
1442 * We know that only the FE is busy here, this should
1443 * happen quickly (as the WAIT is only 200 cycles). If
1444 * we fail, just warn and continue.
1445 */
1446 timeout = jiffies + msecs_to_jiffies(100);
1447 do {
1448 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1449
1450 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1451 break;
1452
1453 if (time_is_before_jiffies(timeout)) {
1454 dev_warn(gpu->dev,
1455 "timed out waiting for idle: idle=0x%x\n",
1456 idle);
1457 break;
1458 }
1459
1460 udelay(5);
1461 } while (1);
1462 }
1463
1464 return etnaviv_gpu_clk_disable(gpu);
1465}
1466
1467#ifdef CONFIG_PM
1468static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1469{
1470 u32 clock;
1471 int ret;
1472
1473 ret = mutex_lock_killable(&gpu->lock);
1474 if (ret)
1475 return ret;
1476
1477 clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1478 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1479
1480 etnaviv_gpu_load_clock(gpu, clock);
1481 etnaviv_gpu_hw_init(gpu);
1482
1483 gpu->switch_context = true;
1484
1485 mutex_unlock(&gpu->lock);
1486
1487 return 0;
1488}
1489#endif
1490
1491static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1492 void *data)
1493{
1494 struct drm_device *drm = data;
1495 struct etnaviv_drm_private *priv = drm->dev_private;
1496 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1497 int ret;
1498
1499#ifdef CONFIG_PM
1500 ret = pm_runtime_get_sync(gpu->dev);
1501#else
1502 ret = etnaviv_gpu_clk_enable(gpu);
1503#endif
1504 if (ret < 0)
1505 return ret;
1506
1507 gpu->drm = drm;
1508 gpu->fence_context = fence_context_alloc(1);
1509 spin_lock_init(&gpu->fence_spinlock);
1510
1511 INIT_LIST_HEAD(&gpu->active_cmd_list);
1512 INIT_WORK(&gpu->retire_work, retire_worker);
1513 INIT_WORK(&gpu->recover_work, recover_worker);
1514 init_waitqueue_head(&gpu->fence_event);
1515
1516 setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
1517 (unsigned long)gpu);
1518
1519 priv->gpu[priv->num_gpus++] = gpu;
1520
1521 pm_runtime_mark_last_busy(gpu->dev);
1522 pm_runtime_put_autosuspend(gpu->dev);
1523
1524 return 0;
1525}
1526
1527static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1528 void *data)
1529{
1530 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1531
1532 DBG("%s", dev_name(gpu->dev));
1533
1534 hangcheck_disable(gpu);
1535
1536#ifdef CONFIG_PM
1537 pm_runtime_get_sync(gpu->dev);
1538 pm_runtime_put_sync_suspend(gpu->dev);
1539#else
1540 etnaviv_gpu_hw_suspend(gpu);
1541#endif
1542
1543 if (gpu->buffer) {
1544 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1545 gpu->buffer = NULL;
1546 }
1547
1548 if (gpu->mmu) {
1549 etnaviv_iommu_destroy(gpu->mmu);
1550 gpu->mmu = NULL;
1551 }
1552
1553 gpu->drm = NULL;
1554}
1555
1556static const struct component_ops gpu_ops = {
1557 .bind = etnaviv_gpu_bind,
1558 .unbind = etnaviv_gpu_unbind,
1559};
1560
1561static const struct of_device_id etnaviv_gpu_match[] = {
1562 {
1563 .compatible = "vivante,gc"
1564 },
1565 { /* sentinel */ }
1566};
1567
1568static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1569{
1570 struct device *dev = &pdev->dev;
1571 struct etnaviv_gpu *gpu;
1572 int err = 0;
1573
1574 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1575 if (!gpu)
1576 return -ENOMEM;
1577
1578 gpu->dev = &pdev->dev;
1579 mutex_init(&gpu->lock);
1580
1581 /*
1582 * Set the GPU base address to the start of physical memory. This
1583 * ensures that if we have up to 2GB, the v1 MMU can address the
1584 * highest memory. This is important as command buffers may be
1585 * allocated outside of this limit.
1586 */
1587 gpu->memory_base = PHYS_OFFSET;
1588
1589 /* Map registers: */
1590 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1591 if (IS_ERR(gpu->mmio))
1592 return PTR_ERR(gpu->mmio);
1593
1594 /* Get Interrupt: */
1595 gpu->irq = platform_get_irq(pdev, 0);
1596 if (gpu->irq < 0) {
1597 err = gpu->irq;
1598 dev_err(dev, "failed to get irq: %d\n", err);
1599 goto fail;
1600 }
1601
1602 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1603 dev_name(gpu->dev), gpu);
1604 if (err) {
1605 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1606 goto fail;
1607 }
1608
1609 /* Get Clocks: */
1610 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1611 DBG("clk_bus: %p", gpu->clk_bus);
1612 if (IS_ERR(gpu->clk_bus))
1613 gpu->clk_bus = NULL;
1614
1615 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1616 DBG("clk_core: %p", gpu->clk_core);
1617 if (IS_ERR(gpu->clk_core))
1618 gpu->clk_core = NULL;
1619
1620 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1621 DBG("clk_shader: %p", gpu->clk_shader);
1622 if (IS_ERR(gpu->clk_shader))
1623 gpu->clk_shader = NULL;
1624
1625 /* TODO: figure out max mapped size */
1626 dev_set_drvdata(dev, gpu);
1627
1628 /*
1629 * We treat the device as initially suspended. The runtime PM
1630 * autosuspend delay is rather arbitary: no measurements have
1631 * yet been performed to determine an appropriate value.
1632 */
1633 pm_runtime_use_autosuspend(gpu->dev);
1634 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1635 pm_runtime_enable(gpu->dev);
1636
1637 err = component_add(&pdev->dev, &gpu_ops);
1638 if (err < 0) {
1639 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1640 goto fail;
1641 }
1642
1643 return 0;
1644
1645fail:
1646 return err;
1647}
1648
1649static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1650{
1651 component_del(&pdev->dev, &gpu_ops);
1652 pm_runtime_disable(&pdev->dev);
1653 return 0;
1654}
1655
1656#ifdef CONFIG_PM
1657static int etnaviv_gpu_rpm_suspend(struct device *dev)
1658{
1659 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1660 u32 idle, mask;
1661
1662 /* If we have outstanding fences, we're not idle */
1663 if (gpu->completed_fence != gpu->active_fence)
1664 return -EBUSY;
1665
1666 /* Check whether the hardware (except FE) is idle */
1667 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1668 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1669 if (idle != mask)
1670 return -EBUSY;
1671
1672 return etnaviv_gpu_hw_suspend(gpu);
1673}
1674
1675static int etnaviv_gpu_rpm_resume(struct device *dev)
1676{
1677 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1678 int ret;
1679
1680 ret = etnaviv_gpu_clk_enable(gpu);
1681 if (ret)
1682 return ret;
1683
1684 /* Re-initialise the basic hardware state */
1685 if (gpu->drm && gpu->buffer) {
1686 ret = etnaviv_gpu_hw_resume(gpu);
1687 if (ret) {
1688 etnaviv_gpu_clk_disable(gpu);
1689 return ret;
1690 }
1691 }
1692
1693 return 0;
1694}
1695#endif
1696
1697static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1698 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1699 NULL)
1700};
1701
1702struct platform_driver etnaviv_gpu_driver = {
1703 .driver = {
1704 .name = "etnaviv-gpu",
1705 .owner = THIS_MODULE,
1706 .pm = &etnaviv_gpu_pm_ops,
1707 .of_match_table = etnaviv_gpu_match,
1708 },
1709 .probe = etnaviv_gpu_platform_probe,
1710 .remove = etnaviv_gpu_platform_remove,
1711 .id_table = gpu_ids,
1712};
Linux kernel - Deliverables
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