[deliverable/linux.git] / drivers / gpu / drm / fsl-dcu / fsl_dcu_drm_crtc.c

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * Freescale DCU drm device driver
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/regmap.h>

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>

#include "fsl_dcu_drm_crtc.h"
#include "fsl_dcu_drm_drv.h"
#include "fsl_dcu_drm_plane.h"

static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc,
					  struct drm_crtc_state *old_crtc_state)
{
}

static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc,
					 struct drm_crtc_state *state)
{
	return 0;
}

static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
					  struct drm_crtc_state *old_crtc_state)
{
}

static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;

	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
			   DCU_MODE_DCU_MODE_MASK,
			   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
		     DCU_UPDATE_MODE_READREG);
}

static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;

	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
			   DCU_MODE_DCU_MODE_MASK,
			   DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
		     DCU_UPDATE_MODE_READREG);
}

static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc,
					const struct drm_display_mode *mode,
					struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
	struct drm_display_mode *mode = &crtc->state->mode;
	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index, pol = 0;
	unsigned long dcuclk;

	index = drm_crtc_index(crtc);
	dcuclk = clk_get_rate(fsl_dev->clk);
	div = dcuclk / mode->clock / 1000;

	/* Configure timings: */
	hbp = mode->htotal - mode->hsync_end;
	hfp = mode->hsync_start - mode->hdisplay;
	hsw = mode->hsync_end - mode->hsync_start;
	vbp = mode->vtotal - mode->vsync_end;
	vfp = mode->vsync_start - mode->vdisplay;
	vsw = mode->vsync_end - mode->vsync_start;

	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		pol |= DCU_SYN_POL_INV_HS_LOW;

	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		pol |= DCU_SYN_POL_INV_VS_LOW;

	regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
		     DCU_HSYN_PARA_BP(hbp) |
		     DCU_HSYN_PARA_PW(hsw) |
		     DCU_HSYN_PARA_FP(hfp));
	regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
		     DCU_VSYN_PARA_BP(vbp) |
		     DCU_VSYN_PARA_PW(vsw) |
		     DCU_VSYN_PARA_FP(vfp));
	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
		     DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
		     DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
	regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
	regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
		     DCU_BGND_G(0) | DCU_BGND_B(0));
	regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
		     DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
	regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
		     DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
		     DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
		     DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
		     DCU_UPDATE_MODE_READREG);
	return;
}

static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
	.atomic_begin = fsl_dcu_drm_crtc_atomic_begin,
	.atomic_check = fsl_dcu_drm_crtc_atomic_check,
	.atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
	.disable = fsl_dcu_drm_disable_crtc,
	.enable = fsl_dcu_drm_crtc_enable,
	.mode_fixup = fsl_dcu_drm_crtc_mode_fixup,
	.mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
};

static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	.destroy = drm_crtc_cleanup,
	.page_flip = drm_atomic_helper_page_flip,
	.reset = drm_atomic_helper_crtc_reset,
	.set_config = drm_atomic_helper_set_config,
};

int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
{
	struct drm_plane *primary;
	struct drm_crtc *crtc = &fsl_dev->crtc;
	unsigned int i, j, reg_num;
	int ret;

	primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
	if (!primary)
		return -ENOMEM;

	ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
					&fsl_dcu_drm_crtc_funcs, NULL);
	if (ret) {
		primary->funcs->destroy(primary);
		return ret;
	}

	drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);

	if (!strcmp(fsl_dev->soc->name, "ls1021a"))
		reg_num = LS1021A_LAYER_REG_NUM;
	else
		reg_num = VF610_LAYER_REG_NUM;
	for (i = 0; i < fsl_dev->soc->total_layer; i++) {
		for (j = 1; j <= reg_num; j++)
			regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
	}
	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
			   DCU_MODE_DCU_MODE_MASK,
			   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
		     DCU_UPDATE_MODE_READREG);

	return 0;
}
Commit	Line	Data
109eee2f JW	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* Freescale DCU drm device driver
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/regmap.h>
	14
	15	#include <drm/drmP.h>
	16	#include <drm/drm_atomic.h>
	17	#include <drm/drm_atomic_helper.h>
	18	#include <drm/drm_crtc.h>
	19	#include <drm/drm_crtc_helper.h>
	20
	21	#include "fsl_dcu_drm_crtc.h"
	22	#include "fsl_dcu_drm_drv.h"
	23	#include "fsl_dcu_drm_plane.h"
	24
	25	static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc,
	26	struct drm_crtc_state *old_crtc_state)
	27	{
	28	}
	29
	30	static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc,
	31	struct drm_crtc_state *state)
	32	{
	33	return 0;
	34	}
	35
	36	static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
	37	struct drm_crtc_state *old_crtc_state)
	38	{
	39	}
	40
	41	static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
	42	{
	43	struct drm_device *dev = crtc->dev;
	44	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
109eee2f	45
e291d298 SA	46	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
	47	DCU_MODE_DCU_MODE_MASK,
	48	DCU_MODE_DCU_MODE(DCU_MODE_OFF));
	49	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
	50	DCU_UPDATE_MODE_READREG);
109eee2f JW	51	}
	52
	53	static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
	54	{
	55	struct drm_device *dev = crtc->dev;
	56	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
109eee2f	57
e291d298 SA	58	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
	59	DCU_MODE_DCU_MODE_MASK,
	60	DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
	61	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
	62	DCU_UPDATE_MODE_READREG);
109eee2f JW	63	}
	64
	65	static bool fsl_dcu_drm_crtc_mode_fixup(struct drm_crtc *crtc,
	66	const struct drm_display_mode *mode,
	67	struct drm_display_mode *adjusted_mode)
	68	{
	69	return true;
	70	}
	71
	72	static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
	73	{
	74	struct drm_device *dev = crtc->dev;
	75	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
	76	struct drm_display_mode *mode = &crtc->state->mode;
4bc390c6	77	unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index, pol = 0;
109eee2f	78	unsigned long dcuclk;
109eee2f JW	79
	80	index = drm_crtc_index(crtc);
	81	dcuclk = clk_get_rate(fsl_dev->clk);
	82	div = dcuclk / mode->clock / 1000;
	83
	84	/* Configure timings: */
	85	hbp = mode->htotal - mode->hsync_end;
	86	hfp = mode->hsync_start - mode->hdisplay;
	87	hsw = mode->hsync_end - mode->hsync_start;
	88	vbp = mode->vtotal - mode->vsync_end;
	89	vfp = mode->vsync_start - mode->vdisplay;
	90	vsw = mode->vsync_end - mode->vsync_start;
	91
4bc390c6 SA	92	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
	93	pol \|= DCU_SYN_POL_INV_HS_LOW;
	94
	95	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
	96	pol \|= DCU_SYN_POL_INV_VS_LOW;
	97
e291d298 SA	98	regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
	99	DCU_HSYN_PARA_BP(hbp) \|
	100	DCU_HSYN_PARA_PW(hsw) \|
	101	DCU_HSYN_PARA_FP(hfp));
	102	regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
	103	DCU_VSYN_PARA_BP(vbp) \|
	104	DCU_VSYN_PARA_PW(vsw) \|
	105	DCU_VSYN_PARA_FP(vfp));
	106	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
	107	DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) \|
	108	DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
	109	regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
4bc390c6	110	regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
e291d298 SA	111	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) \|
	112	DCU_BGND_G(0) \| DCU_BGND_B(0));
	113	regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
	114	DCU_MODE_BLEND_ITER(1) \| DCU_MODE_RASTER_EN);
	115	regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
	116	DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) \|
	117	DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) \|
	118	DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
	119	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
	120	DCU_UPDATE_MODE_READREG);
109eee2f	121	return;
109eee2f JW	122	}
	123
	124	static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
	125	.atomic_begin = fsl_dcu_drm_crtc_atomic_begin,
	126	.atomic_check = fsl_dcu_drm_crtc_atomic_check,
	127	.atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
	128	.disable = fsl_dcu_drm_disable_crtc,
	129	.enable = fsl_dcu_drm_crtc_enable,
	130	.mode_fixup = fsl_dcu_drm_crtc_mode_fixup,
	131	.mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
	132	};
	133
	134	static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
	135	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
	136	.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
	137	.destroy = drm_crtc_cleanup,
	138	.page_flip = drm_atomic_helper_page_flip,
	139	.reset = drm_atomic_helper_crtc_reset,
	140	.set_config = drm_atomic_helper_set_config,
	141	};
	142
	143	int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
	144	{
	145	struct drm_plane *primary;
	146	struct drm_crtc *crtc = &fsl_dev->crtc;
	147	unsigned int i, j, reg_num;
	148	int ret;
	149
	150	primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
72cc05a5 SA	151	if (!primary)
	152	return -ENOMEM;
	153
109eee2f	154	ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
f9882876	155	&fsl_dcu_drm_crtc_funcs, NULL);
72cc05a5 SA	156	if (ret) {
72cc05a5 SA	157	primary->funcs->destroy(primary);
109eee2f	158	return ret;
72cc05a5	159	}
109eee2f JW	160
	161	drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
	162
	163	if (!strcmp(fsl_dev->soc->name, "ls1021a"))
	164	reg_num = LS1021A_LAYER_REG_NUM;
	165	else
	166	reg_num = VF610_LAYER_REG_NUM;
f76b9873 SA	167	for (i = 0; i < fsl_dev->soc->total_layer; i++) {
f76b9873 SA	168	for (j = 1; j <= reg_num; j++)
e291d298	169	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
109eee2f	170	}
e291d298 SA	171	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
	172	DCU_MODE_DCU_MODE_MASK,
	173	DCU_MODE_DCU_MODE(DCU_MODE_OFF));
	174	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
	175	DCU_UPDATE_MODE_READREG);
109eee2f JW	176
109eee2f JW	177	return 0;
109eee2f	178	}