drm/fsl-dcu: add TCON driver
[deliverable/linux.git] / drivers / gpu / drm / fsl-dcu / fsl_dcu_drm_drv.c
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1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * Freescale DCU drm device driver
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <linux/io.h>
15#include <linux/mfd/syscon.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20#include <linux/pm.h>
21#include <linux/pm_runtime.h>
22#include <linux/regmap.h>
23
24#include <drm/drmP.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_gem_cma_helper.h>
27
28#include "fsl_dcu_drm_crtc.h"
29#include "fsl_dcu_drm_drv.h"
fb127b79 30#include "fsl_tcon.h"
109eee2f 31
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32static bool fsl_dcu_drm_is_volatile_reg(struct device *dev, unsigned int reg)
33{
34 if (reg == DCU_INT_STATUS || reg == DCU_UPDATE_MODE)
35 return true;
36
37 return false;
38}
39
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40static const struct regmap_config fsl_dcu_regmap_config = {
41 .reg_bits = 32,
42 .reg_stride = 4,
43 .val_bits = 32,
44 .cache_type = REGCACHE_RBTREE,
efb8b491
SA
45
46 .volatile_reg = fsl_dcu_drm_is_volatile_reg,
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47};
48
49static int fsl_dcu_drm_irq_init(struct drm_device *dev)
50{
51 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
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52 int ret;
53
54 ret = drm_irq_install(dev, fsl_dev->irq);
55 if (ret < 0)
56 dev_err(dev->dev, "failed to install IRQ handler\n");
57
e291d298 58 regmap_write(fsl_dev->regmap, DCU_INT_STATUS, 0);
638c93f6 59 regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
e291d298
SA
60 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
61 DCU_UPDATE_MODE_READREG);
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62
63 return ret;
64}
65
66static int fsl_dcu_load(struct drm_device *drm, unsigned long flags)
67{
68 struct device *dev = drm->dev;
69 struct fsl_dcu_drm_device *fsl_dev = drm->dev_private;
70 int ret;
71
72 ret = fsl_dcu_drm_modeset_init(fsl_dev);
73 if (ret < 0) {
74 dev_err(dev, "failed to initialize mode setting\n");
75 return ret;
76 }
77
78 ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
79 if (ret < 0) {
80 dev_err(dev, "failed to initialize vblank\n");
81 goto done;
82 }
83 drm->vblank_disable_allowed = true;
84
85 ret = fsl_dcu_drm_irq_init(drm);
86 if (ret < 0)
87 goto done;
88 drm->irq_enabled = true;
89
90 fsl_dcu_fbdev_init(drm);
91
92 return 0;
93done:
94 if (ret) {
95 drm_mode_config_cleanup(drm);
96 drm_vblank_cleanup(drm);
97 drm_irq_uninstall(drm);
98 drm->dev_private = NULL;
99 }
100
101 return ret;
102}
103
104static int fsl_dcu_unload(struct drm_device *dev)
105{
106 drm_mode_config_cleanup(dev);
107 drm_vblank_cleanup(dev);
108 drm_irq_uninstall(dev);
109
110 dev->dev_private = NULL;
111
112 return 0;
113}
114
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115static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg)
116{
117 struct drm_device *dev = arg;
118 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
119 unsigned int int_status;
120 int ret;
121
122 ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
e291d298
SA
123 if (ret) {
124 dev_err(dev->dev, "read DCU_INT_STATUS failed\n");
125 return IRQ_NONE;
126 }
127
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128 if (int_status & DCU_INT_STATUS_VBLANK)
129 drm_handle_vblank(dev, 0);
130
e291d298
SA
131 regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
132 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
133 DCU_UPDATE_MODE_READREG);
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134
135 return IRQ_HANDLED;
136}
137
88e72717 138static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, unsigned int pipe)
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139{
140 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
141 unsigned int value;
109eee2f 142
e291d298 143 regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
109eee2f 144 value &= ~DCU_INT_MASK_VBLANK;
e291d298
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145 regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
146
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147 return 0;
148}
149
88e72717
TR
150static void fsl_dcu_drm_disable_vblank(struct drm_device *dev,
151 unsigned int pipe)
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152{
153 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
154 unsigned int value;
109eee2f 155
e291d298 156 regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
109eee2f 157 value |= DCU_INT_MASK_VBLANK;
e291d298 158 regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
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159}
160
161static const struct file_operations fsl_dcu_drm_fops = {
162 .owner = THIS_MODULE,
163 .open = drm_open,
164 .release = drm_release,
165 .unlocked_ioctl = drm_ioctl,
166#ifdef CONFIG_COMPAT
167 .compat_ioctl = drm_compat_ioctl,
168#endif
169 .poll = drm_poll,
170 .read = drm_read,
171 .llseek = no_llseek,
172 .mmap = drm_gem_cma_mmap,
173};
174
175static struct drm_driver fsl_dcu_drm_driver = {
176 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET
177 | DRIVER_PRIME | DRIVER_ATOMIC,
178 .load = fsl_dcu_load,
179 .unload = fsl_dcu_unload,
109eee2f 180 .irq_handler = fsl_dcu_drm_irq,
b44f8408 181 .get_vblank_counter = drm_vblank_no_hw_counter,
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182 .enable_vblank = fsl_dcu_drm_enable_vblank,
183 .disable_vblank = fsl_dcu_drm_disable_vblank,
184 .gem_free_object = drm_gem_cma_free_object,
185 .gem_vm_ops = &drm_gem_cma_vm_ops,
186 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
187 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
188 .gem_prime_import = drm_gem_prime_import,
189 .gem_prime_export = drm_gem_prime_export,
190 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
191 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
192 .gem_prime_vmap = drm_gem_cma_prime_vmap,
193 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
194 .gem_prime_mmap = drm_gem_cma_prime_mmap,
195 .dumb_create = drm_gem_cma_dumb_create,
196 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
197 .dumb_destroy = drm_gem_dumb_destroy,
198 .fops = &fsl_dcu_drm_fops,
199 .name = "fsl-dcu-drm",
200 .desc = "Freescale DCU DRM",
201 .date = "20150213",
202 .major = 1,
203 .minor = 0,
204};
205
206#ifdef CONFIG_PM_SLEEP
207static int fsl_dcu_drm_pm_suspend(struct device *dev)
208{
209 struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
210
211 if (!fsl_dev)
212 return 0;
213
214 drm_kms_helper_poll_disable(fsl_dev->drm);
215 regcache_cache_only(fsl_dev->regmap, true);
216 regcache_mark_dirty(fsl_dev->regmap);
217 clk_disable(fsl_dev->clk);
218 clk_unprepare(fsl_dev->clk);
219
220 return 0;
221}
222
223static int fsl_dcu_drm_pm_resume(struct device *dev)
224{
225 struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
226 int ret;
227
228 if (!fsl_dev)
229 return 0;
230
231 ret = clk_enable(fsl_dev->clk);
232 if (ret < 0) {
233 dev_err(dev, "failed to enable dcu clk\n");
234 clk_unprepare(fsl_dev->clk);
235 return ret;
236 }
237 ret = clk_prepare(fsl_dev->clk);
238 if (ret < 0) {
239 dev_err(dev, "failed to prepare dcu clk\n");
240 return ret;
241 }
242
243 drm_kms_helper_poll_enable(fsl_dev->drm);
244 regcache_cache_only(fsl_dev->regmap, false);
245 regcache_sync(fsl_dev->regmap);
246
247 return 0;
248}
249#endif
250
251static const struct dev_pm_ops fsl_dcu_drm_pm_ops = {
252 SET_SYSTEM_SLEEP_PM_OPS(fsl_dcu_drm_pm_suspend, fsl_dcu_drm_pm_resume)
253};
254
255static const struct fsl_dcu_soc_data fsl_dcu_ls1021a_data = {
256 .name = "ls1021a",
257 .total_layer = 16,
258 .max_layer = 4,
259};
260
261static const struct fsl_dcu_soc_data fsl_dcu_vf610_data = {
262 .name = "vf610",
263 .total_layer = 64,
264 .max_layer = 6,
265};
266
267static const struct of_device_id fsl_dcu_of_match[] = {
268 {
269 .compatible = "fsl,ls1021a-dcu",
270 .data = &fsl_dcu_ls1021a_data,
271 }, {
272 .compatible = "fsl,vf610-dcu",
273 .data = &fsl_dcu_vf610_data,
274 }, {
275 },
276};
277MODULE_DEVICE_TABLE(of, fsl_dcu_of_match);
278
279static int fsl_dcu_drm_probe(struct platform_device *pdev)
280{
281 struct fsl_dcu_drm_device *fsl_dev;
282 struct drm_device *drm;
283 struct device *dev = &pdev->dev;
284 struct resource *res;
285 void __iomem *base;
286 struct drm_driver *driver = &fsl_dcu_drm_driver;
2d701449
SA
287 struct clk *pix_clk_in;
288 char pix_clk_name[32];
289 const char *pix_clk_in_name;
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290 const struct of_device_id *id;
291 int ret;
292
293 fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
294 if (!fsl_dev)
295 return -ENOMEM;
296
73fa3033
SA
297 id = of_match_node(fsl_dcu_of_match, pdev->dev.of_node);
298 if (!id)
299 return -ENODEV;
300 fsl_dev->soc = id->data;
301
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302 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
303 if (!res) {
304 dev_err(dev, "could not get memory IO resource\n");
305 return -ENODEV;
306 }
307
308 base = devm_ioremap_resource(dev, res);
309 if (IS_ERR(base)) {
310 ret = PTR_ERR(base);
311 return ret;
312 }
313
314 fsl_dev->irq = platform_get_irq(pdev, 0);
315 if (fsl_dev->irq < 0) {
316 dev_err(dev, "failed to get irq\n");
317 return -ENXIO;
318 }
319
73fa3033
SA
320 fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
321 &fsl_dcu_regmap_config);
322 if (IS_ERR(fsl_dev->regmap)) {
323 dev_err(dev, "regmap init failed\n");
324 return PTR_ERR(fsl_dev->regmap);
325 }
326
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327 fsl_dev->clk = devm_clk_get(dev, "dcu");
328 if (IS_ERR(fsl_dev->clk)) {
109eee2f 329 dev_err(dev, "failed to get dcu clock\n");
73fa3033 330 return PTR_ERR(fsl_dev->clk);
109eee2f 331 }
73fa3033 332 ret = clk_prepare_enable(fsl_dev->clk);
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333 if (ret < 0) {
334 dev_err(dev, "failed to enable dcu clk\n");
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335 return ret;
336 }
337
2d701449
SA
338 pix_clk_in = devm_clk_get(dev, "pix");
339 if (IS_ERR(pix_clk_in)) {
340 /* legancy binding, use dcu clock as pixel clock input */
341 pix_clk_in = fsl_dev->clk;
342 }
343
344 pix_clk_in_name = __clk_get_name(pix_clk_in);
345 snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
346 fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
347 pix_clk_in_name, 0, base + DCU_DIV_RATIO,
348 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
f93500f4 349 if (IS_ERR(fsl_dev->pix_clk)) {
2d701449
SA
350 dev_err(dev, "failed to register pix clk\n");
351 ret = PTR_ERR(fsl_dev->pix_clk);
352 goto disable_clk;
f93500f4 353 }
2d701449 354
f93500f4
SA
355 ret = clk_prepare_enable(fsl_dev->pix_clk);
356 if (ret < 0) {
357 dev_err(dev, "failed to enable pix clk\n");
2d701449 358 goto unregister_pix_clk;
f93500f4
SA
359 }
360
fb127b79
SA
361 fsl_dev->tcon = fsl_tcon_init(dev);
362
109eee2f 363 drm = drm_dev_alloc(driver, dev);
73fa3033
SA
364 if (!drm) {
365 ret = -ENOMEM;
f93500f4 366 goto disable_pix_clk;
73fa3033 367 }
109eee2f
JW
368
369 fsl_dev->dev = dev;
370 fsl_dev->drm = drm;
371 fsl_dev->np = dev->of_node;
372 drm->dev_private = fsl_dev;
373 dev_set_drvdata(dev, fsl_dev);
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374
375 ret = drm_dev_register(drm, 0);
376 if (ret < 0)
377 goto unref;
378
379 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name,
380 driver->major, driver->minor, driver->patchlevel,
381 driver->date, drm->primary->index);
382
383 return 0;
384
385unref:
386 drm_dev_unref(drm);
f93500f4
SA
387disable_pix_clk:
388 clk_disable_unprepare(fsl_dev->pix_clk);
2d701449
SA
389unregister_pix_clk:
390 clk_unregister(fsl_dev->pix_clk);
73fa3033
SA
391disable_clk:
392 clk_disable_unprepare(fsl_dev->clk);
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JW
393 return ret;
394}
395
396static int fsl_dcu_drm_remove(struct platform_device *pdev)
397{
398 struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
399
73fa3033 400 clk_disable_unprepare(fsl_dev->clk);
f93500f4 401 clk_disable_unprepare(fsl_dev->pix_clk);
2d701449 402 clk_unregister(fsl_dev->pix_clk);
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JW
403 drm_put_dev(fsl_dev->drm);
404
405 return 0;
406}
407
408static struct platform_driver fsl_dcu_drm_platform_driver = {
409 .probe = fsl_dcu_drm_probe,
410 .remove = fsl_dcu_drm_remove,
411 .driver = {
412 .name = "fsl-dcu",
413 .pm = &fsl_dcu_drm_pm_ops,
414 .of_match_table = fsl_dcu_of_match,
415 },
416};
417
418module_platform_driver(fsl_dcu_drm_platform_driver);
419
420MODULE_DESCRIPTION("Freescale DCU DRM Driver");
421MODULE_LICENSE("GPL");
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