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e7792ce2 RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
c707c361 | 18 | #include <linux/component.h> |
893c3e53 | 19 | #include <linux/hdmi.h> |
e7792ce2 | 20 | #include <linux/module.h> |
12473b7d | 21 | #include <linux/irq.h> |
f0b33b28 | 22 | #include <sound/asoundef.h> |
7e567624 | 23 | #include <sound/hdmi-codec.h> |
e7792ce2 RC |
24 | |
25 | #include <drm/drmP.h> | |
9736e988 | 26 | #include <drm/drm_atomic_helper.h> |
e7792ce2 | 27 | #include <drm/drm_crtc_helper.h> |
e7792ce2 | 28 | #include <drm/drm_edid.h> |
5dbcf319 | 29 | #include <drm/drm_of.h> |
c4c11dd1 | 30 | #include <drm/i2c/tda998x.h> |
e7792ce2 RC |
31 | |
32 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) | |
33 | ||
7e567624 JS |
34 | struct tda998x_audio_port { |
35 | u8 format; /* AFMT_xxx */ | |
36 | u8 config; /* AP value */ | |
37 | }; | |
38 | ||
e7792ce2 RC |
39 | struct tda998x_priv { |
40 | struct i2c_client *cec; | |
2f7f730a | 41 | struct i2c_client *hdmi; |
ed9a8426 | 42 | struct mutex mutex; |
e66e03ab RK |
43 | u16 rev; |
44 | u8 current_page; | |
e7792ce2 | 45 | int dpms; |
c4c11dd1 | 46 | bool is_hdmi_sink; |
5e74c22c RK |
47 | u8 vip_cntrl_0; |
48 | u8 vip_cntrl_1; | |
49 | u8 vip_cntrl_2; | |
95db3b25 | 50 | struct tda998x_audio_params audio_params; |
12473b7d | 51 | |
7e567624 JS |
52 | struct platform_device *audio_pdev; |
53 | struct mutex audio_mutex; | |
54 | ||
12473b7d JFM |
55 | wait_queue_head_t wq_edid; |
56 | volatile int wq_edid_wait; | |
0fc6f44d RK |
57 | |
58 | struct work_struct detect_work; | |
59 | struct timer_list edid_delay_timer; | |
60 | wait_queue_head_t edid_delay_waitq; | |
61 | bool edid_delay_active; | |
78e401f9 RK |
62 | |
63 | struct drm_encoder encoder; | |
eed64b59 | 64 | struct drm_connector connector; |
7e567624 JS |
65 | |
66 | struct tda998x_audio_port audio_port[2]; | |
e7792ce2 RC |
67 | }; |
68 | ||
9525c4dd RK |
69 | #define conn_to_tda998x_priv(x) \ |
70 | container_of(x, struct tda998x_priv, connector) | |
71 | ||
72 | #define enc_to_tda998x_priv(x) \ | |
73 | container_of(x, struct tda998x_priv, encoder) | |
74 | ||
e7792ce2 RC |
75 | /* The TDA9988 series of devices use a paged register scheme.. to simplify |
76 | * things we encode the page # in upper bits of the register #. To read/ | |
77 | * write a given register, we need to make sure CURPAGE register is set | |
78 | * appropriately. Which implies reads/writes are not atomic. Fun! | |
79 | */ | |
80 | ||
81 | #define REG(page, addr) (((page) << 8) | (addr)) | |
82 | #define REG2ADDR(reg) ((reg) & 0xff) | |
83 | #define REG2PAGE(reg) (((reg) >> 8) & 0xff) | |
84 | ||
85 | #define REG_CURPAGE 0xff /* write */ | |
86 | ||
87 | ||
88 | /* Page 00h: General Control */ | |
89 | #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ | |
90 | #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ | |
91 | # define MAIN_CNTRL0_SR (1 << 0) | |
92 | # define MAIN_CNTRL0_DECS (1 << 1) | |
93 | # define MAIN_CNTRL0_DEHS (1 << 2) | |
94 | # define MAIN_CNTRL0_CECS (1 << 3) | |
95 | # define MAIN_CNTRL0_CEHS (1 << 4) | |
96 | # define MAIN_CNTRL0_SCALER (1 << 7) | |
97 | #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ | |
98 | #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ | |
99 | # define SOFTRESET_AUDIO (1 << 0) | |
100 | # define SOFTRESET_I2C_MASTER (1 << 1) | |
101 | #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ | |
102 | #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ | |
103 | #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ | |
104 | # define I2C_MASTER_DIS_MM (1 << 0) | |
105 | # define I2C_MASTER_DIS_FILT (1 << 1) | |
106 | # define I2C_MASTER_APP_STRT_LAT (1 << 2) | |
c4c11dd1 RK |
107 | #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ |
108 | # define FEAT_POWERDOWN_SPDIF (1 << 3) | |
e7792ce2 RC |
109 | #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ |
110 | #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ | |
111 | #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ | |
112 | # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) | |
c4c11dd1 | 113 | #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ |
e7792ce2 RC |
114 | #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ |
115 | #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ | |
116 | #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ | |
117 | #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ | |
118 | #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ | |
119 | # define VIP_CNTRL_0_MIRR_A (1 << 7) | |
120 | # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) | |
121 | # define VIP_CNTRL_0_MIRR_B (1 << 3) | |
122 | # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) | |
123 | #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ | |
124 | # define VIP_CNTRL_1_MIRR_C (1 << 7) | |
125 | # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) | |
126 | # define VIP_CNTRL_1_MIRR_D (1 << 3) | |
127 | # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) | |
128 | #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ | |
129 | # define VIP_CNTRL_2_MIRR_E (1 << 7) | |
130 | # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) | |
131 | # define VIP_CNTRL_2_MIRR_F (1 << 3) | |
132 | # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) | |
133 | #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ | |
134 | # define VIP_CNTRL_3_X_TGL (1 << 0) | |
135 | # define VIP_CNTRL_3_H_TGL (1 << 1) | |
136 | # define VIP_CNTRL_3_V_TGL (1 << 2) | |
137 | # define VIP_CNTRL_3_EMB (1 << 3) | |
138 | # define VIP_CNTRL_3_SYNC_DE (1 << 4) | |
139 | # define VIP_CNTRL_3_SYNC_HS (1 << 5) | |
140 | # define VIP_CNTRL_3_DE_INT (1 << 6) | |
141 | # define VIP_CNTRL_3_EDGE (1 << 7) | |
142 | #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ | |
143 | # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) | |
144 | # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) | |
145 | # define VIP_CNTRL_4_CCIR656 (1 << 4) | |
146 | # define VIP_CNTRL_4_656_ALT (1 << 5) | |
147 | # define VIP_CNTRL_4_TST_656 (1 << 6) | |
148 | # define VIP_CNTRL_4_TST_PAT (1 << 7) | |
149 | #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ | |
150 | # define VIP_CNTRL_5_CKCASE (1 << 0) | |
151 | # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) | |
c4c11dd1 | 152 | #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ |
10df1a95 JFM |
153 | # define MUX_AP_SELECT_I2S 0x64 |
154 | # define MUX_AP_SELECT_SPDIF 0x40 | |
bcb2481d | 155 | #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ |
e7792ce2 RC |
156 | #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ |
157 | # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) | |
158 | # define MAT_CONTRL_MAT_BP (1 << 2) | |
159 | #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ | |
160 | #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ | |
161 | #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ | |
162 | #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ | |
163 | #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ | |
164 | #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ | |
165 | #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ | |
166 | #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ | |
167 | #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ | |
168 | #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ | |
169 | #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ | |
170 | #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ | |
171 | #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ | |
172 | #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ | |
173 | #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ | |
174 | #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ | |
175 | #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ | |
088d61d1 SH |
176 | #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ |
177 | #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ | |
e7792ce2 RC |
178 | #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ |
179 | #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ | |
088d61d1 SH |
180 | #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ |
181 | #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ | |
e7792ce2 RC |
182 | #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ |
183 | #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ | |
184 | #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ | |
185 | #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ | |
186 | #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ | |
187 | #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ | |
188 | #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ | |
189 | #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ | |
190 | #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ | |
191 | #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ | |
088d61d1 SH |
192 | #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ |
193 | #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ | |
194 | #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ | |
195 | #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ | |
e7792ce2 RC |
196 | #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ |
197 | #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ | |
198 | #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ | |
199 | #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ | |
200 | #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ | |
088d61d1 SH |
201 | # define TBG_CNTRL_0_TOP_TGL (1 << 0) |
202 | # define TBG_CNTRL_0_TOP_SEL (1 << 1) | |
203 | # define TBG_CNTRL_0_DE_EXT (1 << 2) | |
204 | # define TBG_CNTRL_0_TOP_EXT (1 << 3) | |
e7792ce2 RC |
205 | # define TBG_CNTRL_0_FRAME_DIS (1 << 5) |
206 | # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) | |
207 | # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) | |
208 | #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ | |
088d61d1 SH |
209 | # define TBG_CNTRL_1_H_TGL (1 << 0) |
210 | # define TBG_CNTRL_1_V_TGL (1 << 1) | |
211 | # define TBG_CNTRL_1_TGL_EN (1 << 2) | |
212 | # define TBG_CNTRL_1_X_EXT (1 << 3) | |
213 | # define TBG_CNTRL_1_H_EXT (1 << 4) | |
214 | # define TBG_CNTRL_1_V_EXT (1 << 5) | |
e7792ce2 RC |
215 | # define TBG_CNTRL_1_DWIN_DIS (1 << 6) |
216 | #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ | |
217 | #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ | |
218 | # define HVF_CNTRL_0_SM (1 << 7) | |
219 | # define HVF_CNTRL_0_RWB (1 << 6) | |
220 | # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) | |
221 | # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) | |
222 | #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ | |
223 | # define HVF_CNTRL_1_FOR (1 << 0) | |
224 | # define HVF_CNTRL_1_YUVBLK (1 << 1) | |
225 | # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) | |
226 | # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) | |
227 | # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) | |
228 | #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ | |
c4c11dd1 RK |
229 | #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ |
230 | # define I2S_FORMAT(x) (((x) & 3) << 0) | |
231 | #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ | |
10df1a95 JFM |
232 | # define AIP_CLKSEL_AIP_SPDIF (0 << 3) |
233 | # define AIP_CLKSEL_AIP_I2S (1 << 3) | |
234 | # define AIP_CLKSEL_FS_ACLK (0 << 0) | |
235 | # define AIP_CLKSEL_FS_MCLK (1 << 0) | |
236 | # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) | |
e7792ce2 RC |
237 | |
238 | /* Page 02h: PLL settings */ | |
239 | #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ | |
240 | # define PLL_SERIAL_1_SRL_FDN (1 << 0) | |
241 | # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) | |
242 | # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) | |
243 | #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ | |
3ae471f7 | 244 | # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) |
e7792ce2 RC |
245 | # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) |
246 | #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ | |
247 | # define PLL_SERIAL_3_SRL_CCIR (1 << 0) | |
248 | # define PLL_SERIAL_3_SRL_DE (1 << 2) | |
249 | # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) | |
250 | #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ | |
251 | #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ | |
252 | #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ | |
253 | #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ | |
254 | #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ | |
255 | #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ | |
256 | #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ | |
257 | #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ | |
258 | #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ | |
c4c11dd1 RK |
259 | # define AUDIO_DIV_SERCLK_1 0 |
260 | # define AUDIO_DIV_SERCLK_2 1 | |
261 | # define AUDIO_DIV_SERCLK_4 2 | |
262 | # define AUDIO_DIV_SERCLK_8 3 | |
263 | # define AUDIO_DIV_SERCLK_16 4 | |
264 | # define AUDIO_DIV_SERCLK_32 5 | |
e7792ce2 RC |
265 | #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ |
266 | # define SEL_CLK_SEL_CLK1 (1 << 0) | |
267 | # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) | |
268 | # define SEL_CLK_ENA_SC_CLK (1 << 3) | |
269 | #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ | |
270 | ||
271 | ||
272 | /* Page 09h: EDID Control */ | |
273 | #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ | |
274 | /* next 127 successive registers are the EDID block */ | |
275 | #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ | |
276 | #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ | |
277 | #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ | |
278 | #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ | |
279 | #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ | |
280 | ||
281 | ||
282 | /* Page 10h: information frames and packets */ | |
c4c11dd1 RK |
283 | #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ |
284 | #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ | |
285 | #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ | |
286 | #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ | |
287 | #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ | |
e7792ce2 RC |
288 | |
289 | ||
290 | /* Page 11h: audio settings and content info packets */ | |
291 | #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ | |
292 | # define AIP_CNTRL_0_RST_FIFO (1 << 0) | |
293 | # define AIP_CNTRL_0_SWAP (1 << 1) | |
294 | # define AIP_CNTRL_0_LAYOUT (1 << 2) | |
295 | # define AIP_CNTRL_0_ACR_MAN (1 << 5) | |
296 | # define AIP_CNTRL_0_RST_CTS (1 << 6) | |
c4c11dd1 RK |
297 | #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ |
298 | # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) | |
299 | # define CA_I2S_HBR_CHSTAT (1 << 6) | |
300 | #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ | |
301 | #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ | |
302 | #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ | |
303 | #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ | |
304 | #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ | |
305 | #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ | |
306 | #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ | |
307 | #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ | |
308 | # define CTS_N_K(x) (((x) & 7) << 0) | |
309 | # define CTS_N_M(x) (((x) & 3) << 4) | |
e7792ce2 RC |
310 | #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ |
311 | # define ENC_CNTRL_RST_ENC (1 << 0) | |
312 | # define ENC_CNTRL_RST_SEL (1 << 1) | |
313 | # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) | |
c4c11dd1 RK |
314 | #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ |
315 | # define DIP_FLAGS_ACR (1 << 0) | |
316 | # define DIP_FLAGS_GC (1 << 1) | |
317 | #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ | |
318 | # define DIP_IF_FLAGS_IF1 (1 << 1) | |
319 | # define DIP_IF_FLAGS_IF2 (1 << 2) | |
320 | # define DIP_IF_FLAGS_IF3 (1 << 3) | |
321 | # define DIP_IF_FLAGS_IF4 (1 << 4) | |
322 | # define DIP_IF_FLAGS_IF5 (1 << 5) | |
323 | #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ | |
e7792ce2 RC |
324 | |
325 | ||
326 | /* Page 12h: HDCP and OTP */ | |
327 | #define REG_TX3 REG(0x12, 0x9a) /* read/write */ | |
063b472f RK |
328 | #define REG_TX4 REG(0x12, 0x9b) /* read/write */ |
329 | # define TX4_PD_RAM (1 << 1) | |
e7792ce2 RC |
330 | #define REG_TX33 REG(0x12, 0xb8) /* read/write */ |
331 | # define TX33_HDMI (1 << 1) | |
332 | ||
333 | ||
334 | /* Page 13h: Gamut related metadata packets */ | |
335 | ||
336 | ||
337 | ||
338 | /* CEC registers: (not paged) | |
339 | */ | |
12473b7d JFM |
340 | #define REG_CEC_INTSTATUS 0xee /* read */ |
341 | # define CEC_INTSTATUS_CEC (1 << 0) | |
342 | # define CEC_INTSTATUS_HDMI (1 << 1) | |
e7792ce2 RC |
343 | #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ |
344 | # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) | |
345 | # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) | |
346 | # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) | |
347 | # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) | |
12473b7d JFM |
348 | #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ |
349 | #define REG_CEC_RXSHPDINT 0xfd /* read */ | |
ec5d3e83 RK |
350 | # define CEC_RXSHPDINT_RXSENS BIT(0) |
351 | # define CEC_RXSHPDINT_HPD BIT(1) | |
e7792ce2 RC |
352 | #define REG_CEC_RXSHPDLEV 0xfe /* read */ |
353 | # define CEC_RXSHPDLEV_RXSENS (1 << 0) | |
354 | # define CEC_RXSHPDLEV_HPD (1 << 1) | |
355 | ||
356 | #define REG_CEC_ENAMODS 0xff /* read/write */ | |
357 | # define CEC_ENAMODS_DIS_FRO (1 << 6) | |
358 | # define CEC_ENAMODS_DIS_CCLK (1 << 5) | |
359 | # define CEC_ENAMODS_EN_RXSENS (1 << 2) | |
360 | # define CEC_ENAMODS_EN_HDMI (1 << 1) | |
361 | # define CEC_ENAMODS_EN_CEC (1 << 0) | |
362 | ||
363 | ||
364 | /* Device versions: */ | |
365 | #define TDA9989N2 0x0101 | |
366 | #define TDA19989 0x0201 | |
367 | #define TDA19989N2 0x0202 | |
368 | #define TDA19988 0x0301 | |
369 | ||
370 | static void | |
e66e03ab | 371 | cec_write(struct tda998x_priv *priv, u16 addr, u8 val) |
e7792ce2 | 372 | { |
2f7f730a | 373 | struct i2c_client *client = priv->cec; |
e66e03ab | 374 | u8 buf[] = {addr, val}; |
e7792ce2 RC |
375 | int ret; |
376 | ||
704d63f5 | 377 | ret = i2c_master_send(client, buf, sizeof(buf)); |
e7792ce2 RC |
378 | if (ret < 0) |
379 | dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); | |
380 | } | |
381 | ||
e66e03ab RK |
382 | static u8 |
383 | cec_read(struct tda998x_priv *priv, u8 addr) | |
e7792ce2 | 384 | { |
2f7f730a | 385 | struct i2c_client *client = priv->cec; |
e66e03ab | 386 | u8 val; |
e7792ce2 RC |
387 | int ret; |
388 | ||
389 | ret = i2c_master_send(client, &addr, sizeof(addr)); | |
390 | if (ret < 0) | |
391 | goto fail; | |
392 | ||
393 | ret = i2c_master_recv(client, &val, sizeof(val)); | |
394 | if (ret < 0) | |
395 | goto fail; | |
396 | ||
397 | return val; | |
398 | ||
399 | fail: | |
400 | dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); | |
401 | return 0; | |
402 | } | |
403 | ||
7d2eadc9 | 404 | static int |
e66e03ab | 405 | set_page(struct tda998x_priv *priv, u16 reg) |
e7792ce2 | 406 | { |
e7792ce2 | 407 | if (REG2PAGE(reg) != priv->current_page) { |
2f7f730a | 408 | struct i2c_client *client = priv->hdmi; |
e66e03ab | 409 | u8 buf[] = { |
e7792ce2 RC |
410 | REG_CURPAGE, REG2PAGE(reg) |
411 | }; | |
412 | int ret = i2c_master_send(client, buf, sizeof(buf)); | |
7d2eadc9 | 413 | if (ret < 0) { |
288ffc73 | 414 | dev_err(&client->dev, "%s %04x err %d\n", __func__, |
704d63f5 | 415 | reg, ret); |
7d2eadc9 JFM |
416 | return ret; |
417 | } | |
e7792ce2 RC |
418 | |
419 | priv->current_page = REG2PAGE(reg); | |
420 | } | |
7d2eadc9 | 421 | return 0; |
e7792ce2 RC |
422 | } |
423 | ||
424 | static int | |
e66e03ab | 425 | reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) |
e7792ce2 | 426 | { |
2f7f730a | 427 | struct i2c_client *client = priv->hdmi; |
e66e03ab | 428 | u8 addr = REG2ADDR(reg); |
e7792ce2 RC |
429 | int ret; |
430 | ||
ed9a8426 | 431 | mutex_lock(&priv->mutex); |
7d2eadc9 JFM |
432 | ret = set_page(priv, reg); |
433 | if (ret < 0) | |
ed9a8426 | 434 | goto out; |
e7792ce2 RC |
435 | |
436 | ret = i2c_master_send(client, &addr, sizeof(addr)); | |
437 | if (ret < 0) | |
438 | goto fail; | |
439 | ||
440 | ret = i2c_master_recv(client, buf, cnt); | |
441 | if (ret < 0) | |
442 | goto fail; | |
443 | ||
ed9a8426 | 444 | goto out; |
e7792ce2 RC |
445 | |
446 | fail: | |
447 | dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); | |
ed9a8426 JFM |
448 | out: |
449 | mutex_unlock(&priv->mutex); | |
e7792ce2 RC |
450 | return ret; |
451 | } | |
452 | ||
c4c11dd1 | 453 | static void |
e66e03ab | 454 | reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) |
c4c11dd1 | 455 | { |
2f7f730a | 456 | struct i2c_client *client = priv->hdmi; |
e66e03ab | 457 | u8 buf[cnt+1]; |
c4c11dd1 RK |
458 | int ret; |
459 | ||
460 | buf[0] = REG2ADDR(reg); | |
461 | memcpy(&buf[1], p, cnt); | |
462 | ||
ed9a8426 | 463 | mutex_lock(&priv->mutex); |
7d2eadc9 JFM |
464 | ret = set_page(priv, reg); |
465 | if (ret < 0) | |
ed9a8426 | 466 | goto out; |
c4c11dd1 RK |
467 | |
468 | ret = i2c_master_send(client, buf, cnt + 1); | |
469 | if (ret < 0) | |
470 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
ed9a8426 JFM |
471 | out: |
472 | mutex_unlock(&priv->mutex); | |
c4c11dd1 RK |
473 | } |
474 | ||
7d2eadc9 | 475 | static int |
e66e03ab | 476 | reg_read(struct tda998x_priv *priv, u16 reg) |
e7792ce2 | 477 | { |
e66e03ab | 478 | u8 val = 0; |
7d2eadc9 JFM |
479 | int ret; |
480 | ||
481 | ret = reg_read_range(priv, reg, &val, sizeof(val)); | |
482 | if (ret < 0) | |
483 | return ret; | |
e7792ce2 RC |
484 | return val; |
485 | } | |
486 | ||
487 | static void | |
e66e03ab | 488 | reg_write(struct tda998x_priv *priv, u16 reg, u8 val) |
e7792ce2 | 489 | { |
2f7f730a | 490 | struct i2c_client *client = priv->hdmi; |
e66e03ab | 491 | u8 buf[] = {REG2ADDR(reg), val}; |
e7792ce2 RC |
492 | int ret; |
493 | ||
ed9a8426 | 494 | mutex_lock(&priv->mutex); |
7d2eadc9 JFM |
495 | ret = set_page(priv, reg); |
496 | if (ret < 0) | |
ed9a8426 | 497 | goto out; |
e7792ce2 | 498 | |
704d63f5 | 499 | ret = i2c_master_send(client, buf, sizeof(buf)); |
e7792ce2 RC |
500 | if (ret < 0) |
501 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
ed9a8426 JFM |
502 | out: |
503 | mutex_unlock(&priv->mutex); | |
e7792ce2 RC |
504 | } |
505 | ||
506 | static void | |
e66e03ab | 507 | reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) |
e7792ce2 | 508 | { |
2f7f730a | 509 | struct i2c_client *client = priv->hdmi; |
e66e03ab | 510 | u8 buf[] = {REG2ADDR(reg), val >> 8, val}; |
e7792ce2 RC |
511 | int ret; |
512 | ||
ed9a8426 | 513 | mutex_lock(&priv->mutex); |
7d2eadc9 JFM |
514 | ret = set_page(priv, reg); |
515 | if (ret < 0) | |
ed9a8426 | 516 | goto out; |
e7792ce2 | 517 | |
704d63f5 | 518 | ret = i2c_master_send(client, buf, sizeof(buf)); |
e7792ce2 RC |
519 | if (ret < 0) |
520 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
ed9a8426 JFM |
521 | out: |
522 | mutex_unlock(&priv->mutex); | |
e7792ce2 RC |
523 | } |
524 | ||
525 | static void | |
e66e03ab | 526 | reg_set(struct tda998x_priv *priv, u16 reg, u8 val) |
e7792ce2 | 527 | { |
7d2eadc9 JFM |
528 | int old_val; |
529 | ||
530 | old_val = reg_read(priv, reg); | |
531 | if (old_val >= 0) | |
532 | reg_write(priv, reg, old_val | val); | |
e7792ce2 RC |
533 | } |
534 | ||
535 | static void | |
e66e03ab | 536 | reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) |
e7792ce2 | 537 | { |
7d2eadc9 JFM |
538 | int old_val; |
539 | ||
540 | old_val = reg_read(priv, reg); | |
541 | if (old_val >= 0) | |
542 | reg_write(priv, reg, old_val & ~val); | |
e7792ce2 RC |
543 | } |
544 | ||
545 | static void | |
2f7f730a | 546 | tda998x_reset(struct tda998x_priv *priv) |
e7792ce2 RC |
547 | { |
548 | /* reset audio and i2c master: */ | |
81b53a16 | 549 | reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); |
e7792ce2 | 550 | msleep(50); |
81b53a16 | 551 | reg_write(priv, REG_SOFTRESET, 0); |
e7792ce2 RC |
552 | msleep(50); |
553 | ||
554 | /* reset transmitter: */ | |
2f7f730a JFM |
555 | reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); |
556 | reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); | |
e7792ce2 RC |
557 | |
558 | /* PLL registers common configuration */ | |
2f7f730a JFM |
559 | reg_write(priv, REG_PLL_SERIAL_1, 0x00); |
560 | reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); | |
561 | reg_write(priv, REG_PLL_SERIAL_3, 0x00); | |
562 | reg_write(priv, REG_SERIALIZER, 0x00); | |
563 | reg_write(priv, REG_BUFFER_OUT, 0x00); | |
564 | reg_write(priv, REG_PLL_SCG1, 0x00); | |
565 | reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); | |
566 | reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); | |
567 | reg_write(priv, REG_PLL_SCGN1, 0xfa); | |
568 | reg_write(priv, REG_PLL_SCGN2, 0x00); | |
569 | reg_write(priv, REG_PLL_SCGR1, 0x5b); | |
570 | reg_write(priv, REG_PLL_SCGR2, 0x00); | |
571 | reg_write(priv, REG_PLL_SCG2, 0x10); | |
bcb2481d RK |
572 | |
573 | /* Write the default value MUX register */ | |
2f7f730a | 574 | reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); |
e7792ce2 RC |
575 | } |
576 | ||
0fc6f44d RK |
577 | /* |
578 | * The TDA998x has a problem when trying to read the EDID close to a | |
579 | * HPD assertion: it needs a delay of 100ms to avoid timing out while | |
580 | * trying to read EDID data. | |
581 | * | |
582 | * However, tda998x_encoder_get_modes() may be called at any moment | |
9525c4dd | 583 | * after tda998x_connector_detect() indicates that we are connected, so |
0fc6f44d RK |
584 | * we need to delay probing modes in tda998x_encoder_get_modes() after |
585 | * we have seen a HPD inactive->active transition. This code implements | |
586 | * that delay. | |
587 | */ | |
588 | static void tda998x_edid_delay_done(unsigned long data) | |
589 | { | |
590 | struct tda998x_priv *priv = (struct tda998x_priv *)data; | |
591 | ||
592 | priv->edid_delay_active = false; | |
593 | wake_up(&priv->edid_delay_waitq); | |
594 | schedule_work(&priv->detect_work); | |
595 | } | |
596 | ||
597 | static void tda998x_edid_delay_start(struct tda998x_priv *priv) | |
598 | { | |
599 | priv->edid_delay_active = true; | |
600 | mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); | |
601 | } | |
602 | ||
603 | static int tda998x_edid_delay_wait(struct tda998x_priv *priv) | |
604 | { | |
605 | return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); | |
606 | } | |
607 | ||
608 | /* | |
609 | * We need to run the KMS hotplug event helper outside of our threaded | |
610 | * interrupt routine as this can call back into our get_modes method, | |
611 | * which will want to make use of interrupts. | |
612 | */ | |
613 | static void tda998x_detect_work(struct work_struct *work) | |
6833d26e | 614 | { |
6833d26e | 615 | struct tda998x_priv *priv = |
0fc6f44d | 616 | container_of(work, struct tda998x_priv, detect_work); |
78e401f9 | 617 | struct drm_device *dev = priv->encoder.dev; |
6833d26e | 618 | |
0fc6f44d RK |
619 | if (dev) |
620 | drm_kms_helper_hotplug_event(dev); | |
6833d26e JFM |
621 | } |
622 | ||
12473b7d JFM |
623 | /* |
624 | * only 2 interrupts may occur: screen plug/unplug and EDID read | |
625 | */ | |
626 | static irqreturn_t tda998x_irq_thread(int irq, void *data) | |
627 | { | |
628 | struct tda998x_priv *priv = data; | |
629 | u8 sta, cec, lvl, flag0, flag1, flag2; | |
f84a97d4 | 630 | bool handled = false; |
12473b7d | 631 | |
12473b7d JFM |
632 | sta = cec_read(priv, REG_CEC_INTSTATUS); |
633 | cec = cec_read(priv, REG_CEC_RXSHPDINT); | |
634 | lvl = cec_read(priv, REG_CEC_RXSHPDLEV); | |
635 | flag0 = reg_read(priv, REG_INT_FLAGS_0); | |
636 | flag1 = reg_read(priv, REG_INT_FLAGS_1); | |
637 | flag2 = reg_read(priv, REG_INT_FLAGS_2); | |
638 | DRM_DEBUG_DRIVER( | |
639 | "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", | |
640 | sta, cec, lvl, flag0, flag1, flag2); | |
ec5d3e83 RK |
641 | |
642 | if (cec & CEC_RXSHPDINT_HPD) { | |
0fc6f44d RK |
643 | if (lvl & CEC_RXSHPDLEV_HPD) |
644 | tda998x_edid_delay_start(priv); | |
645 | else | |
646 | schedule_work(&priv->detect_work); | |
647 | ||
f84a97d4 | 648 | handled = true; |
12473b7d | 649 | } |
ec5d3e83 RK |
650 | |
651 | if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { | |
652 | priv->wq_edid_wait = 0; | |
653 | wake_up(&priv->wq_edid); | |
654 | handled = true; | |
655 | } | |
656 | ||
f84a97d4 | 657 | return IRQ_RETVAL(handled); |
12473b7d JFM |
658 | } |
659 | ||
c4c11dd1 | 660 | static void |
e66e03ab | 661 | tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr, |
96795df1 | 662 | union hdmi_infoframe *frame) |
c4c11dd1 | 663 | { |
96795df1 RK |
664 | u8 buf[32]; |
665 | ssize_t len; | |
666 | ||
667 | len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); | |
668 | if (len < 0) { | |
669 | dev_err(&priv->hdmi->dev, | |
670 | "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", | |
671 | frame->any.type, len); | |
672 | return; | |
673 | } | |
674 | ||
2f7f730a | 675 | reg_clear(priv, REG_DIP_IF_FLAGS, bit); |
96795df1 | 676 | reg_write_range(priv, addr, buf, len); |
2f7f730a | 677 | reg_set(priv, REG_DIP_IF_FLAGS, bit); |
c4c11dd1 RK |
678 | } |
679 | ||
95db3b25 JS |
680 | static int tda998x_write_aif(struct tda998x_priv *priv, |
681 | struct hdmi_audio_infoframe *cea) | |
c4c11dd1 | 682 | { |
96795df1 RK |
683 | union hdmi_infoframe frame; |
684 | ||
95db3b25 | 685 | frame.audio = *cea; |
4a6ca1a2 | 686 | |
96795df1 | 687 | tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); |
95db3b25 JS |
688 | |
689 | return 0; | |
c4c11dd1 RK |
690 | } |
691 | ||
692 | static void | |
2f7f730a | 693 | tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) |
c4c11dd1 | 694 | { |
96795df1 | 695 | union hdmi_infoframe frame; |
8c7a075d | 696 | |
96795df1 RK |
697 | drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode); |
698 | frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; | |
8c7a075d | 699 | |
96795df1 | 700 | tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); |
c4c11dd1 RK |
701 | } |
702 | ||
2f7f730a | 703 | static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) |
c4c11dd1 RK |
704 | { |
705 | if (on) { | |
2f7f730a JFM |
706 | reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); |
707 | reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); | |
708 | reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); | |
c4c11dd1 | 709 | } else { |
2f7f730a | 710 | reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
c4c11dd1 RK |
711 | } |
712 | } | |
713 | ||
95db3b25 | 714 | static int |
2f7f730a | 715 | tda998x_configure_audio(struct tda998x_priv *priv, |
95db3b25 JS |
716 | struct tda998x_audio_params *params, |
717 | unsigned mode_clock) | |
c4c11dd1 | 718 | { |
e66e03ab RK |
719 | u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv; |
720 | u32 n; | |
c4c11dd1 RK |
721 | |
722 | /* Enable audio ports */ | |
95db3b25 | 723 | reg_write(priv, REG_ENA_AP, params->config); |
c4c11dd1 RK |
724 | |
725 | /* Set audio input source */ | |
95db3b25 | 726 | switch (params->format) { |
c4c11dd1 | 727 | case AFMT_SPDIF: |
95db3b25 | 728 | reg_write(priv, REG_ENA_ACLK, 0); |
10df1a95 JFM |
729 | reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF); |
730 | clksel_aip = AIP_CLKSEL_AIP_SPDIF; | |
731 | clksel_fs = AIP_CLKSEL_FS_FS64SPDIF; | |
c4c11dd1 | 732 | cts_n = CTS_N_M(3) | CTS_N_K(3); |
c4c11dd1 RK |
733 | break; |
734 | ||
735 | case AFMT_I2S: | |
95db3b25 | 736 | reg_write(priv, REG_ENA_ACLK, 1); |
10df1a95 JFM |
737 | reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); |
738 | clksel_aip = AIP_CLKSEL_AIP_I2S; | |
739 | clksel_fs = AIP_CLKSEL_FS_ACLK; | |
95db3b25 JS |
740 | switch (params->sample_width) { |
741 | case 16: | |
742 | cts_n = CTS_N_M(3) | CTS_N_K(1); | |
743 | break; | |
744 | case 18: | |
745 | case 20: | |
746 | case 24: | |
747 | cts_n = CTS_N_M(3) | CTS_N_K(2); | |
748 | break; | |
749 | default: | |
750 | case 32: | |
751 | cts_n = CTS_N_M(3) | CTS_N_K(3); | |
752 | break; | |
753 | } | |
c4c11dd1 | 754 | break; |
3b28802e DH |
755 | |
756 | default: | |
7e567624 | 757 | dev_err(&priv->hdmi->dev, "Unsupported I2S format\n"); |
95db3b25 | 758 | return -EINVAL; |
c4c11dd1 RK |
759 | } |
760 | ||
2f7f730a | 761 | reg_write(priv, REG_AIP_CLKSEL, clksel_aip); |
a8b517e5 JFM |
762 | reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | |
763 | AIP_CNTRL_0_ACR_MAN); /* auto CTS */ | |
2f7f730a | 764 | reg_write(priv, REG_CTS_N, cts_n); |
c4c11dd1 RK |
765 | |
766 | /* | |
767 | * Audio input somehow depends on HDMI line rate which is | |
768 | * related to pixclk. Testing showed that modes with pixclk | |
769 | * >100MHz need a larger divider while <40MHz need the default. | |
770 | * There is no detailed info in the datasheet, so we just | |
771 | * assume 100MHz requires larger divider. | |
772 | */ | |
2470fecc | 773 | adiv = AUDIO_DIV_SERCLK_8; |
95db3b25 | 774 | if (mode_clock > 100000) |
2470fecc JFM |
775 | adiv++; /* AUDIO_DIV_SERCLK_16 */ |
776 | ||
777 | /* S/PDIF asks for a larger divider */ | |
95db3b25 | 778 | if (params->format == AFMT_SPDIF) |
2470fecc JFM |
779 | adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */ |
780 | ||
2f7f730a | 781 | reg_write(priv, REG_AUDIO_DIV, adiv); |
c4c11dd1 RK |
782 | |
783 | /* | |
784 | * This is the approximate value of N, which happens to be | |
785 | * the recommended values for non-coherent clocks. | |
786 | */ | |
95db3b25 | 787 | n = 128 * params->sample_rate / 1000; |
c4c11dd1 RK |
788 | |
789 | /* Write the CTS and N values */ | |
790 | buf[0] = 0x44; | |
791 | buf[1] = 0x42; | |
792 | buf[2] = 0x01; | |
793 | buf[3] = n; | |
794 | buf[4] = n >> 8; | |
795 | buf[5] = n >> 16; | |
2f7f730a | 796 | reg_write_range(priv, REG_ACR_CTS_0, buf, 6); |
c4c11dd1 RK |
797 | |
798 | /* Set CTS clock reference */ | |
2f7f730a | 799 | reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs); |
c4c11dd1 RK |
800 | |
801 | /* Reset CTS generator */ | |
2f7f730a JFM |
802 | reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); |
803 | reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); | |
c4c11dd1 | 804 | |
95db3b25 JS |
805 | /* Write the channel status |
806 | * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because | |
807 | * there is a separate register for each I2S wire. | |
808 | */ | |
809 | buf[0] = params->status[0]; | |
810 | buf[1] = params->status[1]; | |
811 | buf[2] = params->status[3]; | |
812 | buf[3] = params->status[4]; | |
2f7f730a | 813 | reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); |
c4c11dd1 | 814 | |
2f7f730a | 815 | tda998x_audio_mute(priv, true); |
73d5e253 | 816 | msleep(20); |
2f7f730a | 817 | tda998x_audio_mute(priv, false); |
c4c11dd1 | 818 | |
95db3b25 | 819 | return tda998x_write_aif(priv, ¶ms->cea); |
c4c11dd1 RK |
820 | } |
821 | ||
e7792ce2 RC |
822 | /* DRM encoder functions */ |
823 | ||
a8f4d4d6 RK |
824 | static void tda998x_encoder_set_config(struct tda998x_priv *priv, |
825 | const struct tda998x_encoder_params *p) | |
e7792ce2 | 826 | { |
c4c11dd1 RK |
827 | priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | |
828 | (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | | |
829 | VIP_CNTRL_0_SWAP_B(p->swap_b) | | |
830 | (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); | |
831 | priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | | |
832 | (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | | |
833 | VIP_CNTRL_1_SWAP_D(p->swap_d) | | |
834 | (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); | |
835 | priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | | |
836 | (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | | |
837 | VIP_CNTRL_2_SWAP_F(p->swap_f) | | |
838 | (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); | |
839 | ||
95db3b25 | 840 | priv->audio_params = p->audio_params; |
e7792ce2 RC |
841 | } |
842 | ||
9525c4dd | 843 | static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) |
e7792ce2 | 844 | { |
9525c4dd RK |
845 | struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); |
846 | ||
e7792ce2 RC |
847 | /* we only care about on or off: */ |
848 | if (mode != DRM_MODE_DPMS_ON) | |
849 | mode = DRM_MODE_DPMS_OFF; | |
850 | ||
851 | if (mode == priv->dpms) | |
852 | return; | |
853 | ||
854 | switch (mode) { | |
855 | case DRM_MODE_DPMS_ON: | |
c4c11dd1 | 856 | /* enable video ports, audio will be enabled later */ |
2f7f730a JFM |
857 | reg_write(priv, REG_ENA_VP_0, 0xff); |
858 | reg_write(priv, REG_ENA_VP_1, 0xff); | |
859 | reg_write(priv, REG_ENA_VP_2, 0xff); | |
e7792ce2 | 860 | /* set muxing after enabling ports: */ |
2f7f730a JFM |
861 | reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); |
862 | reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); | |
863 | reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); | |
e7792ce2 RC |
864 | break; |
865 | case DRM_MODE_DPMS_OFF: | |
db6aaf4d | 866 | /* disable video ports */ |
2f7f730a JFM |
867 | reg_write(priv, REG_ENA_VP_0, 0x00); |
868 | reg_write(priv, REG_ENA_VP_1, 0x00); | |
869 | reg_write(priv, REG_ENA_VP_2, 0x00); | |
e7792ce2 RC |
870 | break; |
871 | } | |
872 | ||
873 | priv->dpms = mode; | |
874 | } | |
875 | ||
9525c4dd RK |
876 | static int tda998x_connector_mode_valid(struct drm_connector *connector, |
877 | struct drm_display_mode *mode) | |
e7792ce2 | 878 | { |
e4618c46 LDA |
879 | /* TDA19988 dotclock can go up to 165MHz */ |
880 | struct tda998x_priv *priv = conn_to_tda998x_priv(connector); | |
881 | ||
882 | if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) | |
92fbdfcd RK |
883 | return MODE_CLOCK_HIGH; |
884 | if (mode->htotal >= BIT(13)) | |
885 | return MODE_BAD_HVALUE; | |
886 | if (mode->vtotal >= BIT(11)) | |
887 | return MODE_BAD_VVALUE; | |
e7792ce2 RC |
888 | return MODE_OK; |
889 | } | |
890 | ||
891 | static void | |
9525c4dd | 892 | tda998x_encoder_mode_set(struct drm_encoder *encoder, |
a8f4d4d6 RK |
893 | struct drm_display_mode *mode, |
894 | struct drm_display_mode *adjusted_mode) | |
e7792ce2 | 895 | { |
9525c4dd | 896 | struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); |
e66e03ab RK |
897 | u16 ref_pix, ref_line, n_pix, n_line; |
898 | u16 hs_pix_s, hs_pix_e; | |
899 | u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; | |
900 | u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; | |
901 | u16 vwin1_line_s, vwin1_line_e; | |
902 | u16 vwin2_line_s, vwin2_line_e; | |
903 | u16 de_pix_s, de_pix_e; | |
904 | u8 reg, div, rep; | |
e7792ce2 | 905 | |
088d61d1 SH |
906 | /* |
907 | * Internally TDA998x is using ITU-R BT.656 style sync but | |
908 | * we get VESA style sync. TDA998x is using a reference pixel | |
909 | * relative to ITU to sync to the input frame and for output | |
910 | * sync generation. Currently, we are using reference detection | |
911 | * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point | |
912 | * which is position of rising VS with coincident rising HS. | |
913 | * | |
914 | * Now there is some issues to take care of: | |
915 | * - HDMI data islands require sync-before-active | |
916 | * - TDA998x register values must be > 0 to be enabled | |
917 | * - REFLINE needs an additional offset of +1 | |
918 | * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB | |
919 | * | |
920 | * So we add +1 to all horizontal and vertical register values, | |
921 | * plus an additional +3 for REFPIX as we are using RGB input only. | |
e7792ce2 | 922 | */ |
088d61d1 SH |
923 | n_pix = mode->htotal; |
924 | n_line = mode->vtotal; | |
925 | ||
926 | hs_pix_e = mode->hsync_end - mode->hdisplay; | |
927 | hs_pix_s = mode->hsync_start - mode->hdisplay; | |
928 | de_pix_e = mode->htotal; | |
929 | de_pix_s = mode->htotal - mode->hdisplay; | |
930 | ref_pix = 3 + hs_pix_s; | |
931 | ||
179f1aa4 SH |
932 | /* |
933 | * Attached LCD controllers may generate broken sync. Allow | |
934 | * those to adjust the position of the rising VS edge by adding | |
935 | * HSKEW to ref_pix. | |
936 | */ | |
937 | if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) | |
938 | ref_pix += adjusted_mode->hskew; | |
939 | ||
088d61d1 SH |
940 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { |
941 | ref_line = 1 + mode->vsync_start - mode->vdisplay; | |
942 | vwin1_line_s = mode->vtotal - mode->vdisplay - 1; | |
943 | vwin1_line_e = vwin1_line_s + mode->vdisplay; | |
944 | vs1_pix_s = vs1_pix_e = hs_pix_s; | |
945 | vs1_line_s = mode->vsync_start - mode->vdisplay; | |
946 | vs1_line_e = vs1_line_s + | |
947 | mode->vsync_end - mode->vsync_start; | |
948 | vwin2_line_s = vwin2_line_e = 0; | |
949 | vs2_pix_s = vs2_pix_e = 0; | |
950 | vs2_line_s = vs2_line_e = 0; | |
951 | } else { | |
952 | ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; | |
953 | vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; | |
954 | vwin1_line_e = vwin1_line_s + mode->vdisplay/2; | |
955 | vs1_pix_s = vs1_pix_e = hs_pix_s; | |
956 | vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; | |
957 | vs1_line_e = vs1_line_s + | |
958 | (mode->vsync_end - mode->vsync_start)/2; | |
959 | vwin2_line_s = vwin1_line_s + mode->vtotal/2; | |
960 | vwin2_line_e = vwin2_line_s + mode->vdisplay/2; | |
961 | vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; | |
962 | vs2_line_s = vs1_line_s + mode->vtotal/2 ; | |
963 | vs2_line_e = vs2_line_s + | |
964 | (mode->vsync_end - mode->vsync_start)/2; | |
965 | } | |
e7792ce2 RC |
966 | |
967 | div = 148500 / mode->clock; | |
3ae471f7 JFM |
968 | if (div != 0) { |
969 | div--; | |
970 | if (div > 3) | |
971 | div = 3; | |
972 | } | |
e7792ce2 | 973 | |
e7792ce2 | 974 | /* mute the audio FIFO: */ |
2f7f730a | 975 | reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
e7792ce2 RC |
976 | |
977 | /* set HDMI HDCP mode off: */ | |
81b53a16 | 978 | reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); |
2f7f730a JFM |
979 | reg_clear(priv, REG_TX33, TX33_HDMI); |
980 | reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); | |
e7792ce2 | 981 | |
e7792ce2 | 982 | /* no pre-filter or interpolator: */ |
2f7f730a | 983 | reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | |
e7792ce2 | 984 | HVF_CNTRL_0_INTPOL(0)); |
2f7f730a JFM |
985 | reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); |
986 | reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | | |
e7792ce2 | 987 | VIP_CNTRL_4_BLC(0)); |
e7792ce2 | 988 | |
2f7f730a | 989 | reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); |
a8b517e5 JFM |
990 | reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | |
991 | PLL_SERIAL_3_SRL_DE); | |
2f7f730a JFM |
992 | reg_write(priv, REG_SERIALIZER, 0); |
993 | reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); | |
e7792ce2 RC |
994 | |
995 | /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ | |
996 | rep = 0; | |
2f7f730a JFM |
997 | reg_write(priv, REG_RPT_CNTRL, 0); |
998 | reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | | |
e7792ce2 RC |
999 | SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); |
1000 | ||
2f7f730a | 1001 | reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | |
e7792ce2 RC |
1002 | PLL_SERIAL_2_SRL_PR(rep)); |
1003 | ||
e7792ce2 | 1004 | /* set color matrix bypass flag: */ |
81b53a16 JFM |
1005 | reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | |
1006 | MAT_CONTRL_MAT_SC(1)); | |
e7792ce2 RC |
1007 | |
1008 | /* set BIAS tmds value: */ | |
2f7f730a | 1009 | reg_write(priv, REG_ANA_GENERAL, 0x09); |
e7792ce2 | 1010 | |
088d61d1 SH |
1011 | /* |
1012 | * Sync on rising HSYNC/VSYNC | |
1013 | */ | |
81b53a16 | 1014 | reg = VIP_CNTRL_3_SYNC_HS; |
088d61d1 SH |
1015 | |
1016 | /* | |
1017 | * TDA19988 requires high-active sync at input stage, | |
1018 | * so invert low-active sync provided by master encoder here | |
1019 | */ | |
1020 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
81b53a16 | 1021 | reg |= VIP_CNTRL_3_H_TGL; |
e7792ce2 | 1022 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
81b53a16 JFM |
1023 | reg |= VIP_CNTRL_3_V_TGL; |
1024 | reg_write(priv, REG_VIP_CNTRL_3, reg); | |
2f7f730a JFM |
1025 | |
1026 | reg_write(priv, REG_VIDFORMAT, 0x00); | |
1027 | reg_write16(priv, REG_REFPIX_MSB, ref_pix); | |
1028 | reg_write16(priv, REG_REFLINE_MSB, ref_line); | |
1029 | reg_write16(priv, REG_NPIX_MSB, n_pix); | |
1030 | reg_write16(priv, REG_NLINE_MSB, n_line); | |
1031 | reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); | |
1032 | reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); | |
1033 | reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); | |
1034 | reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); | |
1035 | reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); | |
1036 | reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); | |
1037 | reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); | |
1038 | reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); | |
1039 | reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); | |
1040 | reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); | |
1041 | reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); | |
1042 | reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); | |
1043 | reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); | |
1044 | reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); | |
1045 | reg_write16(priv, REG_DE_START_MSB, de_pix_s); | |
1046 | reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); | |
e7792ce2 RC |
1047 | |
1048 | if (priv->rev == TDA19988) { | |
1049 | /* let incoming pixels fill the active space (if any) */ | |
2f7f730a | 1050 | reg_write(priv, REG_ENABLE_SPACE, 0x00); |
e7792ce2 RC |
1051 | } |
1052 | ||
81b53a16 JFM |
1053 | /* |
1054 | * Always generate sync polarity relative to input sync and | |
1055 | * revert input stage toggled sync at output stage | |
1056 | */ | |
1057 | reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; | |
1058 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1059 | reg |= TBG_CNTRL_1_H_TGL; | |
1060 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1061 | reg |= TBG_CNTRL_1_V_TGL; | |
1062 | reg_write(priv, REG_TBG_CNTRL_1, reg); | |
1063 | ||
e7792ce2 | 1064 | /* must be last register set: */ |
81b53a16 | 1065 | reg_write(priv, REG_TBG_CNTRL_0, 0); |
c4c11dd1 RK |
1066 | |
1067 | /* Only setup the info frames if the sink is HDMI */ | |
1068 | if (priv->is_hdmi_sink) { | |
1069 | /* We need to turn HDMI HDCP stuff on to get audio through */ | |
81b53a16 JFM |
1070 | reg &= ~TBG_CNTRL_1_DWIN_DIS; |
1071 | reg_write(priv, REG_TBG_CNTRL_1, reg); | |
2f7f730a JFM |
1072 | reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); |
1073 | reg_set(priv, REG_TX33, TX33_HDMI); | |
c4c11dd1 | 1074 | |
2f7f730a | 1075 | tda998x_write_avi(priv, adjusted_mode); |
c4c11dd1 | 1076 | |
95db3b25 | 1077 | if (priv->audio_params.format != AFMT_UNUSED) { |
7e567624 | 1078 | mutex_lock(&priv->audio_mutex); |
95db3b25 JS |
1079 | tda998x_configure_audio(priv, |
1080 | &priv->audio_params, | |
1081 | adjusted_mode->clock); | |
7e567624 | 1082 | mutex_unlock(&priv->audio_mutex); |
95db3b25 | 1083 | } |
c4c11dd1 | 1084 | } |
e7792ce2 RC |
1085 | } |
1086 | ||
1087 | static enum drm_connector_status | |
9525c4dd | 1088 | tda998x_connector_detect(struct drm_connector *connector, bool force) |
e7792ce2 | 1089 | { |
9525c4dd | 1090 | struct tda998x_priv *priv = conn_to_tda998x_priv(connector); |
e66e03ab | 1091 | u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); |
2f7f730a | 1092 | |
e7792ce2 RC |
1093 | return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : |
1094 | connector_status_disconnected; | |
1095 | } | |
1096 | ||
07259f8b | 1097 | static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) |
e7792ce2 | 1098 | { |
07259f8b | 1099 | struct tda998x_priv *priv = data; |
e66e03ab | 1100 | u8 offset, segptr; |
e7792ce2 RC |
1101 | int ret, i; |
1102 | ||
e7792ce2 RC |
1103 | offset = (blk & 1) ? 128 : 0; |
1104 | segptr = blk / 2; | |
1105 | ||
2f7f730a JFM |
1106 | reg_write(priv, REG_DDC_ADDR, 0xa0); |
1107 | reg_write(priv, REG_DDC_OFFS, offset); | |
1108 | reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); | |
1109 | reg_write(priv, REG_DDC_SEGM, segptr); | |
e7792ce2 RC |
1110 | |
1111 | /* enable reading EDID: */ | |
12473b7d | 1112 | priv->wq_edid_wait = 1; |
2f7f730a | 1113 | reg_write(priv, REG_EDID_CTRL, 0x1); |
e7792ce2 RC |
1114 | |
1115 | /* flag must be cleared by sw: */ | |
2f7f730a | 1116 | reg_write(priv, REG_EDID_CTRL, 0x0); |
e7792ce2 RC |
1117 | |
1118 | /* wait for block read to complete: */ | |
12473b7d JFM |
1119 | if (priv->hdmi->irq) { |
1120 | i = wait_event_timeout(priv->wq_edid, | |
1121 | !priv->wq_edid_wait, | |
1122 | msecs_to_jiffies(100)); | |
1123 | if (i < 0) { | |
5e7fe2fe | 1124 | dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); |
12473b7d JFM |
1125 | return i; |
1126 | } | |
1127 | } else { | |
713456db RK |
1128 | for (i = 100; i > 0; i--) { |
1129 | msleep(1); | |
12473b7d JFM |
1130 | ret = reg_read(priv, REG_INT_FLAGS_2); |
1131 | if (ret < 0) | |
1132 | return ret; | |
1133 | if (ret & INT_FLAGS_2_EDID_BLK_RD) | |
1134 | break; | |
1135 | } | |
e7792ce2 RC |
1136 | } |
1137 | ||
12473b7d | 1138 | if (i == 0) { |
5e7fe2fe | 1139 | dev_err(&priv->hdmi->dev, "read edid timeout\n"); |
e7792ce2 | 1140 | return -ETIMEDOUT; |
12473b7d | 1141 | } |
e7792ce2 | 1142 | |
07259f8b LP |
1143 | ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); |
1144 | if (ret != length) { | |
5e7fe2fe RK |
1145 | dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", |
1146 | blk, ret); | |
e7792ce2 RC |
1147 | return ret; |
1148 | } | |
1149 | ||
e7792ce2 RC |
1150 | return 0; |
1151 | } | |
1152 | ||
9525c4dd | 1153 | static int tda998x_connector_get_modes(struct drm_connector *connector) |
e7792ce2 | 1154 | { |
9525c4dd | 1155 | struct tda998x_priv *priv = conn_to_tda998x_priv(connector); |
07259f8b LP |
1156 | struct edid *edid; |
1157 | int n; | |
e7792ce2 | 1158 | |
0fc6f44d RK |
1159 | /* |
1160 | * If we get killed while waiting for the HPD timeout, return | |
1161 | * no modes found: we are not in a restartable path, so we | |
1162 | * can't handle signals gracefully. | |
1163 | */ | |
1164 | if (tda998x_edid_delay_wait(priv)) | |
1165 | return 0; | |
1166 | ||
063b472f | 1167 | if (priv->rev == TDA19988) |
2f7f730a | 1168 | reg_clear(priv, REG_TX4, TX4_PD_RAM); |
063b472f | 1169 | |
07259f8b | 1170 | edid = drm_do_get_edid(connector, read_edid_block, priv); |
e7792ce2 | 1171 | |
063b472f | 1172 | if (priv->rev == TDA19988) |
2f7f730a | 1173 | reg_set(priv, REG_TX4, TX4_PD_RAM); |
063b472f | 1174 | |
07259f8b LP |
1175 | if (!edid) { |
1176 | dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); | |
1177 | return 0; | |
e7792ce2 RC |
1178 | } |
1179 | ||
07259f8b LP |
1180 | drm_mode_connector_update_edid_property(connector, edid); |
1181 | n = drm_add_edid_modes(connector, edid); | |
1182 | priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); | |
7e567624 JS |
1183 | drm_edid_to_eld(connector, edid); |
1184 | ||
07259f8b LP |
1185 | kfree(edid); |
1186 | ||
e7792ce2 RC |
1187 | return n; |
1188 | } | |
1189 | ||
a8f4d4d6 RK |
1190 | static void tda998x_encoder_set_polling(struct tda998x_priv *priv, |
1191 | struct drm_connector *connector) | |
e7792ce2 | 1192 | { |
12473b7d JFM |
1193 | if (priv->hdmi->irq) |
1194 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
1195 | else | |
1196 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | | |
1197 | DRM_CONNECTOR_POLL_DISCONNECT; | |
e7792ce2 RC |
1198 | } |
1199 | ||
a8f4d4d6 | 1200 | static void tda998x_destroy(struct tda998x_priv *priv) |
e7792ce2 | 1201 | { |
12473b7d JFM |
1202 | /* disable all IRQs and free the IRQ handler */ |
1203 | cec_write(priv, REG_CEC_RXSHPDINTENA, 0); | |
1204 | reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); | |
0fc6f44d | 1205 | |
7e567624 JS |
1206 | if (priv->audio_pdev) |
1207 | platform_device_unregister(priv->audio_pdev); | |
1208 | ||
0fc6f44d | 1209 | if (priv->hdmi->irq) |
12473b7d | 1210 | free_irq(priv->hdmi->irq, priv); |
0fc6f44d RK |
1211 | |
1212 | del_timer_sync(&priv->edid_delay_timer); | |
1213 | cancel_work_sync(&priv->detect_work); | |
12473b7d | 1214 | |
89fc8686 | 1215 | i2c_unregister_device(priv->cec); |
a8f4d4d6 RK |
1216 | } |
1217 | ||
7e567624 JS |
1218 | static int tda998x_audio_hw_params(struct device *dev, void *data, |
1219 | struct hdmi_codec_daifmt *daifmt, | |
1220 | struct hdmi_codec_params *params) | |
1221 | { | |
1222 | struct tda998x_priv *priv = dev_get_drvdata(dev); | |
1223 | int i, ret; | |
1224 | struct tda998x_audio_params audio = { | |
1225 | .sample_width = params->sample_width, | |
1226 | .sample_rate = params->sample_rate, | |
1227 | .cea = params->cea, | |
1228 | }; | |
1229 | ||
1230 | if (!priv->encoder.crtc) | |
1231 | return -ENODEV; | |
1232 | ||
1233 | memcpy(audio.status, params->iec.status, | |
1234 | min(sizeof(audio.status), sizeof(params->iec.status))); | |
1235 | ||
1236 | switch (daifmt->fmt) { | |
1237 | case HDMI_I2S: | |
1238 | if (daifmt->bit_clk_inv || daifmt->frame_clk_inv || | |
1239 | daifmt->bit_clk_master || daifmt->frame_clk_master) { | |
1240 | dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, | |
1241 | daifmt->bit_clk_inv, daifmt->frame_clk_inv, | |
1242 | daifmt->bit_clk_master, | |
1243 | daifmt->frame_clk_master); | |
1244 | return -EINVAL; | |
1245 | } | |
1246 | for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) | |
1247 | if (priv->audio_port[i].format == AFMT_I2S) | |
1248 | audio.config = priv->audio_port[i].config; | |
1249 | audio.format = AFMT_I2S; | |
1250 | break; | |
1251 | case HDMI_SPDIF: | |
1252 | for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) | |
1253 | if (priv->audio_port[i].format == AFMT_SPDIF) | |
1254 | audio.config = priv->audio_port[i].config; | |
1255 | audio.format = AFMT_SPDIF; | |
1256 | break; | |
1257 | default: | |
1258 | dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); | |
1259 | return -EINVAL; | |
1260 | } | |
1261 | ||
1262 | if (audio.config == 0) { | |
1263 | dev_err(dev, "%s: No audio configutation found\n", __func__); | |
1264 | return -EINVAL; | |
1265 | } | |
1266 | ||
1267 | mutex_lock(&priv->audio_mutex); | |
1268 | ret = tda998x_configure_audio(priv, | |
1269 | &audio, | |
1270 | priv->encoder.crtc->hwmode.clock); | |
1271 | ||
1272 | if (ret == 0) | |
1273 | priv->audio_params = audio; | |
1274 | mutex_unlock(&priv->audio_mutex); | |
1275 | ||
1276 | return ret; | |
1277 | } | |
1278 | ||
1279 | static void tda998x_audio_shutdown(struct device *dev, void *data) | |
1280 | { | |
1281 | struct tda998x_priv *priv = dev_get_drvdata(dev); | |
1282 | ||
1283 | mutex_lock(&priv->audio_mutex); | |
1284 | ||
1285 | reg_write(priv, REG_ENA_AP, 0); | |
1286 | ||
1287 | priv->audio_params.format = AFMT_UNUSED; | |
1288 | ||
1289 | mutex_unlock(&priv->audio_mutex); | |
1290 | } | |
1291 | ||
1292 | int tda998x_audio_digital_mute(struct device *dev, void *data, bool enable) | |
1293 | { | |
1294 | struct tda998x_priv *priv = dev_get_drvdata(dev); | |
1295 | ||
1296 | mutex_lock(&priv->audio_mutex); | |
1297 | ||
1298 | tda998x_audio_mute(priv, enable); | |
1299 | ||
1300 | mutex_unlock(&priv->audio_mutex); | |
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static int tda998x_audio_get_eld(struct device *dev, void *data, | |
1305 | uint8_t *buf, size_t len) | |
1306 | { | |
1307 | struct tda998x_priv *priv = dev_get_drvdata(dev); | |
1308 | struct drm_mode_config *config = &priv->encoder.dev->mode_config; | |
1309 | struct drm_connector *connector; | |
1310 | int ret = -ENODEV; | |
1311 | ||
1312 | mutex_lock(&config->mutex); | |
1313 | list_for_each_entry(connector, &config->connector_list, head) { | |
1314 | if (&priv->encoder == connector->encoder) { | |
1315 | memcpy(buf, connector->eld, | |
1316 | min(sizeof(connector->eld), len)); | |
1317 | ret = 0; | |
1318 | } | |
1319 | } | |
1320 | mutex_unlock(&config->mutex); | |
1321 | ||
1322 | return ret; | |
1323 | } | |
1324 | ||
1325 | static const struct hdmi_codec_ops audio_codec_ops = { | |
1326 | .hw_params = tda998x_audio_hw_params, | |
1327 | .audio_shutdown = tda998x_audio_shutdown, | |
1328 | .digital_mute = tda998x_audio_digital_mute, | |
1329 | .get_eld = tda998x_audio_get_eld, | |
1330 | }; | |
1331 | ||
1332 | static int tda998x_audio_codec_init(struct tda998x_priv *priv, | |
1333 | struct device *dev) | |
1334 | { | |
1335 | struct hdmi_codec_pdata codec_data = { | |
1336 | .ops = &audio_codec_ops, | |
1337 | .max_i2s_channels = 2, | |
1338 | }; | |
1339 | int i; | |
1340 | ||
1341 | for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) { | |
1342 | if (priv->audio_port[i].format == AFMT_I2S && | |
1343 | priv->audio_port[i].config != 0) | |
1344 | codec_data.i2s = 1; | |
1345 | if (priv->audio_port[i].format == AFMT_SPDIF && | |
1346 | priv->audio_port[i].config != 0) | |
1347 | codec_data.spdif = 1; | |
1348 | } | |
1349 | ||
1350 | priv->audio_pdev = platform_device_register_data( | |
1351 | dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, | |
1352 | &codec_data, sizeof(codec_data)); | |
1353 | ||
1354 | return PTR_ERR_OR_ZERO(priv->audio_pdev); | |
1355 | } | |
1356 | ||
e7792ce2 RC |
1357 | /* I2C driver functions */ |
1358 | ||
7e567624 JS |
1359 | static int tda998x_get_audio_ports(struct tda998x_priv *priv, |
1360 | struct device_node *np) | |
1361 | { | |
1362 | const u32 *port_data; | |
1363 | u32 size; | |
1364 | int i; | |
1365 | ||
1366 | port_data = of_get_property(np, "audio-ports", &size); | |
1367 | if (!port_data) | |
1368 | return 0; | |
1369 | ||
1370 | size /= sizeof(u32); | |
1371 | if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) { | |
1372 | dev_err(&priv->hdmi->dev, | |
1373 | "Bad number of elements in audio-ports dt-property\n"); | |
1374 | return -EINVAL; | |
1375 | } | |
1376 | ||
1377 | size /= 2; | |
1378 | ||
1379 | for (i = 0; i < size; i++) { | |
1380 | u8 afmt = be32_to_cpup(&port_data[2*i]); | |
1381 | u8 ena_ap = be32_to_cpup(&port_data[2*i+1]); | |
1382 | ||
1383 | if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) { | |
1384 | dev_err(&priv->hdmi->dev, | |
1385 | "Bad audio format %u\n", afmt); | |
1386 | return -EINVAL; | |
1387 | } | |
1388 | ||
1389 | priv->audio_port[i].format = afmt; | |
1390 | priv->audio_port[i].config = ena_ap; | |
1391 | } | |
1392 | ||
1393 | if (priv->audio_port[0].format == priv->audio_port[1].format) { | |
1394 | dev_err(&priv->hdmi->dev, | |
1395 | "There can only be on I2S port and one SPDIF port\n"); | |
1396 | return -EINVAL; | |
1397 | } | |
1398 | return 0; | |
1399 | } | |
1400 | ||
a8f4d4d6 | 1401 | static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) |
e7792ce2 | 1402 | { |
0d44ea19 JFM |
1403 | struct device_node *np = client->dev.of_node; |
1404 | u32 video; | |
fb7544d7 | 1405 | int rev_lo, rev_hi, ret; |
cfe38757 | 1406 | unsigned short cec_addr; |
e7792ce2 | 1407 | |
5e74c22c RK |
1408 | priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); |
1409 | priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); | |
1410 | priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); | |
1411 | ||
2eb4c7b1 | 1412 | priv->current_page = 0xff; |
2f7f730a | 1413 | priv->hdmi = client; |
cfe38757 AJ |
1414 | /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ |
1415 | cec_addr = 0x34 + (client->addr & 0x03); | |
1416 | priv->cec = i2c_new_dummy(client->adapter, cec_addr); | |
a8f4d4d6 | 1417 | if (!priv->cec) |
6ae668cc | 1418 | return -ENODEV; |
12473b7d | 1419 | |
e7792ce2 RC |
1420 | priv->dpms = DRM_MODE_DPMS_OFF; |
1421 | ||
ed9a8426 | 1422 | mutex_init(&priv->mutex); /* protect the page access */ |
0fc6f44d RK |
1423 | init_waitqueue_head(&priv->edid_delay_waitq); |
1424 | setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done, | |
1425 | (unsigned long)priv); | |
1426 | INIT_WORK(&priv->detect_work, tda998x_detect_work); | |
ed9a8426 | 1427 | |
e7792ce2 | 1428 | /* wake up the device: */ |
2f7f730a | 1429 | cec_write(priv, REG_CEC_ENAMODS, |
e7792ce2 RC |
1430 | CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); |
1431 | ||
2f7f730a | 1432 | tda998x_reset(priv); |
e7792ce2 RC |
1433 | |
1434 | /* read version: */ | |
fb7544d7 RK |
1435 | rev_lo = reg_read(priv, REG_VERSION_LSB); |
1436 | rev_hi = reg_read(priv, REG_VERSION_MSB); | |
1437 | if (rev_lo < 0 || rev_hi < 0) { | |
1438 | ret = rev_lo < 0 ? rev_lo : rev_hi; | |
7d2eadc9 | 1439 | goto fail; |
fb7544d7 RK |
1440 | } |
1441 | ||
1442 | priv->rev = rev_lo | rev_hi << 8; | |
e7792ce2 RC |
1443 | |
1444 | /* mask off feature bits: */ | |
1445 | priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ | |
1446 | ||
1447 | switch (priv->rev) { | |
b728fab7 JFM |
1448 | case TDA9989N2: |
1449 | dev_info(&client->dev, "found TDA9989 n2"); | |
1450 | break; | |
1451 | case TDA19989: | |
1452 | dev_info(&client->dev, "found TDA19989"); | |
1453 | break; | |
1454 | case TDA19989N2: | |
1455 | dev_info(&client->dev, "found TDA19989 n2"); | |
1456 | break; | |
1457 | case TDA19988: | |
1458 | dev_info(&client->dev, "found TDA19988"); | |
1459 | break; | |
e7792ce2 | 1460 | default: |
b728fab7 JFM |
1461 | dev_err(&client->dev, "found unsupported device: %04x\n", |
1462 | priv->rev); | |
e7792ce2 RC |
1463 | goto fail; |
1464 | } | |
1465 | ||
1466 | /* after reset, enable DDC: */ | |
2f7f730a | 1467 | reg_write(priv, REG_DDC_DISABLE, 0x00); |
e7792ce2 RC |
1468 | |
1469 | /* set clock on DDC channel: */ | |
2f7f730a | 1470 | reg_write(priv, REG_TX3, 39); |
e7792ce2 RC |
1471 | |
1472 | /* if necessary, disable multi-master: */ | |
1473 | if (priv->rev == TDA19989) | |
2f7f730a | 1474 | reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); |
e7792ce2 | 1475 | |
2f7f730a | 1476 | cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, |
e7792ce2 RC |
1477 | CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); |
1478 | ||
12473b7d JFM |
1479 | /* initialize the optional IRQ */ |
1480 | if (client->irq) { | |
1481 | int irqf_trigger; | |
1482 | ||
6833d26e | 1483 | /* init read EDID waitqueue and HDP work */ |
12473b7d JFM |
1484 | init_waitqueue_head(&priv->wq_edid); |
1485 | ||
1486 | /* clear pending interrupts */ | |
1487 | reg_read(priv, REG_INT_FLAGS_0); | |
1488 | reg_read(priv, REG_INT_FLAGS_1); | |
1489 | reg_read(priv, REG_INT_FLAGS_2); | |
1490 | ||
1491 | irqf_trigger = | |
1492 | irqd_get_trigger_type(irq_get_irq_data(client->irq)); | |
1493 | ret = request_threaded_irq(client->irq, NULL, | |
1494 | tda998x_irq_thread, | |
1495 | irqf_trigger | IRQF_ONESHOT, | |
1496 | "tda998x", priv); | |
1497 | if (ret) { | |
1498 | dev_err(&client->dev, | |
1499 | "failed to request IRQ#%u: %d\n", | |
1500 | client->irq, ret); | |
1501 | goto fail; | |
1502 | } | |
1503 | ||
1504 | /* enable HPD irq */ | |
1505 | cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); | |
1506 | } | |
1507 | ||
e4782627 JFM |
1508 | /* enable EDID read irq: */ |
1509 | reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); | |
1510 | ||
0d44ea19 JFM |
1511 | if (!np) |
1512 | return 0; /* non-DT */ | |
1513 | ||
7e567624 | 1514 | /* get the device tree parameters */ |
0d44ea19 JFM |
1515 | ret = of_property_read_u32(np, "video-ports", &video); |
1516 | if (ret == 0) { | |
1517 | priv->vip_cntrl_0 = video >> 16; | |
1518 | priv->vip_cntrl_1 = video >> 8; | |
1519 | priv->vip_cntrl_2 = video; | |
1520 | } | |
1521 | ||
7e567624 | 1522 | mutex_init(&priv->audio_mutex); /* Protect access from audio thread */ |
e7792ce2 | 1523 | |
7e567624 JS |
1524 | ret = tda998x_get_audio_ports(priv, np); |
1525 | if (ret) | |
1526 | goto fail; | |
1527 | ||
1528 | if (priv->audio_port[0].format != AFMT_UNUSED) | |
1529 | tda998x_audio_codec_init(priv, &client->dev); | |
1530 | ||
1531 | return 0; | |
e7792ce2 RC |
1532 | fail: |
1533 | /* if encoder_init fails, the encoder slave is never registered, | |
1534 | * so cleanup here: | |
1535 | */ | |
1536 | if (priv->cec) | |
1537 | i2c_unregister_device(priv->cec); | |
e7792ce2 RC |
1538 | return -ENXIO; |
1539 | } | |
1540 | ||
c707c361 RK |
1541 | static void tda998x_encoder_prepare(struct drm_encoder *encoder) |
1542 | { | |
9525c4dd | 1543 | tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
c707c361 RK |
1544 | } |
1545 | ||
1546 | static void tda998x_encoder_commit(struct drm_encoder *encoder) | |
1547 | { | |
9525c4dd | 1548 | tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
c707c361 RK |
1549 | } |
1550 | ||
1551 | static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = { | |
9525c4dd | 1552 | .dpms = tda998x_encoder_dpms, |
c707c361 RK |
1553 | .prepare = tda998x_encoder_prepare, |
1554 | .commit = tda998x_encoder_commit, | |
9525c4dd | 1555 | .mode_set = tda998x_encoder_mode_set, |
c707c361 RK |
1556 | }; |
1557 | ||
1558 | static void tda998x_encoder_destroy(struct drm_encoder *encoder) | |
1559 | { | |
a3584f60 | 1560 | struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); |
c707c361 | 1561 | |
a3584f60 | 1562 | tda998x_destroy(priv); |
c707c361 RK |
1563 | drm_encoder_cleanup(encoder); |
1564 | } | |
1565 | ||
1566 | static const struct drm_encoder_funcs tda998x_encoder_funcs = { | |
1567 | .destroy = tda998x_encoder_destroy, | |
1568 | }; | |
1569 | ||
c707c361 RK |
1570 | static struct drm_encoder * |
1571 | tda998x_connector_best_encoder(struct drm_connector *connector) | |
1572 | { | |
a3584f60 | 1573 | struct tda998x_priv *priv = conn_to_tda998x_priv(connector); |
c707c361 | 1574 | |
a3584f60 | 1575 | return &priv->encoder; |
c707c361 RK |
1576 | } |
1577 | ||
1578 | static | |
1579 | const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { | |
1580 | .get_modes = tda998x_connector_get_modes, | |
1581 | .mode_valid = tda998x_connector_mode_valid, | |
1582 | .best_encoder = tda998x_connector_best_encoder, | |
1583 | }; | |
1584 | ||
c707c361 RK |
1585 | static void tda998x_connector_destroy(struct drm_connector *connector) |
1586 | { | |
74cd62ea | 1587 | drm_connector_unregister(connector); |
c707c361 RK |
1588 | drm_connector_cleanup(connector); |
1589 | } | |
1590 | ||
dad82ea3 JS |
1591 | static int tda998x_connector_dpms(struct drm_connector *connector, int mode) |
1592 | { | |
1593 | if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC)) | |
1594 | return drm_atomic_helper_connector_dpms(connector, mode); | |
1595 | else | |
1596 | return drm_helper_connector_dpms(connector, mode); | |
1597 | } | |
1598 | ||
c707c361 | 1599 | static const struct drm_connector_funcs tda998x_connector_funcs = { |
dad82ea3 | 1600 | .dpms = tda998x_connector_dpms, |
9736e988 | 1601 | .reset = drm_atomic_helper_connector_reset, |
c707c361 RK |
1602 | .fill_modes = drm_helper_probe_single_connector_modes, |
1603 | .detect = tda998x_connector_detect, | |
1604 | .destroy = tda998x_connector_destroy, | |
9736e988 LDA |
1605 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
1606 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
c707c361 RK |
1607 | }; |
1608 | ||
1609 | static int tda998x_bind(struct device *dev, struct device *master, void *data) | |
1610 | { | |
1611 | struct tda998x_encoder_params *params = dev->platform_data; | |
1612 | struct i2c_client *client = to_i2c_client(dev); | |
1613 | struct drm_device *drm = data; | |
a3584f60 | 1614 | struct tda998x_priv *priv; |
e66e03ab | 1615 | u32 crtcs = 0; |
c707c361 RK |
1616 | int ret; |
1617 | ||
1618 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
1619 | if (!priv) | |
1620 | return -ENOMEM; | |
1621 | ||
1622 | dev_set_drvdata(dev, priv); | |
1623 | ||
5dbcf319 RK |
1624 | if (dev->of_node) |
1625 | crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); | |
1626 | ||
1627 | /* If no CRTCs were found, fall back to our old behaviour */ | |
1628 | if (crtcs == 0) { | |
1629 | dev_warn(dev, "Falling back to first CRTC\n"); | |
1630 | crtcs = 1 << 0; | |
1631 | } | |
1632 | ||
a3584f60 RK |
1633 | priv->connector.interlace_allowed = 1; |
1634 | priv->encoder.possible_crtcs = crtcs; | |
c707c361 | 1635 | |
a3584f60 | 1636 | ret = tda998x_create(client, priv); |
c707c361 RK |
1637 | if (ret) |
1638 | return ret; | |
1639 | ||
1640 | if (!dev->of_node && params) | |
a3584f60 | 1641 | tda998x_encoder_set_config(priv, params); |
c707c361 | 1642 | |
a3584f60 | 1643 | tda998x_encoder_set_polling(priv, &priv->connector); |
c707c361 | 1644 | |
a3584f60 RK |
1645 | drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs); |
1646 | ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs, | |
13a3d91f | 1647 | DRM_MODE_ENCODER_TMDS, NULL); |
c707c361 RK |
1648 | if (ret) |
1649 | goto err_encoder; | |
1650 | ||
a3584f60 | 1651 | drm_connector_helper_add(&priv->connector, |
c707c361 | 1652 | &tda998x_connector_helper_funcs); |
a3584f60 | 1653 | ret = drm_connector_init(drm, &priv->connector, |
c707c361 RK |
1654 | &tda998x_connector_funcs, |
1655 | DRM_MODE_CONNECTOR_HDMIA); | |
1656 | if (ret) | |
1657 | goto err_connector; | |
1658 | ||
a3584f60 | 1659 | ret = drm_connector_register(&priv->connector); |
c707c361 RK |
1660 | if (ret) |
1661 | goto err_sysfs; | |
1662 | ||
a3584f60 | 1663 | drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder); |
c707c361 RK |
1664 | |
1665 | return 0; | |
1666 | ||
1667 | err_sysfs: | |
a3584f60 | 1668 | drm_connector_cleanup(&priv->connector); |
c707c361 | 1669 | err_connector: |
a3584f60 | 1670 | drm_encoder_cleanup(&priv->encoder); |
c707c361 | 1671 | err_encoder: |
a3584f60 | 1672 | tda998x_destroy(priv); |
c707c361 RK |
1673 | return ret; |
1674 | } | |
1675 | ||
1676 | static void tda998x_unbind(struct device *dev, struct device *master, | |
1677 | void *data) | |
1678 | { | |
a3584f60 | 1679 | struct tda998x_priv *priv = dev_get_drvdata(dev); |
c707c361 | 1680 | |
debd15ce | 1681 | drm_connector_unregister(&priv->connector); |
a3584f60 RK |
1682 | drm_connector_cleanup(&priv->connector); |
1683 | drm_encoder_cleanup(&priv->encoder); | |
1684 | tda998x_destroy(priv); | |
c707c361 RK |
1685 | } |
1686 | ||
1687 | static const struct component_ops tda998x_ops = { | |
1688 | .bind = tda998x_bind, | |
1689 | .unbind = tda998x_unbind, | |
1690 | }; | |
1691 | ||
1692 | static int | |
1693 | tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) | |
1694 | { | |
1695 | return component_add(&client->dev, &tda998x_ops); | |
1696 | } | |
1697 | ||
1698 | static int tda998x_remove(struct i2c_client *client) | |
1699 | { | |
1700 | component_del(&client->dev, &tda998x_ops); | |
1701 | return 0; | |
1702 | } | |
1703 | ||
0d44ea19 JFM |
1704 | #ifdef CONFIG_OF |
1705 | static const struct of_device_id tda998x_dt_ids[] = { | |
1706 | { .compatible = "nxp,tda998x", }, | |
1707 | { } | |
1708 | }; | |
1709 | MODULE_DEVICE_TABLE(of, tda998x_dt_ids); | |
1710 | #endif | |
1711 | ||
e7792ce2 RC |
1712 | static struct i2c_device_id tda998x_ids[] = { |
1713 | { "tda998x", 0 }, | |
1714 | { } | |
1715 | }; | |
1716 | MODULE_DEVICE_TABLE(i2c, tda998x_ids); | |
1717 | ||
3d58e318 RK |
1718 | static struct i2c_driver tda998x_driver = { |
1719 | .probe = tda998x_probe, | |
1720 | .remove = tda998x_remove, | |
1721 | .driver = { | |
1722 | .name = "tda998x", | |
1723 | .of_match_table = of_match_ptr(tda998x_dt_ids), | |
e7792ce2 | 1724 | }, |
3d58e318 | 1725 | .id_table = tda998x_ids, |
e7792ce2 RC |
1726 | }; |
1727 | ||
3d58e318 | 1728 | module_i2c_driver(tda998x_driver); |
e7792ce2 RC |
1729 | |
1730 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1731 | MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); | |
1732 | MODULE_LICENSE("GPL"); |