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drm/i915: fix possible refcount leak when resetting forcewake
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
e9b73c67
CW		 33#include <uapi/drm/i915_drm.h>
34
585fb111 35#include "i915_reg.h"
79e53945 36#include "intel_bios.h"
8187a2b7 37#include "intel_ringbuffer.h"
0260c420 38#include "i915_gem_gtt.h"
0839ccb8 39#include <linux/io-mapping.h>
f899fc64 40#include <linux/i2c.h>
c167a6fc 41#include <linux/i2c-algo-bit.h>
0ade6386 42#include <drm/intel-gtt.h>
aaa6fd2a 43#include <linux/backlight.h>
5cc9ed4b 44#include <linux/hashtable.h>
2911a35b 45#include <linux/intel-iommu.h>
742cbee8 46#include <linux/kref.h>
9ee32fea 47#include <linux/pm_qos.h>
585fb111 48
1da177e4
LT		 49/* General customization:
50 */
51
52#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
53
54#define DRIVER_NAME "i915"
55#define DRIVER_DESC "Intel Graphics"
673a394b 56#define DRIVER_DATE "20080730"
1da177e4 57
317c35d1 58enum pipe {
752aa88a 59 INVALID_PIPE = -1,
317c35d1
JB		 60 PIPE_A = 0,
61 PIPE_B,
9db4a9c7 62 PIPE_C,
a57c774a
AK		 63 _PIPE_EDP,
64 I915_MAX_PIPES = _PIPE_EDP
317c35d1 65};
9db4a9c7 66#define pipe_name(p) ((p) + 'A')
317c35d1 67
a5c961d1
PZ		 68enum transcoder {
69 TRANSCODER_A = 0,
70 TRANSCODER_B,
71 TRANSCODER_C,
a57c774a
AK		 72 TRANSCODER_EDP,
73 I915_MAX_TRANSCODERS
a5c961d1
PZ		 74};
75#define transcoder_name(t) ((t) + 'A')
76
80824003
JB		 77enum plane {
78 PLANE_A = 0,
79 PLANE_B,
9db4a9c7 80 PLANE_C,
80824003 81};
9db4a9c7 82#define plane_name(p) ((p) + 'A')
52440211 83
d615a166 84#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
06da8da2 85
2b139522
ED		 86enum port {
87 PORT_A = 0,
88 PORT_B,
89 PORT_C,
90 PORT_D,
91 PORT_E,
92 I915_MAX_PORTS
93};
94#define port_name(p) ((p) + 'A')
95
a09caddd 96#define I915_NUM_PHYS_VLV 2
e4607fcf
CML		 97
98enum dpio_channel {
99 DPIO_CH0,
100 DPIO_CH1
101};
102
103enum dpio_phy {
104 DPIO_PHY0,
105 DPIO_PHY1
106};
107
b97186f0
PZ		 108enum intel_display_power_domain {
109 POWER_DOMAIN_PIPE_A,
110 POWER_DOMAIN_PIPE_B,
111 POWER_DOMAIN_PIPE_C,
112 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
114 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
115 POWER_DOMAIN_TRANSCODER_A,
116 POWER_DOMAIN_TRANSCODER_B,
117 POWER_DOMAIN_TRANSCODER_C,
f52e353e 118 POWER_DOMAIN_TRANSCODER_EDP,
319be8ae
ID		 119 POWER_DOMAIN_PORT_DDI_A_2_LANES,
120 POWER_DOMAIN_PORT_DDI_A_4_LANES,
121 POWER_DOMAIN_PORT_DDI_B_2_LANES,
122 POWER_DOMAIN_PORT_DDI_B_4_LANES,
123 POWER_DOMAIN_PORT_DDI_C_2_LANES,
124 POWER_DOMAIN_PORT_DDI_C_4_LANES,
125 POWER_DOMAIN_PORT_DDI_D_2_LANES,
126 POWER_DOMAIN_PORT_DDI_D_4_LANES,
127 POWER_DOMAIN_PORT_DSI,
128 POWER_DOMAIN_PORT_CRT,
129 POWER_DOMAIN_PORT_OTHER,
cdf8dd7f 130 POWER_DOMAIN_VGA,
fbeeaa23 131 POWER_DOMAIN_AUDIO,
baa70707 132 POWER_DOMAIN_INIT,
bddc7645
ID		 133
134 POWER_DOMAIN_NUM,
b97186f0
PZ		 135};
136
137#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
138#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
139 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
f52e353e
ID		 140#define POWER_DOMAIN_TRANSCODER(tran) \
141 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
142 (tran) + POWER_DOMAIN_TRANSCODER_A)
b97186f0 143
1d843f9d
EE		 144enum hpd_pin {
145 HPD_NONE = 0,
146 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
147 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
148 HPD_CRT,
149 HPD_SDVO_B,
150 HPD_SDVO_C,
151 HPD_PORT_B,
152 HPD_PORT_C,
153 HPD_PORT_D,
154 HPD_NUM_PINS
155};
156
2a2d5482
CW		 157#define I915_GEM_GPU_DOMAINS \
158 (I915_GEM_DOMAIN_RENDER | \
159 I915_GEM_DOMAIN_SAMPLER | \
160 I915_GEM_DOMAIN_COMMAND | \
161 I915_GEM_DOMAIN_INSTRUCTION | \
162 I915_GEM_DOMAIN_VERTEX)
62fdfeaf 163
7eb552ae 164#define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
d615a166 165#define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
9db4a9c7 166
d79b814d
DL		 167#define for_each_crtc(dev, crtc) \
168 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
169
d063ae48
DL		 170#define for_each_intel_crtc(dev, intel_crtc) \
171 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
172
6c2b7c12
DV		 173#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
174 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
175 if ((intel_encoder)->base.crtc == (__crtc))
176
53f5e3ca
JB		 177#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
178 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
179 if ((intel_connector)->base.encoder == (__encoder))
180
e7b903d2 181struct drm_i915_private;
5cc9ed4b 182struct i915_mmu_object;
e7b903d2 183
46edb027
DV		 184enum intel_dpll_id {
185 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
186 /* real shared dpll ids must be >= 0 */
187 DPLL_ID_PCH_PLL_A,
188 DPLL_ID_PCH_PLL_B,
189};
190#define I915_NUM_PLLS 2
191
5358901f 192struct intel_dpll_hw_state {
66e985c0 193 uint32_t dpll;
8bcc2795 194 uint32_t dpll_md;
66e985c0
DV		 195 uint32_t fp0;
196 uint32_t fp1;
5358901f
DV		 197};
198
e72f9fbf 199struct intel_shared_dpll {
ee7b9f93
JB		 200 int refcount; /* count of number of CRTCs sharing this PLL */
201 int active; /* count of number of active CRTCs (i.e. DPMS on) */
202 bool on; /* is the PLL actually active? Disabled during modeset */
46edb027
DV		 203 const char *name;
204 /* should match the index in the dev_priv->shared_dplls array */
205 enum intel_dpll_id id;
5358901f 206 struct intel_dpll_hw_state hw_state;
15bdd4cf
DV		 207 void (*mode_set)(struct drm_i915_private *dev_priv,
208 struct intel_shared_dpll *pll);
e7b903d2
DV		 209 void (*enable)(struct drm_i915_private *dev_priv,
210 struct intel_shared_dpll *pll);
211 void (*disable)(struct drm_i915_private *dev_priv,
212 struct intel_shared_dpll *pll);
5358901f
DV		 213 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
214 struct intel_shared_dpll *pll,
215 struct intel_dpll_hw_state *hw_state);
ee7b9f93 216};
ee7b9f93 217
e69d0bc1
DV		 218/* Used by dp and fdi links */
219struct intel_link_m_n {
220 uint32_t tu;
221 uint32_t gmch_m;
222 uint32_t gmch_n;
223 uint32_t link_m;
224 uint32_t link_n;
225};
226
227void intel_link_compute_m_n(int bpp, int nlanes,
228 int pixel_clock, int link_clock,
229 struct intel_link_m_n *m_n);
230
6441ab5f
PZ		 231struct intel_ddi_plls {
232 int spll_refcount;
233 int wrpll1_refcount;
234 int wrpll2_refcount;
235};
236
1da177e4
LT		 237/* Interface history:
238 *
239 * 1.1: Original.
0d6aa60b
DA		 240 * 1.2: Add Power Management
241 * 1.3: Add vblank support
de227f5f 242 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 243 * 1.5: Add vblank pipe configuration
2228ed67
MCA		 244 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
245 * - Support vertical blank on secondary display pipe
1da177e4
LT		 246 */
247#define DRIVER_MAJOR 1
2228ed67 248#define DRIVER_MINOR 6
1da177e4
LT		 249#define DRIVER_PATCHLEVEL 0
250
23bc5982 251#define WATCH_LISTS 0
42d6ab48 252#define WATCH_GTT 0
673a394b 253
0a3e67a4
JB		 254struct opregion_header;
255struct opregion_acpi;
256struct opregion_swsci;
257struct opregion_asle;
258
8ee1c3db 259struct intel_opregion {
5bc4418b
BW		 260 struct opregion_header __iomem *header;
261 struct opregion_acpi __iomem *acpi;
262 struct opregion_swsci __iomem *swsci;
ebde53c7
JN		 263 u32 swsci_gbda_sub_functions;
264 u32 swsci_sbcb_sub_functions;
5bc4418b
BW		 265 struct opregion_asle __iomem *asle;
266 void __iomem *vbt;
01fe9dbd 267 u32 __iomem *lid_state;
91a60f20 268 struct work_struct asle_work;
8ee1c3db 269};
44834a67 270#define OPREGION_SIZE (8*1024)
8ee1c3db 271
6ef3d427
CW		 272struct intel_overlay;
273struct intel_overlay_error_state;
274
7c1c2871
DA		 275struct drm_i915_master_private {
276 drm_local_map_t *sarea;
277 struct _drm_i915_sarea *sarea_priv;
278};
de151cf6 279#define I915_FENCE_REG_NONE -1
42b5aeab
VS		 280#define I915_MAX_NUM_FENCES 32
281/* 32 fences + sign bit for FENCE_REG_NONE */
282#define I915_MAX_NUM_FENCE_BITS 6
de151cf6
JB		 283
284struct drm_i915_fence_reg {
007cc8ac 285 struct list_head lru_list;
caea7476 286 struct drm_i915_gem_object *obj;
1690e1eb 287 int pin_count;
de151cf6 288};
7c1c2871 289
9b9d172d 290struct sdvo_device_mapping {
e957d772 291 u8 initialized;
9b9d172d 292 u8 dvo_port;
293 u8 slave_addr;
294 u8 dvo_wiring;
e957d772 295 u8 i2c_pin;
b1083333 296 u8 ddc_pin;
9b9d172d 297};
298
c4a1d9e4
CW		 299struct intel_display_error_state;
300
63eeaf38 301struct drm_i915_error_state {
742cbee8 302 struct kref ref;
585b0288
BW		 303 struct timeval time;
304
cb383002 305 char error_msg[128];
48b031e3 306 u32 reset_count;
62d5d69b 307 u32 suspend_count;
cb383002 308
585b0288 309 /* Generic register state */
63eeaf38
JB		 310 u32 eir;
311 u32 pgtbl_er;
be998e2e 312 u32 ier;
b9a3906b 313 u32 ccid;
0f3b6849
CW		 314 u32 derrmr;
315 u32 forcewake;
585b0288
BW		 316 u32 error; /* gen6+ */
317 u32 err_int; /* gen7 */
318 u32 done_reg;
91ec5d11
BW		 319 u32 gac_eco;
320 u32 gam_ecochk;
321 u32 gab_ctl;
322 u32 gfx_mode;
585b0288 323 u32 extra_instdone[I915_NUM_INSTDONE_REG];
585b0288
BW		 324 u64 fence[I915_MAX_NUM_FENCES];
325 struct intel_overlay_error_state *overlay;
326 struct intel_display_error_state *display;
327
52d39a21 328 struct drm_i915_error_ring {
372fbb8e 329 bool valid;
362b8af7
BW		 330 /* Software tracked state */
331 bool waiting;
332 int hangcheck_score;
333 enum intel_ring_hangcheck_action hangcheck_action;
334 int num_requests;
335
336 /* our own tracking of ring head and tail */
337 u32 cpu_ring_head;
338 u32 cpu_ring_tail;
339
340 u32 semaphore_seqno[I915_NUM_RINGS - 1];
341
342 /* Register state */
343 u32 tail;
344 u32 head;
345 u32 ctl;
346 u32 hws;
347 u32 ipeir;
348 u32 ipehr;
349 u32 instdone;
362b8af7
BW		 350 u32 bbstate;
351 u32 instpm;
352 u32 instps;
353 u32 seqno;
354 u64 bbaddr;
50877445 355 u64 acthd;
362b8af7 356 u32 fault_reg;
13ffadd1 357 u64 faddr;
362b8af7
BW		 358 u32 rc_psmi; /* sleep state */
359 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
360
52d39a21
CW		 361 struct drm_i915_error_object {
362 int page_count;
363 u32 gtt_offset;
364 u32 *pages[0];
ab0e7ff9 365 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
362b8af7 366
52d39a21
CW		 367 struct drm_i915_error_request {
368 long jiffies;
369 u32 seqno;
ee4f42b1 370 u32 tail;
52d39a21 371 } *requests;
6c7a01ec
BW		 372
373 struct {
374 u32 gfx_mode;
375 union {
376 u64 pdp[4];
377 u32 pp_dir_base;
378 };
379 } vm_info;
ab0e7ff9
CW		 380
381 pid_t pid;
382 char comm[TASK_COMM_LEN];
52d39a21 383 } ring[I915_NUM_RINGS];
9df30794 384 struct drm_i915_error_buffer {
a779e5ab 385 u32 size;
9df30794 386 u32 name;
0201f1ec 387 u32 rseqno, wseqno;
9df30794
CW		 388 u32 gtt_offset;
389 u32 read_domains;
390 u32 write_domain;
4b9de737 391 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
9df30794
CW		 392 s32 pinned:2;
393 u32 tiling:2;
394 u32 dirty:1;
395 u32 purgeable:1;
5cc9ed4b 396 u32 userptr:1;
5d1333fc 397 s32 ring:4;
f56383cb 398 u32 cache_level:3;
95f5301d 399 } **active_bo, **pinned_bo;
6c7a01ec 400
95f5301d 401 u32 *active_bo_count, *pinned_bo_count;
63eeaf38
JB		 402};
403
7bd688cd 404struct intel_connector;
b8cecdf5 405struct intel_crtc_config;
46f297fb 406struct intel_plane_config;
0e8ffe1b 407struct intel_crtc;
ee9300bb
DV		 408struct intel_limit;
409struct dpll;
b8cecdf5 410
e70236a8 411struct drm_i915_display_funcs {
ee5382ae 412 bool (*fbc_enabled)(struct drm_device *dev);
993495ae 413 void (*enable_fbc)(struct drm_crtc *crtc);
e70236a8
JB		 414 void (*disable_fbc)(struct drm_device *dev);
415 int (*get_display_clock_speed)(struct drm_device *dev);
416 int (*get_fifo_size)(struct drm_device *dev, int plane);
ee9300bb
DV		 417 /**
418 * find_dpll() - Find the best values for the PLL
419 * @limit: limits for the PLL
420 * @crtc: current CRTC
421 * @target: target frequency in kHz
422 * @refclk: reference clock frequency in kHz
423 * @match_clock: if provided, @best_clock P divider must
424 * match the P divider from @match_clock
425 * used for LVDS downclocking
426 * @best_clock: best PLL values found
427 *
428 * Returns true on success, false on failure.
429 */
430 bool (*find_dpll)(const struct intel_limit *limit,
431 struct drm_crtc *crtc,
432 int target, int refclk,
433 struct dpll *match_clock,
434 struct dpll *best_clock);
46ba614c 435 void (*update_wm)(struct drm_crtc *crtc);
adf3d35e
VS		 436 void (*update_sprite_wm)(struct drm_plane *plane,
437 struct drm_crtc *crtc,
4c4ff43a 438 uint32_t sprite_width, int pixel_size,
bdd57d03 439 bool enable, bool scaled);
47fab737 440 void (*modeset_global_resources)(struct drm_device *dev);
0e8ffe1b
DV		 441 /* Returns the active state of the crtc, and if the crtc is active,
442 * fills out the pipe-config with the hw state. */
443 bool (*get_pipe_config)(struct intel_crtc *,
444 struct intel_crtc_config *);
46f297fb
JB		 445 void (*get_plane_config)(struct intel_crtc *,
446 struct intel_plane_config *);
f564048e 447 int (*crtc_mode_set)(struct drm_crtc *crtc,
f564048e
EA		 448 int x, int y,
449 struct drm_framebuffer *old_fb);
76e5a89c
DV		 450 void (*crtc_enable)(struct drm_crtc *crtc);
451 void (*crtc_disable)(struct drm_crtc *crtc);
ee7b9f93 452 void (*off)(struct drm_crtc *crtc);
e0dac65e 453 void (*write_eld)(struct drm_connector *connector,
34427052
JN		 454 struct drm_crtc *crtc,
455 struct drm_display_mode *mode);
674cf967 456 void (*fdi_link_train)(struct drm_crtc *crtc);
6067aaea 457 void (*init_clock_gating)(struct drm_device *dev);
8c9f3aaf
JB		 458 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
459 struct drm_framebuffer *fb,
ed8d1975 460 struct drm_i915_gem_object *obj,
a4872ba6 461 struct intel_engine_cs *ring,
ed8d1975 462 uint32_t flags);
29b9bde6
DV		 463 void (*update_primary_plane)(struct drm_crtc *crtc,
464 struct drm_framebuffer *fb,
465 int x, int y);
20afbda2 466 void (*hpd_irq_setup)(struct drm_device *dev);
e70236a8
JB		 467 /* clock updates for mode set */
468 /* cursor updates */
469 /* render clock increase/decrease */
470 /* display clock increase/decrease */
471 /* pll clock increase/decrease */
7bd688cd
JN		 472
473 int (*setup_backlight)(struct intel_connector *connector);
7bd688cd
JN		 474 uint32_t (*get_backlight)(struct intel_connector *connector);
475 void (*set_backlight)(struct intel_connector *connector,
476 uint32_t level);
477 void (*disable_backlight)(struct intel_connector *connector);
478 void (*enable_backlight)(struct intel_connector *connector);
e70236a8
JB		 479};
480
907b28c5 481struct intel_uncore_funcs {
c8d9a590
D		 482 void (*force_wake_get)(struct drm_i915_private *dev_priv,
483 int fw_engine);
484 void (*force_wake_put)(struct drm_i915_private *dev_priv,
485 int fw_engine);
0b274481
BW		 486
487 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
488 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
489 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
490 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
491
492 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
493 uint8_t val, bool trace);
494 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
495 uint16_t val, bool trace);
496 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
497 uint32_t val, bool trace);
498 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
499 uint64_t val, bool trace);
990bbdad
CW		 500};
501
907b28c5
CW		 502struct intel_uncore {
503 spinlock_t lock; /** lock is also taken in irq contexts. */
504
505 struct intel_uncore_funcs funcs;
506
507 unsigned fifo_count;
508 unsigned forcewake_count;
aec347ab 509
940aece4
D		 510 unsigned fw_rendercount;
511 unsigned fw_mediacount;
512
8232644c 513 struct timer_list force_wake_timer;
907b28c5
CW		 514};
515
79fc46df
DL		 516#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
517 func(is_mobile) sep \
518 func(is_i85x) sep \
519 func(is_i915g) sep \
520 func(is_i945gm) sep \
521 func(is_g33) sep \
522 func(need_gfx_hws) sep \
523 func(is_g4x) sep \
524 func(is_pineview) sep \
525 func(is_broadwater) sep \
526 func(is_crestline) sep \
527 func(is_ivybridge) sep \
528 func(is_valleyview) sep \
529 func(is_haswell) sep \
b833d685 530 func(is_preliminary) sep \
79fc46df
DL		 531 func(has_fbc) sep \
532 func(has_pipe_cxsr) sep \
533 func(has_hotplug) sep \
534 func(cursor_needs_physical) sep \
535 func(has_overlay) sep \
536 func(overlay_needs_physical) sep \
537 func(supports_tv) sep \
dd93be58 538 func(has_llc) sep \
30568c45
DL		 539 func(has_ddi) sep \
540 func(has_fpga_dbg)
c96ea64e 541
a587f779
DL		 542#define DEFINE_FLAG(name) u8 name:1
543#define SEP_SEMICOLON ;
c96ea64e 544
cfdf1fa2 545struct intel_device_info {
10fce67a 546 u32 display_mmio_offset;
7eb552ae 547 u8 num_pipes:3;
d615a166 548 u8 num_sprites[I915_MAX_PIPES];
c96c3a8c 549 u8 gen;
73ae478c 550 u8 ring_mask; /* Rings supported by the HW */
a587f779 551 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
a57c774a
AK		 552 /* Register offsets for the various display pipes and transcoders */
553 int pipe_offsets[I915_MAX_TRANSCODERS];
554 int trans_offsets[I915_MAX_TRANSCODERS];
a57c774a 555 int palette_offsets[I915_MAX_PIPES];
5efb3e28 556 int cursor_offsets[I915_MAX_PIPES];
cfdf1fa2
KH		 557};
558
a587f779
DL		 559#undef DEFINE_FLAG
560#undef SEP_SEMICOLON
561
7faf1ab2
DV		 562enum i915_cache_level {
563 I915_CACHE_NONE = 0,
350ec881
CW		 564 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
565 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
566 caches, eg sampler/render caches, and the
567 large Last-Level-Cache. LLC is coherent with
568 the CPU, but L3 is only visible to the GPU. */
651d794f 569 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
7faf1ab2
DV		 570};
571
e59ec13d
MK		 572struct i915_ctx_hang_stats {
573 /* This context had batch pending when hang was declared */
574 unsigned batch_pending;
575
576 /* This context had batch active when hang was declared */
577 unsigned batch_active;
be62acb4
MK		 578
579 /* Time when this context was last blamed for a GPU reset */
580 unsigned long guilty_ts;
581
582 /* This context is banned to submit more work */
583 bool banned;
e59ec13d 584};
40521054
BW		 585
586/* This must match up with the value previously used for execbuf2.rsvd1. */
587#define DEFAULT_CONTEXT_ID 0
273497e5 588struct intel_context {
dce3271b 589 struct kref ref;
40521054 590 int id;
e0556841 591 bool is_initialized;
3ccfd19d 592 uint8_t remap_slice;
40521054 593 struct drm_i915_file_private *file_priv;
a4872ba6 594 struct intel_engine_cs *last_ring;
40521054 595 struct drm_i915_gem_object *obj;
e59ec13d 596 struct i915_ctx_hang_stats hang_stats;
c7c48dfd 597 struct i915_address_space *vm;
a33afea5
BW		 598
599 struct list_head link;
40521054
BW		 600};
601
5c3fe8b0
BW		 602struct i915_fbc {
603 unsigned long size;
604 unsigned int fb_id;
605 enum plane plane;
606 int y;
607
608 struct drm_mm_node *compressed_fb;
609 struct drm_mm_node *compressed_llb;
610
611 struct intel_fbc_work {
612 struct delayed_work work;
613 struct drm_crtc *crtc;
614 struct drm_framebuffer *fb;
5c3fe8b0
BW		 615 } *fbc_work;
616
29ebf90f
CW		 617 enum no_fbc_reason {
618 FBC_OK, /* FBC is enabled */
619 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
5c3fe8b0
BW		 620 FBC_NO_OUTPUT, /* no outputs enabled to compress */
621 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
622 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
623 FBC_MODE_TOO_LARGE, /* mode too large for compression */
624 FBC_BAD_PLANE, /* fbc not supported on plane */
625 FBC_NOT_TILED, /* buffer not tiled */
626 FBC_MULTIPLE_PIPES, /* more than one pipe active */
627 FBC_MODULE_PARAM,
628 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
629 } no_fbc_reason;
b5e50c3f
JB		 630};
631
439d7ac0
PB		 632struct i915_drrs {
633 struct intel_connector *connector;
634};
635
a031d709
RV		 636struct i915_psr {
637 bool sink_support;
638 bool source_ok;
6118efe5 639 bool setup_done;
3f51e471 640};
5c3fe8b0 641
3bad0781 642enum intel_pch {
f0350830 643 PCH_NONE = 0, /* No PCH present */
3bad0781
ZW		 644 PCH_IBX, /* Ibexpeak PCH */
645 PCH_CPT, /* Cougarpoint PCH */
eb877ebf 646 PCH_LPT, /* Lynxpoint PCH */
40c7ead9 647 PCH_NOP,
3bad0781
ZW		 648};
649
988d6ee8
PZ		 650enum intel_sbi_destination {
651 SBI_ICLK,
652 SBI_MPHY,
653};
654
b690e96c 655#define QUIRK_PIPEA_FORCE (1<<0)
435793df 656#define QUIRK_LVDS_SSC_DISABLE (1<<1)
4dca20ef 657#define QUIRK_INVERT_BRIGHTNESS (1<<2)
b690e96c 658
8be48d92 659struct intel_fbdev;
1630fe75 660struct intel_fbc_work;
38651674 661
c2b9152f
DV		 662struct intel_gmbus {
663 struct i2c_adapter adapter;
f2ce9faf 664 u32 force_bit;
c2b9152f 665 u32 reg0;
36c785f0 666 u32 gpio_reg;
c167a6fc 667 struct i2c_algo_bit_data bit_algo;
c2b9152f
DV		 668 struct drm_i915_private *dev_priv;
669};
670
f4c956ad 671struct i915_suspend_saved_registers {
ba8bbcf6
JB		 672 u8 saveLBB;
673 u32 saveDSPACNTR;
674 u32 saveDSPBCNTR;
e948e994 675 u32 saveDSPARB;
ba8bbcf6
JB		 676 u32 savePIPEACONF;
677 u32 savePIPEBCONF;
678 u32 savePIPEASRC;
679 u32 savePIPEBSRC;
680 u32 saveFPA0;
681 u32 saveFPA1;
682 u32 saveDPLL_A;
683 u32 saveDPLL_A_MD;
684 u32 saveHTOTAL_A;
685 u32 saveHBLANK_A;
686 u32 saveHSYNC_A;
687 u32 saveVTOTAL_A;
688 u32 saveVBLANK_A;
689 u32 saveVSYNC_A;
690 u32 saveBCLRPAT_A;
5586c8bc 691 u32 saveTRANSACONF;
42048781
ZW		 692 u32 saveTRANS_HTOTAL_A;
693 u32 saveTRANS_HBLANK_A;
694 u32 saveTRANS_HSYNC_A;
695 u32 saveTRANS_VTOTAL_A;
696 u32 saveTRANS_VBLANK_A;
697 u32 saveTRANS_VSYNC_A;
0da3ea12 698 u32 savePIPEASTAT;
ba8bbcf6
JB		 699 u32 saveDSPASTRIDE;
700 u32 saveDSPASIZE;
701 u32 saveDSPAPOS;
585fb111 702 u32 saveDSPAADDR;
ba8bbcf6
JB		 703 u32 saveDSPASURF;
704 u32 saveDSPATILEOFF;
705 u32 savePFIT_PGM_RATIOS;
0eb96d6e 706 u32 saveBLC_HIST_CTL;
ba8bbcf6
JB		 707 u32 saveBLC_PWM_CTL;
708 u32 saveBLC_PWM_CTL2;
07bf139b 709 u32 saveBLC_HIST_CTL_B;
42048781
ZW		 710 u32 saveBLC_CPU_PWM_CTL;
711 u32 saveBLC_CPU_PWM_CTL2;
ba8bbcf6
JB		 712 u32 saveFPB0;
713 u32 saveFPB1;
714 u32 saveDPLL_B;
715 u32 saveDPLL_B_MD;
716 u32 saveHTOTAL_B;
717 u32 saveHBLANK_B;
718 u32 saveHSYNC_B;
719 u32 saveVTOTAL_B;
720 u32 saveVBLANK_B;
721 u32 saveVSYNC_B;
722 u32 saveBCLRPAT_B;
5586c8bc 723 u32 saveTRANSBCONF;
42048781
ZW		 724 u32 saveTRANS_HTOTAL_B;
725 u32 saveTRANS_HBLANK_B;
726 u32 saveTRANS_HSYNC_B;
727 u32 saveTRANS_VTOTAL_B;
728 u32 saveTRANS_VBLANK_B;
729 u32 saveTRANS_VSYNC_B;
0da3ea12 730 u32 savePIPEBSTAT;
ba8bbcf6
JB		 731 u32 saveDSPBSTRIDE;
732 u32 saveDSPBSIZE;
733 u32 saveDSPBPOS;
585fb111 734 u32 saveDSPBADDR;
ba8bbcf6
JB		 735 u32 saveDSPBSURF;
736 u32 saveDSPBTILEOFF;
585fb111
JB		 737 u32 saveVGA0;
738 u32 saveVGA1;
739 u32 saveVGA_PD;
ba8bbcf6
JB		 740 u32 saveVGACNTRL;
741 u32 saveADPA;
742 u32 saveLVDS;
585fb111
JB		 743 u32 savePP_ON_DELAYS;
744 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 745 u32 saveDVOA;
746 u32 saveDVOB;
747 u32 saveDVOC;
748 u32 savePP_ON;
749 u32 savePP_OFF;
750 u32 savePP_CONTROL;
585fb111 751 u32 savePP_DIVISOR;
ba8bbcf6
JB		 752 u32 savePFIT_CONTROL;
753 u32 save_palette_a[256];
754 u32 save_palette_b[256];
ba8bbcf6 755 u32 saveFBC_CONTROL;
0da3ea12
JB		 756 u32 saveIER;
757 u32 saveIIR;
758 u32 saveIMR;
42048781
ZW		 759 u32 saveDEIER;
760 u32 saveDEIMR;
761 u32 saveGTIER;
762 u32 saveGTIMR;
763 u32 saveFDI_RXA_IMR;
764 u32 saveFDI_RXB_IMR;
1f84e550 765 u32 saveCACHE_MODE_0;
1f84e550 766 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 767 u32 saveSWF0[16];
768 u32 saveSWF1[16];
769 u32 saveSWF2[3];
770 u8 saveMSR;
771 u8 saveSR[8];
123f794f 772 u8 saveGR[25];
ba8bbcf6 773 u8 saveAR_INDEX;
a59e122a 774 u8 saveAR[21];
ba8bbcf6 775 u8 saveDACMASK;
a59e122a 776 u8 saveCR[37];
4b9de737 777 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1fd1c624
EA		 778 u32 saveCURACNTR;
779 u32 saveCURAPOS;
780 u32 saveCURABASE;
781 u32 saveCURBCNTR;
782 u32 saveCURBPOS;
783 u32 saveCURBBASE;
784 u32 saveCURSIZE;
a4fc5ed6
KP		 785 u32 saveDP_B;
786 u32 saveDP_C;
787 u32 saveDP_D;
788 u32 savePIPEA_GMCH_DATA_M;
789 u32 savePIPEB_GMCH_DATA_M;
790 u32 savePIPEA_GMCH_DATA_N;
791 u32 savePIPEB_GMCH_DATA_N;
792 u32 savePIPEA_DP_LINK_M;
793 u32 savePIPEB_DP_LINK_M;
794 u32 savePIPEA_DP_LINK_N;
795 u32 savePIPEB_DP_LINK_N;
42048781
ZW		 796 u32 saveFDI_RXA_CTL;
797 u32 saveFDI_TXA_CTL;
798 u32 saveFDI_RXB_CTL;
799 u32 saveFDI_TXB_CTL;
800 u32 savePFA_CTL_1;
801 u32 savePFB_CTL_1;
802 u32 savePFA_WIN_SZ;
803 u32 savePFB_WIN_SZ;
804 u32 savePFA_WIN_POS;
805 u32 savePFB_WIN_POS;
5586c8bc
ZW		 806 u32 savePCH_DREF_CONTROL;
807 u32 saveDISP_ARB_CTL;
808 u32 savePIPEA_DATA_M1;
809 u32 savePIPEA_DATA_N1;
810 u32 savePIPEA_LINK_M1;
811 u32 savePIPEA_LINK_N1;
812 u32 savePIPEB_DATA_M1;
813 u32 savePIPEB_DATA_N1;
814 u32 savePIPEB_LINK_M1;
815 u32 savePIPEB_LINK_N1;
b5b72e89 816 u32 saveMCHBAR_RENDER_STANDBY;
cda2bb78 817 u32 savePCH_PORT_HOTPLUG;
f4c956ad 818};
c85aa885 819
ddeea5b0
ID		 820struct vlv_s0ix_state {
821 /* GAM */
822 u32 wr_watermark;
823 u32 gfx_prio_ctrl;
824 u32 arb_mode;
825 u32 gfx_pend_tlb0;
826 u32 gfx_pend_tlb1;
827 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
828 u32 media_max_req_count;
829 u32 gfx_max_req_count;
830 u32 render_hwsp;
831 u32 ecochk;
832 u32 bsd_hwsp;
833 u32 blt_hwsp;
834 u32 tlb_rd_addr;
835
836 /* MBC */
837 u32 g3dctl;
838 u32 gsckgctl;
839 u32 mbctl;
840
841 /* GCP */
842 u32 ucgctl1;
843 u32 ucgctl3;
844 u32 rcgctl1;
845 u32 rcgctl2;
846 u32 rstctl;
847 u32 misccpctl;
848
849 /* GPM */
850 u32 gfxpause;
851 u32 rpdeuhwtc;
852 u32 rpdeuc;
853 u32 ecobus;
854 u32 pwrdwnupctl;
855 u32 rp_down_timeout;
856 u32 rp_deucsw;
857 u32 rcubmabdtmr;
858 u32 rcedata;
859 u32 spare2gh;
860
861 /* Display 1 CZ domain */
862 u32 gt_imr;
863 u32 gt_ier;
864 u32 pm_imr;
865 u32 pm_ier;
866 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
867
868 /* GT SA CZ domain */
869 u32 tilectl;
870 u32 gt_fifoctl;
871 u32 gtlc_wake_ctrl;
872 u32 gtlc_survive;
873 u32 pmwgicz;
874
875 /* Display 2 CZ domain */
876 u32 gu_ctl0;
877 u32 gu_ctl1;
878 u32 clock_gate_dis2;
879};
880
c85aa885 881struct intel_gen6_power_mgmt {
59cdb63d 882 /* work and pm_iir are protected by dev_priv->irq_lock */
c85aa885
DV		 883 struct work_struct work;
884 u32 pm_iir;
59cdb63d 885
b39fb297
BW		 886 /* Frequencies are stored in potentially platform dependent multiples.
887 * In other words, *_freq needs to be multiplied by X to be interesting.
888 * Soft limits are those which are used for the dynamic reclocking done
889 * by the driver (raise frequencies under heavy loads, and lower for
890 * lighter loads). Hard limits are those imposed by the hardware.
891 *
892 * A distinction is made for overclocking, which is never enabled by
893 * default, and is considered to be above the hard limit if it's
894 * possible at all.
895 */
896 u8 cur_freq; /* Current frequency (cached, may not == HW) */
897 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
898 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
899 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
900 u8 min_freq; /* AKA RPn. Minimum frequency */
901 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
902 u8 rp1_freq; /* "less than" RP0 power/freqency */
903 u8 rp0_freq; /* Non-overclocked max frequency. */
1a01ab3b 904
dd75fdc8
CW		 905 int last_adj;
906 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
907
c0951f0c 908 bool enabled;
1a01ab3b 909 struct delayed_work delayed_resume_work;
4fc688ce
JB		 910
911 /*
912 * Protects RPS/RC6 register access and PCU communication.
913 * Must be taken after struct_mutex if nested.
914 */
915 struct mutex hw_lock;
c85aa885
DV		 916};
917
1a240d4d
DV		 918/* defined intel_pm.c */
919extern spinlock_t mchdev_lock;
920
c85aa885
DV		 921struct intel_ilk_power_mgmt {
922 u8 cur_delay;
923 u8 min_delay;
924 u8 max_delay;
925 u8 fmax;
926 u8 fstart;
927
928 u64 last_count1;
929 unsigned long last_time1;
930 unsigned long chipset_power;
931 u64 last_count2;
932 struct timespec last_time2;
933 unsigned long gfx_power;
934 u8 corr;
935
936 int c_m;
937 int r_t;
3e373948
DV		 938
939 struct drm_i915_gem_object *pwrctx;
940 struct drm_i915_gem_object *renderctx;
c85aa885
DV		 941};
942
c6cb582e
ID		 943struct drm_i915_private;
944struct i915_power_well;
945
946struct i915_power_well_ops {
947 /*
948 * Synchronize the well's hw state to match the current sw state, for
949 * example enable/disable it based on the current refcount. Called
950 * during driver init and resume time, possibly after first calling
951 * the enable/disable handlers.
952 */
953 void (*sync_hw)(struct drm_i915_private *dev_priv,
954 struct i915_power_well *power_well);
955 /*
956 * Enable the well and resources that depend on it (for example
957 * interrupts located on the well). Called after the 0->1 refcount
958 * transition.
959 */
960 void (*enable)(struct drm_i915_private *dev_priv,
961 struct i915_power_well *power_well);
962 /*
963 * Disable the well and resources that depend on it. Called after
964 * the 1->0 refcount transition.
965 */
966 void (*disable)(struct drm_i915_private *dev_priv,
967 struct i915_power_well *power_well);
968 /* Returns the hw enabled state. */
969 bool (*is_enabled)(struct drm_i915_private *dev_priv,
970 struct i915_power_well *power_well);
971};
972
a38911a3
WX		 973/* Power well structure for haswell */
974struct i915_power_well {
c1ca727f 975 const char *name;
6f3ef5dd 976 bool always_on;
a38911a3
WX		 977 /* power well enable/disable usage count */
978 int count;
c1ca727f 979 unsigned long domains;
77961eb9 980 unsigned long data;
c6cb582e 981 const struct i915_power_well_ops *ops;
a38911a3
WX		 982};
983
83c00f55 984struct i915_power_domains {
baa70707
ID		 985 /*
986 * Power wells needed for initialization at driver init and suspend
987 * time are on. They are kept on until after the first modeset.
988 */
989 bool init_power_on;
0d116a29 990 bool initializing;
c1ca727f 991 int power_well_count;
baa70707 992
83c00f55 993 struct mutex lock;
1da51581 994 int domain_use_count[POWER_DOMAIN_NUM];
c1ca727f 995 struct i915_power_well *power_wells;
83c00f55
ID		 996};
997
231f42a4
DV		 998struct i915_dri1_state {
999 unsigned allow_batchbuffer : 1;
1000 u32 __iomem *gfx_hws_cpu_addr;
1001
1002 unsigned int cpp;
1003 int back_offset;
1004 int front_offset;
1005 int current_page;
1006 int page_flipping;
1007
1008 uint32_t counter;
1009};
1010
db1b76ca
DV		 1011struct i915_ums_state {
1012 /**
1013 * Flag if the X Server, and thus DRM, is not currently in
1014 * control of the device.
1015 *
1016 * This is set between LeaveVT and EnterVT. It needs to be
1017 * replaced with a semaphore. It also needs to be
1018 * transitioned away from for kernel modesetting.
1019 */
1020 int mm_suspended;
1021};
1022
35a85ac6 1023#define MAX_L3_SLICES 2
a4da4fa4 1024struct intel_l3_parity {
35a85ac6 1025 u32 *remap_info[MAX_L3_SLICES];
a4da4fa4 1026 struct work_struct error_work;
35a85ac6 1027 int which_slice;
a4da4fa4
DV		 1028};
1029
4b5aed62 1030struct i915_gem_mm {
4b5aed62
DV		 1031 /** Memory allocator for GTT stolen memory */
1032 struct drm_mm stolen;
4b5aed62
DV		 1033 /** List of all objects in gtt_space. Used to restore gtt
1034 * mappings on resume */
1035 struct list_head bound_list;
1036 /**
1037 * List of objects which are not bound to the GTT (thus
1038 * are idle and not used by the GPU) but still have
1039 * (presumably uncached) pages still attached.
1040 */
1041 struct list_head unbound_list;
1042
1043 /** Usable portion of the GTT for GEM */
1044 unsigned long stolen_base; /* limited to low memory (32-bit) */
1045
4b5aed62
DV		 1046 /** PPGTT used for aliasing the PPGTT with the GTT */
1047 struct i915_hw_ppgtt *aliasing_ppgtt;
1048
2cfcd32a 1049 struct notifier_block oom_notifier;
ceabbba5 1050 struct shrinker shrinker;
4b5aed62
DV		 1051 bool shrinker_no_lock_stealing;
1052
4b5aed62
DV		 1053 /** LRU list of objects with fence regs on them. */
1054 struct list_head fence_list;
1055
1056 /**
1057 * We leave the user IRQ off as much as possible,
1058 * but this means that requests will finish and never
1059 * be retired once the system goes idle. Set a timer to
1060 * fire periodically while the ring is running. When it
1061 * fires, go retire requests.
1062 */
1063 struct delayed_work retire_work;
1064
b29c19b6
CW		 1065 /**
1066 * When we detect an idle GPU, we want to turn on
1067 * powersaving features. So once we see that there
1068 * are no more requests outstanding and no more
1069 * arrive within a small period of time, we fire
1070 * off the idle_work.
1071 */
1072 struct delayed_work idle_work;
1073
4b5aed62
DV		 1074 /**
1075 * Are we in a non-interruptible section of code like
1076 * modesetting?
1077 */
1078 bool interruptible;
1079
f62a0076
CW		 1080 /**
1081 * Is the GPU currently considered idle, or busy executing userspace
1082 * requests? Whilst idle, we attempt to power down the hardware and
1083 * display clocks. In order to reduce the effect on performance, there
1084 * is a slight delay before we do so.
1085 */
1086 bool busy;
1087
bdf1e7e3
DV		 1088 /* the indicator for dispatch video commands on two BSD rings */
1089 int bsd_ring_dispatch_index;
1090
4b5aed62
DV		 1091 /** Bit 6 swizzling required for X tiling */
1092 uint32_t bit_6_swizzle_x;
1093 /** Bit 6 swizzling required for Y tiling */
1094 uint32_t bit_6_swizzle_y;
1095
4b5aed62 1096 /* accounting, useful for userland debugging */
c20e8355 1097 spinlock_t object_stat_lock;
4b5aed62
DV		 1098 size_t object_memory;
1099 u32 object_count;
1100};
1101
edc3d884
MK		 1102struct drm_i915_error_state_buf {
1103 unsigned bytes;
1104 unsigned size;
1105 int err;
1106 u8 *buf;
1107 loff_t start;
1108 loff_t pos;
1109};
1110
fc16b48b
MK		 1111struct i915_error_state_file_priv {
1112 struct drm_device *dev;
1113 struct drm_i915_error_state *error;
1114};
1115
99584db3
DV		 1116struct i915_gpu_error {
1117 /* For hangcheck timer */
1118#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1119#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
be62acb4
MK		 1120 /* Hang gpu twice in this window and your context gets banned */
1121#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1122
99584db3 1123 struct timer_list hangcheck_timer;
99584db3
DV		 1124
1125 /* For reset and error_state handling. */
1126 spinlock_t lock;
1127 /* Protected by the above dev->gpu_error.lock. */
1128 struct drm_i915_error_state *first_error;
1129 struct work_struct work;
99584db3 1130
094f9a54
CW		 1131
1132 unsigned long missed_irq_rings;
1133
1f83fee0 1134 /**
2ac0f450 1135 * State variable controlling the reset flow and count
1f83fee0 1136 *
2ac0f450
MK		 1137 * This is a counter which gets incremented when reset is triggered,
1138 * and again when reset has been handled. So odd values (lowest bit set)
1139 * means that reset is in progress and even values that
1140 * (reset_counter >> 1):th reset was successfully completed.
1141 *
1142 * If reset is not completed succesfully, the I915_WEDGE bit is
1143 * set meaning that hardware is terminally sour and there is no
1144 * recovery. All waiters on the reset_queue will be woken when
1145 * that happens.
1146 *
1147 * This counter is used by the wait_seqno code to notice that reset
1148 * event happened and it needs to restart the entire ioctl (since most
1149 * likely the seqno it waited for won't ever signal anytime soon).
f69061be
DV		 1150 *
1151 * This is important for lock-free wait paths, where no contended lock
1152 * naturally enforces the correct ordering between the bail-out of the
1153 * waiter and the gpu reset work code.
1f83fee0
DV		 1154 */
1155 atomic_t reset_counter;
1156
1f83fee0 1157#define I915_RESET_IN_PROGRESS_FLAG 1
2ac0f450 1158#define I915_WEDGED (1 << 31)
1f83fee0
DV		 1159
1160 /**
1161 * Waitqueue to signal when the reset has completed. Used by clients
1162 * that wait for dev_priv->mm.wedged to settle.
1163 */
1164 wait_queue_head_t reset_queue;
33196ded 1165
88b4aa87
MK		 1166 /* Userspace knobs for gpu hang simulation;
1167 * combines both a ring mask, and extra flags
1168 */
1169 u32 stop_rings;
1170#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1171#define I915_STOP_RING_ALLOW_WARN (1 << 30)
094f9a54
CW		 1172
1173 /* For missed irq/seqno simulation. */
1174 unsigned int test_irq_rings;
99584db3
DV		 1175};
1176
b8efb17b
ZR		 1177enum modeset_restore {
1178 MODESET_ON_LID_OPEN,
1179 MODESET_DONE,
1180 MODESET_SUSPENDED,
1181};
1182
6acab15a
PZ		 1183struct ddi_vbt_port_info {
1184 uint8_t hdmi_level_shift;
311a2094
PZ		 1185
1186 uint8_t supports_dvi:1;
1187 uint8_t supports_hdmi:1;
1188 uint8_t supports_dp:1;
6acab15a
PZ		 1189};
1190
83a7280e
PB		 1191enum drrs_support_type {
1192 DRRS_NOT_SUPPORTED = 0,
1193 STATIC_DRRS_SUPPORT = 1,
1194 SEAMLESS_DRRS_SUPPORT = 2
1195};
1196
41aa3448
RV		 1197struct intel_vbt_data {
1198 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1199 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1200
1201 /* Feature bits */
1202 unsigned int int_tv_support:1;
1203 unsigned int lvds_dither:1;
1204 unsigned int lvds_vbt:1;
1205 unsigned int int_crt_support:1;
1206 unsigned int lvds_use_ssc:1;
1207 unsigned int display_clock_mode:1;
1208 unsigned int fdi_rx_polarity_inverted:1;
3e6bd011 1209 unsigned int has_mipi:1;
41aa3448
RV		 1210 int lvds_ssc_freq;
1211 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1212
83a7280e
PB		 1213 enum drrs_support_type drrs_type;
1214
41aa3448
RV		 1215 /* eDP */
1216 int edp_rate;
1217 int edp_lanes;
1218 int edp_preemphasis;
1219 int edp_vswing;
1220 bool edp_initialized;
1221 bool edp_support;
1222 int edp_bpp;
1223 struct edp_power_seq edp_pps;
1224
f00076d2
JN		 1225 struct {
1226 u16 pwm_freq_hz;
39fbc9c8 1227 bool present;
f00076d2
JN		 1228 bool active_low_pwm;
1229 } backlight;
1230
d17c5443
SK		 1231 /* MIPI DSI */
1232 struct {
3e6bd011 1233 u16 port;
d17c5443 1234 u16 panel_id;
d3b542fc
SK		 1235 struct mipi_config *config;
1236 struct mipi_pps_data *pps;
1237 u8 seq_version;
1238 u32 size;
1239 u8 *data;
1240 u8 *sequence[MIPI_SEQ_MAX];
d17c5443
SK		 1241 } dsi;
1242
41aa3448
RV		 1243 int crt_ddc_pin;
1244
1245 int child_dev_num;
768f69c9 1246 union child_device_config *child_dev;
6acab15a
PZ		 1247
1248 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
41aa3448
RV		 1249};
1250
77c122bc
VS		 1251enum intel_ddb_partitioning {
1252 INTEL_DDB_PART_1_2,
1253 INTEL_DDB_PART_5_6, /* IVB+ */
1254};
1255
1fd527cc
VS		 1256struct intel_wm_level {
1257 bool enable;
1258 uint32_t pri_val;
1259 uint32_t spr_val;
1260 uint32_t cur_val;
1261 uint32_t fbc_val;
1262};
1263
820c1980 1264struct ilk_wm_values {
609cedef
VS		 1265 uint32_t wm_pipe[3];
1266 uint32_t wm_lp[3];
1267 uint32_t wm_lp_spr[3];
1268 uint32_t wm_linetime[3];
1269 bool enable_fbc_wm;
1270 enum intel_ddb_partitioning partitioning;
1271};
1272
c67a470b 1273/*
765dab67
PZ		 1274 * This struct helps tracking the state needed for runtime PM, which puts the
1275 * device in PCI D3 state. Notice that when this happens, nothing on the
1276 * graphics device works, even register access, so we don't get interrupts nor
1277 * anything else.
c67a470b 1278 *
765dab67
PZ		 1279 * Every piece of our code that needs to actually touch the hardware needs to
1280 * either call intel_runtime_pm_get or call intel_display_power_get with the
1281 * appropriate power domain.
a8a8bd54 1282 *
765dab67
PZ		 1283 * Our driver uses the autosuspend delay feature, which means we'll only really
1284 * suspend if we stay with zero refcount for a certain amount of time. The
1285 * default value is currently very conservative (see intel_init_runtime_pm), but
1286 * it can be changed with the standard runtime PM files from sysfs.
c67a470b
PZ		 1287 *
1288 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1289 * goes back to false exactly before we reenable the IRQs. We use this variable
1290 * to check if someone is trying to enable/disable IRQs while they're supposed
1291 * to be disabled. This shouldn't happen and we'll print some error messages in
730488b2 1292 * case it happens.
c67a470b 1293 *
765dab67 1294 * For more, read the Documentation/power/runtime_pm.txt.
c67a470b 1295 */
5d584b2e
PZ		 1296struct i915_runtime_pm {
1297 bool suspended;
1298 bool irqs_disabled;
c67a470b
PZ		 1299};
1300
926321d5
DV		 1301enum intel_pipe_crc_source {
1302 INTEL_PIPE_CRC_SOURCE_NONE,
1303 INTEL_PIPE_CRC_SOURCE_PLANE1,
1304 INTEL_PIPE_CRC_SOURCE_PLANE2,
1305 INTEL_PIPE_CRC_SOURCE_PF,
5b3a856b 1306 INTEL_PIPE_CRC_SOURCE_PIPE,
3d099a05
DV		 1307 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1308 INTEL_PIPE_CRC_SOURCE_TV,
1309 INTEL_PIPE_CRC_SOURCE_DP_B,
1310 INTEL_PIPE_CRC_SOURCE_DP_C,
1311 INTEL_PIPE_CRC_SOURCE_DP_D,
46a19188 1312 INTEL_PIPE_CRC_SOURCE_AUTO,
926321d5
DV		 1313 INTEL_PIPE_CRC_SOURCE_MAX,
1314};
1315
8bf1e9f1 1316struct intel_pipe_crc_entry {
ac2300d4 1317 uint32_t frame;
8bf1e9f1
SH		 1318 uint32_t crc[5];
1319};
1320
b2c88f5b 1321#define INTEL_PIPE_CRC_ENTRIES_NR 128
8bf1e9f1 1322struct intel_pipe_crc {
d538bbdf
DL		 1323 spinlock_t lock;
1324 bool opened; /* exclusive access to the result file */
e5f75aca 1325 struct intel_pipe_crc_entry *entries;
926321d5 1326 enum intel_pipe_crc_source source;
d538bbdf 1327 int head, tail;
07144428 1328 wait_queue_head_t wq;
8bf1e9f1
SH		 1329};
1330
77fec556 1331struct drm_i915_private {
f4c956ad 1332 struct drm_device *dev;
42dcedd4 1333 struct kmem_cache *slab;
f4c956ad 1334
5c969aa7 1335 const struct intel_device_info info;
f4c956ad
DV		 1336
1337 int relative_constants_mode;
1338
1339 void __iomem *regs;
1340
907b28c5 1341 struct intel_uncore uncore;
f4c956ad
DV		 1342
1343 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1344
28c70f16 1345
f4c956ad
DV		 1346 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1347 * controller on different i2c buses. */
1348 struct mutex gmbus_mutex;
1349
1350 /**
1351 * Base address of the gmbus and gpio block.
1352 */
1353 uint32_t gpio_mmio_base;
1354
b6fdd0f2
SS		 1355 /* MMIO base address for MIPI regs */
1356 uint32_t mipi_mmio_base;
1357
28c70f16
DV		 1358 wait_queue_head_t gmbus_wait_queue;
1359
f4c956ad 1360 struct pci_dev *bridge_dev;
a4872ba6 1361 struct intel_engine_cs ring[I915_NUM_RINGS];
f72b3435 1362 uint32_t last_seqno, next_seqno;
f4c956ad
DV		 1363
1364 drm_dma_handle_t *status_page_dmah;
f4c956ad
DV		 1365 struct resource mch_res;
1366
f4c956ad
DV		 1367 /* protects the irq masks */
1368 spinlock_t irq_lock;
1369
f8b79e58
ID		 1370 bool display_irqs_enabled;
1371
9ee32fea
DV		 1372 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1373 struct pm_qos_request pm_qos;
1374
f4c956ad 1375 /* DPIO indirect register protection */
09153000 1376 struct mutex dpio_lock;
f4c956ad
DV		 1377
1378 /** Cached value of IMR to avoid reads in updating the bitfield */
abd58f01
BW		 1379 union {
1380 u32 irq_mask;
1381 u32 de_irq_mask[I915_MAX_PIPES];
1382 };
f4c956ad 1383 u32 gt_irq_mask;
605cd25b 1384 u32 pm_irq_mask;
a6706b45 1385 u32 pm_rps_events;
91d181dd 1386 u32 pipestat_irq_mask[I915_MAX_PIPES];
f4c956ad 1387
f4c956ad 1388 struct work_struct hotplug_work;
52d7eced 1389 bool enable_hotplug_processing;
b543fb04
EE		 1390 struct {
1391 unsigned long hpd_last_jiffies;
1392 int hpd_cnt;
1393 enum {
1394 HPD_ENABLED = 0,
1395 HPD_DISABLED = 1,
1396 HPD_MARK_DISABLED = 2
1397 } hpd_mark;
1398 } hpd_stats[HPD_NUM_PINS];
142e2398 1399 u32 hpd_event_bits;
ac4c16c5 1400 struct timer_list hotplug_reenable_timer;
f4c956ad 1401
5c3fe8b0 1402 struct i915_fbc fbc;
439d7ac0 1403 struct i915_drrs drrs;
f4c956ad 1404 struct intel_opregion opregion;
41aa3448 1405 struct intel_vbt_data vbt;
f4c956ad
DV		 1406
1407 /* overlay */
1408 struct intel_overlay *overlay;
f4c956ad 1409
58c68779
JN		 1410 /* backlight registers and fields in struct intel_panel */
1411 spinlock_t backlight_lock;
31ad8ec6 1412
f4c956ad 1413 /* LVDS info */
f4c956ad
DV		 1414 bool no_aux_handshake;
1415
f4c956ad
DV		 1416 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1417 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1418 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1419
1420 unsigned int fsb_freq, mem_freq, is_ddr3;
d60c4473 1421 unsigned int vlv_cdclk_freq;
f4c956ad 1422
645416f5
DV		 1423 /**
1424 * wq - Driver workqueue for GEM.
1425 *
1426 * NOTE: Work items scheduled here are not allowed to grab any modeset
1427 * locks, for otherwise the flushing done in the pageflip code will
1428 * result in deadlocks.
1429 */
f4c956ad
DV		 1430 struct workqueue_struct *wq;
1431
1432 /* Display functions */
1433 struct drm_i915_display_funcs display;
1434
1435 /* PCH chipset type */
1436 enum intel_pch pch_type;
17a303ec 1437 unsigned short pch_id;
f4c956ad
DV		 1438
1439 unsigned long quirks;
1440
b8efb17b
ZR		 1441 enum modeset_restore modeset_restore;
1442 struct mutex modeset_restore_lock;
673a394b 1443
a7bbbd63 1444 struct list_head vm_list; /* Global list of all address spaces */
0260c420 1445 struct i915_gtt gtt; /* VM representing the global address space */
5d4545ae 1446
4b5aed62 1447 struct i915_gem_mm mm;
5cc9ed4b
CW		 1448#if defined(CONFIG_MMU_NOTIFIER)
1449 DECLARE_HASHTABLE(mmu_notifiers, 7);
1450#endif
8781342d 1451
8781342d
DV		 1452 /* Kernel Modesetting */
1453
9b9d172d 1454 struct sdvo_device_mapping sdvo_mappings[2];
652c393a 1455
76c4ac04
DL		 1456 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1457 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
6b95a207
KH		 1458 wait_queue_head_t pending_flip_queue;
1459
c4597872
DV		 1460#ifdef CONFIG_DEBUG_FS
1461 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1462#endif
1463
e72f9fbf
DV		 1464 int num_shared_dpll;
1465 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
6441ab5f 1466 struct intel_ddi_plls ddi_plls;
e4607fcf 1467 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
ee7b9f93 1468
652c393a
JB		 1469 /* Reclocking support */
1470 bool render_reclock_avail;
1471 bool lvds_downclock_avail;
18f9ed12
ZY		 1472 /* indicates the reduced downclock for LVDS*/
1473 int lvds_downclock;
652c393a 1474 u16 orig_clock;
f97108d1 1475
c4804411 1476 bool mchbar_need_disable;
f97108d1 1477
a4da4fa4
DV		 1478 struct intel_l3_parity l3_parity;
1479
59124506
BW		 1480 /* Cannot be determined by PCIID. You must always read a register. */
1481 size_t ellc_size;
1482
c6a828d3 1483 /* gen6+ rps state */
c85aa885 1484 struct intel_gen6_power_mgmt rps;
c6a828d3 1485
20e4d407
DV		 1486 /* ilk-only ips/rps state. Everything in here is protected by the global
1487 * mchdev_lock in intel_pm.c */
c85aa885 1488 struct intel_ilk_power_mgmt ips;
b5e50c3f 1489
83c00f55 1490 struct i915_power_domains power_domains;
a38911a3 1491
a031d709 1492 struct i915_psr psr;
3f51e471 1493
99584db3 1494 struct i915_gpu_error gpu_error;
ae681d96 1495
c9cddffc
JB		 1496 struct drm_i915_gem_object *vlv_pctx;
1497
4520f53a 1498#ifdef CONFIG_DRM_I915_FBDEV
8be48d92
DA		 1499 /* list of fbdev register on this device */
1500 struct intel_fbdev *fbdev;
4520f53a 1501#endif
e953fd7b 1502
073f34d9
JB		 1503 /*
1504 * The console may be contended at resume, but we don't
1505 * want it to block on it.
1506 */
1507 struct work_struct console_resume_work;
1508
e953fd7b 1509 struct drm_property *broadcast_rgb_property;
3f43c48d 1510 struct drm_property *force_audio_property;
e3689190 1511
254f965c 1512 uint32_t hw_context_size;
a33afea5 1513 struct list_head context_list;
f4c956ad 1514
3e68320e 1515 u32 fdi_rx_config;
68d18ad7 1516
842f1c8b 1517 u32 suspend_count;
f4c956ad 1518 struct i915_suspend_saved_registers regfile;
ddeea5b0 1519 struct vlv_s0ix_state vlv_s0ix_state;
231f42a4 1520
53615a5e
VS		 1521 struct {
1522 /*
1523 * Raw watermark latency values:
1524 * in 0.1us units for WM0,
1525 * in 0.5us units for WM1+.
1526 */
1527 /* primary */
1528 uint16_t pri_latency[5];
1529 /* sprite */
1530 uint16_t spr_latency[5];
1531 /* cursor */
1532 uint16_t cur_latency[5];
609cedef
VS		 1533
1534 /* current hardware state */
820c1980 1535 struct ilk_wm_values hw;
53615a5e
VS		 1536 } wm;
1537
8a187455
PZ		 1538 struct i915_runtime_pm pm;
1539
231f42a4
DV		 1540 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1541 * here! */
1542 struct i915_dri1_state dri1;
db1b76ca
DV		 1543 /* Old ums support infrastructure, same warning applies. */
1544 struct i915_ums_state ums;
bdf1e7e3
DV		 1545
1546 /*
1547 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1548 * will be rejected. Instead look for a better place.
1549 */
77fec556 1550};
1da177e4 1551
2c1792a1
CW		 1552static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1553{
1554 return dev->dev_private;
1555}
1556
b4519513
CW		 1557/* Iterate over initialised rings */
1558#define for_each_ring(ring__, dev_priv__, i__) \
1559 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1560 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1561
b1d7e4b4
WF		 1562enum hdmi_force_audio {
1563 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1564 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1565 HDMI_AUDIO_AUTO, /* trust EDID */
1566 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1567};
1568
190d6cd5 1569#define I915_GTT_OFFSET_NONE ((u32)-1)
ed2f3452 1570
37e680a1
CW		 1571struct drm_i915_gem_object_ops {
1572 /* Interface between the GEM object and its backing storage.
1573 * get_pages() is called once prior to the use of the associated set
1574 * of pages before to binding them into the GTT, and put_pages() is
1575 * called after we no longer need them. As we expect there to be
1576 * associated cost with migrating pages between the backing storage
1577 * and making them available for the GPU (e.g. clflush), we may hold
1578 * onto the pages after they are no longer referenced by the GPU
1579 * in case they may be used again shortly (for example migrating the
1580 * pages to a different memory domain within the GTT). put_pages()
1581 * will therefore most likely be called when the object itself is
1582 * being released or under memory pressure (where we attempt to
1583 * reap pages for the shrinker).
1584 */
1585 int (*get_pages)(struct drm_i915_gem_object *);
1586 void (*put_pages)(struct drm_i915_gem_object *);
5cc9ed4b
CW		 1587 int (*dmabuf_export)(struct drm_i915_gem_object *);
1588 void (*release)(struct drm_i915_gem_object *);
37e680a1
CW		 1589};
1590
673a394b 1591struct drm_i915_gem_object {
c397b908 1592 struct drm_gem_object base;
673a394b 1593
37e680a1
CW		 1594 const struct drm_i915_gem_object_ops *ops;
1595
2f633156
BW		 1596 /** List of VMAs backed by this object */
1597 struct list_head vma_list;
1598
c1ad11fc
CW		 1599 /** Stolen memory for this object, instead of being backed by shmem. */
1600 struct drm_mm_node *stolen;
35c20a60 1601 struct list_head global_list;
673a394b 1602
69dc4987 1603 struct list_head ring_list;
b25cb2f8
BW		 1604 /** Used in execbuf to temporarily hold a ref */
1605 struct list_head obj_exec_link;
673a394b
EA		 1606
1607 /**
65ce3027
CW		 1608 * This is set if the object is on the active lists (has pending
1609 * rendering and so a non-zero seqno), and is not set if it i s on
1610 * inactive (ready to be unbound) list.
673a394b 1611 */
0206e353 1612 unsigned int active:1;
673a394b
EA		 1613
1614 /**
1615 * This is set if the object has been written to since last bound
1616 * to the GTT
1617 */
0206e353 1618 unsigned int dirty:1;
778c3544
DV		 1619
1620 /**
1621 * Fence register bits (if any) for this object. Will be set
1622 * as needed when mapped into the GTT.
1623 * Protected by dev->struct_mutex.
778c3544 1624 */
4b9de737 1625 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
778c3544 1626
778c3544
DV		 1627 /**
1628 * Advice: are the backing pages purgeable?
1629 */
0206e353 1630 unsigned int madv:2;
778c3544 1631
778c3544
DV		 1632 /**
1633 * Current tiling mode for the object.
1634 */
0206e353 1635 unsigned int tiling_mode:2;
5d82e3e6
CW		 1636 /**
1637 * Whether the tiling parameters for the currently associated fence
1638 * register have changed. Note that for the purposes of tracking
1639 * tiling changes we also treat the unfenced register, the register
1640 * slot that the object occupies whilst it executes a fenced
1641 * command (such as BLT on gen2/3), as a "fence".
1642 */
1643 unsigned int fence_dirty:1;
778c3544 1644
75e9e915
DV		 1645 /**
1646 * Is the object at the current location in the gtt mappable and
1647 * fenceable? Used to avoid costly recalculations.
1648 */
0206e353 1649 unsigned int map_and_fenceable:1;
75e9e915 1650
fb7d516a
DV		 1651 /**
1652 * Whether the current gtt mapping needs to be mappable (and isn't just
1653 * mappable by accident). Track pin and fault separate for a more
1654 * accurate mappable working set.
1655 */
0206e353
AJ		 1656 unsigned int fault_mappable:1;
1657 unsigned int pin_mappable:1;
cc98b413 1658 unsigned int pin_display:1;
fb7d516a 1659
caea7476
CW		 1660 /*
1661 * Is the GPU currently using a fence to access this buffer,
1662 */
1663 unsigned int pending_fenced_gpu_access:1;
1664 unsigned int fenced_gpu_access:1;
1665
651d794f 1666 unsigned int cache_level:3;
93dfb40c 1667
7bddb01f 1668 unsigned int has_aliasing_ppgtt_mapping:1;
74898d7e 1669 unsigned int has_global_gtt_mapping:1;
9da3da66 1670 unsigned int has_dma_mapping:1;
7bddb01f 1671
9da3da66 1672 struct sg_table *pages;
a5570178 1673 int pages_pin_count;
673a394b 1674
1286ff73 1675 /* prime dma-buf support */
9a70cc2a
DA		 1676 void *dma_buf_vmapping;
1677 int vmapping_count;
1678
a4872ba6 1679 struct intel_engine_cs *ring;
caea7476 1680
1c293ea3 1681 /** Breadcrumb of last rendering to the buffer. */
0201f1ec
CW		 1682 uint32_t last_read_seqno;
1683 uint32_t last_write_seqno;
caea7476
CW		 1684 /** Breadcrumb of last fenced GPU access to the buffer. */
1685 uint32_t last_fenced_seqno;
673a394b 1686
778c3544 1687 /** Current tiling stride for the object, if it's tiled. */
de151cf6 1688 uint32_t stride;
673a394b 1689
80075d49
DV		 1690 /** References from framebuffers, locks out tiling changes. */
1691 unsigned long framebuffer_references;
1692
280b713b 1693 /** Record of address bit 17 of each page at last unbind. */
d312ec25 1694 unsigned long *bit_17;
280b713b 1695
79e53945 1696 /** User space pin count and filp owning the pin */
aa5f8021 1697 unsigned long user_pin_count;
79e53945 1698 struct drm_file *pin_filp;
71acb5eb
DA		 1699
1700 /** for phy allocated objects */
00731155 1701 drm_dma_handle_t *phys_handle;
673a394b 1702
5cc9ed4b
CW		 1703 union {
1704 struct i915_gem_userptr {
1705 uintptr_t ptr;
1706 unsigned read_only :1;
1707 unsigned workers :4;
1708#define I915_GEM_USERPTR_MAX_WORKERS 15
1709
1710 struct mm_struct *mm;
1711 struct i915_mmu_object *mn;
1712 struct work_struct *work;
1713 } userptr;
1714 };
1715};
62b8b215 1716#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
23010e43 1717
673a394b
EA		 1718/**
1719 * Request queue structure.
1720 *
1721 * The request queue allows us to note sequence numbers that have been emitted
1722 * and may be associated with active buffers to be retired.
1723 *
1724 * By keeping this list, we can avoid having to do questionable
1725 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1726 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1727 */
1728struct drm_i915_gem_request {
852835f3 1729 /** On Which ring this request was generated */
a4872ba6 1730 struct intel_engine_cs *ring;
852835f3 1731
673a394b
EA		 1732 /** GEM sequence number associated with this request. */
1733 uint32_t seqno;
1734
7d736f4f
MK		 1735 /** Position in the ringbuffer of the start of the request */
1736 u32 head;
1737
1738 /** Position in the ringbuffer of the end of the request */
a71d8d94
CW		 1739 u32 tail;
1740
0e50e96b 1741 /** Context related to this request */
273497e5 1742 struct intel_context *ctx;
0e50e96b 1743
7d736f4f
MK		 1744 /** Batch buffer related to this request if any */
1745 struct drm_i915_gem_object *batch_obj;
1746
673a394b
EA		 1747 /** Time at which this request was emitted, in jiffies. */
1748 unsigned long emitted_jiffies;
1749
b962442e 1750 /** global list entry for this request */
673a394b 1751 struct list_head list;
b962442e 1752
f787a5f5 1753 struct drm_i915_file_private *file_priv;
b962442e
EA		 1754 /** file_priv list entry for this request */
1755 struct list_head client_list;
673a394b
EA		 1756};
1757
1758struct drm_i915_file_private {
b29c19b6 1759 struct drm_i915_private *dev_priv;
ab0e7ff9 1760 struct drm_file *file;
b29c19b6 1761
673a394b 1762 struct {
99057c81 1763 spinlock_t lock;
b962442e 1764 struct list_head request_list;
b29c19b6 1765 struct delayed_work idle_work;
673a394b 1766 } mm;
40521054 1767 struct idr context_idr;
e59ec13d 1768
b29c19b6 1769 atomic_t rps_wait_boost;
a4872ba6 1770 struct intel_engine_cs *bsd_ring;
673a394b
EA		 1771};
1772
351e3db2
BV		 1773/*
1774 * A command that requires special handling by the command parser.
1775 */
1776struct drm_i915_cmd_descriptor {
1777 /*
1778 * Flags describing how the command parser processes the command.
1779 *
1780 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1781 * a length mask if not set
1782 * CMD_DESC_SKIP: The command is allowed but does not follow the
1783 * standard length encoding for the opcode range in
1784 * which it falls
1785 * CMD_DESC_REJECT: The command is never allowed
1786 * CMD_DESC_REGISTER: The command should be checked against the
1787 * register whitelist for the appropriate ring
1788 * CMD_DESC_MASTER: The command is allowed if the submitting process
1789 * is the DRM master
1790 */
1791 u32 flags;
1792#define CMD_DESC_FIXED (1<<0)
1793#define CMD_DESC_SKIP (1<<1)
1794#define CMD_DESC_REJECT (1<<2)
1795#define CMD_DESC_REGISTER (1<<3)
1796#define CMD_DESC_BITMASK (1<<4)
1797#define CMD_DESC_MASTER (1<<5)
1798
1799 /*
1800 * The command's unique identification bits and the bitmask to get them.
1801 * This isn't strictly the opcode field as defined in the spec and may
1802 * also include type, subtype, and/or subop fields.
1803 */
1804 struct {
1805 u32 value;
1806 u32 mask;
1807 } cmd;
1808
1809 /*
1810 * The command's length. The command is either fixed length (i.e. does
1811 * not include a length field) or has a length field mask. The flag
1812 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1813 * a length mask. All command entries in a command table must include
1814 * length information.
1815 */
1816 union {
1817 u32 fixed;
1818 u32 mask;
1819 } length;
1820
1821 /*
1822 * Describes where to find a register address in the command to check
1823 * against the ring's register whitelist. Only valid if flags has the
1824 * CMD_DESC_REGISTER bit set.
1825 */
1826 struct {
1827 u32 offset;
1828 u32 mask;
1829 } reg;
1830
1831#define MAX_CMD_DESC_BITMASKS 3
1832 /*
1833 * Describes command checks where a particular dword is masked and
1834 * compared against an expected value. If the command does not match
1835 * the expected value, the parser rejects it. Only valid if flags has
1836 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1837 * are valid.
d4d48035
BV		 1838 *
1839 * If the check specifies a non-zero condition_mask then the parser
1840 * only performs the check when the bits specified by condition_mask
1841 * are non-zero.
351e3db2
BV		 1842 */
1843 struct {
1844 u32 offset;
1845 u32 mask;
1846 u32 expected;
d4d48035
BV		 1847 u32 condition_offset;
1848 u32 condition_mask;
351e3db2
BV		 1849 } bits[MAX_CMD_DESC_BITMASKS];
1850};
1851
1852/*
1853 * A table of commands requiring special handling by the command parser.
1854 *
1855 * Each ring has an array of tables. Each table consists of an array of command
1856 * descriptors, which must be sorted with command opcodes in ascending order.
1857 */
1858struct drm_i915_cmd_table {
1859 const struct drm_i915_cmd_descriptor *table;
1860 int count;
1861};
1862
5c969aa7 1863#define INTEL_INFO(dev) (&to_i915(dev)->info)
cae5852d 1864
ffbab09b
VS		 1865#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1866#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
cae5852d 1867#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
ffbab09b 1868#define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
cae5852d 1869#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
ffbab09b
VS		 1870#define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1871#define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
cae5852d
ZN		 1872#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1873#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1874#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
ffbab09b 1875#define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
cae5852d 1876#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
ffbab09b
VS		 1877#define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1878#define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
cae5852d
ZN		 1879#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1880#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
ffbab09b 1881#define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
4b65177b 1882#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
ffbab09b
VS		 1883#define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1884 (dev)->pdev->device == 0x0152 || \
1885 (dev)->pdev->device == 0x015a)
1886#define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1887 (dev)->pdev->device == 0x0106 || \
1888 (dev)->pdev->device == 0x010A)
70a3eb7a 1889#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
6df4027b 1890#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
4cae9ae0 1891#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
8179f1f0 1892#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
cae5852d 1893#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
ed1c9e2c 1894#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
ffbab09b 1895 ((dev)->pdev->device & 0xFF00) == 0x0C00)
5dd8c4c3
BW		 1896#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1897 (((dev)->pdev->device & 0xf) == 0x2 || \
1898 ((dev)->pdev->device & 0xf) == 0x6 || \
1899 ((dev)->pdev->device & 0xf) == 0xe))
1900#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
ffbab09b 1901 ((dev)->pdev->device & 0xFF00) == 0x0A00)
5dd8c4c3 1902#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
9435373e 1903#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
ffbab09b 1904 ((dev)->pdev->device & 0x00F0) == 0x0020)
9bbfd20a
PZ		 1905/* ULX machines are also considered ULT. */
1906#define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
1907 (dev)->pdev->device == 0x0A1E)
b833d685 1908#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
cae5852d 1909
85436696
JB		 1910/*
1911 * The genX designation typically refers to the render engine, so render
1912 * capability related checks should use IS_GEN, while display and other checks
1913 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1914 * chips, etc.).
1915 */
cae5852d
ZN		 1916#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1917#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1918#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1919#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1920#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
85436696 1921#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
d2980845 1922#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
cae5852d 1923
73ae478c
BW		 1924#define RENDER_RING (1<<RCS)
1925#define BSD_RING (1<<VCS)
1926#define BLT_RING (1<<BCS)
1927#define VEBOX_RING (1<<VECS)
845f74a7 1928#define BSD2_RING (1<<VCS2)
63c42e56 1929#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
845f74a7 1930#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
63c42e56
BW		 1931#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1932#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1933#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1934#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
1935 to_i915(dev)->ellc_size)
cae5852d
ZN		 1936#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1937
254f965c 1938#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
7365fb78
JB		 1939#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
1940#define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
c5dc5cec 1941#define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
7e0d96bc 1942#define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1d2a314c 1943
05394f39 1944#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
cae5852d
ZN		 1945#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1946
b45305fc
DV		 1947/* Early gen2 have a totally busted CS tlb and require pinned batches. */
1948#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
4e6b788c
DV		 1949/*
1950 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1951 * even when in MSI mode. This results in spurious interrupt warnings if the
1952 * legacy irq no. is shared with another device. The kernel then disables that
1953 * interrupt source and so prevents the other device from working properly.
1954 */
1955#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1956#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
b45305fc 1957
cae5852d
ZN		 1958/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1959 * rows, which changed the alignment requirements and fence programming.
1960 */
1961#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1962 IS_I915GM(dev)))
1963#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1964#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1965#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
cae5852d
ZN		 1966#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1967#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
cae5852d
ZN		 1968
1969#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1970#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
3a77c4c4 1971#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
cae5852d 1972
2a114cc1 1973#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
f5adf94e 1974
dd93be58 1975#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
30568c45 1976#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
ed8546ac 1977#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
6157d3c8 1978#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
fd7f8cce 1979 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
affa9354 1980
17a303ec
PZ		 1981#define INTEL_PCH_DEVICE_ID_MASK 0xff00
1982#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1983#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1984#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1985#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1986#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1987
2c1792a1 1988#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
eb877ebf 1989#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
cae5852d
ZN		 1990#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1991#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
40c7ead9 1992#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
45e6e3a1 1993#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
cae5852d 1994
040d2baa
BW		 1995/* DPF == dynamic parity feature */
1996#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1997#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
e1ef7cc2 1998
c8735b0c
BW		 1999#define GT_FREQUENCY_MULTIPLIER 50
2000
05394f39
CW		 2001#include "i915_trace.h"
2002
baa70943 2003extern const struct drm_ioctl_desc i915_ioctls[];
b3a83639
DA		 2004extern int i915_max_ioctl;
2005
6a9ee8af
DA		 2006extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2007extern int i915_resume(struct drm_device *dev);
7c1c2871
DA		 2008extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2009extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2010
d330a953
JN		 2011/* i915_params.c */
2012struct i915_params {
2013 int modeset;
2014 int panel_ignore_lid;
2015 unsigned int powersave;
2016 int semaphores;
2017 unsigned int lvds_downclock;
2018 int lvds_channel_mode;
2019 int panel_use_ssc;
2020 int vbt_sdvo_panel_type;
2021 int enable_rc6;
2022 int enable_fbc;
d330a953
JN		 2023 int enable_ppgtt;
2024 int enable_psr;
2025 unsigned int preliminary_hw_support;
2026 int disable_power_well;
2027 int enable_ips;
e5aa6541 2028 int invert_brightness;
351e3db2 2029 int enable_cmd_parser;
e5aa6541
DL		 2030 /* leave bools at the end to not create holes */
2031 bool enable_hangcheck;
2032 bool fastboot;
d330a953
JN		 2033 bool prefault_disable;
2034 bool reset;
a0bae57f 2035 bool disable_display;
7a10dfa6 2036 bool disable_vtd_wa;
d330a953
JN		 2037};
2038extern struct i915_params i915 __read_mostly;
2039
1da177e4 2040 /* i915_dma.c */
d05c617e 2041void i915_update_dri1_breadcrumb(struct drm_device *dev);
84b1fd10 2042extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 2043extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 2044extern int i915_driver_unload(struct drm_device *);
673a394b 2045extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
84b1fd10 2046extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac
EA		 2047extern void i915_driver_preclose(struct drm_device *dev,
2048 struct drm_file *file_priv);
673a394b
EA		 2049extern void i915_driver_postclose(struct drm_device *dev,
2050 struct drm_file *file_priv);
84b1fd10 2051extern int i915_driver_device_is_agp(struct drm_device * dev);
c43b5634 2052#ifdef CONFIG_COMPAT
0d6aa60b
DA		 2053extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2054 unsigned long arg);
c43b5634 2055#endif
673a394b 2056extern int i915_emit_box(struct drm_device *dev,
c4e7a414
CW		 2057 struct drm_clip_rect *box,
2058 int DR1, int DR4);
8e96d9c4 2059extern int intel_gpu_reset(struct drm_device *dev);
d4b8bb2a 2060extern int i915_reset(struct drm_device *dev);
7648fa99
JB		 2061extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2062extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2063extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2064extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
650ad970 2065int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
7648fa99 2066
073f34d9 2067extern void intel_console_resume(struct work_struct *work);
af6061af 2068
1da177e4 2069/* i915_irq.c */
10cd45b6 2070void i915_queue_hangcheck(struct drm_device *dev);
58174462
MK		 2071__printf(3, 4)
2072void i915_handle_error(struct drm_device *dev, bool wedged,
2073 const char *fmt, ...);
1da177e4 2074
76c3552f
D		 2075void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2076 int new_delay);
f71d4af4 2077extern void intel_irq_init(struct drm_device *dev);
20afbda2 2078extern void intel_hpd_init(struct drm_device *dev);
907b28c5
CW		 2079
2080extern void intel_uncore_sanitize(struct drm_device *dev);
2081extern void intel_uncore_early_sanitize(struct drm_device *dev);
2082extern void intel_uncore_init(struct drm_device *dev);
907b28c5 2083extern void intel_uncore_check_errors(struct drm_device *dev);
aec347ab 2084extern void intel_uncore_fini(struct drm_device *dev);
b1f14ad0 2085
7c463586 2086void
50227e1c 2087i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2088 u32 status_mask);
7c463586
KP		 2089
2090void
50227e1c 2091i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
755e9019 2092 u32 status_mask);
7c463586 2093
f8b79e58
ID		 2094void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2095void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2096
673a394b
EA		 2097/* i915_gem.c */
2098int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2099 struct drm_file *file_priv);
2100int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *file_priv);
2102int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *file_priv);
2104int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
de151cf6
JB		 2108int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv);
673a394b
EA		 2110int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *file_priv);
2112int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *file_priv);
2114int i915_gem_execbuffer(struct drm_device *dev, void *data,
2115 struct drm_file *file_priv);
76446cac
JB		 2116int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2117 struct drm_file *file_priv);
673a394b
EA		 2118int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *file_priv);
2120int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *file_priv);
2122int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *file_priv);
199adf40
BW		 2124int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2125 struct drm_file *file);
2126int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2127 struct drm_file *file);
673a394b
EA		 2128int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *file_priv);
3ef94daa
CW		 2130int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2131 struct drm_file *file_priv);
673a394b
EA		 2132int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2133 struct drm_file *file_priv);
2134int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2135 struct drm_file *file_priv);
2136int i915_gem_set_tiling(struct drm_device *dev, void *data,
2137 struct drm_file *file_priv);
2138int i915_gem_get_tiling(struct drm_device *dev, void *data,
2139 struct drm_file *file_priv);
5cc9ed4b
CW		 2140int i915_gem_init_userptr(struct drm_device *dev);
2141int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2142 struct drm_file *file);
5a125c3c
EA		 2143int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2144 struct drm_file *file_priv);
23ba4fd0
BW		 2145int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2146 struct drm_file *file_priv);
673a394b 2147void i915_gem_load(struct drm_device *dev);
42dcedd4
CW		 2148void *i915_gem_object_alloc(struct drm_device *dev);
2149void i915_gem_object_free(struct drm_i915_gem_object *obj);
37e680a1
CW		 2150void i915_gem_object_init(struct drm_i915_gem_object *obj,
2151 const struct drm_i915_gem_object_ops *ops);
05394f39
CW		 2152struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2153 size_t size);
7e0d96bc
BW		 2154void i915_init_vm(struct drm_i915_private *dev_priv,
2155 struct i915_address_space *vm);
673a394b 2156void i915_gem_free_object(struct drm_gem_object *obj);
2f633156 2157void i915_gem_vma_destroy(struct i915_vma *vma);
42dcedd4 2158
1ec9e26d
DV		 2159#define PIN_MAPPABLE 0x1
2160#define PIN_NONBLOCK 0x2
bf3d149b 2161#define PIN_GLOBAL 0x4
d23db88c
CW		 2162#define PIN_OFFSET_BIAS 0x8
2163#define PIN_OFFSET_MASK (~4095)
2021746e 2164int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
c37e2204 2165 struct i915_address_space *vm,
2021746e 2166 uint32_t alignment,
d23db88c 2167 uint64_t flags);
07fe0b12 2168int __must_check i915_vma_unbind(struct i915_vma *vma);
dd624afd 2169int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
48018a57 2170void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
05394f39 2171void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
673a394b 2172void i915_gem_lastclose(struct drm_device *dev);
f787a5f5 2173
4c914c0c
BV		 2174int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2175 int *needs_clflush);
2176
37e680a1 2177int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
9da3da66
CW		 2178static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2179{
67d5a50c
ID		 2180 struct sg_page_iter sg_iter;
2181
2182 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2db76d7c 2183 return sg_page_iter_page(&sg_iter);
67d5a50c
ID		 2184
2185 return NULL;
9da3da66 2186}
a5570178
CW		 2187static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2188{
2189 BUG_ON(obj->pages == NULL);
2190 obj->pages_pin_count++;
2191}
2192static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2193{
2194 BUG_ON(obj->pages_pin_count == 0);
2195 obj->pages_pin_count--;
2196}
2197
54cf91dc 2198int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2911a35b 2199int i915_gem_object_sync(struct drm_i915_gem_object *obj,
a4872ba6 2200 struct intel_engine_cs *to);
e2d05a8b 2201void i915_vma_move_to_active(struct i915_vma *vma,
a4872ba6 2202 struct intel_engine_cs *ring);
ff72145b
DA		 2203int i915_gem_dumb_create(struct drm_file *file_priv,
2204 struct drm_device *dev,
2205 struct drm_mode_create_dumb *args);
2206int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2207 uint32_t handle, uint64_t *offset);
f787a5f5
CW		 2208/**
2209 * Returns true if seq1 is later than seq2.
2210 */
2211static inline bool
2212i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2213{
2214 return (int32_t)(seq1 - seq2) >= 0;
2215}
2216
fca26bb4
MK		 2217int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2218int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
06d98131 2219int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
d9e86c0e 2220int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2021746e 2221
d8ffa60b
DV		 2222bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2223void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
1690e1eb 2224
8d9fc7fd 2225struct drm_i915_gem_request *
a4872ba6 2226i915_gem_find_active_request(struct intel_engine_cs *ring);
8d9fc7fd 2227
b29c19b6 2228bool i915_gem_retire_requests(struct drm_device *dev);
a4872ba6 2229void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
33196ded 2230int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
d6b2c790 2231 bool interruptible);
1f83fee0
DV		 2232static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2233{
2234 return unlikely(atomic_read(&error->reset_counter)
2ac0f450 2235 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
1f83fee0
DV		 2236}
2237
2238static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2239{
2ac0f450
MK		 2240 return atomic_read(&error->reset_counter) & I915_WEDGED;
2241}
2242
2243static inline u32 i915_reset_count(struct i915_gpu_error *error)
2244{
2245 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
1f83fee0 2246}
a71d8d94 2247
88b4aa87
MK		 2248static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2249{
2250 return dev_priv->gpu_error.stop_rings == 0 ||
2251 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2252}
2253
2254static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2255{
2256 return dev_priv->gpu_error.stop_rings == 0 ||
2257 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2258}
2259
069efc1d 2260void i915_gem_reset(struct drm_device *dev);
000433b6 2261bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
a8198eea 2262int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1070a42b 2263int __must_check i915_gem_init(struct drm_device *dev);
f691e2f4 2264int __must_check i915_gem_init_hw(struct drm_device *dev);
a4872ba6 2265int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
f691e2f4 2266void i915_gem_init_swizzling(struct drm_device *dev);
79e53945 2267void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
b2da9fe5 2268int __must_check i915_gpu_idle(struct drm_device *dev);
45c5f202 2269int __must_check i915_gem_suspend(struct drm_device *dev);
a4872ba6 2270int __i915_add_request(struct intel_engine_cs *ring,
0025c077 2271 struct drm_file *file,
7d736f4f 2272 struct drm_i915_gem_object *batch_obj,
0025c077
MK		 2273 u32 *seqno);
2274#define i915_add_request(ring, seqno) \
854c94a7 2275 __i915_add_request(ring, NULL, NULL, seqno)
a4872ba6 2276int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
199b2bc2 2277 uint32_t seqno);
de151cf6 2278int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2021746e
CW		 2279int __must_check
2280i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2281 bool write);
2282int __must_check
dabdfe02
CW		 2283i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2284int __must_check
2da3b9b9
CW		 2285i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2286 u32 alignment,
a4872ba6 2287 struct intel_engine_cs *pipelined);
cc98b413 2288void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
00731155 2289int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
6eeefaf3 2290 int align);
b29c19b6 2291int i915_gem_open(struct drm_device *dev, struct drm_file *file);
05394f39 2292void i915_gem_release(struct drm_device *dev, struct drm_file *file);
673a394b 2293
0fa87796
ID		 2294uint32_t
2295i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
467cffba 2296uint32_t
d865110c
ID		 2297i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2298 int tiling_mode, bool fenced);
467cffba 2299
e4ffd173
CW		 2300int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2301 enum i915_cache_level cache_level);
2302
1286ff73
DV		 2303struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2304 struct dma_buf *dma_buf);
2305
2306struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2307 struct drm_gem_object *gem_obj, int flags);
2308
19b2dbde
CW		 2309void i915_gem_restore_fences(struct drm_device *dev);
2310
a70a3148
BW		 2311unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2312 struct i915_address_space *vm);
2313bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2314bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2315 struct i915_address_space *vm);
2316unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2317 struct i915_address_space *vm);
2318struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2319 struct i915_address_space *vm);
accfef2e
BW		 2320struct i915_vma *
2321i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2322 struct i915_address_space *vm);
5c2abbea
BW		 2323
2324struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
d7f46fc4
BW		 2325static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2326 struct i915_vma *vma;
2327 list_for_each_entry(vma, &obj->vma_list, vma_link)
2328 if (vma->pin_count > 0)
2329 return true;
2330 return false;
2331}
5c2abbea 2332
a70a3148
BW		 2333/* Some GGTT VM helpers */
2334#define obj_to_ggtt(obj) \
2335 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2336static inline bool i915_is_ggtt(struct i915_address_space *vm)
2337{
2338 struct i915_address_space *ggtt =
2339 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2340 return vm == ggtt;
2341}
2342
2343static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2344{
2345 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2346}
2347
2348static inline unsigned long
2349i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2350{
2351 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2352}
2353
2354static inline unsigned long
2355i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2356{
2357 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2358}
c37e2204
BW		 2359
2360static inline int __must_check
2361i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2362 uint32_t alignment,
1ec9e26d 2363 unsigned flags)
c37e2204 2364{
bf3d149b 2365 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
c37e2204 2366}
a70a3148 2367
b287110e
DV		 2368static inline int
2369i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2370{
2371 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2372}
2373
2374void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2375
254f965c 2376/* i915_gem_context.c */
0eea67eb 2377#define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
8245be31 2378int __must_check i915_gem_context_init(struct drm_device *dev);
254f965c 2379void i915_gem_context_fini(struct drm_device *dev);
acce9ffa 2380void i915_gem_context_reset(struct drm_device *dev);
e422b888 2381int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2fa48d8d 2382int i915_gem_context_enable(struct drm_i915_private *dev_priv);
254f965c 2383void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
a4872ba6 2384int i915_switch_context(struct intel_engine_cs *ring,
273497e5
OM		 2385 struct intel_context *to);
2386struct intel_context *
41bde553 2387i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
dce3271b 2388void i915_gem_context_free(struct kref *ctx_ref);
273497e5 2389static inline void i915_gem_context_reference(struct intel_context *ctx)
dce3271b 2390{
691e6415 2391 kref_get(&ctx->ref);
dce3271b
MK		 2392}
2393
273497e5 2394static inline void i915_gem_context_unreference(struct intel_context *ctx)
dce3271b 2395{
691e6415 2396 kref_put(&ctx->ref, i915_gem_context_free);
dce3271b
MK		 2397}
2398
273497e5 2399static inline bool i915_gem_context_is_default(const struct intel_context *c)
3fac8978
MK		 2400{
2401 return c->id == DEFAULT_CONTEXT_ID;
2402}
2403
84624813
BW		 2404int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2405 struct drm_file *file);
2406int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2407 struct drm_file *file);
1286ff73 2408
9d0a6fa6 2409/* i915_gem_render_state.c */
a4872ba6 2410int i915_gem_render_state_init(struct intel_engine_cs *ring);
679845ed
BW		 2411/* i915_gem_evict.c */
2412int __must_check i915_gem_evict_something(struct drm_device *dev,
2413 struct i915_address_space *vm,
2414 int min_size,
2415 unsigned alignment,
2416 unsigned cache_level,
d23db88c
CW		 2417 unsigned long start,
2418 unsigned long end,
1ec9e26d 2419 unsigned flags);
679845ed
BW		 2420int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2421int i915_gem_evict_everything(struct drm_device *dev);
1d2a314c 2422
0260c420 2423/* belongs in i915_gem_gtt.h */
d09105c6 2424static inline void i915_gem_chipset_flush(struct drm_device *dev)
e76e9aeb
BW		 2425{
2426 if (INTEL_INFO(dev)->gen < 6)
2427 intel_gtt_chipset_flush();
2428}
246cbfb5 2429
9797fbfb
CW		 2430/* i915_gem_stolen.c */
2431int i915_gem_init_stolen(struct drm_device *dev);
11be49eb
CW		 2432int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2433void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
9797fbfb 2434void i915_gem_cleanup_stolen(struct drm_device *dev);
0104fdbb
CW		 2435struct drm_i915_gem_object *
2436i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
866d12b4
CW		 2437struct drm_i915_gem_object *
2438i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2439 u32 stolen_offset,
2440 u32 gtt_offset,
2441 u32 size);
9797fbfb 2442
673a394b 2443/* i915_gem_tiling.c */
2c1792a1 2444static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
e9b73c67 2445{
50227e1c 2446 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
e9b73c67
CW		 2447
2448 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2449 obj->tiling_mode != I915_TILING_NONE;
2450}
2451
673a394b 2452void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
05394f39
CW		 2453void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2454void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
673a394b
EA		 2455
2456/* i915_gem_debug.c */
23bc5982
CW		 2457#if WATCH_LISTS
2458int i915_verify_lists(struct drm_device *dev);
673a394b 2459#else
23bc5982 2460#define i915_verify_lists(dev) 0
673a394b 2461#endif
1da177e4 2462
2017263e 2463/* i915_debugfs.c */
27c202ad
BG		 2464int i915_debugfs_init(struct drm_minor *minor);
2465void i915_debugfs_cleanup(struct drm_minor *minor);
f8c168fa 2466#ifdef CONFIG_DEBUG_FS
07144428
DL		 2467void intel_display_crc_init(struct drm_device *dev);
2468#else
f8c168fa 2469static inline void intel_display_crc_init(struct drm_device *dev) {}
07144428 2470#endif
84734a04
MK		 2471
2472/* i915_gpu_error.c */
edc3d884
MK		 2473__printf(2, 3)
2474void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
fc16b48b
MK		 2475int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2476 const struct i915_error_state_file_priv *error);
4dc955f7
MK		 2477int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2478 size_t count, loff_t pos);
2479static inline void i915_error_state_buf_release(
2480 struct drm_i915_error_state_buf *eb)
2481{
2482 kfree(eb->buf);
2483}
58174462
MK		 2484void i915_capture_error_state(struct drm_device *dev, bool wedge,
2485 const char *error_msg);
84734a04
MK		 2486void i915_error_state_get(struct drm_device *dev,
2487 struct i915_error_state_file_priv *error_priv);
2488void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2489void i915_destroy_error_state(struct drm_device *dev);
2490
2491void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2492const char *i915_cache_level_str(int type);
2017263e 2493
351e3db2 2494/* i915_cmd_parser.c */
d728c8ef 2495int i915_cmd_parser_get_version(void);
a4872ba6
OM		 2496int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2497void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2498bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2499int i915_parse_cmds(struct intel_engine_cs *ring,
351e3db2
BV		 2500 struct drm_i915_gem_object *batch_obj,
2501 u32 batch_start_offset,
2502 bool is_master);
2503
317c35d1
JB		 2504/* i915_suspend.c */
2505extern int i915_save_state(struct drm_device *dev);
2506extern int i915_restore_state(struct drm_device *dev);
0a3e67a4 2507
d8157a36
DV		 2508/* i915_ums.c */
2509void i915_save_display_reg(struct drm_device *dev);
2510void i915_restore_display_reg(struct drm_device *dev);
317c35d1 2511
0136db58
BW		 2512/* i915_sysfs.c */
2513void i915_setup_sysfs(struct drm_device *dev_priv);
2514void i915_teardown_sysfs(struct drm_device *dev_priv);
2515
f899fc64
CW		 2516/* intel_i2c.c */
2517extern int intel_setup_gmbus(struct drm_device *dev);
2518extern void intel_teardown_gmbus(struct drm_device *dev);
8f375e10 2519static inline bool intel_gmbus_is_port_valid(unsigned port)
3bd7d909 2520{
2ed06c93 2521 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
3bd7d909
DK		 2522}
2523
2524extern struct i2c_adapter *intel_gmbus_get_adapter(
2525 struct drm_i915_private *dev_priv, unsigned port);
e957d772
CW		 2526extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2527extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
8f375e10 2528static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
b8232e90
CW		 2529{
2530 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2531}
f899fc64
CW		 2532extern void intel_i2c_reset(struct drm_device *dev);
2533
3b617967 2534/* intel_opregion.c */
9c4b0a68 2535struct intel_encoder;
44834a67 2536#ifdef CONFIG_ACPI
27d50c82 2537extern int intel_opregion_setup(struct drm_device *dev);
44834a67
CW		 2538extern void intel_opregion_init(struct drm_device *dev);
2539extern void intel_opregion_fini(struct drm_device *dev);
3b617967 2540extern void intel_opregion_asle_intr(struct drm_device *dev);
9c4b0a68
JN		 2541extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2542 bool enable);
ecbc5cf3
JN		 2543extern int intel_opregion_notify_adapter(struct drm_device *dev,
2544 pci_power_t state);
65e082c9 2545#else
27d50c82 2546static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
44834a67
CW		 2547static inline void intel_opregion_init(struct drm_device *dev) { return; }
2548static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3b617967 2549static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
9c4b0a68
JN		 2550static inline int
2551intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2552{
2553 return 0;
2554}
ecbc5cf3
JN		 2555static inline int
2556intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2557{
2558 return 0;
2559}
65e082c9 2560#endif
8ee1c3db 2561
723bfd70
JB		 2562/* intel_acpi.c */
2563#ifdef CONFIG_ACPI
2564extern void intel_register_dsm_handler(void);
2565extern void intel_unregister_dsm_handler(void);
2566#else
2567static inline void intel_register_dsm_handler(void) { return; }
2568static inline void intel_unregister_dsm_handler(void) { return; }
2569#endif /* CONFIG_ACPI */
2570
79e53945 2571/* modesetting */
f817586c 2572extern void intel_modeset_init_hw(struct drm_device *dev);
7d708ee4 2573extern void intel_modeset_suspend_hw(struct drm_device *dev);
79e53945 2574extern void intel_modeset_init(struct drm_device *dev);
2c7111db 2575extern void intel_modeset_gem_init(struct drm_device *dev);
79e53945 2576extern void intel_modeset_cleanup(struct drm_device *dev);
4932e2c3 2577extern void intel_connector_unregister(struct intel_connector *);
28d52043 2578extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
45e2b5f6
DV		 2579extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2580 bool force_restore);
44cec740 2581extern void i915_redisable_vga(struct drm_device *dev);
04098753 2582extern void i915_redisable_vga_power_on(struct drm_device *dev);
ee5382ae 2583extern bool intel_fbc_enabled(struct drm_device *dev);
43a9539f 2584extern void intel_disable_fbc(struct drm_device *dev);
7648fa99 2585extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
dde86e2d 2586extern void intel_init_pch_refclk(struct drm_device *dev);
3b8d8d91 2587extern void gen6_set_rps(struct drm_device *dev, u8 val);
0a073b84
JB		 2588extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2589extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2590extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
0206e353
AJ		 2591extern void intel_detect_pch(struct drm_device *dev);
2592extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
0136db58 2593extern int intel_enable_rc6(const struct drm_device *dev);
3bad0781 2594
2911a35b 2595extern bool i915_semaphore_is_enabled(struct drm_device *dev);
c0c7babc
BW		 2596int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2597 struct drm_file *file);
b6359918
MK		 2598int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2599 struct drm_file *file);
575155a9 2600
6ef3d427
CW		 2601/* overlay */
2602extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
edc3d884
MK		 2603extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2604 struct intel_overlay_error_state *error);
c4a1d9e4
CW		 2605
2606extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
edc3d884 2607extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
c4a1d9e4
CW		 2608 struct drm_device *dev,
2609 struct intel_display_error_state *error);
6ef3d427 2610
b7287d80
BW		 2611/* On SNB platform, before reading ring registers forcewake bit
2612 * must be set to prevent GT core from power down and stale values being
2613 * returned.
2614 */
c8d9a590
D		 2615void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2616void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
e998c40f 2617void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
b7287d80 2618
42c0526c
BW		 2619int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2620int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
59de0813
JN		 2621
2622/* intel_sideband.c */
64936258
JN		 2623u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2624void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2625u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
e9f882a3
JN		 2626u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2627void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2628u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2629void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2630u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2631void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
f3419158
JB		 2632u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2633void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
e9f882a3
JN		 2634u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2635void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
5e69f97f
CML		 2636u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2637void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
59de0813
JN		 2638u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2639 enum intel_sbi_destination destination);
2640void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2641 enum intel_sbi_destination destination);
e9fe51c6
SK		 2642u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2643void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
0a073b84 2644
2ec3815f
VS		 2645int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2646int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
42c0526c 2647
c8d9a590
D		 2648#define FORCEWAKE_RENDER (1 << 0)
2649#define FORCEWAKE_MEDIA (1 << 1)
2650#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2651
2652
0b274481
BW		 2653#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2654#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2655
2656#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2657#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2658#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2659#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2660
2661#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2662#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2663#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2664#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2665
698b3135
CW		 2666/* Be very careful with read/write 64-bit values. On 32-bit machines, they
2667 * will be implemented using 2 32-bit writes in an arbitrary order with
2668 * an arbitrary delay between them. This can cause the hardware to
2669 * act upon the intermediate value, possibly leading to corruption and
2670 * machine death. You have been warned.
2671 */
0b274481
BW		 2672#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2673#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
cae5852d 2674
50877445
CW		 2675#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2676 u32 upper = I915_READ(upper_reg); \
2677 u32 lower = I915_READ(lower_reg); \
2678 u32 tmp = I915_READ(upper_reg); \
2679 if (upper != tmp) { \
2680 upper = tmp; \
2681 lower = I915_READ(lower_reg); \
2682 WARN_ON(I915_READ(upper_reg) != upper); \
2683 } \
2684 (u64)upper << 32 | lower; })
2685
cae5852d
ZN		 2686#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2687#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2688
55bc60db
VS		 2689/* "Broadcast RGB" property */
2690#define INTEL_BROADCAST_RGB_AUTO 0
2691#define INTEL_BROADCAST_RGB_FULL 1
2692#define INTEL_BROADCAST_RGB_LIMITED 2
ba4f01a3 2693
766aa1c4
VS		 2694static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2695{
2696 if (HAS_PCH_SPLIT(dev))
2697 return CPU_VGACNTRL;
2698 else if (IS_VALLEYVIEW(dev))
2699 return VLV_VGACNTRL;
2700 else
2701 return VGACNTRL;
2702}
2703
2bb4629a
VS		 2704static inline void __user *to_user_ptr(u64 address)
2705{
2706 return (void __user *)(uintptr_t)address;
2707}
2708
df97729f
ID		 2709static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2710{
2711 unsigned long j = msecs_to_jiffies(m);
2712
2713 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2714}
2715
2716static inline unsigned long
2717timespec_to_jiffies_timeout(const struct timespec *value)
2718{
2719 unsigned long j = timespec_to_jiffies(value);
2720
2721 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2722}
2723
dce56b3c
PZ		 2724/*
2725 * If you need to wait X milliseconds between events A and B, but event B
2726 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2727 * when event A happened, then just before event B you call this function and
2728 * pass the timestamp as the first argument, and X as the second argument.
2729 */
2730static inline void
2731wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2732{
ec5e0cfb 2733 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
dce56b3c
PZ		 2734
2735 /*
2736 * Don't re-read the value of "jiffies" every time since it may change
2737 * behind our back and break the math.
2738 */
2739 tmp_jiffies = jiffies;
2740 target_jiffies = timestamp_jiffies +
2741 msecs_to_jiffies_timeout(to_wait_ms);
2742
2743 if (time_after(target_jiffies, tmp_jiffies)) {
ec5e0cfb
ID		 2744 remaining_jiffies = target_jiffies - tmp_jiffies;
2745 while (remaining_jiffies)
2746 remaining_jiffies =
2747 schedule_timeout_uninterruptible(remaining_jiffies);
dce56b3c
PZ		 2748 }
2749}
2750
1da177e4 2751#endif
Linux kernel - Deliverables
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