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254f965c BW |
1 | /* |
2 | * Copyright © 2011-2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * This file implements HW context support. On gen5+ a HW context consists of an | |
30 | * opaque GPU object which is referenced at times of context saves and restores. | |
31 | * With RC6 enabled, the context is also referenced as the GPU enters and exists | |
32 | * from RC6 (GPU has it's own internal power context, except on gen5). Though | |
33 | * something like a context does exist for the media ring, the code only | |
34 | * supports contexts for the render ring. | |
35 | * | |
36 | * In software, there is a distinction between contexts created by the user, | |
37 | * and the default HW context. The default HW context is used by GPU clients | |
38 | * that do not request setup of their own hardware context. The default | |
39 | * context's state is never restored to help prevent programming errors. This | |
40 | * would happen if a client ran and piggy-backed off another clients GPU state. | |
41 | * The default context only exists to give the GPU some offset to load as the | |
42 | * current to invoke a save of the context we actually care about. In fact, the | |
43 | * code could likely be constructed, albeit in a more complicated fashion, to | |
44 | * never use the default context, though that limits the driver's ability to | |
45 | * swap out, and/or destroy other contexts. | |
46 | * | |
47 | * All other contexts are created as a request by the GPU client. These contexts | |
48 | * store GPU state, and thus allow GPU clients to not re-emit state (and | |
49 | * potentially query certain state) at any time. The kernel driver makes | |
50 | * certain that the appropriate commands are inserted. | |
51 | * | |
52 | * The context life cycle is semi-complicated in that context BOs may live | |
53 | * longer than the context itself because of the way the hardware, and object | |
54 | * tracking works. Below is a very crude representation of the state machine | |
55 | * describing the context life. | |
56 | * refcount pincount active | |
57 | * S0: initial state 0 0 0 | |
58 | * S1: context created 1 0 0 | |
59 | * S2: context is currently running 2 1 X | |
60 | * S3: GPU referenced, but not current 2 0 1 | |
61 | * S4: context is current, but destroyed 1 1 0 | |
62 | * S5: like S3, but destroyed 1 0 1 | |
63 | * | |
64 | * The most common (but not all) transitions: | |
65 | * S0->S1: client creates a context | |
66 | * S1->S2: client submits execbuf with context | |
67 | * S2->S3: other clients submits execbuf with context | |
68 | * S3->S1: context object was retired | |
69 | * S3->S2: clients submits another execbuf | |
70 | * S2->S4: context destroy called with current context | |
71 | * S3->S5->S0: destroy path | |
72 | * S4->S5->S0: destroy path on current context | |
73 | * | |
74 | * There are two confusing terms used above: | |
75 | * The "current context" means the context which is currently running on the | |
508842a0 | 76 | * GPU. The GPU has loaded its state already and has stored away the gtt |
254f965c BW |
77 | * offset of the BO. The GPU is not actively referencing the data at this |
78 | * offset, but it will on the next context switch. The only way to avoid this | |
79 | * is to do a GPU reset. | |
80 | * | |
81 | * An "active context' is one which was previously the "current context" and is | |
82 | * on the active list waiting for the next context switch to occur. Until this | |
83 | * happens, the object must remain at the same gtt offset. It is therefore | |
84 | * possible to destroy a context, but it is still active. | |
85 | * | |
86 | */ | |
87 | ||
760285e7 DH |
88 | #include <drm/drmP.h> |
89 | #include <drm/i915_drm.h> | |
254f965c | 90 | #include "i915_drv.h" |
198c974d | 91 | #include "i915_trace.h" |
254f965c | 92 | |
b2e862d0 CW |
93 | #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1 |
94 | ||
40521054 BW |
95 | /* This is a HW constraint. The value below is the largest known requirement |
96 | * I've seen in a spec to date, and that was a workaround for a non-shipping | |
97 | * part. It should be safe to decrease this, but it's more future proof as is. | |
98 | */ | |
b731d33d BW |
99 | #define GEN6_CONTEXT_ALIGN (64<<10) |
100 | #define GEN7_CONTEXT_ALIGN 4096 | |
40521054 | 101 | |
c033666a | 102 | static size_t get_context_alignment(struct drm_i915_private *dev_priv) |
b731d33d | 103 | { |
c033666a | 104 | if (IS_GEN6(dev_priv)) |
b731d33d BW |
105 | return GEN6_CONTEXT_ALIGN; |
106 | ||
107 | return GEN7_CONTEXT_ALIGN; | |
108 | } | |
109 | ||
c033666a | 110 | static int get_context_size(struct drm_i915_private *dev_priv) |
254f965c | 111 | { |
254f965c BW |
112 | int ret; |
113 | u32 reg; | |
114 | ||
c033666a | 115 | switch (INTEL_GEN(dev_priv)) { |
254f965c BW |
116 | case 6: |
117 | reg = I915_READ(CXT_SIZE); | |
118 | ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; | |
119 | break; | |
120 | case 7: | |
4f91dd6f | 121 | reg = I915_READ(GEN7_CXT_SIZE); |
c033666a | 122 | if (IS_HASWELL(dev_priv)) |
a0de80a0 | 123 | ret = HSW_CXT_TOTAL_SIZE; |
2e4291e0 BW |
124 | else |
125 | ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; | |
254f965c | 126 | break; |
8897644a BW |
127 | case 8: |
128 | ret = GEN8_CXT_TOTAL_SIZE; | |
129 | break; | |
254f965c BW |
130 | default: |
131 | BUG(); | |
132 | } | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
dce3271b | 137 | void i915_gem_context_free(struct kref *ctx_ref) |
40521054 | 138 | { |
e2efd130 | 139 | struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); |
bca44d80 | 140 | int i; |
40521054 | 141 | |
91c8a326 | 142 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
198c974d | 143 | trace_i915_context_free(ctx); |
50e046b6 | 144 | GEM_BUG_ON(!ctx->closed); |
198c974d | 145 | |
ae6c4806 DV |
146 | i915_ppgtt_put(ctx->ppgtt); |
147 | ||
bca44d80 CW |
148 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
149 | struct intel_context *ce = &ctx->engine[i]; | |
150 | ||
151 | if (!ce->state) | |
152 | continue; | |
153 | ||
154 | WARN_ON(ce->pin_count); | |
dca33ecc | 155 | if (ce->ring) |
7e37f889 | 156 | intel_ring_free(ce->ring); |
bca44d80 | 157 | |
bf3783e5 | 158 | i915_vma_put(ce->state); |
bca44d80 CW |
159 | } |
160 | ||
c84455b4 | 161 | put_pid(ctx->pid); |
c7c48dfd | 162 | list_del(&ctx->link); |
5d1808ec CW |
163 | |
164 | ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id); | |
40521054 BW |
165 | kfree(ctx); |
166 | } | |
167 | ||
8c857917 | 168 | struct drm_i915_gem_object * |
aa0c13da OM |
169 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size) |
170 | { | |
171 | struct drm_i915_gem_object *obj; | |
172 | int ret; | |
173 | ||
499f2697 CW |
174 | lockdep_assert_held(&dev->struct_mutex); |
175 | ||
d37cd8a8 | 176 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
177 | if (IS_ERR(obj)) |
178 | return obj; | |
aa0c13da OM |
179 | |
180 | /* | |
181 | * Try to make the context utilize L3 as well as LLC. | |
182 | * | |
183 | * On VLV we don't have L3 controls in the PTEs so we | |
184 | * shouldn't touch the cache level, especially as that | |
185 | * would make the object snooped which might have a | |
186 | * negative performance impact. | |
4d3e904c WB |
187 | * |
188 | * Snooping is required on non-llc platforms in execlist | |
189 | * mode, but since all GGTT accesses use PAT entry 0 we | |
190 | * get snooping anyway regardless of cache_level. | |
191 | * | |
192 | * This is only applicable for Ivy Bridge devices since | |
193 | * later platforms don't have L3 control bits in the PTE. | |
aa0c13da | 194 | */ |
4d3e904c | 195 | if (IS_IVYBRIDGE(dev)) { |
aa0c13da OM |
196 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); |
197 | /* Failure shouldn't ever happen this early */ | |
198 | if (WARN_ON(ret)) { | |
f8c417cd | 199 | i915_gem_object_put(obj); |
aa0c13da OM |
200 | return ERR_PTR(ret); |
201 | } | |
202 | } | |
203 | ||
204 | return obj; | |
205 | } | |
206 | ||
50e046b6 CW |
207 | static void i915_ppgtt_close(struct i915_address_space *vm) |
208 | { | |
209 | struct list_head *phases[] = { | |
210 | &vm->active_list, | |
211 | &vm->inactive_list, | |
212 | &vm->unbound_list, | |
213 | NULL, | |
214 | }, **phase; | |
215 | ||
216 | GEM_BUG_ON(vm->closed); | |
217 | vm->closed = true; | |
218 | ||
219 | for (phase = phases; *phase; phase++) { | |
220 | struct i915_vma *vma, *vn; | |
221 | ||
222 | list_for_each_entry_safe(vma, vn, *phase, vm_link) | |
3272db53 | 223 | if (!i915_vma_is_closed(vma)) |
50e046b6 CW |
224 | i915_vma_close(vma); |
225 | } | |
226 | } | |
227 | ||
228 | static void context_close(struct i915_gem_context *ctx) | |
229 | { | |
230 | GEM_BUG_ON(ctx->closed); | |
231 | ctx->closed = true; | |
232 | if (ctx->ppgtt) | |
233 | i915_ppgtt_close(&ctx->ppgtt->base); | |
234 | ctx->file_priv = ERR_PTR(-EBADF); | |
235 | i915_gem_context_put(ctx); | |
236 | } | |
237 | ||
5d1808ec CW |
238 | static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) |
239 | { | |
240 | int ret; | |
241 | ||
242 | ret = ida_simple_get(&dev_priv->context_hw_ida, | |
243 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
244 | if (ret < 0) { | |
245 | /* Contexts are only released when no longer active. | |
246 | * Flush any pending retires to hopefully release some | |
247 | * stale contexts and try again. | |
248 | */ | |
c033666a | 249 | i915_gem_retire_requests(dev_priv); |
5d1808ec CW |
250 | ret = ida_simple_get(&dev_priv->context_hw_ida, |
251 | 0, MAX_CONTEXT_HW_ID, GFP_KERNEL); | |
252 | if (ret < 0) | |
253 | return ret; | |
254 | } | |
255 | ||
256 | *out = ret; | |
257 | return 0; | |
258 | } | |
259 | ||
e2efd130 | 260 | static struct i915_gem_context * |
0eea67eb | 261 | __create_hw_context(struct drm_device *dev, |
ee960be7 | 262 | struct drm_i915_file_private *file_priv) |
40521054 | 263 | { |
fac5e23e | 264 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 265 | struct i915_gem_context *ctx; |
c8c470af | 266 | int ret; |
40521054 | 267 | |
f94982b0 | 268 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
146937e5 BW |
269 | if (ctx == NULL) |
270 | return ERR_PTR(-ENOMEM); | |
40521054 | 271 | |
5d1808ec CW |
272 | ret = assign_hw_id(dev_priv, &ctx->hw_id); |
273 | if (ret) { | |
274 | kfree(ctx); | |
275 | return ERR_PTR(ret); | |
276 | } | |
277 | ||
dce3271b | 278 | kref_init(&ctx->ref); |
691e6415 | 279 | list_add_tail(&ctx->link, &dev_priv->context_list); |
9ea4feec | 280 | ctx->i915 = dev_priv; |
40521054 | 281 | |
0cb26a8e CW |
282 | ctx->ggtt_alignment = get_context_alignment(dev_priv); |
283 | ||
691e6415 | 284 | if (dev_priv->hw_context_size) { |
bf3783e5 CW |
285 | struct drm_i915_gem_object *obj; |
286 | struct i915_vma *vma; | |
287 | ||
288 | obj = i915_gem_alloc_context_obj(dev, | |
289 | dev_priv->hw_context_size); | |
aa0c13da OM |
290 | if (IS_ERR(obj)) { |
291 | ret = PTR_ERR(obj); | |
4615d4c9 | 292 | goto err_out; |
691e6415 | 293 | } |
bf3783e5 CW |
294 | |
295 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); | |
296 | if (IS_ERR(vma)) { | |
297 | i915_gem_object_put(obj); | |
298 | ret = PTR_ERR(vma); | |
299 | goto err_out; | |
300 | } | |
301 | ||
302 | ctx->engine[RCS].state = vma; | |
691e6415 | 303 | } |
40521054 BW |
304 | |
305 | /* Default context will never have a file_priv */ | |
691e6415 CW |
306 | if (file_priv != NULL) { |
307 | ret = idr_alloc(&file_priv->context_idr, ctx, | |
821d66dd | 308 | DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); |
691e6415 CW |
309 | if (ret < 0) |
310 | goto err_out; | |
311 | } else | |
821d66dd | 312 | ret = DEFAULT_CONTEXT_HANDLE; |
dce3271b MK |
313 | |
314 | ctx->file_priv = file_priv; | |
c84455b4 CW |
315 | if (file_priv) |
316 | ctx->pid = get_task_pid(current, PIDTYPE_PID); | |
317 | ||
821d66dd | 318 | ctx->user_handle = ret; |
3ccfd19d BW |
319 | /* NB: Mark all slices as needing a remap so that when the context first |
320 | * loads it will restore whatever remap state already exists. If there | |
321 | * is no remap info, it will be a NOP. */ | |
b2e862d0 | 322 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); |
40521054 | 323 | |
676fa572 | 324 | ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD; |
bcd794c2 | 325 | ctx->ring_size = 4 * PAGE_SIZE; |
c01fc532 ZW |
326 | ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) << |
327 | GEN8_CTX_ADDRESSING_MODE_SHIFT; | |
3c7ba635 | 328 | ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier); |
676fa572 | 329 | |
146937e5 | 330 | return ctx; |
40521054 BW |
331 | |
332 | err_out: | |
50e046b6 | 333 | context_close(ctx); |
146937e5 | 334 | return ERR_PTR(ret); |
40521054 BW |
335 | } |
336 | ||
254f965c BW |
337 | /** |
338 | * The default context needs to exist per ring that uses contexts. It stores the | |
339 | * context state of the GPU for applications that don't utilize HW contexts, as | |
340 | * well as an idle case. | |
341 | */ | |
e2efd130 | 342 | static struct i915_gem_context * |
0eea67eb | 343 | i915_gem_create_context(struct drm_device *dev, |
d624d86e | 344 | struct drm_i915_file_private *file_priv) |
254f965c | 345 | { |
e2efd130 | 346 | struct i915_gem_context *ctx; |
40521054 | 347 | |
499f2697 | 348 | lockdep_assert_held(&dev->struct_mutex); |
40521054 | 349 | |
0eea67eb | 350 | ctx = __create_hw_context(dev, file_priv); |
146937e5 | 351 | if (IS_ERR(ctx)) |
a45d0f6a | 352 | return ctx; |
40521054 | 353 | |
d624d86e | 354 | if (USES_FULL_PPGTT(dev)) { |
2bfa996e CW |
355 | struct i915_hw_ppgtt *ppgtt = |
356 | i915_ppgtt_create(to_i915(dev), file_priv); | |
bdf4fd7e | 357 | |
c6aab916 | 358 | if (IS_ERR(ppgtt)) { |
0eea67eb BW |
359 | DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n", |
360 | PTR_ERR(ppgtt)); | |
c6aab916 | 361 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
50e046b6 | 362 | context_close(ctx); |
c6aab916 | 363 | return ERR_CAST(ppgtt); |
ae6c4806 DV |
364 | } |
365 | ||
366 | ctx->ppgtt = ppgtt; | |
367 | } | |
bdf4fd7e | 368 | |
198c974d DCS |
369 | trace_i915_context_create(ctx); |
370 | ||
a45d0f6a | 371 | return ctx; |
254f965c BW |
372 | } |
373 | ||
c8c35799 ZW |
374 | /** |
375 | * i915_gem_context_create_gvt - create a GVT GEM context | |
376 | * @dev: drm device * | |
377 | * | |
378 | * This function is used to create a GVT specific GEM context. | |
379 | * | |
380 | * Returns: | |
381 | * pointer to i915_gem_context on success, error pointer if failed | |
382 | * | |
383 | */ | |
384 | struct i915_gem_context * | |
385 | i915_gem_context_create_gvt(struct drm_device *dev) | |
386 | { | |
387 | struct i915_gem_context *ctx; | |
388 | int ret; | |
389 | ||
390 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
391 | return ERR_PTR(-ENODEV); | |
392 | ||
393 | ret = i915_mutex_lock_interruptible(dev); | |
394 | if (ret) | |
395 | return ERR_PTR(ret); | |
396 | ||
397 | ctx = i915_gem_create_context(dev, NULL); | |
398 | if (IS_ERR(ctx)) | |
399 | goto out; | |
400 | ||
401 | ctx->execlists_force_single_submission = true; | |
402 | ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */ | |
403 | out: | |
404 | mutex_unlock(&dev->struct_mutex); | |
405 | return ctx; | |
406 | } | |
407 | ||
e2efd130 | 408 | static void i915_gem_context_unpin(struct i915_gem_context *ctx, |
a0b4a6a8 TU |
409 | struct intel_engine_cs *engine) |
410 | { | |
f4e2dece TU |
411 | if (i915.enable_execlists) { |
412 | intel_lr_context_unpin(ctx, engine); | |
413 | } else { | |
bca44d80 CW |
414 | struct intel_context *ce = &ctx->engine[engine->id]; |
415 | ||
416 | if (ce->state) | |
bf3783e5 | 417 | i915_vma_unpin(ce->state); |
bca44d80 | 418 | |
9a6feaf0 | 419 | i915_gem_context_put(ctx); |
f4e2dece | 420 | } |
a0b4a6a8 TU |
421 | } |
422 | ||
8245be31 | 423 | int i915_gem_context_init(struct drm_device *dev) |
254f965c | 424 | { |
fac5e23e | 425 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 426 | struct i915_gem_context *ctx; |
254f965c | 427 | |
2fa48d8d BW |
428 | /* Init should only be called once per module load. Eventually the |
429 | * restriction on the context_disabled check can be loosened. */ | |
ed54c1a1 | 430 | if (WARN_ON(dev_priv->kernel_context)) |
8245be31 | 431 | return 0; |
254f965c | 432 | |
c033666a CW |
433 | if (intel_vgpu_active(dev_priv) && |
434 | HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { | |
a0bd6c31 ZL |
435 | if (!i915.enable_execlists) { |
436 | DRM_INFO("Only EXECLIST mode is supported in vgpu.\n"); | |
437 | return -EINVAL; | |
438 | } | |
439 | } | |
440 | ||
5d1808ec CW |
441 | /* Using the simple ida interface, the max is limited by sizeof(int) */ |
442 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX); | |
443 | ida_init(&dev_priv->context_hw_ida); | |
444 | ||
ede7d42b OM |
445 | if (i915.enable_execlists) { |
446 | /* NB: intentionally left blank. We will allocate our own | |
447 | * backing objects as we need them, thank you very much */ | |
448 | dev_priv->hw_context_size = 0; | |
c033666a CW |
449 | } else if (HAS_HW_CONTEXTS(dev_priv)) { |
450 | dev_priv->hw_context_size = | |
451 | round_up(get_context_size(dev_priv), 4096); | |
691e6415 CW |
452 | if (dev_priv->hw_context_size > (1<<20)) { |
453 | DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n", | |
454 | dev_priv->hw_context_size); | |
455 | dev_priv->hw_context_size = 0; | |
456 | } | |
254f965c BW |
457 | } |
458 | ||
d624d86e | 459 | ctx = i915_gem_create_context(dev, NULL); |
691e6415 CW |
460 | if (IS_ERR(ctx)) { |
461 | DRM_ERROR("Failed to create default global context (error %ld)\n", | |
462 | PTR_ERR(ctx)); | |
463 | return PTR_ERR(ctx); | |
254f965c BW |
464 | } |
465 | ||
ed54c1a1 | 466 | dev_priv->kernel_context = ctx; |
67e3d297 | 467 | |
ede7d42b OM |
468 | DRM_DEBUG_DRIVER("%s context support initialized\n", |
469 | i915.enable_execlists ? "LR" : | |
470 | dev_priv->hw_context_size ? "HW" : "fake"); | |
8245be31 | 471 | return 0; |
254f965c BW |
472 | } |
473 | ||
b2e862d0 CW |
474 | void i915_gem_context_lost(struct drm_i915_private *dev_priv) |
475 | { | |
476 | struct intel_engine_cs *engine; | |
477 | ||
91c8a326 | 478 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
499f2697 | 479 | |
b2e862d0 | 480 | for_each_engine(engine, dev_priv) { |
bca44d80 CW |
481 | if (engine->last_context) { |
482 | i915_gem_context_unpin(engine->last_context, engine); | |
483 | engine->last_context = NULL; | |
484 | } | |
b2e862d0 CW |
485 | } |
486 | ||
c7c3c07d CW |
487 | /* Force the GPU state to be restored on enabling */ |
488 | if (!i915.enable_execlists) { | |
a168b2d8 CW |
489 | struct i915_gem_context *ctx; |
490 | ||
491 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
492 | if (!i915_gem_context_is_default(ctx)) | |
493 | continue; | |
494 | ||
495 | for_each_engine(engine, dev_priv) | |
496 | ctx->engine[engine->id].initialised = false; | |
497 | ||
498 | ctx->remap_slice = ALL_L3_SLICES(dev_priv); | |
499 | } | |
500 | ||
c7c3c07d CW |
501 | for_each_engine(engine, dev_priv) { |
502 | struct intel_context *kce = | |
503 | &dev_priv->kernel_context->engine[engine->id]; | |
504 | ||
505 | kce->initialised = true; | |
506 | } | |
507 | } | |
b2e862d0 CW |
508 | } |
509 | ||
254f965c BW |
510 | void i915_gem_context_fini(struct drm_device *dev) |
511 | { | |
fac5e23e | 512 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2efd130 | 513 | struct i915_gem_context *dctx = dev_priv->kernel_context; |
b2e862d0 | 514 | |
499f2697 CW |
515 | lockdep_assert_held(&dev->struct_mutex); |
516 | ||
50e046b6 | 517 | context_close(dctx); |
ed54c1a1 | 518 | dev_priv->kernel_context = NULL; |
5d1808ec CW |
519 | |
520 | ida_destroy(&dev_priv->context_hw_ida); | |
254f965c BW |
521 | } |
522 | ||
40521054 BW |
523 | static int context_idr_cleanup(int id, void *p, void *data) |
524 | { | |
e2efd130 | 525 | struct i915_gem_context *ctx = p; |
40521054 | 526 | |
50e046b6 | 527 | context_close(ctx); |
40521054 | 528 | return 0; |
254f965c BW |
529 | } |
530 | ||
e422b888 BW |
531 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) |
532 | { | |
533 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 534 | struct i915_gem_context *ctx; |
e422b888 BW |
535 | |
536 | idr_init(&file_priv->context_idr); | |
537 | ||
0eea67eb | 538 | mutex_lock(&dev->struct_mutex); |
d624d86e | 539 | ctx = i915_gem_create_context(dev, file_priv); |
0eea67eb BW |
540 | mutex_unlock(&dev->struct_mutex); |
541 | ||
f83d6518 | 542 | if (IS_ERR(ctx)) { |
0eea67eb | 543 | idr_destroy(&file_priv->context_idr); |
f83d6518 | 544 | return PTR_ERR(ctx); |
0eea67eb BW |
545 | } |
546 | ||
e422b888 BW |
547 | return 0; |
548 | } | |
549 | ||
254f965c BW |
550 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) |
551 | { | |
40521054 | 552 | struct drm_i915_file_private *file_priv = file->driver_priv; |
254f965c | 553 | |
499f2697 CW |
554 | lockdep_assert_held(&dev->struct_mutex); |
555 | ||
73c273eb | 556 | idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL); |
40521054 | 557 | idr_destroy(&file_priv->context_idr); |
40521054 BW |
558 | } |
559 | ||
e0556841 | 560 | static inline int |
1d719cda | 561 | mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) |
e0556841 | 562 | { |
c033666a | 563 | struct drm_i915_private *dev_priv = req->i915; |
7e37f889 | 564 | struct intel_ring *ring = req->ring; |
4a570db5 | 565 | struct intel_engine_cs *engine = req->engine; |
e80f14b6 | 566 | u32 flags = hw_flags | MI_MM_SPACE_GTT; |
2c550183 CW |
567 | const int num_rings = |
568 | /* Use an extended w/a on ivb+ if signalling from other rings */ | |
39df9190 | 569 | i915.semaphores ? |
c1bb1145 | 570 | INTEL_INFO(dev_priv)->num_rings - 1 : |
2c550183 | 571 | 0; |
b4ac5afc | 572 | int len, ret; |
e0556841 | 573 | |
12b0286f BW |
574 | /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB |
575 | * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value | |
576 | * explicitly, so we rely on the value at ring init, stored in | |
577 | * itlb_before_ctx_switch. | |
578 | */ | |
c033666a | 579 | if (IS_GEN6(dev_priv)) { |
7c9cf4e3 | 580 | ret = engine->emit_flush(req, EMIT_INVALIDATE); |
12b0286f BW |
581 | if (ret) |
582 | return ret; | |
583 | } | |
584 | ||
e80f14b6 | 585 | /* These flags are for resource streamer on HSW+ */ |
c033666a | 586 | if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) |
4c436d55 | 587 | flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN); |
c033666a | 588 | else if (INTEL_GEN(dev_priv) < 8) |
e80f14b6 BW |
589 | flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); |
590 | ||
2c550183 CW |
591 | |
592 | len = 4; | |
c033666a | 593 | if (INTEL_GEN(dev_priv) >= 7) |
e9135c4f | 594 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); |
2c550183 | 595 | |
5fb9de1a | 596 | ret = intel_ring_begin(req, len); |
e0556841 BW |
597 | if (ret) |
598 | return ret; | |
599 | ||
b3f797ac | 600 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ |
c033666a | 601 | if (INTEL_GEN(dev_priv) >= 7) { |
b5321f30 | 602 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
2c550183 CW |
603 | if (num_rings) { |
604 | struct intel_engine_cs *signaller; | |
605 | ||
b5321f30 | 606 | intel_ring_emit(ring, |
e2f80391 | 607 | MI_LOAD_REGISTER_IMM(num_rings)); |
c033666a | 608 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 609 | if (signaller == engine) |
2c550183 CW |
610 | continue; |
611 | ||
b5321f30 | 612 | intel_ring_emit_reg(ring, |
e2f80391 | 613 | RING_PSMI_CTL(signaller->mmio_base)); |
b5321f30 | 614 | intel_ring_emit(ring, |
e2f80391 | 615 | _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
2c550183 CW |
616 | } |
617 | } | |
618 | } | |
e37ec39b | 619 | |
b5321f30 CW |
620 | intel_ring_emit(ring, MI_NOOP); |
621 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
bde13ebd CW |
622 | intel_ring_emit(ring, |
623 | i915_ggtt_offset(req->ctx->engine[RCS].state) | flags); | |
2b7e8082 VS |
624 | /* |
625 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
626 | * WaMiSetContext_Hang:snb,ivb,vlv | |
627 | */ | |
b5321f30 | 628 | intel_ring_emit(ring, MI_NOOP); |
e0556841 | 629 | |
c033666a | 630 | if (INTEL_GEN(dev_priv) >= 7) { |
2c550183 CW |
631 | if (num_rings) { |
632 | struct intel_engine_cs *signaller; | |
e9135c4f | 633 | i915_reg_t last_reg = {}; /* keep gcc quiet */ |
2c550183 | 634 | |
b5321f30 | 635 | intel_ring_emit(ring, |
e2f80391 | 636 | MI_LOAD_REGISTER_IMM(num_rings)); |
c033666a | 637 | for_each_engine(signaller, dev_priv) { |
e2f80391 | 638 | if (signaller == engine) |
2c550183 CW |
639 | continue; |
640 | ||
e9135c4f | 641 | last_reg = RING_PSMI_CTL(signaller->mmio_base); |
b5321f30 CW |
642 | intel_ring_emit_reg(ring, last_reg); |
643 | intel_ring_emit(ring, | |
e2f80391 | 644 | _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); |
2c550183 | 645 | } |
e9135c4f CW |
646 | |
647 | /* Insert a delay before the next switch! */ | |
b5321f30 | 648 | intel_ring_emit(ring, |
e9135c4f CW |
649 | MI_STORE_REGISTER_MEM | |
650 | MI_SRM_LRM_GLOBAL_GTT); | |
b5321f30 | 651 | intel_ring_emit_reg(ring, last_reg); |
bde13ebd CW |
652 | intel_ring_emit(ring, |
653 | i915_ggtt_offset(engine->scratch)); | |
b5321f30 | 654 | intel_ring_emit(ring, MI_NOOP); |
2c550183 | 655 | } |
b5321f30 | 656 | intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
2c550183 | 657 | } |
e37ec39b | 658 | |
b5321f30 | 659 | intel_ring_advance(ring); |
e0556841 BW |
660 | |
661 | return ret; | |
662 | } | |
663 | ||
d200cda6 | 664 | static int remap_l3(struct drm_i915_gem_request *req, int slice) |
b0ebde39 | 665 | { |
ff55b5e8 | 666 | u32 *remap_info = req->i915->l3_parity.remap_info[slice]; |
7e37f889 | 667 | struct intel_ring *ring = req->ring; |
b0ebde39 CW |
668 | int i, ret; |
669 | ||
ff55b5e8 | 670 | if (!remap_info) |
b0ebde39 CW |
671 | return 0; |
672 | ||
ff55b5e8 | 673 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); |
b0ebde39 CW |
674 | if (ret) |
675 | return ret; | |
676 | ||
677 | /* | |
678 | * Note: We do not worry about the concurrent register cacheline hang | |
679 | * here because no other code should access these registers other than | |
680 | * at initialization time. | |
681 | */ | |
b5321f30 | 682 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); |
ff55b5e8 | 683 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { |
b5321f30 CW |
684 | intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i)); |
685 | intel_ring_emit(ring, remap_info[i]); | |
b0ebde39 | 686 | } |
b5321f30 CW |
687 | intel_ring_emit(ring, MI_NOOP); |
688 | intel_ring_advance(ring); | |
b0ebde39 | 689 | |
ff55b5e8 | 690 | return 0; |
b0ebde39 CW |
691 | } |
692 | ||
f9326be5 CW |
693 | static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt, |
694 | struct intel_engine_cs *engine, | |
e2efd130 | 695 | struct i915_gem_context *to) |
317b4e90 | 696 | { |
563222a7 BW |
697 | if (to->remap_slice) |
698 | return false; | |
699 | ||
bca44d80 | 700 | if (!to->engine[RCS].initialised) |
fcb5106d CW |
701 | return false; |
702 | ||
f9326be5 | 703 | if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
fcb5106d | 704 | return false; |
317b4e90 | 705 | |
fcb5106d | 706 | return to == engine->last_context; |
317b4e90 BW |
707 | } |
708 | ||
709 | static bool | |
f9326be5 CW |
710 | needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, |
711 | struct intel_engine_cs *engine, | |
e2efd130 | 712 | struct i915_gem_context *to) |
317b4e90 | 713 | { |
f9326be5 | 714 | if (!ppgtt) |
317b4e90 BW |
715 | return false; |
716 | ||
f9326be5 CW |
717 | /* Always load the ppgtt on first use */ |
718 | if (!engine->last_context) | |
719 | return true; | |
720 | ||
721 | /* Same context without new entries, skip */ | |
e1a8daa2 | 722 | if (engine->last_context == to && |
f9326be5 | 723 | !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings)) |
e1a8daa2 CW |
724 | return false; |
725 | ||
726 | if (engine->id != RCS) | |
317b4e90 BW |
727 | return true; |
728 | ||
c033666a | 729 | if (INTEL_GEN(engine->i915) < 8) |
317b4e90 BW |
730 | return true; |
731 | ||
732 | return false; | |
733 | } | |
734 | ||
735 | static bool | |
f9326be5 | 736 | needs_pd_load_post(struct i915_hw_ppgtt *ppgtt, |
e2efd130 | 737 | struct i915_gem_context *to, |
f9326be5 | 738 | u32 hw_flags) |
317b4e90 | 739 | { |
f9326be5 | 740 | if (!ppgtt) |
317b4e90 BW |
741 | return false; |
742 | ||
fcb5106d | 743 | if (!IS_GEN8(to->i915)) |
317b4e90 BW |
744 | return false; |
745 | ||
6702cf16 | 746 | if (hw_flags & MI_RESTORE_INHIBIT) |
317b4e90 BW |
747 | return true; |
748 | ||
749 | return false; | |
750 | } | |
751 | ||
e1a8daa2 | 752 | static int do_rcs_switch(struct drm_i915_gem_request *req) |
e0556841 | 753 | { |
e2efd130 | 754 | struct i915_gem_context *to = req->ctx; |
4a570db5 | 755 | struct intel_engine_cs *engine = req->engine; |
f9326be5 | 756 | struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt; |
bf3783e5 | 757 | struct i915_vma *vma = to->engine[RCS].state; |
e2efd130 | 758 | struct i915_gem_context *from; |
fcb5106d | 759 | u32 hw_flags; |
3ccfd19d | 760 | int ret, i; |
e0556841 | 761 | |
f9326be5 | 762 | if (skip_rcs_switch(ppgtt, engine, to)) |
9a3b5304 CW |
763 | return 0; |
764 | ||
7abc98fa CW |
765 | /* Clear this page out of any CPU caches for coherent swap-in/out. */ |
766 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
767 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, false); | |
768 | if (ret) | |
769 | return ret; | |
770 | } | |
771 | ||
7e0d96bc | 772 | /* Trying to pin first makes error handling easier. */ |
bf3783e5 | 773 | ret = i915_vma_pin(vma, 0, to->ggtt_alignment, PIN_GLOBAL); |
e1a8daa2 CW |
774 | if (ret) |
775 | return ret; | |
67e3d297 | 776 | |
acc240d4 DV |
777 | /* |
778 | * Pin can switch back to the default context if we end up calling into | |
779 | * evict_everything - as a last ditch gtt defrag effort that also | |
780 | * switches to the default context. Hence we need to reload from here. | |
fcb5106d CW |
781 | * |
782 | * XXX: Doing so is painfully broken! | |
acc240d4 | 783 | */ |
e2f80391 | 784 | from = engine->last_context; |
acc240d4 | 785 | |
f9326be5 | 786 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
fcb5106d CW |
787 | /* Older GENs and non render rings still want the load first, |
788 | * "PP_DCLV followed by PP_DIR_BASE register through Load | |
789 | * Register Immediate commands in Ring Buffer before submitting | |
790 | * a context."*/ | |
791 | trace_switch_mm(engine, to); | |
f9326be5 | 792 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d | 793 | if (ret) |
bf3783e5 | 794 | goto err; |
fcb5106d CW |
795 | } |
796 | ||
bca44d80 | 797 | if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) |
6702cf16 BW |
798 | /* NB: If we inhibit the restore, the context is not allowed to |
799 | * die because future work may end up depending on valid address | |
800 | * space. This means we must enforce that a page table load | |
801 | * occur when this occurs. */ | |
fcb5106d | 802 | hw_flags = MI_RESTORE_INHIBIT; |
f9326be5 | 803 | else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings) |
fcb5106d CW |
804 | hw_flags = MI_FORCE_RESTORE; |
805 | else | |
806 | hw_flags = 0; | |
e0556841 | 807 | |
fcb5106d CW |
808 | if (to != from || (hw_flags & MI_FORCE_RESTORE)) { |
809 | ret = mi_set_context(req, hw_flags); | |
3ccfd19d | 810 | if (ret) |
bf3783e5 | 811 | goto err; |
3ccfd19d BW |
812 | } |
813 | ||
e0556841 BW |
814 | /* The backing object for the context is done after switching to the |
815 | * *next* context. Therefore we cannot retire the previous context until | |
816 | * the next context has already started running. In fact, the below code | |
817 | * is a bit suboptimal because the retiring can occur simply after the | |
818 | * MI_SET_CONTEXT instead of when the next seqno has completed. | |
819 | */ | |
112522f6 | 820 | if (from != NULL) { |
e0556841 BW |
821 | /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the |
822 | * whole damn pipeline, we don't need to explicitly mark the | |
823 | * object dirty. The only exception is that the context must be | |
824 | * correct in case the object gets swapped out. Ideally we'd be | |
825 | * able to defer doing this until we know the object would be | |
826 | * swapped, but there is no way to do that yet. | |
827 | */ | |
bf3783e5 CW |
828 | i915_vma_move_to_active(from->engine[RCS].state, req, 0); |
829 | /* state is kept alive until the next request */ | |
830 | i915_vma_unpin(from->engine[RCS].state); | |
9a6feaf0 | 831 | i915_gem_context_put(from); |
e0556841 | 832 | } |
9a6feaf0 | 833 | engine->last_context = i915_gem_context_get(to); |
e0556841 | 834 | |
fcb5106d CW |
835 | /* GEN8 does *not* require an explicit reload if the PDPs have been |
836 | * setup, and we do not wish to move them. | |
837 | */ | |
f9326be5 | 838 | if (needs_pd_load_post(ppgtt, to, hw_flags)) { |
fcb5106d | 839 | trace_switch_mm(engine, to); |
f9326be5 | 840 | ret = ppgtt->switch_mm(ppgtt, req); |
fcb5106d CW |
841 | /* The hardware context switch is emitted, but we haven't |
842 | * actually changed the state - so it's probably safe to bail | |
843 | * here. Still, let the user know something dangerous has | |
844 | * happened. | |
845 | */ | |
846 | if (ret) | |
847 | return ret; | |
848 | } | |
849 | ||
f9326be5 CW |
850 | if (ppgtt) |
851 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); | |
fcb5106d CW |
852 | |
853 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
854 | if (!(to->remap_slice & (1<<i))) | |
855 | continue; | |
856 | ||
d200cda6 | 857 | ret = remap_l3(req, i); |
fcb5106d CW |
858 | if (ret) |
859 | return ret; | |
860 | ||
861 | to->remap_slice &= ~(1<<i); | |
862 | } | |
863 | ||
bca44d80 | 864 | if (!to->engine[RCS].initialised) { |
e2f80391 TU |
865 | if (engine->init_context) { |
866 | ret = engine->init_context(req); | |
86d7f238 | 867 | if (ret) |
fcb5106d | 868 | return ret; |
86d7f238 | 869 | } |
bca44d80 | 870 | to->engine[RCS].initialised = true; |
46470fc9 MK |
871 | } |
872 | ||
e0556841 | 873 | return 0; |
7e0d96bc | 874 | |
bf3783e5 CW |
875 | err: |
876 | i915_vma_unpin(vma); | |
7e0d96bc | 877 | return ret; |
e0556841 BW |
878 | } |
879 | ||
880 | /** | |
881 | * i915_switch_context() - perform a GPU context switch. | |
ba01cc93 | 882 | * @req: request for which we'll execute the context switch |
e0556841 BW |
883 | * |
884 | * The context life cycle is simple. The context refcount is incremented and | |
885 | * decremented by 1 and create and destroy. If the context is in use by the GPU, | |
ecdb5fd8 | 886 | * it will have a refcount > 1. This allows us to destroy the context abstract |
e0556841 | 887 | * object while letting the normal object tracking destroy the backing BO. |
ecdb5fd8 TD |
888 | * |
889 | * This function should not be used in execlists mode. Instead the context is | |
890 | * switched by writing to the ELSP and requests keep a reference to their | |
891 | * context. | |
e0556841 | 892 | */ |
ba01cc93 | 893 | int i915_switch_context(struct drm_i915_gem_request *req) |
e0556841 | 894 | { |
4a570db5 | 895 | struct intel_engine_cs *engine = req->engine; |
e0556841 | 896 | |
91c8a326 | 897 | lockdep_assert_held(&req->i915->drm.struct_mutex); |
5b043f4e CW |
898 | if (i915.enable_execlists) |
899 | return 0; | |
0eea67eb | 900 | |
bca44d80 | 901 | if (!req->ctx->engine[engine->id].state) { |
e2efd130 | 902 | struct i915_gem_context *to = req->ctx; |
f9326be5 CW |
903 | struct i915_hw_ppgtt *ppgtt = |
904 | to->ppgtt ?: req->i915->mm.aliasing_ppgtt; | |
e1a8daa2 | 905 | |
f9326be5 | 906 | if (needs_pd_load_pre(ppgtt, engine, to)) { |
e1a8daa2 CW |
907 | int ret; |
908 | ||
909 | trace_switch_mm(engine, to); | |
f9326be5 | 910 | ret = ppgtt->switch_mm(ppgtt, req); |
e1a8daa2 CW |
911 | if (ret) |
912 | return ret; | |
913 | ||
f9326be5 | 914 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
e1a8daa2 CW |
915 | } |
916 | ||
917 | if (to != engine->last_context) { | |
e2f80391 | 918 | if (engine->last_context) |
9a6feaf0 CW |
919 | i915_gem_context_put(engine->last_context); |
920 | engine->last_context = i915_gem_context_get(to); | |
691e6415 | 921 | } |
e1a8daa2 | 922 | |
c482972a | 923 | return 0; |
a95f6a00 | 924 | } |
c482972a | 925 | |
e1a8daa2 | 926 | return do_rcs_switch(req); |
e0556841 | 927 | } |
84624813 | 928 | |
945657b4 CW |
929 | int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv) |
930 | { | |
931 | struct intel_engine_cs *engine; | |
932 | ||
933 | for_each_engine(engine, dev_priv) { | |
934 | struct drm_i915_gem_request *req; | |
935 | int ret; | |
936 | ||
937 | if (engine->last_context == NULL) | |
938 | continue; | |
939 | ||
940 | if (engine->last_context == dev_priv->kernel_context) | |
941 | continue; | |
942 | ||
943 | req = i915_gem_request_alloc(engine, dev_priv->kernel_context); | |
944 | if (IS_ERR(req)) | |
945 | return PTR_ERR(req); | |
946 | ||
5b043f4e | 947 | ret = i915_switch_context(req); |
945657b4 CW |
948 | i915_add_request_no_flush(req); |
949 | if (ret) | |
950 | return ret; | |
951 | } | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
ec3e9963 | 956 | static bool contexts_enabled(struct drm_device *dev) |
691e6415 | 957 | { |
ec3e9963 | 958 | return i915.enable_execlists || to_i915(dev)->hw_context_size; |
691e6415 CW |
959 | } |
960 | ||
84624813 BW |
961 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
962 | struct drm_file *file) | |
963 | { | |
84624813 BW |
964 | struct drm_i915_gem_context_create *args = data; |
965 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 966 | struct i915_gem_context *ctx; |
84624813 BW |
967 | int ret; |
968 | ||
ec3e9963 | 969 | if (!contexts_enabled(dev)) |
5fa8be65 DV |
970 | return -ENODEV; |
971 | ||
b31e5136 CW |
972 | if (args->pad != 0) |
973 | return -EINVAL; | |
974 | ||
84624813 BW |
975 | ret = i915_mutex_lock_interruptible(dev); |
976 | if (ret) | |
977 | return ret; | |
978 | ||
d624d86e | 979 | ctx = i915_gem_create_context(dev, file_priv); |
84624813 | 980 | mutex_unlock(&dev->struct_mutex); |
be636387 DC |
981 | if (IS_ERR(ctx)) |
982 | return PTR_ERR(ctx); | |
84624813 | 983 | |
821d66dd | 984 | args->ctx_id = ctx->user_handle; |
84624813 BW |
985 | DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); |
986 | ||
be636387 | 987 | return 0; |
84624813 BW |
988 | } |
989 | ||
990 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
991 | struct drm_file *file) | |
992 | { | |
993 | struct drm_i915_gem_context_destroy *args = data; | |
994 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
e2efd130 | 995 | struct i915_gem_context *ctx; |
84624813 BW |
996 | int ret; |
997 | ||
b31e5136 CW |
998 | if (args->pad != 0) |
999 | return -EINVAL; | |
1000 | ||
821d66dd | 1001 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE) |
c2cf2416 | 1002 | return -ENOENT; |
0eea67eb | 1003 | |
84624813 BW |
1004 | ret = i915_mutex_lock_interruptible(dev); |
1005 | if (ret) | |
1006 | return ret; | |
1007 | ||
ca585b5d | 1008 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
72ad5c45 | 1009 | if (IS_ERR(ctx)) { |
84624813 | 1010 | mutex_unlock(&dev->struct_mutex); |
72ad5c45 | 1011 | return PTR_ERR(ctx); |
84624813 BW |
1012 | } |
1013 | ||
d28b99ab | 1014 | idr_remove(&file_priv->context_idr, ctx->user_handle); |
50e046b6 | 1015 | context_close(ctx); |
84624813 BW |
1016 | mutex_unlock(&dev->struct_mutex); |
1017 | ||
1018 | DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); | |
1019 | return 0; | |
1020 | } | |
c9dc0f35 CW |
1021 | |
1022 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, | |
1023 | struct drm_file *file) | |
1024 | { | |
1025 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1026 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1027 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1028 | int ret; |
1029 | ||
1030 | ret = i915_mutex_lock_interruptible(dev); | |
1031 | if (ret) | |
1032 | return ret; | |
1033 | ||
ca585b5d | 1034 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1035 | if (IS_ERR(ctx)) { |
1036 | mutex_unlock(&dev->struct_mutex); | |
1037 | return PTR_ERR(ctx); | |
1038 | } | |
1039 | ||
1040 | args->size = 0; | |
1041 | switch (args->param) { | |
1042 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
1043 | args->value = ctx->hang_stats.ban_period_seconds; | |
1044 | break; | |
b1b38278 DW |
1045 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1046 | args->value = ctx->flags & CONTEXT_NO_ZEROMAP; | |
1047 | break; | |
fa8848f2 CW |
1048 | case I915_CONTEXT_PARAM_GTT_SIZE: |
1049 | if (ctx->ppgtt) | |
1050 | args->value = ctx->ppgtt->base.total; | |
1051 | else if (to_i915(dev)->mm.aliasing_ppgtt) | |
1052 | args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total; | |
1053 | else | |
62106b4f | 1054 | args->value = to_i915(dev)->ggtt.base.total; |
fa8848f2 | 1055 | break; |
bc3d6744 CW |
1056 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: |
1057 | args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE); | |
1058 | break; | |
c9dc0f35 CW |
1059 | default: |
1060 | ret = -EINVAL; | |
1061 | break; | |
1062 | } | |
1063 | mutex_unlock(&dev->struct_mutex); | |
1064 | ||
1065 | return ret; | |
1066 | } | |
1067 | ||
1068 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
1069 | struct drm_file *file) | |
1070 | { | |
1071 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1072 | struct drm_i915_gem_context_param *args = data; | |
e2efd130 | 1073 | struct i915_gem_context *ctx; |
c9dc0f35 CW |
1074 | int ret; |
1075 | ||
1076 | ret = i915_mutex_lock_interruptible(dev); | |
1077 | if (ret) | |
1078 | return ret; | |
1079 | ||
ca585b5d | 1080 | ctx = i915_gem_context_lookup(file_priv, args->ctx_id); |
c9dc0f35 CW |
1081 | if (IS_ERR(ctx)) { |
1082 | mutex_unlock(&dev->struct_mutex); | |
1083 | return PTR_ERR(ctx); | |
1084 | } | |
1085 | ||
1086 | switch (args->param) { | |
1087 | case I915_CONTEXT_PARAM_BAN_PERIOD: | |
1088 | if (args->size) | |
1089 | ret = -EINVAL; | |
1090 | else if (args->value < ctx->hang_stats.ban_period_seconds && | |
1091 | !capable(CAP_SYS_ADMIN)) | |
1092 | ret = -EPERM; | |
1093 | else | |
1094 | ctx->hang_stats.ban_period_seconds = args->value; | |
1095 | break; | |
b1b38278 DW |
1096 | case I915_CONTEXT_PARAM_NO_ZEROMAP: |
1097 | if (args->size) { | |
1098 | ret = -EINVAL; | |
1099 | } else { | |
1100 | ctx->flags &= ~CONTEXT_NO_ZEROMAP; | |
1101 | ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0; | |
bc3d6744 CW |
1102 | } |
1103 | break; | |
1104 | case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: | |
1105 | if (args->size) { | |
1106 | ret = -EINVAL; | |
1107 | } else { | |
1108 | if (args->value) | |
1109 | ctx->flags |= CONTEXT_NO_ERROR_CAPTURE; | |
1110 | else | |
1111 | ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE; | |
b1b38278 DW |
1112 | } |
1113 | break; | |
c9dc0f35 CW |
1114 | default: |
1115 | ret = -EINVAL; | |
1116 | break; | |
1117 | } | |
1118 | mutex_unlock(&dev->struct_mutex); | |
1119 | ||
1120 | return ret; | |
1121 | } | |
d538704b CW |
1122 | |
1123 | int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, | |
1124 | void *data, struct drm_file *file) | |
1125 | { | |
fac5e23e | 1126 | struct drm_i915_private *dev_priv = to_i915(dev); |
d538704b CW |
1127 | struct drm_i915_reset_stats *args = data; |
1128 | struct i915_ctx_hang_stats *hs; | |
e2efd130 | 1129 | struct i915_gem_context *ctx; |
d538704b CW |
1130 | int ret; |
1131 | ||
1132 | if (args->flags || args->pad) | |
1133 | return -EINVAL; | |
1134 | ||
1135 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) | |
1136 | return -EPERM; | |
1137 | ||
bdb04614 | 1138 | ret = i915_mutex_lock_interruptible(dev); |
d538704b CW |
1139 | if (ret) |
1140 | return ret; | |
1141 | ||
ca585b5d | 1142 | ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id); |
d538704b CW |
1143 | if (IS_ERR(ctx)) { |
1144 | mutex_unlock(&dev->struct_mutex); | |
1145 | return PTR_ERR(ctx); | |
1146 | } | |
1147 | hs = &ctx->hang_stats; | |
1148 | ||
1149 | if (capable(CAP_SYS_ADMIN)) | |
1150 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1151 | else | |
1152 | args->reset_count = 0; | |
1153 | ||
1154 | args->batch_active = hs->batch_active; | |
1155 | args->batch_pending = hs->batch_pending; | |
1156 | ||
1157 | mutex_unlock(&dev->struct_mutex); | |
1158 | ||
1159 | return 0; | |
1160 | } |