[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_gem_tiling.c

/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include <linux/string.h>
#include <linux/bitops.h>
#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"

/**
 * DOC: buffer object tiling
 *
 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
 * declare fence register requirements.
 *
 * In principle GEM doesn't care at all about the internal data layout of an
 * object, and hence it also doesn't care about tiling or swizzling. There's two
 * exceptions:
 *
 * - For X and Y tiling the hardware provides detilers for CPU access, so called
 *   fences. Since there's only a limited amount of them the kernel must manage
 *   these, and therefore userspace must tell the kernel the object tiling if it
 *   wants to use fences for detiling.
 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
 *   depends upon the physical page frame number. When swapping such objects the
 *   page frame number might change and the kernel must be able to fix this up
 *   and hence now the tiling. Note that on a subset of platforms with
 *   asymmetric memory channel population the swizzling pattern changes in an
 *   unknown way, and for those the kernel simply forbids swapping completely.
 *
 * Since neither of this applies for new tiling layouts on modern platforms like
 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
 * Anything else can be handled in userspace entirely without the kernel's
 * invovlement.
 */

/* Check pitch constriants for all chips & tiling formats */
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
	int tile_width;

	/* Linear is always fine */
	if (tiling_mode == I915_TILING_NONE)
		return true;

	if (tiling_mode > I915_TILING_LAST)
		return false;

	if (IS_GEN2(dev) ||
	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
		tile_width = 128;
	else
		tile_width = 512;

	/* check maximum stride & object size */
	/* i965+ stores the end address of the gtt mapping in the fence
	 * reg, so dont bother to check the size */
	if (INTEL_INFO(dev)->gen >= 7) {
		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
			return false;
	} else if (INTEL_INFO(dev)->gen >= 4) {
		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
			return false;
	} else {
		if (stride > 8192)
			return false;

		if (IS_GEN3(dev)) {
			if (size > I830_FENCE_MAX_SIZE_VAL << 20)
				return false;
		} else {
			if (size > I830_FENCE_MAX_SIZE_VAL << 19)
				return false;
		}
	}

	if (stride < tile_width)
		return false;

	/* 965+ just needs multiples of tile width */
	if (INTEL_INFO(dev)->gen >= 4) {
		if (stride & (tile_width - 1))
			return false;
		return true;
	}

	/* Pre-965 needs power of two tile widths */
	if (stride & (stride - 1))
		return false;

	return true;
}

static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
{
	struct drm_i915_private *dev_priv = to_i915(vma->vm->dev);
	u32 size;

	if (!i915_vma_is_map_and_fenceable(vma))
		return true;

	if (INTEL_GEN(dev_priv) == 3) {
		if (vma->node.start & ~I915_FENCE_START_MASK)
			return false;
	} else {
		if (vma->node.start & ~I830_FENCE_START_MASK)
			return false;
	}

	size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode);
	if (vma->node.size < size)
		return false;

	if (vma->node.start & (size - 1))
		return false;

	return true;
}

/* Make the current GTT allocation valid for the change in tiling. */
static int
i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, int tiling_mode)
{
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
	struct i915_vma *vma;
	int ret;

	if (tiling_mode == I915_TILING_NONE)
		return 0;

	if (INTEL_GEN(dev_priv) >= 4)
		return 0;

	list_for_each_entry(vma, &obj->vma_list, obj_link) {
		if (i915_vma_fence_prepare(vma, tiling_mode))
			continue;

		ret = i915_vma_unbind(vma);
		if (ret)
			return ret;
	}

	return 0;
}

/**
 * i915_gem_set_tiling - IOCTL handler to set tiling mode
 * @dev: DRM device
 * @data: data pointer for the ioctl
 * @file: DRM file for the ioctl call
 *
 * Sets the tiling mode of an object, returning the required swizzling of
 * bit 6 of addresses in the object.
 *
 * Called by the user via ioctl.
 *
 * Returns:
 * Zero on success, negative errno on failure.
 */
int
i915_gem_set_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_set_tiling *args = data;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct drm_i915_gem_object *obj;
	int err = 0;

	/* Make sure we don't cross-contaminate obj->tiling_and_stride */
	BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);

	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj)
		return -ENOENT;

	if (!i915_tiling_ok(dev,
			    args->stride, obj->base.size, args->tiling_mode)) {
		i915_gem_object_put_unlocked(obj);
		return -EINVAL;
	}

	intel_runtime_pm_get(dev_priv);

	mutex_lock(&dev->struct_mutex);
	if (obj->pin_display || obj->framebuffer_references) {
		err = -EBUSY;
		goto err;
	}

	if (args->tiling_mode == I915_TILING_NONE) {
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		args->stride = 0;
	} else {
		if (args->tiling_mode == I915_TILING_X)
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		else
			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;

		/* Hide bit 17 swizzling from the user.  This prevents old Mesa
		 * from aborting the application on sw fallbacks to bit 17,
		 * and we use the pread/pwrite bit17 paths to swizzle for it.
		 * If there was a user that was relying on the swizzle
		 * information for drm_intel_bo_map()ed reads/writes this would
		 * break it, but we don't have any of those.
		 */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

		/* If we can't handle the swizzling, make it untiled. */
		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
			args->tiling_mode = I915_TILING_NONE;
			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
			args->stride = 0;
		}
	}

	if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
	    args->stride != i915_gem_object_get_stride(obj)) {
		/* We need to rebind the object if its current allocation
		 * no longer meets the alignment restrictions for its new
		 * tiling mode. Otherwise we can just leave it alone, but
		 * need to ensure that any fence register is updated before
		 * the next fenced (either through the GTT or by the BLT unit
		 * on older GPUs) access.
		 *
		 * After updating the tiling parameters, we then flag whether
		 * we need to update an associated fence register. Note this
		 * has to also include the unfenced register the GPU uses
		 * whilst executing a fenced command for an untiled object.
		 */

		err = i915_gem_object_fence_prepare(obj, args->tiling_mode);
		if (!err) {
			struct i915_vma *vma;

			if (obj->pages &&
			    obj->madv == I915_MADV_WILLNEED &&
			    dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
				if (args->tiling_mode == I915_TILING_NONE)
					i915_gem_object_unpin_pages(obj);
				if (!i915_gem_object_is_tiled(obj))
					i915_gem_object_pin_pages(obj);
			}

			list_for_each_entry(vma, &obj->vma_list, obj_link) {
				if (!vma->fence)
					continue;

				vma->fence->dirty = true;
			}
			obj->tiling_and_stride =
				args->stride | args->tiling_mode;

			/* Force the fence to be reacquired for GTT access */
			i915_gem_release_mmap(obj);
		}
	}
	/* we have to maintain this existing ABI... */
	args->stride = i915_gem_object_get_stride(obj);
	args->tiling_mode = i915_gem_object_get_tiling(obj);

	/* Try to preallocate memory required to save swizzling on put-pages */
	if (i915_gem_object_needs_bit17_swizzle(obj)) {
		if (obj->bit_17 == NULL) {
			obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
					      sizeof(long), GFP_KERNEL);
		}
	} else {
		kfree(obj->bit_17);
		obj->bit_17 = NULL;
	}

err:
	i915_gem_object_put(obj);
	mutex_unlock(&dev->struct_mutex);

	intel_runtime_pm_put(dev_priv);

	return err;
}

/**
 * i915_gem_get_tiling - IOCTL handler to get tiling mode
 * @dev: DRM device
 * @data: data pointer for the ioctl
 * @file: DRM file for the ioctl call
 *
 * Returns the current tiling mode and required bit 6 swizzling for the object.
 *
 * Called by the user via ioctl.
 *
 * Returns:
 * Zero on success, negative errno on failure.
 */
int
i915_gem_get_tiling(struct drm_device *dev, void *data,
		   struct drm_file *file)
{
	struct drm_i915_gem_get_tiling *args = data;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct drm_i915_gem_object *obj;

	obj = i915_gem_object_lookup(file, args->handle);
	if (!obj)
		return -ENOENT;

	args->tiling_mode = READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
	switch (args->tiling_mode) {
	case I915_TILING_X:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
		break;
	case I915_TILING_Y:
		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
		break;
	case I915_TILING_NONE:
		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
		break;
	default:
		DRM_ERROR("unknown tiling mode\n");
	}

	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
		args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
	else
		args->phys_swizzle_mode = args->swizzle_mode;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;

	i915_gem_object_put_unlocked(obj);
	return 0;
}
Commit	Line	Data
673a394b EA	1	/*
	2	* Copyright © 2008 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*
	26	*/
	27
760285e7 DH	28	#include <linux/string.h>
	29	#include <linux/bitops.h>
	30	#include <drm/drmP.h>
	31	#include <drm/i915_drm.h>
673a394b EA	32	#include "i915_drv.h"
673a394b EA	33
3271dca4 DV	34	/**
3271dca4 DV	35	* DOC: buffer object tiling
673a394b	36	*
3271dca4 DV	37	* i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
3271dca4 DV	38	* declare fence register requirements.
673a394b	39	*
3271dca4 DV	40	* In principle GEM doesn't care at all about the internal data layout of an
	41	* object, and hence it also doesn't care about tiling or swizzling. There's two
	42	* exceptions:
673a394b	43	*
3271dca4 DV	44	* - For X and Y tiling the hardware provides detilers for CPU access, so called
	45	* fences. Since there's only a limited amount of them the kernel must manage
	46	* these, and therefore userspace must tell the kernel the object tiling if it
	47	* wants to use fences for detiling.
	48	* - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
	49	* depends upon the physical page frame number. When swapping such objects the
	50	* page frame number might change and the kernel must be able to fix this up
	51	* and hence now the tiling. Note that on a subset of platforms with
	52	* asymmetric memory channel population the swizzling pattern changes in an
	53	* unknown way, and for those the kernel simply forbids swapping completely.
673a394b	54	*
3271dca4 DV	55	* Since neither of this applies for new tiling layouts on modern platforms like
	56	* W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
	57	* Anything else can be handled in userspace entirely without the kernel's
	58	* invovlement.
673a394b EA	59	*/
673a394b EA	60
0f973f27	61	/* Check pitch constriants for all chips & tiling formats */
a00b10c3	62	static bool
0f973f27 JB	63	i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
0f973f27 JB	64	{
0ee537ab	65	int tile_width;
0f973f27 JB	66
	67	/* Linear is always fine */
	68	if (tiling_mode == I915_TILING_NONE)
	69	return true;
	70
deeb1519 CW	71	if (tiling_mode > I915_TILING_LAST)
	72	return false;
	73
a6c45cf0	74	if (IS_GEN2(dev) \|\|
e76a16de	75	(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
0f973f27 JB	76	tile_width = 128;
	77	else
	78	tile_width = 512;
	79
8d7773a3	80	/* check maximum stride & object size */
3a062478 VS	81	/* i965+ stores the end address of the gtt mapping in the fence
	82	* reg, so dont bother to check the size */
	83	if (INTEL_INFO(dev)->gen >= 7) {
	84	if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
	85	return false;
	86	} else if (INTEL_INFO(dev)->gen >= 4) {
8d7773a3 DV	87	if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
8d7773a3 DV	88	return false;
a6c45cf0	89	} else {
c36a2a6d	90	if (stride > 8192)
8d7773a3	91	return false;
e76a16de	92
c36a2a6d DV	93	if (IS_GEN3(dev)) {
	94	if (size > I830_FENCE_MAX_SIZE_VAL << 20)
	95	return false;
	96	} else {
	97	if (size > I830_FENCE_MAX_SIZE_VAL << 19)
	98	return false;
	99	}
8d7773a3 DV	100	}
8d7773a3 DV	101
fe48d8de VS	102	if (stride < tile_width)
	103	return false;
	104
0f973f27	105	/* 965+ just needs multiples of tile width */
a6c45cf0	106	if (INTEL_INFO(dev)->gen >= 4) {
0f973f27 JB	107	if (stride & (tile_width - 1))
	108	return false;
	109	return true;
	110	}
	111
	112	/* Pre-965 needs power of two tile widths */
0f973f27 JB	113	if (stride & (stride - 1))
	114	return false;
	115
0f973f27 JB	116	return true;
	117	}
	118
49ef5294 CW	119	static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
	120	{
	121	struct drm_i915_private *dev_priv = to_i915(vma->vm->dev);
	122	u32 size;
	123
	124	if (!i915_vma_is_map_and_fenceable(vma))
	125	return true;
	126
	127	if (INTEL_GEN(dev_priv) == 3) {
	128	if (vma->node.start & ~I915_FENCE_START_MASK)
	129	return false;
	130	} else {
	131	if (vma->node.start & ~I830_FENCE_START_MASK)
	132	return false;
	133	}
	134
	135	size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode);
	136	if (vma->node.size < size)
	137	return false;
	138
	139	if (vma->node.start & (size - 1))
	140	return false;
	141
	142	return true;
	143	}
	144
f23eda8c CW	145	/* Make the current GTT allocation valid for the change in tiling. */
	146	static int
	147	i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, int tiling_mode)
52dc7d32	148	{
a9f1481f	149	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
f23eda8c	150	struct i915_vma *vma;
49ef5294	151	int ret;
52dc7d32 CW	152
52dc7d32 CW	153	if (tiling_mode == I915_TILING_NONE)
f23eda8c	154	return 0;
52dc7d32	155
a9f1481f	156	if (INTEL_GEN(dev_priv) >= 4)
f23eda8c CW	157	return 0;
f23eda8c CW	158
49ef5294 CW	159	list_for_each_entry(vma, &obj->vma_list, obj_link) {
	160	if (i915_vma_fence_prepare(vma, tiling_mode))
	161	continue;
a6c45cf0	162
49ef5294 CW	163	ret = i915_vma_unbind(vma);
	164	if (ret)
	165	return ret;
df153158 CW	166	}
df153158 CW	167
f23eda8c	168	return 0;
52dc7d32 CW	169	}
52dc7d32 CW	170
673a394b	171	/**
3271dca4 DV	172	* i915_gem_set_tiling - IOCTL handler to set tiling mode
	173	* @dev: DRM device
	174	* @data: data pointer for the ioctl
	175	* @file: DRM file for the ioctl call
	176	*
673a394b EA	177	* Sets the tiling mode of an object, returning the required swizzling of
673a394b EA	178	* bit 6 of addresses in the object.
3271dca4 DV	179	*
	180	* Called by the user via ioctl.
	181	*
	182	* Returns:
	183	* Zero on success, negative errno on failure.
673a394b EA	184	*/
	185	int
	186	i915_gem_set_tiling(struct drm_device dev, void data,
05394f39	187	struct drm_file *file)
673a394b EA	188	{
673a394b EA	189	struct drm_i915_gem_set_tiling *args = data;
fac5e23e	190	struct drm_i915_private *dev_priv = to_i915(dev);
05394f39	191	struct drm_i915_gem_object *obj;
f23eda8c	192	int err = 0;
673a394b	193
3e510a8e CW	194	/* Make sure we don't cross-contaminate obj->tiling_and_stride */
	195	BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
	196
03ac0642 CW	197	obj = i915_gem_object_lookup(file, args->handle);
03ac0642 CW	198	if (!obj)
bf79cb91	199	return -ENOENT;
673a394b	200
05394f39 CW	201	if (!i915_tiling_ok(dev,
05394f39 CW	202	args->stride, obj->base.size, args->tiling_mode)) {
34911fd3	203	i915_gem_object_put_unlocked(obj);
0f973f27	204	return -EINVAL;
72daad40	205	}
0f973f27	206
e64e6bd0 ID	207	intel_runtime_pm_get(dev_priv);
e64e6bd0 ID	208
6c31a614	209	mutex_lock(&dev->struct_mutex);
1f30a614	210	if (obj->pin_display \|\| obj->framebuffer_references) {
f23eda8c	211	err = -EBUSY;
6c31a614	212	goto err;
31770bd4 DV	213	}
31770bd4 DV	214
673a394b	215	if (args->tiling_mode == I915_TILING_NONE) {
673a394b	216	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	217	args->stride = 0;
673a394b EA	218	} else {
	219	if (args->tiling_mode == I915_TILING_X)
	220	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	221	else
	222	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
280b713b EA	223
	224	/* Hide bit 17 swizzling from the user. This prevents old Mesa
	225	* from aborting the application on sw fallbacks to bit 17,
	226	* and we use the pread/pwrite bit17 paths to swizzle for it.
	227	* If there was a user that was relying on the swizzle
	228	* information for drm_intel_bo_map()ed reads/writes this would
	229	* break it, but we don't have any of those.
	230	*/
	231	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	232	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	233	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	234	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	235
673a394b EA	236	/* If we can't handle the swizzling, make it untiled. */
	237	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
	238	args->tiling_mode = I915_TILING_NONE;
	239	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
52dc7d32	240	args->stride = 0;
673a394b EA	241	}
673a394b EA	242	}
0f973f27	243
3e510a8e CW	244	if (args->tiling_mode != i915_gem_object_get_tiling(obj) \|\|
3e510a8e CW	245	args->stride != i915_gem_object_get_stride(obj)) {
52dc7d32 CW	246	/* We need to rebind the object if its current allocation
	247	* no longer meets the alignment restrictions for its new
	248	* tiling mode. Otherwise we can just leave it alone, but
1869b620 CW	249	* need to ensure that any fence register is updated before
	250	* the next fenced (either through the GTT or by the BLT unit
	251	* on older GPUs) access.
5d82e3e6 CW	252	*
	253	* After updating the tiling parameters, we then flag whether
	254	* we need to update an associated fence register. Note this
	255	* has to also include the unfenced register the GPU uses
	256	* whilst executing a fenced command for an untiled object.
0f973f27	257	*/
467cffba	258
f23eda8c CW	259	err = i915_gem_object_fence_prepare(obj, args->tiling_mode);
f23eda8c CW	260	if (!err) {
49ef5294 CW	261	struct i915_vma *vma;
49ef5294 CW	262
656bfa3a DV	263	if (obj->pages &&
	264	obj->madv == I915_MADV_WILLNEED &&
	265	dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
	266	if (args->tiling_mode == I915_TILING_NONE)
	267	i915_gem_object_unpin_pages(obj);
3e510a8e	268	if (!i915_gem_object_is_tiled(obj))
656bfa3a DV	269	i915_gem_object_pin_pages(obj);
	270	}
	271
49ef5294 CW	272	list_for_each_entry(vma, &obj->vma_list, obj_link) {
	273	if (!vma->fence)
	274	continue;
5d82e3e6	275
49ef5294 CW	276	vma->fence->dirty = true;
49ef5294 CW	277	}
3e510a8e CW	278	obj->tiling_and_stride =
3e510a8e CW	279	args->stride \| args->tiling_mode;
1869b620 CW	280
	281	/* Force the fence to be reacquired for GTT access */
	282	i915_gem_release_mmap(obj);
467cffba	283	}
0f973f27	284	}
467cffba	285	/* we have to maintain this existing ABI... */
3e510a8e CW	286	args->stride = i915_gem_object_get_stride(obj);
3e510a8e CW	287	args->tiling_mode = i915_gem_object_get_tiling(obj);
e9b73c67 CW	288
	289	/* Try to preallocate memory required to save swizzling on put-pages */
	290	if (i915_gem_object_needs_bit17_swizzle(obj)) {
	291	if (obj->bit_17 == NULL) {
a1e22653	292	obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
e9b73c67 CW	293	sizeof(long), GFP_KERNEL);
	294	}
	295	} else {
	296	kfree(obj->bit_17);
	297	obj->bit_17 = NULL;
	298	}
	299
6c31a614	300	err:
f8c417cd	301	i915_gem_object_put(obj);
d6873102	302	mutex_unlock(&dev->struct_mutex);
673a394b	303
e64e6bd0 ID	304	intel_runtime_pm_put(dev_priv);
e64e6bd0 ID	305
f23eda8c	306	return err;
673a394b EA	307	}
	308
	309	/**
3271dca4 DV	310	* i915_gem_get_tiling - IOCTL handler to get tiling mode
	311	* @dev: DRM device
	312	* @data: data pointer for the ioctl
	313	* @file: DRM file for the ioctl call
	314	*
673a394b	315	* Returns the current tiling mode and required bit 6 swizzling for the object.
3271dca4 DV	316	*
	317	* Called by the user via ioctl.
	318	*
	319	* Returns:
	320	* Zero on success, negative errno on failure.
673a394b EA	321	*/
	322	int
	323	i915_gem_get_tiling(struct drm_device dev, void data,
05394f39	324	struct drm_file *file)
673a394b EA	325	{
673a394b EA	326	struct drm_i915_gem_get_tiling *args = data;
fac5e23e	327	struct drm_i915_private *dev_priv = to_i915(dev);
05394f39	328	struct drm_i915_gem_object *obj;
673a394b	329
03ac0642 CW	330	obj = i915_gem_object_lookup(file, args->handle);
03ac0642 CW	331	if (!obj)
bf79cb91	332	return -ENOENT;
673a394b	333
3e510a8e	334	args->tiling_mode = READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
9ad36761	335	switch (args->tiling_mode) {
673a394b EA	336	case I915_TILING_X:
	337	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
	338	break;
	339	case I915_TILING_Y:
	340	args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
	341	break;
	342	case I915_TILING_NONE:
	343	args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
	344	break;
	345	default:
	346	DRM_ERROR("unknown tiling mode\n");
	347	}
	348
280b713b	349	/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
5eb3e5a5 CW	350	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
	351	args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
	352	else
	353	args->phys_swizzle_mode = args->swizzle_mode;
280b713b EA	354	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
	355	args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
	356	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
	357	args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
	358
9ad36761	359	i915_gem_object_put_unlocked(obj);
673a394b EA	360	return 0;
673a394b EA	361	}