projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 585fb111 JB |
1 | /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 2 | * All Rights Reserved. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the | |
| 6 | * "Software"), to deal in the Software without restriction, including | |
| 7 | * without limitation the rights to use, copy, modify, merge, publish, | |
| 8 | * distribute, sub license, and/or sell copies of the Software, and to | |
| 9 | * permit persons to whom the Software is furnished to do so, subject to | |
| 10 | * the following conditions: | |
| 11 | * | |
| 12 | * The above copyright notice and this permission notice (including the | |
| 13 | * next paragraph) shall be included in all copies or substantial portions | |
| 14 | * of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
| 19 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
| 20 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
| 21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
| 22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef _I915_REG_H_ | |
| 26 | #define _I915_REG_H_ | |
| 27 | ||
| 5eddb70b | 28 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) |
| 70d21f0e | 29 | #define _PLANE(plane, a, b) _PIPE(plane, a, b) |
| a5c961d1 | 30 | #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) |
| 2b139522 | 31 | #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) |
| 2d401b17 VS |
32 | #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ |
| 33 | (pipe) == PIPE_B ? (b) : (c)) | |
| e7d7cad0 JN |
34 | #define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \ |
| 35 | (port) == PORT_B ? (b) : (c)) | |
| 2b139522 | 36 | |
| 6b26c86d DV |
37 | #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) |
| 38 | #define _MASKED_BIT_DISABLE(a) ((a) << 16) | |
| 39 | ||
| 585fb111 JB |
40 | /* PCI config space */ |
| 41 | ||
| 42 | #define HPLLCC 0xc0 /* 855 only */ | |
| 652c393a | 43 | #define GC_CLOCK_CONTROL_MASK (0xf << 0) |
| 585fb111 JB |
44 | #define GC_CLOCK_133_200 (0 << 0) |
| 45 | #define GC_CLOCK_100_200 (1 << 0) | |
| 46 | #define GC_CLOCK_100_133 (2 << 0) | |
| 47 | #define GC_CLOCK_166_250 (3 << 0) | |
| f97108d1 | 48 | #define GCFGC2 0xda |
| 585fb111 JB |
49 | #define GCFGC 0xf0 /* 915+ only */ |
| 50 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | |
| 51 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
| 52 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) | |
| 257a7ffc DV |
53 | #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) |
| 54 | #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) | |
| 55 | #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) | |
| 56 | #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) | |
| 57 | #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) | |
| 58 | #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) | |
| 585fb111 | 59 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
| 652c393a JB |
60 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
| 61 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) | |
| 62 | #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) | |
| 63 | #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) | |
| 64 | #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) | |
| 65 | #define I965_GC_RENDER_CLOCK_MASK (0xf << 0) | |
| 66 | #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) | |
| 67 | #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) | |
| 68 | #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) | |
| 69 | #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) | |
| 70 | #define I945_GC_RENDER_CLOCK_MASK (7 << 0) | |
| 71 | #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
| 72 | #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
| 73 | #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) | |
| 74 | #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) | |
| 75 | #define I915_GC_RENDER_CLOCK_MASK (7 << 0) | |
| 76 | #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) | |
| 77 | #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) | |
| 78 | #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) | |
| 7f1bdbcb DV |
79 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ |
| 80 | ||
| eeccdcac KG |
81 | |
| 82 | /* Graphics reset regs */ | |
| 59ea9054 | 83 | #define I915_GDRST 0xc0 /* PCI config register */ |
| eeccdcac KG |
84 | #define GRDOM_FULL (0<<2) |
| 85 | #define GRDOM_RENDER (1<<2) | |
| 86 | #define GRDOM_MEDIA (3<<2) | |
| 8a5c2ae7 | 87 | #define GRDOM_MASK (3<<2) |
| 73bbf6bd | 88 | #define GRDOM_RESET_STATUS (1<<1) |
| 5ccce180 | 89 | #define GRDOM_RESET_ENABLE (1<<0) |
| 585fb111 | 90 | |
| b3a3f03d VS |
91 | #define ILK_GDSR 0x2ca4 /* MCHBAR offset */ |
| 92 | #define ILK_GRDOM_FULL (0<<1) | |
| 93 | #define ILK_GRDOM_RENDER (1<<1) | |
| 94 | #define ILK_GRDOM_MEDIA (3<<1) | |
| 95 | #define ILK_GRDOM_MASK (3<<1) | |
| 96 | #define ILK_GRDOM_RESET_ENABLE (1<<0) | |
| 97 | ||
| 07b7ddd9 JB |
98 | #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ |
| 99 | #define GEN6_MBC_SNPCR_SHIFT 21 | |
| 100 | #define GEN6_MBC_SNPCR_MASK (3<<21) | |
| 101 | #define GEN6_MBC_SNPCR_MAX (0<<21) | |
| 102 | #define GEN6_MBC_SNPCR_MED (1<<21) | |
| 103 | #define GEN6_MBC_SNPCR_LOW (2<<21) | |
| 104 | #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ | |
| 105 | ||
| 9e72b46c ID |
106 | #define VLV_G3DCTL 0x9024 |
| 107 | #define VLV_GSCKGCTL 0x9028 | |
| 108 | ||
| 5eb719cd DV |
109 | #define GEN6_MBCTL 0x0907c |
| 110 | #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) | |
| 111 | #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) | |
| 112 | #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) | |
| 113 | #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) | |
| 114 | #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) | |
| 115 | ||
| cff458c2 EA |
116 | #define GEN6_GDRST 0x941c |
| 117 | #define GEN6_GRDOM_FULL (1 << 0) | |
| 118 | #define GEN6_GRDOM_RENDER (1 << 1) | |
| 119 | #define GEN6_GRDOM_MEDIA (1 << 2) | |
| 120 | #define GEN6_GRDOM_BLT (1 << 3) | |
| 121 | ||
| 5eb719cd DV |
122 | #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) |
| 123 | #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) | |
| 124 | #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) | |
| 125 | #define PP_DIR_DCLV_2G 0xffffffff | |
| 126 | ||
| 94e409c1 BW |
127 | #define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) |
| 128 | #define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) | |
| 129 | ||
| 5eb719cd DV |
130 | #define GAM_ECOCHK 0x4090 |
| 131 | #define ECOCHK_SNB_BIT (1<<10) | |
| e3dff585 | 132 | #define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) |
| 5eb719cd DV |
133 | #define ECOCHK_PPGTT_CACHE64B (0x3<<3) |
| 134 | #define ECOCHK_PPGTT_CACHE4B (0x0<<3) | |
| a6f429a5 VS |
135 | #define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) |
| 136 | #define ECOCHK_PPGTT_LLC_IVB (0x1<<3) | |
| 137 | #define ECOCHK_PPGTT_UC_HSW (0x1<<3) | |
| 138 | #define ECOCHK_PPGTT_WT_HSW (0x2<<3) | |
| 139 | #define ECOCHK_PPGTT_WB_HSW (0x3<<3) | |
| 5eb719cd | 140 | |
| 48ecfa10 | 141 | #define GAC_ECO_BITS 0x14090 |
| 3b9d7888 | 142 | #define ECOBITS_SNB_BIT (1<<13) |
| 48ecfa10 DV |
143 | #define ECOBITS_PPGTT_CACHE64B (3<<8) |
| 144 | #define ECOBITS_PPGTT_CACHE4B (0<<8) | |
| 145 | ||
| be901a5a DV |
146 | #define GAB_CTL 0x24000 |
| 147 | #define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) | |
| 148 | ||
| 40bae736 DV |
149 | #define GEN7_BIOS_RESERVED 0x1082C0 |
| 150 | #define GEN7_BIOS_RESERVED_1M (0 << 5) | |
| 151 | #define GEN7_BIOS_RESERVED_256K (1 << 5) | |
| 152 | #define GEN8_BIOS_RESERVED_SHIFT 7 | |
| 153 | #define GEN7_BIOS_RESERVED_MASK 0x1 | |
| 154 | #define GEN8_BIOS_RESERVED_MASK 0x3 | |
| 155 | ||
| 156 | ||
| 585fb111 JB |
157 | /* VGA stuff */ |
| 158 | ||
| 159 | #define VGA_ST01_MDA 0x3ba | |
| 160 | #define VGA_ST01_CGA 0x3da | |
| 161 | ||
| 162 | #define VGA_MSR_WRITE 0x3c2 | |
| 163 | #define VGA_MSR_READ 0x3cc | |
| 164 | #define VGA_MSR_MEM_EN (1<<1) | |
| 165 | #define VGA_MSR_CGA_MODE (1<<0) | |
| 166 | ||
| 5434fd92 | 167 | #define VGA_SR_INDEX 0x3c4 |
| f930ddd0 | 168 | #define SR01 1 |
| 5434fd92 | 169 | #define VGA_SR_DATA 0x3c5 |
| 585fb111 JB |
170 | |
| 171 | #define VGA_AR_INDEX 0x3c0 | |
| 172 | #define VGA_AR_VID_EN (1<<5) | |
| 173 | #define VGA_AR_DATA_WRITE 0x3c0 | |
| 174 | #define VGA_AR_DATA_READ 0x3c1 | |
| 175 | ||
| 176 | #define VGA_GR_INDEX 0x3ce | |
| 177 | #define VGA_GR_DATA 0x3cf | |
| 178 | /* GR05 */ | |
| 179 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 | |
| 180 | #define VGA_GR_MEM_READ_MODE_PLANE 1 | |
| 181 | /* GR06 */ | |
| 182 | #define VGA_GR_MEM_MODE_MASK 0xc | |
| 183 | #define VGA_GR_MEM_MODE_SHIFT 2 | |
| 184 | #define VGA_GR_MEM_A0000_AFFFF 0 | |
| 185 | #define VGA_GR_MEM_A0000_BFFFF 1 | |
| 186 | #define VGA_GR_MEM_B0000_B7FFF 2 | |
| 187 | #define VGA_GR_MEM_B0000_BFFFF 3 | |
| 188 | ||
| 189 | #define VGA_DACMASK 0x3c6 | |
| 190 | #define VGA_DACRX 0x3c7 | |
| 191 | #define VGA_DACWX 0x3c8 | |
| 192 | #define VGA_DACDATA 0x3c9 | |
| 193 | ||
| 194 | #define VGA_CR_INDEX_MDA 0x3b4 | |
| 195 | #define VGA_CR_DATA_MDA 0x3b5 | |
| 196 | #define VGA_CR_INDEX_CGA 0x3d4 | |
| 197 | #define VGA_CR_DATA_CGA 0x3d5 | |
| 198 | ||
| 351e3db2 BV |
199 | /* |
| 200 | * Instruction field definitions used by the command parser | |
| 201 | */ | |
| 202 | #define INSTR_CLIENT_SHIFT 29 | |
| 203 | #define INSTR_CLIENT_MASK 0xE0000000 | |
| 204 | #define INSTR_MI_CLIENT 0x0 | |
| 205 | #define INSTR_BC_CLIENT 0x2 | |
| 206 | #define INSTR_RC_CLIENT 0x3 | |
| 207 | #define INSTR_SUBCLIENT_SHIFT 27 | |
| 208 | #define INSTR_SUBCLIENT_MASK 0x18000000 | |
| 209 | #define INSTR_MEDIA_SUBCLIENT 0x2 | |
| 210 | ||
| 585fb111 JB |
211 | /* |
| 212 | * Memory interface instructions used by the kernel | |
| 213 | */ | |
| 214 | #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) | |
| d4d48035 BV |
215 | /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ |
| 216 | #define MI_GLOBAL_GTT (1<<22) | |
| 585fb111 JB |
217 | |
| 218 | #define MI_NOOP MI_INSTR(0, 0) | |
| 219 | #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) | |
| 220 | #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) | |
| 02e792fb | 221 | #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
| 585fb111 JB |
222 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
| 223 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) | |
| 224 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | |
| 225 | #define MI_FLUSH MI_INSTR(0x04, 0) | |
| 226 | #define MI_READ_FLUSH (1 << 0) | |
| 227 | #define MI_EXE_FLUSH (1 << 1) | |
| 228 | #define MI_NO_WRITE_FLUSH (1 << 2) | |
| 229 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ | |
| 230 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | |
| 1cafd347 | 231 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ |
| 0e79284d BW |
232 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
| 233 | #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) | |
| 234 | #define MI_ARB_ENABLE (1<<0) | |
| 235 | #define MI_ARB_DISABLE (0<<0) | |
| 585fb111 | 236 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
| 88271da3 JB |
237 | #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) |
| 238 | #define MI_SUSPEND_FLUSH_EN (1<<0) | |
| 0206e353 | 239 | #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) |
| 02e792fb DV |
240 | #define MI_OVERLAY_CONTINUE (0x0<<21) |
| 241 | #define MI_OVERLAY_ON (0x1<<21) | |
| 242 | #define MI_OVERLAY_OFF (0x2<<21) | |
| 585fb111 | 243 | #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) |
| 6b95a207 | 244 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
| 1afe3e9d | 245 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
| 6b95a207 | 246 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
| cb05d8de DV |
247 | /* IVB has funny definitions for which plane to flip. */ |
| 248 | #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) | |
| 249 | #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) | |
| 250 | #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) | |
| 251 | #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) | |
| 252 | #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) | |
| 253 | #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) | |
| 830c81db DL |
254 | /* SKL ones */ |
| 255 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) | |
| 256 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) | |
| 257 | #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) | |
| 258 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) | |
| 259 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) | |
| 260 | #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) | |
| 261 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) | |
| 262 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) | |
| 263 | #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) | |
| 3e78998a | 264 | #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ |
| 0e79284d BW |
265 | #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) |
| 266 | #define MI_SEMAPHORE_UPDATE (1<<21) | |
| 267 | #define MI_SEMAPHORE_COMPARE (1<<20) | |
| 268 | #define MI_SEMAPHORE_REGISTER (1<<18) | |
| 269 | #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ | |
| 270 | #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ | |
| 271 | #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ | |
| 272 | #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ | |
| 273 | #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ | |
| 274 | #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ | |
| 275 | #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ | |
| 276 | #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ | |
| 277 | #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ | |
| 278 | #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ | |
| 279 | #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ | |
| 280 | #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ | |
| a028c4b0 DV |
281 | #define MI_SEMAPHORE_SYNC_INVALID (3<<16) |
| 282 | #define MI_SEMAPHORE_SYNC_MASK (3<<16) | |
| aa40d6bb ZN |
283 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) |
| 284 | #define MI_MM_SPACE_GTT (1<<8) | |
| 285 | #define MI_MM_SPACE_PHYSICAL (0<<8) | |
| 286 | #define MI_SAVE_EXT_STATE_EN (1<<3) | |
| 287 | #define MI_RESTORE_EXT_STATE_EN (1<<2) | |
| 88271da3 | 288 | #define MI_FORCE_RESTORE (1<<1) |
| aa40d6bb | 289 | #define MI_RESTORE_INHIBIT (1<<0) |
| 3e78998a BW |
290 | #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ |
| 291 | #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) | |
| 5ee426ca BW |
292 | #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ |
| 293 | #define MI_SEMAPHORE_POLL (1<<15) | |
| 294 | #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) | |
| 585fb111 | 295 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
| 4da46e1e | 296 | #define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2) |
| 585fb111 JB |
297 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
| 298 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) | |
| 299 | #define MI_STORE_DWORD_INDEX_SHIFT 2 | |
| c6642782 DV |
300 | /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: |
| 301 | * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw | |
| 302 | * simply ignores the register load under certain conditions. | |
| 303 | * - One can actually load arbitrary many arbitrary registers: Simply issue x | |
| 304 | * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! | |
| 305 | */ | |
| 7ec55f46 | 306 | #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) |
| 8670d6f9 | 307 | #define MI_LRI_FORCE_POSTED (1<<12) |
| 7ec55f46 | 308 | #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) |
| b76bfeba | 309 | #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) |
| 0e79284d | 310 | #define MI_SRM_LRM_GLOBAL_GTT (1<<22) |
| 71a77e07 | 311 | #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ |
| 9a289771 JB |
312 | #define MI_FLUSH_DW_STORE_INDEX (1<<21) |
| 313 | #define MI_INVALIDATE_TLB (1<<18) | |
| 314 | #define MI_FLUSH_DW_OP_STOREDW (1<<14) | |
| d4d48035 | 315 | #define MI_FLUSH_DW_OP_MASK (3<<14) |
| b18b396b | 316 | #define MI_FLUSH_DW_NOTIFY (1<<8) |
| 9a289771 JB |
317 | #define MI_INVALIDATE_BSD (1<<7) |
| 318 | #define MI_FLUSH_DW_USE_GTT (1<<2) | |
| 319 | #define MI_FLUSH_DW_USE_PPGTT (0<<2) | |
| 585fb111 | 320 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
| d7d4eedd CW |
321 | #define MI_BATCH_NON_SECURE (1) |
| 322 | /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ | |
| 0e79284d | 323 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
| d7d4eedd | 324 | #define MI_BATCH_PPGTT_HSW (1<<8) |
| 0e79284d | 325 | #define MI_BATCH_NON_SECURE_HSW (1<<13) |
| 585fb111 | 326 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
| 65f56876 | 327 | #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ |
| 1c7a0623 | 328 | #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) |
| 0e79284d | 329 | |
| f1f55cc0 NR |
330 | #define MI_PREDICATE_SRC0 (0x2400) |
| 331 | #define MI_PREDICATE_SRC1 (0x2408) | |
| 9435373e RV |
332 | |
| 333 | #define MI_PREDICATE_RESULT_2 (0x2214) | |
| 334 | #define LOWER_SLICE_ENABLED (1<<0) | |
| 335 | #define LOWER_SLICE_DISABLED (0<<0) | |
| 336 | ||
| 585fb111 JB |
337 | /* |
| 338 | * 3D instructions used by the kernel | |
| 339 | */ | |
| 340 | #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) | |
| 341 | ||
| 342 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) | |
| 343 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
| 344 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
| 345 | #define SC_ENABLE_MASK (0x1<<0) | |
| 346 | #define SC_ENABLE (0x1<<0) | |
| 347 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) | |
| 348 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) | |
| 349 | #define SCI_YMIN_MASK (0xffff<<16) | |
| 350 | #define SCI_XMIN_MASK (0xffff<<0) | |
| 351 | #define SCI_YMAX_MASK (0xffff<<16) | |
| 352 | #define SCI_XMAX_MASK (0xffff<<0) | |
| 353 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
| 354 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) | |
| 355 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
| 356 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
| 357 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) | |
| 358 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
| 359 | #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) | |
| 360 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
| 361 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) | |
| c4d69da1 CW |
362 | |
| 363 | #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) | |
| 364 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) | |
| 585fb111 JB |
365 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
| 366 | #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) | |
| c4d69da1 CW |
367 | #define BLT_WRITE_A (2<<20) |
| 368 | #define BLT_WRITE_RGB (1<<20) | |
| 369 | #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) | |
| 585fb111 JB |
370 | #define BLT_DEPTH_8 (0<<24) |
| 371 | #define BLT_DEPTH_16_565 (1<<24) | |
| 372 | #define BLT_DEPTH_16_1555 (2<<24) | |
| 373 | #define BLT_DEPTH_32 (3<<24) | |
| c4d69da1 CW |
374 | #define BLT_ROP_SRC_COPY (0xcc<<16) |
| 375 | #define BLT_ROP_COLOR_COPY (0xf0<<16) | |
| 585fb111 JB |
376 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ |
| 377 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ | |
| 378 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) | |
| 379 | #define ASYNC_FLIP (1<<22) | |
| 380 | #define DISPLAY_PLANE_A (0<<20) | |
| 381 | #define DISPLAY_PLANE_B (1<<20) | |
| fcbc34e4 | 382 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
| b9e1faa7 | 383 | #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ |
| f0a346bd | 384 | #define PIPE_CONTROL_MMIO_WRITE (1<<23) |
| 114d4f70 | 385 | #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) |
| 8d315287 | 386 | #define PIPE_CONTROL_CS_STALL (1<<20) |
| cc0f6398 | 387 | #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) |
| 9d971b37 | 388 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
| d4d48035 | 389 | #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) |
| 9d971b37 KG |
390 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
| 391 | #define PIPE_CONTROL_WRITE_FLUSH (1<<12) | |
| 8d315287 | 392 | #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ |
| 9d971b37 KG |
393 | #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ |
| 394 | #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ | |
| 395 | #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) | |
| 396 | #define PIPE_CONTROL_NOTIFY (1<<8) | |
| 3e78998a | 397 | #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ |
| 8d315287 JB |
398 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) |
| 399 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) | |
| 400 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) | |
| 9d971b37 | 401 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) |
| 8d315287 | 402 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) |
| e552eb70 | 403 | #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ |
| 585fb111 | 404 | |
| 3a6fa984 BV |
405 | /* |
| 406 | * Commands used only by the command parser | |
| 407 | */ | |
| 408 | #define MI_SET_PREDICATE MI_INSTR(0x01, 0) | |
| 409 | #define MI_ARB_CHECK MI_INSTR(0x05, 0) | |
| 410 | #define MI_RS_CONTROL MI_INSTR(0x06, 0) | |
| 411 | #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) | |
| 412 | #define MI_PREDICATE MI_INSTR(0x0C, 0) | |
| 413 | #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) | |
| 414 | #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) | |
| 9c640d1d | 415 | #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) |
| 3a6fa984 BV |
416 | #define MI_URB_CLEAR MI_INSTR(0x19, 0) |
| 417 | #define MI_UPDATE_GTT MI_INSTR(0x23, 0) | |
| 418 | #define MI_CLFLUSH MI_INSTR(0x27, 0) | |
| d4d48035 BV |
419 | #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) |
| 420 | #define MI_REPORT_PERF_COUNT_GGTT (1<<0) | |
| 3a6fa984 BV |
421 | #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) |
| 422 | #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) | |
| 423 | #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) | |
| 424 | #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) | |
| 425 | #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) | |
| 426 | #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) | |
| 427 | ||
| 428 | #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) | |
| 429 | #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) | |
| f0a346bd BV |
430 | #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) |
| 431 | #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) | |
| 3a6fa984 BV |
432 | #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) |
| 433 | #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) | |
| 434 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ | |
| 435 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) | |
| 436 | #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ | |
| 437 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) | |
| 438 | #define GFX_OP_3DSTATE_SO_DECL_LIST \ | |
| 439 | ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) | |
| 440 | ||
| 441 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ | |
| 442 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) | |
| 443 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ | |
| 444 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) | |
| 445 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ | |
| 446 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) | |
| 447 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ | |
| 448 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) | |
| 449 | #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ | |
| 450 | ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) | |
| 451 | ||
| 452 | #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) | |
| 453 | ||
| 454 | #define COLOR_BLT ((0x2<<29)|(0x40<<22)) | |
| 455 | #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) | |
| dc96e9b8 | 456 | |
| 5947de9b BV |
457 | /* |
| 458 | * Registers used only by the command parser | |
| 459 | */ | |
| 460 | #define BCS_SWCTRL 0x22200 | |
| 461 | ||
| 462 | #define HS_INVOCATION_COUNT 0x2300 | |
| 463 | #define DS_INVOCATION_COUNT 0x2308 | |
| 464 | #define IA_VERTICES_COUNT 0x2310 | |
| 465 | #define IA_PRIMITIVES_COUNT 0x2318 | |
| 466 | #define VS_INVOCATION_COUNT 0x2320 | |
| 467 | #define GS_INVOCATION_COUNT 0x2328 | |
| 468 | #define GS_PRIMITIVES_COUNT 0x2330 | |
| 469 | #define CL_INVOCATION_COUNT 0x2338 | |
| 470 | #define CL_PRIMITIVES_COUNT 0x2340 | |
| 471 | #define PS_INVOCATION_COUNT 0x2348 | |
| 472 | #define PS_DEPTH_COUNT 0x2350 | |
| 473 | ||
| 474 | /* There are the 4 64-bit counter registers, one for each stream output */ | |
| 475 | #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) | |
| 476 | ||
| 113a0476 BV |
477 | #define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) |
| 478 | ||
| 479 | #define GEN7_3DPRIM_END_OFFSET 0x2420 | |
| 480 | #define GEN7_3DPRIM_START_VERTEX 0x2430 | |
| 481 | #define GEN7_3DPRIM_VERTEX_COUNT 0x2434 | |
| 482 | #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 | |
| 483 | #define GEN7_3DPRIM_START_INSTANCE 0x243C | |
| 484 | #define GEN7_3DPRIM_BASE_VERTEX 0x2440 | |
| 485 | ||
| 180b813c KG |
486 | #define OACONTROL 0x2360 |
| 487 | ||
| 220375aa BV |
488 | #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 |
| 489 | #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 | |
| 490 | #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ | |
| 491 | _GEN7_PIPEA_DE_LOAD_SL, \ | |
| 492 | _GEN7_PIPEB_DE_LOAD_SL) | |
| 493 | ||
| dc96e9b8 CW |
494 | /* |
| 495 | * Reset registers | |
| 496 | */ | |
| 497 | #define DEBUG_RESET_I830 0x6070 | |
| 498 | #define DEBUG_RESET_FULL (1<<7) | |
| 499 | #define DEBUG_RESET_RENDER (1<<8) | |
| 500 | #define DEBUG_RESET_DISPLAY (1<<9) | |
| 501 | ||
| 57f350b6 | 502 | /* |
| 5a09ae9f JN |
503 | * IOSF sideband |
| 504 | */ | |
| 505 | #define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) | |
| 506 | #define IOSF_DEVFN_SHIFT 24 | |
| 507 | #define IOSF_OPCODE_SHIFT 16 | |
| 508 | #define IOSF_PORT_SHIFT 8 | |
| 509 | #define IOSF_BYTE_ENABLES_SHIFT 4 | |
| 510 | #define IOSF_BAR_SHIFT 1 | |
| 511 | #define IOSF_SB_BUSY (1<<0) | |
| f3419158 | 512 | #define IOSF_PORT_BUNIT 0x3 |
| 5a09ae9f JN |
513 | #define IOSF_PORT_PUNIT 0x4 |
| 514 | #define IOSF_PORT_NC 0x11 | |
| 515 | #define IOSF_PORT_DPIO 0x12 | |
| a09caddd | 516 | #define IOSF_PORT_DPIO_2 0x1a |
| e9f882a3 JN |
517 | #define IOSF_PORT_GPIO_NC 0x13 |
| 518 | #define IOSF_PORT_CCK 0x14 | |
| 519 | #define IOSF_PORT_CCU 0xA9 | |
| 520 | #define IOSF_PORT_GPS_CORE 0x48 | |
| e9fe51c6 | 521 | #define IOSF_PORT_FLISDSI 0x1B |
| 5a09ae9f JN |
522 | #define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) |
| 523 | #define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) | |
| 524 | ||
| 30a970c6 JB |
525 | /* See configdb bunit SB addr map */ |
| 526 | #define BUNIT_REG_BISOC 0x11 | |
| 527 | ||
| 30a970c6 | 528 | #define PUNIT_REG_DSPFREQ 0x36 |
| 383c5a6a VS |
529 | #define DSPFREQSTAT_SHIFT_CHV 24 |
| 530 | #define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) | |
| 531 | #define DSPFREQGUAR_SHIFT_CHV 8 | |
| 532 | #define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) | |
| 30a970c6 JB |
533 | #define DSPFREQSTAT_SHIFT 30 |
| 534 | #define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) | |
| 535 | #define DSPFREQGUAR_SHIFT 14 | |
| 536 | #define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) | |
| 26972b0a VS |
537 | #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) |
| 538 | #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) | |
| 539 | #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) | |
| 540 | #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) | |
| 541 | #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) | |
| 542 | #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) | |
| 543 | #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) | |
| 544 | #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) | |
| 545 | #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) | |
| 546 | #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) | |
| 547 | #define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) | |
| 548 | #define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) | |
| a30180a5 ID |
549 | |
| 550 | /* See the PUNIT HAS v0.8 for the below bits */ | |
| 551 | enum punit_power_well { | |
| 552 | PUNIT_POWER_WELL_RENDER = 0, | |
| 553 | PUNIT_POWER_WELL_MEDIA = 1, | |
| 554 | PUNIT_POWER_WELL_DISP2D = 3, | |
| 555 | PUNIT_POWER_WELL_DPIO_CMN_BC = 5, | |
| 556 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, | |
| 557 | PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, | |
| 558 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, | |
| 559 | PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, | |
| 560 | PUNIT_POWER_WELL_DPIO_RX0 = 10, | |
| 561 | PUNIT_POWER_WELL_DPIO_RX1 = 11, | |
| 5d6f7ea7 | 562 | PUNIT_POWER_WELL_DPIO_CMN_D = 12, |
| 2ce147f3 VS |
563 | /* FIXME: guesswork below */ |
| 564 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, | |
| 565 | PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, | |
| 566 | PUNIT_POWER_WELL_DPIO_RX2 = 15, | |
| a30180a5 ID |
567 | |
| 568 | PUNIT_POWER_WELL_NUM, | |
| 569 | }; | |
| 570 | ||
| 02f4c9e0 CML |
571 | #define PUNIT_REG_PWRGT_CTRL 0x60 |
| 572 | #define PUNIT_REG_PWRGT_STATUS 0x61 | |
| a30180a5 ID |
573 | #define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) |
| 574 | #define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) | |
| 575 | #define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) | |
| 576 | #define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) | |
| 577 | #define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) | |
| 02f4c9e0 | 578 | |
| 5a09ae9f JN |
579 | #define PUNIT_REG_GPU_LFM 0xd3 |
| 580 | #define PUNIT_REG_GPU_FREQ_REQ 0xd4 | |
| 581 | #define PUNIT_REG_GPU_FREQ_STS 0xd8 | |
| c8e9627d | 582 | #define GPLLENABLE (1<<4) |
| e8474409 | 583 | #define GENFREQSTATUS (1<<0) |
| 5a09ae9f | 584 | #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc |
| 31685c25 | 585 | #define PUNIT_REG_CZ_TIMESTAMP 0xce |
| 5a09ae9f JN |
586 | |
| 587 | #define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ | |
| 588 | #define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ | |
| 589 | ||
| 2b6b3a09 D |
590 | #define PUNIT_GPU_STATUS_REG 0xdb |
| 591 | #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 | |
| 592 | #define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff | |
| 593 | #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 | |
| 594 | #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff | |
| 595 | ||
| 596 | #define PUNIT_GPU_DUTYCYCLE_REG 0xdf | |
| 597 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 | |
| 598 | #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff | |
| 599 | ||
| 5a09ae9f JN |
600 | #define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c |
| 601 | #define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 | |
| 602 | #define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 | |
| 603 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 | |
| 604 | #define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 | |
| 605 | #define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 | |
| 606 | #define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 | |
| 607 | #define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 | |
| 608 | #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 | |
| 609 | #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 | |
| 610 | ||
| 31685c25 D |
611 | #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 |
| 612 | #define VLV_RP_UP_EI_THRESHOLD 90 | |
| 613 | #define VLV_RP_DOWN_EI_THRESHOLD 70 | |
| 614 | #define VLV_INT_COUNT_FOR_DOWN_EI 5 | |
| 615 | ||
| be4fc046 | 616 | /* vlv2 north clock has */ |
| 24eb2d59 CML |
617 | #define CCK_FUSE_REG 0x8 |
| 618 | #define CCK_FUSE_HPLL_FREQ_MASK 0x3 | |
| be4fc046 | 619 | #define CCK_REG_DSI_PLL_FUSE 0x44 |
| 620 | #define CCK_REG_DSI_PLL_CONTROL 0x48 | |
| 621 | #define DSI_PLL_VCO_EN (1 << 31) | |
| 622 | #define DSI_PLL_LDO_GATE (1 << 30) | |
| 623 | #define DSI_PLL_P1_POST_DIV_SHIFT 17 | |
| 624 | #define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) | |
| 625 | #define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) | |
| 626 | #define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) | |
| 627 | #define DSI_PLL_MUX_MASK (3 << 9) | |
| 628 | #define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) | |
| 629 | #define DSI_PLL_MUX_DSI0_CCK (1 << 10) | |
| 630 | #define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) | |
| 631 | #define DSI_PLL_MUX_DSI1_CCK (1 << 9) | |
| 632 | #define DSI_PLL_CLK_GATE_MASK (0xf << 5) | |
| 633 | #define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) | |
| 634 | #define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) | |
| 635 | #define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) | |
| 636 | #define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) | |
| 637 | #define DSI_PLL_LOCK (1 << 0) | |
| 638 | #define CCK_REG_DSI_PLL_DIVIDER 0x4c | |
| 639 | #define DSI_PLL_LFSR (1 << 31) | |
| 640 | #define DSI_PLL_FRACTION_EN (1 << 30) | |
| 641 | #define DSI_PLL_FRAC_COUNTER_SHIFT 27 | |
| 642 | #define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) | |
| 643 | #define DSI_PLL_USYNC_CNT_SHIFT 18 | |
| 644 | #define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) | |
| 645 | #define DSI_PLL_N1_DIV_SHIFT 16 | |
| 646 | #define DSI_PLL_N1_DIV_MASK (3 << 16) | |
| 647 | #define DSI_PLL_M1_DIV_SHIFT 0 | |
| 648 | #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) | |
| 30a970c6 | 649 | #define CCK_DISPLAY_CLOCK_CONTROL 0x6b |
| 9cf33db5 VS |
650 | #define DISPLAY_TRUNK_FORCE_ON (1 << 17) |
| 651 | #define DISPLAY_TRUNK_FORCE_OFF (1 << 16) | |
| 652 | #define DISPLAY_FREQUENCY_STATUS (0x1f << 8) | |
| 653 | #define DISPLAY_FREQUENCY_STATUS_SHIFT 8 | |
| 654 | #define DISPLAY_FREQUENCY_VALUES (0x1f << 0) | |
| be4fc046 | 655 | |
| 0e767189 VS |
656 | /** |
| 657 | * DOC: DPIO | |
| 658 | * | |
| 659 | * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI | |
| 660 | * ports. DPIO is the name given to such a display PHY. These PHYs | |
| 661 | * don't follow the standard programming model using direct MMIO | |
| 662 | * registers, and instead their registers must be accessed trough IOSF | |
| 663 | * sideband. VLV has one such PHY for driving ports B and C, and CHV | |
| 664 | * adds another PHY for driving port D. Each PHY responds to specific | |
| 665 | * IOSF-SB port. | |
| 666 | * | |
| 667 | * Each display PHY is made up of one or two channels. Each channel | |
| 668 | * houses a common lane part which contains the PLL and other common | |
| 669 | * logic. CH0 common lane also contains the IOSF-SB logic for the | |
| 670 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock | |
| 671 | * must be running when any DPIO registers are accessed. | |
| 672 | * | |
| 673 | * In addition to having their own registers, the PHYs are also | |
| 674 | * controlled through some dedicated signals from the display | |
| 675 | * controller. These include PLL reference clock enable, PLL enable, | |
| 676 | * and CRI clock selection, for example. | |
| 677 | * | |
| 678 | * Eeach channel also has two splines (also called data lanes), and | |
| 679 | * each spline is made up of one Physical Access Coding Sub-Layer | |
| 680 | * (PCS) block and two TX lanes. So each channel has two PCS blocks | |
| 681 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS | |
| 682 | * data/clock pairs depending on the output type. | |
| 683 | * | |
| 684 | * Additionally the PHY also contains an AUX lane with AUX blocks | |
| 685 | * for each channel. This is used for DP AUX communication, but | |
| 686 | * this fact isn't really relevant for the driver since AUX is | |
| 687 | * controlled from the display controller side. No DPIO registers | |
| 688 | * need to be accessed during AUX communication, | |
| 689 | * | |
| 690 | * Generally the common lane corresponds to the pipe and | |
| 32197aab | 691 | * the spline (PCS/TX) corresponds to the port. |
| 0e767189 VS |
692 | * |
| 693 | * For dual channel PHY (VLV/CHV): | |
| 694 | * | |
| 695 | * pipe A == CMN/PLL/REF CH0 | |
| 54d9d493 | 696 | * |
| 0e767189 VS |
697 | * pipe B == CMN/PLL/REF CH1 |
| 698 | * | |
| 699 | * port B == PCS/TX CH0 | |
| 700 | * | |
| 701 | * port C == PCS/TX CH1 | |
| 702 | * | |
| 703 | * This is especially important when we cross the streams | |
| 704 | * ie. drive port B with pipe B, or port C with pipe A. | |
| 705 | * | |
| 706 | * For single channel PHY (CHV): | |
| 707 | * | |
| 708 | * pipe C == CMN/PLL/REF CH0 | |
| 709 | * | |
| 710 | * port D == PCS/TX CH0 | |
| 711 | * | |
| 712 | * Note: digital port B is DDI0, digital port C is DDI1, | |
| 713 | * digital port D is DDI2 | |
| 714 | */ | |
| 715 | /* | |
| 716 | * Dual channel PHY (VLV/CHV) | |
| 717 | * --------------------------------- | |
| 718 | * | CH0 | CH1 | | |
| 719 | * | CMN/PLL/REF | CMN/PLL/REF | | |
| 720 | * |---------------|---------------| Display PHY | |
| 721 | * | PCS01 | PCS23 | PCS01 | PCS23 | | |
| 722 | * |-------|-------|-------|-------| | |
| 723 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| | |
| 724 | * --------------------------------- | |
| 725 | * | DDI0 | DDI1 | DP/HDMI ports | |
| 726 | * --------------------------------- | |
| 598fac6b | 727 | * |
| 0e767189 VS |
728 | * Single channel PHY (CHV) |
| 729 | * ----------------- | |
| 730 | * | CH0 | | |
| 731 | * | CMN/PLL/REF | | |
| 732 | * |---------------| Display PHY | |
| 733 | * | PCS01 | PCS23 | | |
| 734 | * |-------|-------| | |
| 735 | * |TX0|TX1|TX2|TX3| | |
| 736 | * ----------------- | |
| 737 | * | DDI2 | DP/HDMI port | |
| 738 | * ----------------- | |
| 57f350b6 | 739 | */ |
| 5a09ae9f | 740 | #define DPIO_DEVFN 0 |
| 5a09ae9f | 741 | |
| 54d9d493 | 742 | #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) |
| 57f350b6 JB |
743 | #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ |
| 744 | #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ | |
| 745 | #define DPIO_SFR_BYPASS (1<<1) | |
| 40e9cf64 | 746 | #define DPIO_CMNRST (1<<0) |
| 57f350b6 | 747 | |
| e4607fcf CML |
748 | #define DPIO_PHY(pipe) ((pipe) >> 1) |
| 749 | #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) | |
| 750 | ||
| 598fac6b DV |
751 | /* |
| 752 | * Per pipe/PLL DPIO regs | |
| 753 | */ | |
| ab3c759a | 754 | #define _VLV_PLL_DW3_CH0 0x800c |
| 57f350b6 | 755 | #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ |
| 598fac6b DV |
756 | #define DPIO_POST_DIV_DAC 0 |
| 757 | #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ | |
| 758 | #define DPIO_POST_DIV_LVDS1 2 | |
| 759 | #define DPIO_POST_DIV_LVDS2 3 | |
| 57f350b6 JB |
760 | #define DPIO_K_SHIFT (24) /* 4 bits */ |
| 761 | #define DPIO_P1_SHIFT (21) /* 3 bits */ | |
| 762 | #define DPIO_P2_SHIFT (16) /* 5 bits */ | |
| 763 | #define DPIO_N_SHIFT (12) /* 4 bits */ | |
| 764 | #define DPIO_ENABLE_CALIBRATION (1<<11) | |
| 765 | #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ | |
| 766 | #define DPIO_M2DIV_MASK 0xff | |
| ab3c759a CML |
767 | #define _VLV_PLL_DW3_CH1 0x802c |
| 768 | #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) | |
| 57f350b6 | 769 | |
| ab3c759a | 770 | #define _VLV_PLL_DW5_CH0 0x8014 |
| 57f350b6 JB |
771 | #define DPIO_REFSEL_OVERRIDE 27 |
| 772 | #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ | |
| 773 | #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ | |
| 774 | #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ | |
| b56747aa | 775 | #define DPIO_PLL_REFCLK_SEL_MASK 3 |
| 57f350b6 JB |
776 | #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ |
| 777 | #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ | |
| ab3c759a CML |
778 | #define _VLV_PLL_DW5_CH1 0x8034 |
| 779 | #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) | |
| 57f350b6 | 780 | |
| ab3c759a CML |
781 | #define _VLV_PLL_DW7_CH0 0x801c |
| 782 | #define _VLV_PLL_DW7_CH1 0x803c | |
| 783 | #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) | |
| 57f350b6 | 784 | |
| ab3c759a CML |
785 | #define _VLV_PLL_DW8_CH0 0x8040 |
| 786 | #define _VLV_PLL_DW8_CH1 0x8060 | |
| 787 | #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) | |
| 598fac6b | 788 | |
| ab3c759a CML |
789 | #define VLV_PLL_DW9_BCAST 0xc044 |
| 790 | #define _VLV_PLL_DW9_CH0 0x8044 | |
| 791 | #define _VLV_PLL_DW9_CH1 0x8064 | |
| 792 | #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) | |
| 598fac6b | 793 | |
| ab3c759a CML |
794 | #define _VLV_PLL_DW10_CH0 0x8048 |
| 795 | #define _VLV_PLL_DW10_CH1 0x8068 | |
| 796 | #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) | |
| 598fac6b | 797 | |
| ab3c759a CML |
798 | #define _VLV_PLL_DW11_CH0 0x804c |
| 799 | #define _VLV_PLL_DW11_CH1 0x806c | |
| 800 | #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) | |
| 57f350b6 | 801 | |
| ab3c759a CML |
802 | /* Spec for ref block start counts at DW10 */ |
| 803 | #define VLV_REF_DW13 0x80ac | |
| 598fac6b | 804 | |
| ab3c759a | 805 | #define VLV_CMN_DW0 0x8100 |
| dc96e9b8 | 806 | |
| 598fac6b DV |
807 | /* |
| 808 | * Per DDI channel DPIO regs | |
| 809 | */ | |
| 810 | ||
| ab3c759a CML |
811 | #define _VLV_PCS_DW0_CH0 0x8200 |
| 812 | #define _VLV_PCS_DW0_CH1 0x8400 | |
| 598fac6b DV |
813 | #define DPIO_PCS_TX_LANE2_RESET (1<<16) |
| 814 | #define DPIO_PCS_TX_LANE1_RESET (1<<7) | |
| 570e2a74 VS |
815 | #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4) |
| 816 | #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3) | |
| ab3c759a | 817 | #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) |
| 598fac6b | 818 | |
| 97fd4d5c VS |
819 | #define _VLV_PCS01_DW0_CH0 0x200 |
| 820 | #define _VLV_PCS23_DW0_CH0 0x400 | |
| 821 | #define _VLV_PCS01_DW0_CH1 0x2600 | |
| 822 | #define _VLV_PCS23_DW0_CH1 0x2800 | |
| 823 | #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) | |
| 824 | #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) | |
| 825 | ||
| ab3c759a CML |
826 | #define _VLV_PCS_DW1_CH0 0x8204 |
| 827 | #define _VLV_PCS_DW1_CH1 0x8404 | |
| d2152b25 | 828 | #define CHV_PCS_REQ_SOFTRESET_EN (1<<23) |
| 598fac6b DV |
829 | #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) |
| 830 | #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) | |
| 831 | #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) | |
| 832 | #define DPIO_PCS_CLK_SOFT_RESET (1<<5) | |
| ab3c759a CML |
833 | #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) |
| 834 | ||
| 97fd4d5c VS |
835 | #define _VLV_PCS01_DW1_CH0 0x204 |
| 836 | #define _VLV_PCS23_DW1_CH0 0x404 | |
| 837 | #define _VLV_PCS01_DW1_CH1 0x2604 | |
| 838 | #define _VLV_PCS23_DW1_CH1 0x2804 | |
| 839 | #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) | |
| 840 | #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) | |
| 841 | ||
| ab3c759a CML |
842 | #define _VLV_PCS_DW8_CH0 0x8220 |
| 843 | #define _VLV_PCS_DW8_CH1 0x8420 | |
| 9197c88b VS |
844 | #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) |
| 845 | #define CHV_PCS_USEDCLKCHANNEL (1 << 21) | |
| ab3c759a CML |
846 | #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) |
| 847 | ||
| 848 | #define _VLV_PCS01_DW8_CH0 0x0220 | |
| 849 | #define _VLV_PCS23_DW8_CH0 0x0420 | |
| 850 | #define _VLV_PCS01_DW8_CH1 0x2620 | |
| 851 | #define _VLV_PCS23_DW8_CH1 0x2820 | |
| 852 | #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) | |
| 853 | #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) | |
| 854 | ||
| 855 | #define _VLV_PCS_DW9_CH0 0x8224 | |
| 856 | #define _VLV_PCS_DW9_CH1 0x8424 | |
| a02ef3c7 VS |
857 | #define DPIO_PCS_TX2MARGIN_MASK (0x7<<13) |
| 858 | #define DPIO_PCS_TX2MARGIN_000 (0<<13) | |
| 859 | #define DPIO_PCS_TX2MARGIN_101 (1<<13) | |
| 860 | #define DPIO_PCS_TX1MARGIN_MASK (0x7<<10) | |
| 861 | #define DPIO_PCS_TX1MARGIN_000 (0<<10) | |
| 862 | #define DPIO_PCS_TX1MARGIN_101 (1<<10) | |
| ab3c759a CML |
863 | #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) |
| 864 | ||
| a02ef3c7 VS |
865 | #define _VLV_PCS01_DW9_CH0 0x224 |
| 866 | #define _VLV_PCS23_DW9_CH0 0x424 | |
| 867 | #define _VLV_PCS01_DW9_CH1 0x2624 | |
| 868 | #define _VLV_PCS23_DW9_CH1 0x2824 | |
| 869 | #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) | |
| 870 | #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) | |
| 871 | ||
| 9d556c99 CML |
872 | #define _CHV_PCS_DW10_CH0 0x8228 |
| 873 | #define _CHV_PCS_DW10_CH1 0x8428 | |
| 874 | #define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) | |
| 875 | #define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) | |
| a02ef3c7 VS |
876 | #define DPIO_PCS_TX2DEEMP_MASK (0xf<<24) |
| 877 | #define DPIO_PCS_TX2DEEMP_9P5 (0<<24) | |
| 878 | #define DPIO_PCS_TX2DEEMP_6P0 (2<<24) | |
| 879 | #define DPIO_PCS_TX1DEEMP_MASK (0xf<<16) | |
| 880 | #define DPIO_PCS_TX1DEEMP_9P5 (0<<16) | |
| 881 | #define DPIO_PCS_TX1DEEMP_6P0 (2<<16) | |
| 9d556c99 CML |
882 | #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) |
| 883 | ||
| 1966e59e VS |
884 | #define _VLV_PCS01_DW10_CH0 0x0228 |
| 885 | #define _VLV_PCS23_DW10_CH0 0x0428 | |
| 886 | #define _VLV_PCS01_DW10_CH1 0x2628 | |
| 887 | #define _VLV_PCS23_DW10_CH1 0x2828 | |
| 888 | #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) | |
| 889 | #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) | |
| 890 | ||
| ab3c759a CML |
891 | #define _VLV_PCS_DW11_CH0 0x822c |
| 892 | #define _VLV_PCS_DW11_CH1 0x842c | |
| 570e2a74 VS |
893 | #define DPIO_LANEDESKEW_STRAP_OVRD (1<<3) |
| 894 | #define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1) | |
| 895 | #define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0) | |
| ab3c759a CML |
896 | #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) |
| 897 | ||
| 570e2a74 VS |
898 | #define _VLV_PCS01_DW11_CH0 0x022c |
| 899 | #define _VLV_PCS23_DW11_CH0 0x042c | |
| 900 | #define _VLV_PCS01_DW11_CH1 0x262c | |
| 901 | #define _VLV_PCS23_DW11_CH1 0x282c | |
| 142d2eca VS |
902 | #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) |
| 903 | #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) | |
| 570e2a74 | 904 | |
| ab3c759a CML |
905 | #define _VLV_PCS_DW12_CH0 0x8230 |
| 906 | #define _VLV_PCS_DW12_CH1 0x8430 | |
| 907 | #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) | |
| 908 | ||
| 909 | #define _VLV_PCS_DW14_CH0 0x8238 | |
| 910 | #define _VLV_PCS_DW14_CH1 0x8438 | |
| 911 | #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) | |
| 912 | ||
| 913 | #define _VLV_PCS_DW23_CH0 0x825c | |
| 914 | #define _VLV_PCS_DW23_CH1 0x845c | |
| 915 | #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) | |
| 916 | ||
| 917 | #define _VLV_TX_DW2_CH0 0x8288 | |
| 918 | #define _VLV_TX_DW2_CH1 0x8488 | |
| 1fb44505 VS |
919 | #define DPIO_SWING_MARGIN000_SHIFT 16 |
| 920 | #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) | |
| 9d556c99 | 921 | #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 |
| ab3c759a CML |
922 | #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) |
| 923 | ||
| 924 | #define _VLV_TX_DW3_CH0 0x828c | |
| 925 | #define _VLV_TX_DW3_CH1 0x848c | |
| 9d556c99 CML |
926 | /* The following bit for CHV phy */ |
| 927 | #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) | |
| 1fb44505 VS |
928 | #define DPIO_SWING_MARGIN101_SHIFT 16 |
| 929 | #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) | |
| ab3c759a CML |
930 | #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) |
| 931 | ||
| 932 | #define _VLV_TX_DW4_CH0 0x8290 | |
| 933 | #define _VLV_TX_DW4_CH1 0x8490 | |
| 9d556c99 CML |
934 | #define DPIO_SWING_DEEMPH9P5_SHIFT 24 |
| 935 | #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) | |
| 1fb44505 VS |
936 | #define DPIO_SWING_DEEMPH6P0_SHIFT 16 |
| 937 | #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) | |
| ab3c759a CML |
938 | #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) |
| 939 | ||
| 940 | #define _VLV_TX3_DW4_CH0 0x690 | |
| 941 | #define _VLV_TX3_DW4_CH1 0x2a90 | |
| 942 | #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) | |
| 943 | ||
| 944 | #define _VLV_TX_DW5_CH0 0x8294 | |
| 945 | #define _VLV_TX_DW5_CH1 0x8494 | |
| 598fac6b | 946 | #define DPIO_TX_OCALINIT_EN (1<<31) |
| ab3c759a CML |
947 | #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) |
| 948 | ||
| 949 | #define _VLV_TX_DW11_CH0 0x82ac | |
| 950 | #define _VLV_TX_DW11_CH1 0x84ac | |
| 951 | #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) | |
| 952 | ||
| 953 | #define _VLV_TX_DW14_CH0 0x82b8 | |
| 954 | #define _VLV_TX_DW14_CH1 0x84b8 | |
| 955 | #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) | |
| b56747aa | 956 | |
| 9d556c99 CML |
957 | /* CHV dpPhy registers */ |
| 958 | #define _CHV_PLL_DW0_CH0 0x8000 | |
| 959 | #define _CHV_PLL_DW0_CH1 0x8180 | |
| 960 | #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) | |
| 961 | ||
| 962 | #define _CHV_PLL_DW1_CH0 0x8004 | |
| 963 | #define _CHV_PLL_DW1_CH1 0x8184 | |
| 964 | #define DPIO_CHV_N_DIV_SHIFT 8 | |
| 965 | #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) | |
| 966 | #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) | |
| 967 | ||
| 968 | #define _CHV_PLL_DW2_CH0 0x8008 | |
| 969 | #define _CHV_PLL_DW2_CH1 0x8188 | |
| 970 | #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) | |
| 971 | ||
| 972 | #define _CHV_PLL_DW3_CH0 0x800c | |
| 973 | #define _CHV_PLL_DW3_CH1 0x818c | |
| 974 | #define DPIO_CHV_FRAC_DIV_EN (1 << 16) | |
| 975 | #define DPIO_CHV_FIRST_MOD (0 << 8) | |
| 976 | #define DPIO_CHV_SECOND_MOD (1 << 8) | |
| 977 | #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 | |
| 978 | #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) | |
| 979 | ||
| 980 | #define _CHV_PLL_DW6_CH0 0x8018 | |
| 981 | #define _CHV_PLL_DW6_CH1 0x8198 | |
| 982 | #define DPIO_CHV_GAIN_CTRL_SHIFT 16 | |
| 983 | #define DPIO_CHV_INT_COEFF_SHIFT 8 | |
| 984 | #define DPIO_CHV_PROP_COEFF_SHIFT 0 | |
| 985 | #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) | |
| 986 | ||
| b9e5ac3c VS |
987 | #define _CHV_CMN_DW5_CH0 0x8114 |
| 988 | #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) | |
| 989 | #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) | |
| 990 | #define CHV_BUFRIGHTENA1_FORCE (3 << 20) | |
| 991 | #define CHV_BUFRIGHTENA1_MASK (3 << 20) | |
| 992 | #define CHV_BUFLEFTENA1_DISABLE (0 << 22) | |
| 993 | #define CHV_BUFLEFTENA1_NORMAL (1 << 22) | |
| 994 | #define CHV_BUFLEFTENA1_FORCE (3 << 22) | |
| 995 | #define CHV_BUFLEFTENA1_MASK (3 << 22) | |
| 996 | ||
| 9d556c99 CML |
997 | #define _CHV_CMN_DW13_CH0 0x8134 |
| 998 | #define _CHV_CMN_DW0_CH1 0x8080 | |
| 999 | #define DPIO_CHV_S1_DIV_SHIFT 21 | |
| 1000 | #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ | |
| 1001 | #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ | |
| 1002 | #define DPIO_CHV_K_DIV_SHIFT 4 | |
| 1003 | #define DPIO_PLL_FREQLOCK (1 << 1) | |
| 1004 | #define DPIO_PLL_LOCK (1 << 0) | |
| 1005 | #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) | |
| 1006 | ||
| 1007 | #define _CHV_CMN_DW14_CH0 0x8138 | |
| 1008 | #define _CHV_CMN_DW1_CH1 0x8084 | |
| 1009 | #define DPIO_AFC_RECAL (1 << 14) | |
| 1010 | #define DPIO_DCLKP_EN (1 << 13) | |
| b9e5ac3c VS |
1011 | #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ |
| 1012 | #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ | |
| 1013 | #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ | |
| 1014 | #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ | |
| 1015 | #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ | |
| 1016 | #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ | |
| 1017 | #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ | |
| 1018 | #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ | |
| 9d556c99 CML |
1019 | #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) |
| 1020 | ||
| 9197c88b VS |
1021 | #define _CHV_CMN_DW19_CH0 0x814c |
| 1022 | #define _CHV_CMN_DW6_CH1 0x8098 | |
| 1023 | #define CHV_CMN_USEDCLKCHANNEL (1 << 13) | |
| 1024 | #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) | |
| 1025 | ||
| 9d556c99 CML |
1026 | #define CHV_CMN_DW30 0x8178 |
| 1027 | #define DPIO_LRC_BYPASS (1 << 3) | |
| 1028 | ||
| 1029 | #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ | |
| 1030 | (lane) * 0x200 + (offset)) | |
| 1031 | ||
| f72df8db VS |
1032 | #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) |
| 1033 | #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) | |
| 1034 | #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) | |
| 1035 | #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) | |
| 1036 | #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) | |
| 1037 | #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) | |
| 1038 | #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) | |
| 1039 | #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) | |
| 1040 | #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) | |
| 1041 | #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) | |
| 1042 | #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) | |
| 9d556c99 CML |
1043 | #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) |
| 1044 | #define DPIO_FRC_LATENCY_SHFIT 8 | |
| 1045 | #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) | |
| 1046 | #define DPIO_UPAR_SHIFT 30 | |
| 585fb111 | 1047 | /* |
| de151cf6 | 1048 | * Fence registers |
| 585fb111 | 1049 | */ |
| de151cf6 | 1050 | #define FENCE_REG_830_0 0x2000 |
| dc529a4f | 1051 | #define FENCE_REG_945_8 0x3000 |
| de151cf6 JB |
1052 | #define I830_FENCE_START_MASK 0x07f80000 |
| 1053 | #define I830_FENCE_TILING_Y_SHIFT 12 | |
| 0f973f27 | 1054 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
| de151cf6 JB |
1055 | #define I830_FENCE_PITCH_SHIFT 4 |
| 1056 | #define I830_FENCE_REG_VALID (1<<0) | |
| c36a2a6d | 1057 | #define I915_FENCE_MAX_PITCH_VAL 4 |
| e76a16de | 1058 | #define I830_FENCE_MAX_PITCH_VAL 6 |
| 8d7773a3 | 1059 | #define I830_FENCE_MAX_SIZE_VAL (1<<8) |
| de151cf6 JB |
1060 | |
| 1061 | #define I915_FENCE_START_MASK 0x0ff00000 | |
| 0f973f27 | 1062 | #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) |
| 585fb111 | 1063 | |
| de151cf6 JB |
1064 | #define FENCE_REG_965_0 0x03000 |
| 1065 | #define I965_FENCE_PITCH_SHIFT 2 | |
| 1066 | #define I965_FENCE_TILING_Y_SHIFT 1 | |
| 1067 | #define I965_FENCE_REG_VALID (1<<0) | |
| 8d7773a3 | 1068 | #define I965_FENCE_MAX_PITCH_VAL 0x0400 |
| de151cf6 | 1069 | |
| 4e901fdc EA |
1070 | #define FENCE_REG_SANDYBRIDGE_0 0x100000 |
| 1071 | #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 | |
| 3a062478 | 1072 | #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 |
| 4e901fdc | 1073 | |
| 2b6b3a09 | 1074 | |
| f691e2f4 DV |
1075 | /* control register for cpu gtt access */ |
| 1076 | #define TILECTL 0x101000 | |
| 1077 | #define TILECTL_SWZCTL (1 << 0) | |
| 1078 | #define TILECTL_TLB_PREFETCH_DIS (1 << 2) | |
| 1079 | #define TILECTL_BACKSNOOP_DIS (1 << 3) | |
| 1080 | ||
| de151cf6 JB |
1081 | /* |
| 1082 | * Instruction and interrupt control regs | |
| 1083 | */ | |
| f1e1c212 VS |
1084 | #define PGTBL_CTL 0x02020 |
| 1085 | #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ | |
| 1086 | #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ | |
| 63eeaf38 | 1087 | #define PGTBL_ER 0x02024 |
| 81e7f200 VS |
1088 | #define PRB0_BASE (0x2030-0x30) |
| 1089 | #define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ | |
| 1090 | #define PRB2_BASE (0x2050-0x30) /* gen3 */ | |
| 1091 | #define SRB0_BASE (0x2100-0x30) /* gen2 */ | |
| 1092 | #define SRB1_BASE (0x2110-0x30) /* gen2 */ | |
| 1093 | #define SRB2_BASE (0x2120-0x30) /* 830 */ | |
| 1094 | #define SRB3_BASE (0x2130-0x30) /* 830 */ | |
| 333e9fe9 DV |
1095 | #define RENDER_RING_BASE 0x02000 |
| 1096 | #define BSD_RING_BASE 0x04000 | |
| 1097 | #define GEN6_BSD_RING_BASE 0x12000 | |
| 845f74a7 | 1098 | #define GEN8_BSD2_RING_BASE 0x1c000 |
| 1950de14 | 1099 | #define VEBOX_RING_BASE 0x1a000 |
| 549f7365 | 1100 | #define BLT_RING_BASE 0x22000 |
| 3d281d8c DV |
1101 | #define RING_TAIL(base) ((base)+0x30) |
| 1102 | #define RING_HEAD(base) ((base)+0x34) | |
| 1103 | #define RING_START(base) ((base)+0x38) | |
| 1104 | #define RING_CTL(base) ((base)+0x3c) | |
| 1ec14ad3 CW |
1105 | #define RING_SYNC_0(base) ((base)+0x40) |
| 1106 | #define RING_SYNC_1(base) ((base)+0x44) | |
| 1950de14 BW |
1107 | #define RING_SYNC_2(base) ((base)+0x48) |
| 1108 | #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) | |
| 1109 | #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) | |
| 1110 | #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) | |
| 1111 | #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) | |
| 1112 | #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) | |
| 1113 | #define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) | |
| 1114 | #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) | |
| 1115 | #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) | |
| 1116 | #define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) | |
| 1117 | #define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) | |
| 1118 | #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) | |
| 1119 | #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) | |
| ad776f8b | 1120 | #define GEN6_NOSYNC 0 |
| 8fd26859 | 1121 | #define RING_MAX_IDLE(base) ((base)+0x54) |
| 3d281d8c DV |
1122 | #define RING_HWS_PGA(base) ((base)+0x80) |
| 1123 | #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) | |
| 9e72b46c ID |
1124 | |
| 1125 | #define GEN7_WR_WATERMARK 0x4028 | |
| 1126 | #define GEN7_GFX_PRIO_CTRL 0x402C | |
| 1127 | #define ARB_MODE 0x4030 | |
| f691e2f4 DV |
1128 | #define ARB_MODE_SWIZZLE_SNB (1<<4) |
| 1129 | #define ARB_MODE_SWIZZLE_IVB (1<<5) | |
| 9e72b46c ID |
1130 | #define GEN7_GFX_PEND_TLB0 0x4034 |
| 1131 | #define GEN7_GFX_PEND_TLB1 0x4038 | |
| 1132 | /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ | |
| 1133 | #define GEN7_LRA_LIMITS_BASE 0x403C | |
| 1134 | #define GEN7_LRA_LIMITS_REG_NUM 13 | |
| 1135 | #define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 | |
| 1136 | #define GEN7_GFX_MAX_REQ_COUNT 0x4074 | |
| 1137 | ||
| 31a5336e | 1138 | #define GAMTARBMODE 0x04a08 |
| 4afe8d33 | 1139 | #define ARB_MODE_BWGTLB_DISABLE (1<<9) |
| 31a5336e | 1140 | #define ARB_MODE_SWIZZLE_BDW (1<<1) |
| 4593010b | 1141 | #define RENDER_HWS_PGA_GEN7 (0x04080) |
| 33f3f518 | 1142 | #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) |
| 828c7908 BW |
1143 | #define RING_FAULT_GTTSEL_MASK (1<<11) |
| 1144 | #define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) | |
| 1145 | #define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) | |
| 1146 | #define RING_FAULT_VALID (1<<0) | |
| 33f3f518 | 1147 | #define DONE_REG 0x40b0 |
| fbe5d36e | 1148 | #define GEN8_PRIVATE_PAT 0x40e0 |
| 4593010b EA |
1149 | #define BSD_HWS_PGA_GEN7 (0x04180) |
| 1150 | #define BLT_HWS_PGA_GEN7 (0x04280) | |
| 9a8a2213 | 1151 | #define VEBOX_HWS_PGA_GEN7 (0x04380) |
| 3d281d8c | 1152 | #define RING_ACTHD(base) ((base)+0x74) |
| 50877445 | 1153 | #define RING_ACTHD_UDW(base) ((base)+0x5c) |
| 1ec14ad3 | 1154 | #define RING_NOPID(base) ((base)+0x94) |
| 0f46832f | 1155 | #define RING_IMR(base) ((base)+0xa8) |
| 73d477f6 | 1156 | #define RING_HWSTAM(base) ((base)+0x98) |
| c0c7babc | 1157 | #define RING_TIMESTAMP(base) ((base)+0x358) |
| 585fb111 JB |
1158 | #define TAIL_ADDR 0x001FFFF8 |
| 1159 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
| 1160 | #define HEAD_WRAP_ONE 0x00200000 | |
| 1161 | #define HEAD_ADDR 0x001FFFFC | |
| 1162 | #define RING_NR_PAGES 0x001FF000 | |
| 1163 | #define RING_REPORT_MASK 0x00000006 | |
| 1164 | #define RING_REPORT_64K 0x00000002 | |
| 1165 | #define RING_REPORT_128K 0x00000004 | |
| 1166 | #define RING_NO_REPORT 0x00000000 | |
| 1167 | #define RING_VALID_MASK 0x00000001 | |
| 1168 | #define RING_VALID 0x00000001 | |
| 1169 | #define RING_INVALID 0x00000000 | |
| 4b60e5cb CW |
1170 | #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ |
| 1171 | #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ | |
| 1ec14ad3 | 1172 | #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ |
| 9e72b46c ID |
1173 | |
| 1174 | #define GEN7_TLB_RD_ADDR 0x4700 | |
| 1175 | ||
| 8168bd48 CW |
1176 | #if 0 |
| 1177 | #define PRB0_TAIL 0x02030 | |
| 1178 | #define PRB0_HEAD 0x02034 | |
| 1179 | #define PRB0_START 0x02038 | |
| 1180 | #define PRB0_CTL 0x0203c | |
| 585fb111 JB |
1181 | #define PRB1_TAIL 0x02040 /* 915+ only */ |
| 1182 | #define PRB1_HEAD 0x02044 /* 915+ only */ | |
| 1183 | #define PRB1_START 0x02048 /* 915+ only */ | |
| 1184 | #define PRB1_CTL 0x0204c /* 915+ only */ | |
| 8168bd48 | 1185 | #endif |
| 63eeaf38 JB |
1186 | #define IPEIR_I965 0x02064 |
| 1187 | #define IPEHR_I965 0x02068 | |
| 1188 | #define INSTDONE_I965 0x0206c | |
| d53bd484 BW |
1189 | #define GEN7_INSTDONE_1 0x0206c |
| 1190 | #define GEN7_SC_INSTDONE 0x07100 | |
| 1191 | #define GEN7_SAMPLER_INSTDONE 0x0e160 | |
| 1192 | #define GEN7_ROW_INSTDONE 0x0e164 | |
| 1193 | #define I915_NUM_INSTDONE_REG 4 | |
| d27b1e0e DV |
1194 | #define RING_IPEIR(base) ((base)+0x64) |
| 1195 | #define RING_IPEHR(base) ((base)+0x68) | |
| 1196 | #define RING_INSTDONE(base) ((base)+0x6c) | |
| c1cd90ed DV |
1197 | #define RING_INSTPS(base) ((base)+0x70) |
| 1198 | #define RING_DMA_FADD(base) ((base)+0x78) | |
| 13ffadd1 | 1199 | #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ |
| c1cd90ed | 1200 | #define RING_INSTPM(base) ((base)+0xc0) |
| e9fea574 | 1201 | #define RING_MI_MODE(base) ((base)+0x9c) |
| 63eeaf38 JB |
1202 | #define INSTPS 0x02070 /* 965+ only */ |
| 1203 | #define INSTDONE1 0x0207c /* 965+ only */ | |
| 585fb111 JB |
1204 | #define ACTHD_I965 0x02074 |
| 1205 | #define HWS_PGA 0x02080 | |
| 1206 | #define HWS_ADDRESS_MASK 0xfffff000 | |
| 1207 | #define HWS_START_ADDRESS_SHIFT 4 | |
| 97f5ab66 JB |
1208 | #define PWRCTXA 0x2088 /* 965GM+ only */ |
| 1209 | #define PWRCTX_EN (1<<0) | |
| 585fb111 | 1210 | #define IPEIR 0x02088 |
| 63eeaf38 JB |
1211 | #define IPEHR 0x0208c |
| 1212 | #define INSTDONE 0x02090 | |
| 585fb111 JB |
1213 | #define NOPID 0x02094 |
| 1214 | #define HWSTAM 0x02098 | |
| 9d2f41fa | 1215 | #define DMA_FADD_I8XX 0x020d0 |
| 94e39e28 | 1216 | #define RING_BBSTATE(base) ((base)+0x110) |
| 3dda20a9 VS |
1217 | #define RING_BBADDR(base) ((base)+0x140) |
| 1218 | #define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ | |
| 71cf39b1 | 1219 | |
| f406839f | 1220 | #define ERROR_GEN6 0x040a0 |
| 71e172e8 | 1221 | #define GEN7_ERR_INT 0x44040 |
| de032bf4 | 1222 | #define ERR_INT_POISON (1<<31) |
| 8664281b | 1223 | #define ERR_INT_MMIO_UNCLAIMED (1<<13) |
| 8bf1e9f1 | 1224 | #define ERR_INT_PIPE_CRC_DONE_C (1<<8) |
| 8664281b | 1225 | #define ERR_INT_FIFO_UNDERRUN_C (1<<6) |
| 8bf1e9f1 | 1226 | #define ERR_INT_PIPE_CRC_DONE_B (1<<5) |
| 8664281b | 1227 | #define ERR_INT_FIFO_UNDERRUN_B (1<<3) |
| 8bf1e9f1 | 1228 | #define ERR_INT_PIPE_CRC_DONE_A (1<<2) |
| 5a69b89f | 1229 | #define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) |
| 8664281b | 1230 | #define ERR_INT_FIFO_UNDERRUN_A (1<<0) |
| 7336df65 | 1231 | #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
| f406839f | 1232 | |
| 3f1e109a PZ |
1233 | #define FPGA_DBG 0x42300 |
| 1234 | #define FPGA_DBG_RM_NOCLAIM (1<<31) | |
| 1235 | ||
| 0f3b6849 | 1236 | #define DERRMR 0x44050 |
| 4e0bbc31 | 1237 | /* Note that HBLANK events are reserved on bdw+ */ |
| ffe74d75 CW |
1238 | #define DERRMR_PIPEA_SCANLINE (1<<0) |
| 1239 | #define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) | |
| 1240 | #define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) | |
| 1241 | #define DERRMR_PIPEA_VBLANK (1<<3) | |
| 1242 | #define DERRMR_PIPEA_HBLANK (1<<5) | |
| 1243 | #define DERRMR_PIPEB_SCANLINE (1<<8) | |
| 1244 | #define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) | |
| 1245 | #define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) | |
| 1246 | #define DERRMR_PIPEB_VBLANK (1<<11) | |
| 1247 | #define DERRMR_PIPEB_HBLANK (1<<13) | |
| 1248 | /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ | |
| 1249 | #define DERRMR_PIPEC_SCANLINE (1<<14) | |
| 1250 | #define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) | |
| 1251 | #define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) | |
| 1252 | #define DERRMR_PIPEC_VBLANK (1<<21) | |
| 1253 | #define DERRMR_PIPEC_HBLANK (1<<22) | |
| 1254 | ||
| 0f3b6849 | 1255 | |
| de6e2eaf EA |
1256 | /* GM45+ chicken bits -- debug workaround bits that may be required |
| 1257 | * for various sorts of correct behavior. The top 16 bits of each are | |
| 1258 | * the enables for writing to the corresponding low bit. | |
| 1259 | */ | |
| 1260 | #define _3D_CHICKEN 0x02084 | |
| 4283908e | 1261 | #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) |
| de6e2eaf EA |
1262 | #define _3D_CHICKEN2 0x0208c |
| 1263 | /* Disables pipelining of read flushes past the SF-WIZ interface. | |
| 1264 | * Required on all Ironlake steppings according to the B-Spec, but the | |
| 1265 | * particular danger of not doing so is not specified. | |
| 1266 | */ | |
| 1267 | # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) | |
| 1268 | #define _3D_CHICKEN3 0x02090 | |
| 87f8020e | 1269 | #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) |
| 26b6e44a | 1270 | #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) |
| e927ecde VS |
1271 | #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ |
| 1272 | #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ | |
| de6e2eaf | 1273 | |
| 71cf39b1 EA |
1274 | #define MI_MODE 0x0209c |
| 1275 | # define VS_TIMER_DISPATCH (1 << 6) | |
| fc74d8e0 | 1276 | # define MI_FLUSH_ENABLE (1 << 12) |
| 1c8c38c5 | 1277 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
| e9fea574 | 1278 | # define MODE_IDLE (1 << 9) |
| 9991ae78 | 1279 | # define STOP_RING (1 << 8) |
| 71cf39b1 | 1280 | |
| f8f2ac9a | 1281 | #define GEN6_GT_MODE 0x20d0 |
| a607c1a4 | 1282 | #define GEN7_GT_MODE 0x7008 |
| 8d85d272 VS |
1283 | #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) |
| 1284 | #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) | |
| 1285 | #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) | |
| 1286 | #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) | |
| 1287 | #define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) | |
| 6547fbdb | 1288 | #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) |
| f8f2ac9a | 1289 | |
| 1ec14ad3 | 1290 | #define GFX_MODE 0x02520 |
| b095cd0a | 1291 | #define GFX_MODE_GEN7 0x0229c |
| 5eb719cd | 1292 | #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) |
| 1ec14ad3 | 1293 | #define GFX_RUN_LIST_ENABLE (1<<15) |
| aa83e30d | 1294 | #define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) |
| 1ec14ad3 CW |
1295 | #define GFX_SURFACE_FAULT_ENABLE (1<<12) |
| 1296 | #define GFX_REPLAY_MODE (1<<11) | |
| 1297 | #define GFX_PSMI_GRANULARITY (1<<10) | |
| 1298 | #define GFX_PPGTT_ENABLE (1<<9) | |
| 1299 | ||
| a7e806de | 1300 | #define VLV_DISPLAY_BASE 0x180000 |
| b6fdd0f2 | 1301 | #define VLV_MIPI_BASE VLV_DISPLAY_BASE |
| a7e806de | 1302 | |
| 9e72b46c ID |
1303 | #define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) |
| 1304 | #define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) | |
| 585fb111 JB |
1305 | #define SCPD0 0x0209c /* 915+ only */ |
| 1306 | #define IER 0x020a0 | |
| 1307 | #define IIR 0x020a4 | |
| 1308 | #define IMR 0x020a8 | |
| 1309 | #define ISR 0x020ac | |
| 07ec7ec5 | 1310 | #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) |
| e4443e45 | 1311 | #define GINT_DIS (1<<22) |
| 2d809570 | 1312 | #define GCFG_DIS (1<<8) |
| 9e72b46c | 1313 | #define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) |
| ff763010 VS |
1314 | #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) |
| 1315 | #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) | |
| 1316 | #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) | |
| 1317 | #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) | |
| 1318 | #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) | |
| c9cddffc | 1319 | #define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) |
| 38807746 D |
1320 | #define VLV_PCBR_ADDR_SHIFT 12 |
| 1321 | ||
| 90a72f87 | 1322 | #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ |
| 585fb111 JB |
1323 | #define EIR 0x020b0 |
| 1324 | #define EMR 0x020b4 | |
| 1325 | #define ESR 0x020b8 | |
| 63eeaf38 JB |
1326 | #define GM45_ERROR_PAGE_TABLE (1<<5) |
| 1327 | #define GM45_ERROR_MEM_PRIV (1<<4) | |
| 1328 | #define I915_ERROR_PAGE_TABLE (1<<4) | |
| 1329 | #define GM45_ERROR_CP_PRIV (1<<3) | |
| 1330 | #define I915_ERROR_MEMORY_REFRESH (1<<1) | |
| 1331 | #define I915_ERROR_INSTRUCTION (1<<0) | |
| 585fb111 | 1332 | #define INSTPM 0x020c0 |
| ee980b80 | 1333 | #define INSTPM_SELF_EN (1<<12) /* 915GM only */ |
| 3299254f | 1334 | #define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts |
| 8692d00e CW |
1335 | will not assert AGPBUSY# and will only |
| 1336 | be delivered when out of C3. */ | |
| 84f9f938 | 1337 | #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ |
| 884020bf CW |
1338 | #define INSTPM_TLB_INVALIDATE (1<<9) |
| 1339 | #define INSTPM_SYNC_FLUSH (1<<5) | |
| 585fb111 | 1340 | #define ACTHD 0x020c8 |
| 1038392b VS |
1341 | #define MEM_MODE 0x020cc |
| 1342 | #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ | |
| 1343 | #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ | |
| 1344 | #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ | |
| 585fb111 | 1345 | #define FW_BLC 0x020d8 |
| 8692d00e | 1346 | #define FW_BLC2 0x020dc |
| 585fb111 | 1347 | #define FW_BLC_SELF 0x020e0 /* 915+ only */ |
| ee980b80 LP |
1348 | #define FW_BLC_SELF_EN_MASK (1<<31) |
| 1349 | #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ | |
| 1350 | #define FW_BLC_SELF_EN (1<<15) /* 945 only */ | |
| 7662c8bd SL |
1351 | #define MM_BURST_LENGTH 0x00700000 |
| 1352 | #define MM_FIFO_WATERMARK 0x0001F000 | |
| 1353 | #define LM_BURST_LENGTH 0x00000700 | |
| 1354 | #define LM_FIFO_WATERMARK 0x0000001F | |
| 585fb111 | 1355 | #define MI_ARB_STATE 0x020e4 /* 915+ only */ |
| 45503ded KP |
1356 | |
| 1357 | /* Make render/texture TLB fetches lower priorty than associated data | |
| 1358 | * fetches. This is not turned on by default | |
| 1359 | */ | |
| 1360 | #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) | |
| 1361 | ||
| 1362 | /* Isoch request wait on GTT enable (Display A/B/C streams). | |
| 1363 | * Make isoch requests stall on the TLB update. May cause | |
| 1364 | * display underruns (test mode only) | |
| 1365 | */ | |
| 1366 | #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) | |
| 1367 | ||
| 1368 | /* Block grant count for isoch requests when block count is | |
| 1369 | * set to a finite value. | |
| 1370 | */ | |
| 1371 | #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) | |
| 1372 | #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ | |
| 1373 | #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ | |
| 1374 | #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ | |
| 1375 | #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ | |
| 1376 | ||
| 1377 | /* Enable render writes to complete in C2/C3/C4 power states. | |
| 1378 | * If this isn't enabled, render writes are prevented in low | |
| 1379 | * power states. That seems bad to me. | |
| 1380 | */ | |
| 1381 | #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) | |
| 1382 | ||
| 1383 | /* This acknowledges an async flip immediately instead | |
| 1384 | * of waiting for 2TLB fetches. | |
| 1385 | */ | |
| 1386 | #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) | |
| 1387 | ||
| 1388 | /* Enables non-sequential data reads through arbiter | |
| 1389 | */ | |
| 0206e353 | 1390 | #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) |
| 45503ded KP |
1391 | |
| 1392 | /* Disable FSB snooping of cacheable write cycles from binner/render | |
| 1393 | * command stream | |
| 1394 | */ | |
| 1395 | #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) | |
| 1396 | ||
| 1397 | /* Arbiter time slice for non-isoch streams */ | |
| 1398 | #define MI_ARB_TIME_SLICE_MASK (7 << 5) | |
| 1399 | #define MI_ARB_TIME_SLICE_1 (0 << 5) | |
| 1400 | #define MI_ARB_TIME_SLICE_2 (1 << 5) | |
| 1401 | #define MI_ARB_TIME_SLICE_4 (2 << 5) | |
| 1402 | #define MI_ARB_TIME_SLICE_6 (3 << 5) | |
| 1403 | #define MI_ARB_TIME_SLICE_8 (4 << 5) | |
| 1404 | #define MI_ARB_TIME_SLICE_10 (5 << 5) | |
| 1405 | #define MI_ARB_TIME_SLICE_14 (6 << 5) | |
| 1406 | #define MI_ARB_TIME_SLICE_16 (7 << 5) | |
| 1407 | ||
| 1408 | /* Low priority grace period page size */ | |
| 1409 | #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ | |
| 1410 | #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) | |
| 1411 | ||
| 1412 | /* Disable display A/B trickle feed */ | |
| 1413 | #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) | |
| 1414 | ||
| 1415 | /* Set display plane priority */ | |
| 1416 | #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ | |
| 1417 | #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ | |
| 1418 | ||
| 54e472ae VS |
1419 | #define MI_STATE 0x020e4 /* gen2 only */ |
| 1420 | #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ | |
| 1421 | #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ | |
| 1422 | ||
| 585fb111 | 1423 | #define CACHE_MODE_0 0x02120 /* 915+ only */ |
| 4358a374 | 1424 | #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) |
| 585fb111 JB |
1425 | #define CM0_IZ_OPT_DISABLE (1<<6) |
| 1426 | #define CM0_ZR_OPT_DISABLE (1<<5) | |
| 009be664 | 1427 | #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |
| 585fb111 JB |
1428 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) |
| 1429 | #define CM0_COLOR_EVICT_DISABLE (1<<3) | |
| 1430 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) | |
| 1431 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) | |
| 1432 | #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ | |
| 0f9b91c7 BW |
1433 | #define GFX_FLSH_CNTL_GEN6 0x101008 |
| 1434 | #define GFX_FLSH_CNTL_EN (1<<0) | |
| 1afe3e9d JB |
1435 | #define ECOSKPD 0x021d0 |
| 1436 | #define ECO_GATING_CX_ONLY (1<<3) | |
| 1437 | #define ECO_FLIP_DONE (1<<0) | |
| 585fb111 | 1438 | |
| fe27c606 | 1439 | #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ |
| 4e04632e | 1440 | #define RC_OP_FLUSH_ENABLE (1<<0) |
| fe27c606 | 1441 | #define HIZ_RAW_STALL_OPT_DISABLE (1<<2) |
| fb046853 | 1442 | #define CACHE_MODE_1 0x7004 /* IVB+ */ |
| 5d708680 DL |
1443 | #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) |
| 1444 | #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) | |
| fb046853 | 1445 | |
| 4efe0708 JB |
1446 | #define GEN6_BLITTER_ECOSKPD 0x221d0 |
| 1447 | #define GEN6_BLITTER_LOCK_SHIFT 16 | |
| 1448 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) | |
| 1449 | ||
| 295e8bb7 VS |
1450 | #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 |
| 1451 | #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) | |
| e4443e45 | 1452 | #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) |
| 295e8bb7 | 1453 | |
| 881f47b6 | 1454 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
| 12f55818 CW |
1455 | #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) |
| 1456 | #define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) | |
| 1457 | #define GEN6_BSD_SLEEP_INDICATOR (1 << 3) | |
| 1458 | #define GEN6_BSD_GO_INDICATOR (1 << 4) | |
| 881f47b6 | 1459 | |
| cc609d5d BW |
1460 | /* On modern GEN architectures interrupt control consists of two sets |
| 1461 | * of registers. The first set pertains to the ring generating the | |
| 1462 | * interrupt. The second control is for the functional block generating the | |
| 1463 | * interrupt. These are PM, GT, DE, etc. | |
| 1464 | * | |
| 1465 | * Luckily *knocks on wood* all the ring interrupt bits match up with the | |
| 1466 | * GT interrupt bits, so we don't need to duplicate the defines. | |
| 1467 | * | |
| 1468 | * These defines should cover us well from SNB->HSW with minor exceptions | |
| 1469 | * it can also work on ILK. | |
| 1470 | */ | |
| 1471 | #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) | |
| 1472 | #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) | |
| 1473 | #define GT_BLT_USER_INTERRUPT (1 << 22) | |
| 1474 | #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) | |
| 1475 | #define GT_BSD_USER_INTERRUPT (1 << 12) | |
| 35a85ac6 | 1476 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ |
| 73d477f6 | 1477 | #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) |
| cc609d5d BW |
1478 | #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ |
| 1479 | #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) | |
| 1480 | #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) | |
| 1481 | #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) | |
| 1482 | #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) | |
| 1483 | #define GT_RENDER_USER_INTERRUPT (1 << 0) | |
| 1484 | ||
| 12638c57 BW |
1485 | #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ |
| 1486 | #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ | |
| 1487 | ||
| 35a85ac6 BW |
1488 | #define GT_PARITY_ERROR(dev) \ |
| 1489 | (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ | |
| 45f80d53 | 1490 | (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) |
| 35a85ac6 | 1491 | |
| cc609d5d BW |
1492 | /* These are all the "old" interrupts */ |
| 1493 | #define ILK_BSD_USER_INTERRUPT (1<<5) | |
| fac12f6c VS |
1494 | |
| 1495 | #define I915_PM_INTERRUPT (1<<31) | |
| 1496 | #define I915_ISP_INTERRUPT (1<<22) | |
| 1497 | #define I915_LPE_PIPE_B_INTERRUPT (1<<21) | |
| 1498 | #define I915_LPE_PIPE_A_INTERRUPT (1<<20) | |
| e7d7cad0 | 1499 | #define I915_MIPIC_INTERRUPT (1<<19) |
| fac12f6c | 1500 | #define I915_MIPIA_INTERRUPT (1<<18) |
| cc609d5d BW |
1501 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
| 1502 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | |
| fac12f6c VS |
1503 | #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) |
| 1504 | #define I915_MASTER_ERROR_INTERRUPT (1<<15) | |
| cc609d5d | 1505 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) |
| fac12f6c | 1506 | #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) |
| cc609d5d | 1507 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ |
| fac12f6c | 1508 | #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) |
| cc609d5d | 1509 | #define I915_HWB_OOM_INTERRUPT (1<<13) |
| fac12f6c | 1510 | #define I915_LPE_PIPE_C_INTERRUPT (1<<12) |
| cc609d5d | 1511 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) |
| fac12f6c | 1512 | #define I915_MISC_INTERRUPT (1<<11) |
| cc609d5d | 1513 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) |
| fac12f6c | 1514 | #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) |
| cc609d5d | 1515 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) |
| fac12f6c | 1516 | #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) |
| cc609d5d | 1517 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) |
| fac12f6c | 1518 | #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) |
| cc609d5d BW |
1519 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) |
| 1520 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) | |
| 1521 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) | |
| 1522 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) | |
| 1523 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) | |
| fac12f6c VS |
1524 | #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) |
| 1525 | #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) | |
| cc609d5d | 1526 | #define I915_DEBUG_INTERRUPT (1<<2) |
| fac12f6c | 1527 | #define I915_WINVALID_INTERRUPT (1<<1) |
| cc609d5d BW |
1528 | #define I915_USER_INTERRUPT (1<<1) |
| 1529 | #define I915_ASLE_INTERRUPT (1<<0) | |
| fac12f6c | 1530 | #define I915_BSD_USER_INTERRUPT (1<<25) |
| 881f47b6 XH |
1531 | |
| 1532 | #define GEN6_BSD_RNCID 0x12198 | |
| 1533 | ||
| a1e969e0 BW |
1534 | #define GEN7_FF_THREAD_MODE 0x20a0 |
| 1535 | #define GEN7_FF_SCHED_MASK 0x0077070 | |
| ab57fff1 | 1536 | #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) |
| a1e969e0 BW |
1537 | #define GEN7_FF_TS_SCHED_HS1 (0x5<<16) |
| 1538 | #define GEN7_FF_TS_SCHED_HS0 (0x3<<16) | |
| 1539 | #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) | |
| 1540 | #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ | |
| 41c0b3a8 | 1541 | #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) |
| a1e969e0 BW |
1542 | #define GEN7_FF_VS_SCHED_HS1 (0x5<<12) |
| 1543 | #define GEN7_FF_VS_SCHED_HS0 (0x3<<12) | |
| 1544 | #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ | |
| 1545 | #define GEN7_FF_VS_SCHED_HW (0x0<<12) | |
| 1546 | #define GEN7_FF_DS_SCHED_HS1 (0x5<<4) | |
| 1547 | #define GEN7_FF_DS_SCHED_HS0 (0x3<<4) | |
| 1548 | #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ | |
| 1549 | #define GEN7_FF_DS_SCHED_HW (0x0<<4) | |
| 1550 | ||
| 585fb111 JB |
1551 | /* |
| 1552 | * Framebuffer compression (915+ only) | |
| 1553 | */ | |
| 1554 | ||
| 1555 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ | |
| 1556 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ | |
| 1557 | #define FBC_CONTROL 0x03208 | |
| 1558 | #define FBC_CTL_EN (1<<31) | |
| 1559 | #define FBC_CTL_PERIODIC (1<<30) | |
| 1560 | #define FBC_CTL_INTERVAL_SHIFT (16) | |
| 1561 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) | |
| 49677901 | 1562 | #define FBC_CTL_C3_IDLE (1<<13) |
| 585fb111 | 1563 | #define FBC_CTL_STRIDE_SHIFT (5) |
| 82f34496 | 1564 | #define FBC_CTL_FENCENO_SHIFT (0) |
| 585fb111 JB |
1565 | #define FBC_COMMAND 0x0320c |
| 1566 | #define FBC_CMD_COMPRESS (1<<0) | |
| 1567 | #define FBC_STATUS 0x03210 | |
| 1568 | #define FBC_STAT_COMPRESSING (1<<31) | |
| 1569 | #define FBC_STAT_COMPRESSED (1<<30) | |
| 1570 | #define FBC_STAT_MODIFIED (1<<29) | |
| 82f34496 | 1571 | #define FBC_STAT_CURRENT_LINE_SHIFT (0) |
| 585fb111 JB |
1572 | #define FBC_CONTROL2 0x03214 |
| 1573 | #define FBC_CTL_FENCE_DBL (0<<4) | |
| 1574 | #define FBC_CTL_IDLE_IMM (0<<2) | |
| 1575 | #define FBC_CTL_IDLE_FULL (1<<2) | |
| 1576 | #define FBC_CTL_IDLE_LINE (2<<2) | |
| 1577 | #define FBC_CTL_IDLE_DEBUG (3<<2) | |
| 1578 | #define FBC_CTL_CPU_FENCE (1<<1) | |
| 7f2cf220 | 1579 | #define FBC_CTL_PLANE(plane) ((plane)<<0) |
| f64f1726 | 1580 | #define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ |
| 80824003 | 1581 | #define FBC_TAG 0x03300 |
| 585fb111 JB |
1582 | |
| 1583 | #define FBC_LL_SIZE (1536) | |
| 1584 | ||
| 74dff282 JB |
1585 | /* Framebuffer compression for GM45+ */ |
| 1586 | #define DPFC_CB_BASE 0x3200 | |
| 1587 | #define DPFC_CONTROL 0x3208 | |
| 1588 | #define DPFC_CTL_EN (1<<31) | |
| 7f2cf220 VS |
1589 | #define DPFC_CTL_PLANE(plane) ((plane)<<30) |
| 1590 | #define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) | |
| 74dff282 | 1591 | #define DPFC_CTL_FENCE_EN (1<<29) |
| abe959c7 | 1592 | #define IVB_DPFC_CTL_FENCE_EN (1<<28) |
| 9ce9d069 | 1593 | #define DPFC_CTL_PERSISTENT_MODE (1<<25) |
| 74dff282 JB |
1594 | #define DPFC_SR_EN (1<<10) |
| 1595 | #define DPFC_CTL_LIMIT_1X (0<<6) | |
| 1596 | #define DPFC_CTL_LIMIT_2X (1<<6) | |
| 1597 | #define DPFC_CTL_LIMIT_4X (2<<6) | |
| 1598 | #define DPFC_RECOMP_CTL 0x320c | |
| 1599 | #define DPFC_RECOMP_STALL_EN (1<<27) | |
| 1600 | #define DPFC_RECOMP_STALL_WM_SHIFT (16) | |
| 1601 | #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) | |
| 1602 | #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) | |
| 1603 | #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) | |
| 1604 | #define DPFC_STATUS 0x3210 | |
| 1605 | #define DPFC_INVAL_SEG_SHIFT (16) | |
| 1606 | #define DPFC_INVAL_SEG_MASK (0x07ff0000) | |
| 1607 | #define DPFC_COMP_SEG_SHIFT (0) | |
| 1608 | #define DPFC_COMP_SEG_MASK (0x000003ff) | |
| 1609 | #define DPFC_STATUS2 0x3214 | |
| 1610 | #define DPFC_FENCE_YOFF 0x3218 | |
| 1611 | #define DPFC_CHICKEN 0x3224 | |
| 1612 | #define DPFC_HT_MODIFY (1<<31) | |
| 1613 | ||
| b52eb4dc ZY |
1614 | /* Framebuffer compression for Ironlake */ |
| 1615 | #define ILK_DPFC_CB_BASE 0x43200 | |
| 1616 | #define ILK_DPFC_CONTROL 0x43208 | |
| da46f936 | 1617 | #define FBC_CTL_FALSE_COLOR (1<<10) |
| b52eb4dc ZY |
1618 | /* The bit 28-8 is reserved */ |
| 1619 | #define DPFC_RESERVED (0x1FFFFF00) | |
| 1620 | #define ILK_DPFC_RECOMP_CTL 0x4320c | |
| 1621 | #define ILK_DPFC_STATUS 0x43210 | |
| 1622 | #define ILK_DPFC_FENCE_YOFF 0x43218 | |
| 1623 | #define ILK_DPFC_CHICKEN 0x43224 | |
| 1624 | #define ILK_FBC_RT_BASE 0x2128 | |
| 1625 | #define ILK_FBC_RT_VALID (1<<0) | |
| abe959c7 | 1626 | #define SNB_FBC_FRONT_BUFFER (1<<1) |
| b52eb4dc ZY |
1627 | |
| 1628 | #define ILK_DISPLAY_CHICKEN1 0x42000 | |
| 1629 | #define ILK_FBCQ_DIS (1<<22) | |
| 0206e353 | 1630 | #define ILK_PABSTRETCH_DIS (1<<21) |
| 1398261a | 1631 | |
| b52eb4dc | 1632 | |
| 9c04f015 YL |
1633 | /* |
| 1634 | * Framebuffer compression for Sandybridge | |
| 1635 | * | |
| 1636 | * The following two registers are of type GTTMMADR | |
| 1637 | */ | |
| 1638 | #define SNB_DPFC_CTL_SA 0x100100 | |
| 1639 | #define SNB_CPU_FENCE_ENABLE (1<<29) | |
| 1640 | #define DPFC_CPU_FENCE_OFFSET 0x100104 | |
| 1641 | ||
| abe959c7 RV |
1642 | /* Framebuffer compression for Ivybridge */ |
| 1643 | #define IVB_FBC_RT_BASE 0x7020 | |
| 1644 | ||
| 42db64ef PZ |
1645 | #define IPS_CTL 0x43408 |
| 1646 | #define IPS_ENABLE (1 << 31) | |
| 9c04f015 | 1647 | |
| fd3da6c9 RV |
1648 | #define MSG_FBC_REND_STATE 0x50380 |
| 1649 | #define FBC_REND_NUKE (1<<2) | |
| 1650 | #define FBC_REND_CACHE_CLEAN (1<<1) | |
| 1651 | ||
| 585fb111 JB |
1652 | /* |
| 1653 | * GPIO regs | |
| 1654 | */ | |
| 1655 | #define GPIOA 0x5010 | |
| 1656 | #define GPIOB 0x5014 | |
| 1657 | #define GPIOC 0x5018 | |
| 1658 | #define GPIOD 0x501c | |
| 1659 | #define GPIOE 0x5020 | |
| 1660 | #define GPIOF 0x5024 | |
| 1661 | #define GPIOG 0x5028 | |
| 1662 | #define GPIOH 0x502c | |
| 1663 | # define GPIO_CLOCK_DIR_MASK (1 << 0) | |
| 1664 | # define GPIO_CLOCK_DIR_IN (0 << 1) | |
| 1665 | # define GPIO_CLOCK_DIR_OUT (1 << 1) | |
| 1666 | # define GPIO_CLOCK_VAL_MASK (1 << 2) | |
| 1667 | # define GPIO_CLOCK_VAL_OUT (1 << 3) | |
| 1668 | # define GPIO_CLOCK_VAL_IN (1 << 4) | |
| 1669 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
| 1670 | # define GPIO_DATA_DIR_MASK (1 << 8) | |
| 1671 | # define GPIO_DATA_DIR_IN (0 << 9) | |
| 1672 | # define GPIO_DATA_DIR_OUT (1 << 9) | |
| 1673 | # define GPIO_DATA_VAL_MASK (1 << 10) | |
| 1674 | # define GPIO_DATA_VAL_OUT (1 << 11) | |
| 1675 | # define GPIO_DATA_VAL_IN (1 << 12) | |
| 1676 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
| 1677 | ||
| f899fc64 CW |
1678 | #define GMBUS0 0x5100 /* clock/port select */ |
| 1679 | #define GMBUS_RATE_100KHZ (0<<8) | |
| 1680 | #define GMBUS_RATE_50KHZ (1<<8) | |
| 1681 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ | |
| 1682 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ | |
| 1683 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ | |
| 1684 | #define GMBUS_PORT_DISABLED 0 | |
| 1685 | #define GMBUS_PORT_SSC 1 | |
| 1686 | #define GMBUS_PORT_VGADDC 2 | |
| 1687 | #define GMBUS_PORT_PANEL 3 | |
| c0c35329 | 1688 | #define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ |
| f899fc64 CW |
1689 | #define GMBUS_PORT_DPC 4 /* HDMIC */ |
| 1690 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ | |
| e4fd17af DK |
1691 | #define GMBUS_PORT_DPD 6 /* HDMID */ |
| 1692 | #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ | |
| 2ed06c93 | 1693 | #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) |
| f899fc64 CW |
1694 | #define GMBUS1 0x5104 /* command/status */ |
| 1695 | #define GMBUS_SW_CLR_INT (1<<31) | |
| 1696 | #define GMBUS_SW_RDY (1<<30) | |
| 1697 | #define GMBUS_ENT (1<<29) /* enable timeout */ | |
| 1698 | #define GMBUS_CYCLE_NONE (0<<25) | |
| 1699 | #define GMBUS_CYCLE_WAIT (1<<25) | |
| 1700 | #define GMBUS_CYCLE_INDEX (2<<25) | |
| 1701 | #define GMBUS_CYCLE_STOP (4<<25) | |
| 1702 | #define GMBUS_BYTE_COUNT_SHIFT 16 | |
| 1703 | #define GMBUS_SLAVE_INDEX_SHIFT 8 | |
| 1704 | #define GMBUS_SLAVE_ADDR_SHIFT 1 | |
| 1705 | #define GMBUS_SLAVE_READ (1<<0) | |
| 1706 | #define GMBUS_SLAVE_WRITE (0<<0) | |
| 1707 | #define GMBUS2 0x5108 /* status */ | |
| 1708 | #define GMBUS_INUSE (1<<15) | |
| 1709 | #define GMBUS_HW_WAIT_PHASE (1<<14) | |
| 1710 | #define GMBUS_STALL_TIMEOUT (1<<13) | |
| 1711 | #define GMBUS_INT (1<<12) | |
| 1712 | #define GMBUS_HW_RDY (1<<11) | |
| 1713 | #define GMBUS_SATOER (1<<10) | |
| 1714 | #define GMBUS_ACTIVE (1<<9) | |
| 1715 | #define GMBUS3 0x510c /* data buffer bytes 3-0 */ | |
| 1716 | #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ | |
| 1717 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) | |
| 1718 | #define GMBUS_NAK_EN (1<<3) | |
| 1719 | #define GMBUS_IDLE_EN (1<<2) | |
| 1720 | #define GMBUS_HW_WAIT_EN (1<<1) | |
| 1721 | #define GMBUS_HW_RDY_EN (1<<0) | |
| 1722 | #define GMBUS5 0x5120 /* byte index */ | |
| 1723 | #define GMBUS_2BYTE_INDEX_EN (1<<31) | |
| f0217c42 | 1724 | |
| 585fb111 JB |
1725 | /* |
| 1726 | * Clock control & power management | |
| 1727 | */ | |
| 2d401b17 VS |
1728 | #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) |
| 1729 | #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) | |
| 1730 | #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) | |
| 1731 | #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) | |
| 585fb111 JB |
1732 | |
| 1733 | #define VGA0 0x6000 | |
| 1734 | #define VGA1 0x6004 | |
| 1735 | #define VGA_PD 0x6010 | |
| 1736 | #define VGA0_PD_P2_DIV_4 (1 << 7) | |
| 1737 | #define VGA0_PD_P1_DIV_2 (1 << 5) | |
| 1738 | #define VGA0_PD_P1_SHIFT 0 | |
| 1739 | #define VGA0_PD_P1_MASK (0x1f << 0) | |
| 1740 | #define VGA1_PD_P2_DIV_4 (1 << 15) | |
| 1741 | #define VGA1_PD_P1_DIV_2 (1 << 13) | |
| 1742 | #define VGA1_PD_P1_SHIFT 8 | |
| 1743 | #define VGA1_PD_P1_MASK (0x1f << 8) | |
| 585fb111 | 1744 | #define DPLL_VCO_ENABLE (1 << 31) |
| 4a33e48d DV |
1745 | #define DPLL_SDVO_HIGH_SPEED (1 << 30) |
| 1746 | #define DPLL_DVO_2X_MODE (1 << 30) | |
| 25eb05fc | 1747 | #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) |
| 585fb111 | 1748 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) |
| 25eb05fc | 1749 | #define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) |
| 585fb111 JB |
1750 | #define DPLL_VGA_MODE_DIS (1 << 28) |
| 1751 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
| 1752 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
| 1753 | #define DPLL_MODE_MASK (3 << 26) | |
| 1754 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
| 1755 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
| 1756 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
| 1757 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
| 1758 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
| 1759 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | |
| f2b115e6 | 1760 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
| a0c4da24 | 1761 | #define DPLL_LOCK_VLV (1<<15) |
| 598fac6b | 1762 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
| 25eb05fc | 1763 | #define DPLL_INTEGRATED_CLOCK_VLV (1<<13) |
| 9d556c99 | 1764 | #define DPLL_SSC_REF_CLOCK_CHV (1<<13) |
| 598fac6b DV |
1765 | #define DPLL_PORTC_READY_MASK (0xf << 4) |
| 1766 | #define DPLL_PORTB_READY_MASK (0xf) | |
| 585fb111 | 1767 | |
| 585fb111 | 1768 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 |
| 00fc31b7 CML |
1769 | |
| 1770 | /* Additional CHV pll/phy registers */ | |
| 1771 | #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) | |
| 1772 | #define DPLL_PORTD_READY_MASK (0xf) | |
| 076ed3b2 | 1773 | #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) |
| efd814b7 | 1774 | #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) |
| 076ed3b2 | 1775 | #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) |
| efd814b7 | 1776 | #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) |
| 076ed3b2 | 1777 | |
| 585fb111 JB |
1778 | /* |
| 1779 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
| 1780 | * this field (only one bit may be set). | |
| 1781 | */ | |
| 1782 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
| 1783 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
| f2b115e6 | 1784 | #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 |
| 585fb111 JB |
1785 | /* i830, required in DVO non-gang */ |
| 1786 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) | |
| 1787 | #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
| 1788 | #define PLL_REF_INPUT_DREFCLK (0 << 13) | |
| 1789 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
| 1790 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ | |
| 1791 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
| 1792 | #define PLL_REF_INPUT_MASK (3 << 13) | |
| 1793 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
| f2b115e6 | 1794 | /* Ironlake */ |
| b9055052 ZW |
1795 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 |
| 1796 | # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) | |
| 1797 | # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) | |
| 1798 | # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 | |
| 1799 | # define DPLL_FPA1_P1_POST_DIV_MASK 0xff | |
| 1800 | ||
| 585fb111 JB |
1801 | /* |
| 1802 | * Parallel to Serial Load Pulse phase selection. | |
| 1803 | * Selects the phase for the 10X DPLL clock for the PCIe | |
| 1804 | * digital display port. The range is 4 to 13; 10 or more | |
| 1805 | * is just a flip delay. The default is 6 | |
| 1806 | */ | |
| 1807 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
| 1808 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
| 1809 | /* | |
| 1810 | * SDVO multiplier for 945G/GM. Not used on 965. | |
| 1811 | */ | |
| 1812 | #define SDVO_MULTIPLIER_MASK 0x000000ff | |
| 1813 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
| 1814 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
| a57c774a | 1815 | |
| 2d401b17 VS |
1816 | #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) |
| 1817 | #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) | |
| 1818 | #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) | |
| 1819 | #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) | |
| a57c774a | 1820 | |
| 585fb111 JB |
1821 | /* |
| 1822 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
| 1823 | * | |
| 1824 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
| 1825 | */ | |
| 1826 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
| 1827 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
| 1828 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
| 1829 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
| 1830 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
| 1831 | /* | |
| 1832 | * SDVO/UDI pixel multiplier. | |
| 1833 | * | |
| 1834 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
| 1835 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
| 1836 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
| 1837 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
| 1838 | * the link knowing how many bytes are fill. | |
| 1839 | * | |
| 1840 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
| 1841 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
| 1842 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
| 1843 | * through an SDVO command. | |
| 1844 | * | |
| 1845 | * This register field has values of multiplication factor minus 1, with | |
| 1846 | * a maximum multiplier of 5 for SDVO. | |
| 1847 | */ | |
| 1848 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
| 1849 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
| 1850 | /* | |
| 1851 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
| 1852 | * This best be set to the default value (3) or the CRT won't work. No, | |
| 1853 | * I don't entirely understand what this does... | |
| 1854 | */ | |
| 1855 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
| 1856 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
| 25eb05fc | 1857 | |
| 9db4a9c7 JB |
1858 | #define _FPA0 0x06040 |
| 1859 | #define _FPA1 0x06044 | |
| 1860 | #define _FPB0 0x06048 | |
| 1861 | #define _FPB1 0x0604c | |
| 1862 | #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) | |
| 1863 | #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) | |
| 585fb111 | 1864 | #define FP_N_DIV_MASK 0x003f0000 |
| f2b115e6 | 1865 | #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 |
| 585fb111 JB |
1866 | #define FP_N_DIV_SHIFT 16 |
| 1867 | #define FP_M1_DIV_MASK 0x00003f00 | |
| 1868 | #define FP_M1_DIV_SHIFT 8 | |
| 1869 | #define FP_M2_DIV_MASK 0x0000003f | |
| f2b115e6 | 1870 | #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff |
| 585fb111 JB |
1871 | #define FP_M2_DIV_SHIFT 0 |
| 1872 | #define DPLL_TEST 0x606c | |
| 1873 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) | |
| 1874 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
| 1875 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
| 1876 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
| 1877 | #define DPLLB_TEST_N_BYPASS (1 << 19) | |
| 1878 | #define DPLLB_TEST_M_BYPASS (1 << 18) | |
| 1879 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
| 1880 | #define DPLLA_TEST_N_BYPASS (1 << 3) | |
| 1881 | #define DPLLA_TEST_M_BYPASS (1 << 2) | |
| 1882 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
| 1883 | #define D_STATE 0x6104 | |
| dc96e9b8 | 1884 | #define DSTATE_GFX_RESET_I830 (1<<6) |
| 652c393a JB |
1885 | #define DSTATE_PLL_D3_OFF (1<<3) |
| 1886 | #define DSTATE_GFX_CLOCK_GATING (1<<1) | |
| 1887 | #define DSTATE_DOT_CLOCK_GATING (1<<0) | |
| 5c969aa7 | 1888 | #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) |
| 652c393a JB |
1889 | # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ |
| 1890 | # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ | |
| 1891 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ | |
| 1892 | # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ | |
| 1893 | # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ | |
| 1894 | # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ | |
| 1895 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ | |
| 1896 | # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ | |
| 1897 | # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ | |
| 1898 | # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ | |
| 1899 | # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ | |
| 1900 | # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ | |
| 1901 | # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ | |
| 1902 | # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ | |
| 1903 | # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ | |
| 1904 | # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ | |
| 1905 | # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ | |
| 1906 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ | |
| 1907 | # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ | |
| 1908 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
| 1909 | # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) | |
| 1910 | # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
| 1911 | # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
| 1912 | # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ | |
| 1913 | # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ | |
| 1914 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ | |
| 1915 | # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) | |
| 1916 | # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) | |
| 646b4269 | 1917 | /* |
| 652c393a JB |
1918 | * This bit must be set on the 830 to prevent hangs when turning off the |
| 1919 | * overlay scaler. | |
| 1920 | */ | |
| 1921 | # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) | |
| 1922 | # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) | |
| 1923 | # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
| 1924 | # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ | |
| 1925 | # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ | |
| 1926 | ||
| 1927 | #define RENCLK_GATE_D1 0x6204 | |
| 1928 | # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ | |
| 1929 | # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ | |
| 1930 | # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) | |
| 1931 | # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) | |
| 1932 | # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) | |
| 1933 | # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) | |
| 1934 | # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) | |
| 1935 | # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) | |
| 1936 | # define MAG_CLOCK_GATE_DISABLE (1 << 5) | |
| 646b4269 | 1937 | /* This bit must be unset on 855,865 */ |
| 652c393a JB |
1938 | # define MECI_CLOCK_GATE_DISABLE (1 << 4) |
| 1939 | # define DCMP_CLOCK_GATE_DISABLE (1 << 3) | |
| 1940 | # define MEC_CLOCK_GATE_DISABLE (1 << 2) | |
| 1941 | # define MECO_CLOCK_GATE_DISABLE (1 << 1) | |
| 646b4269 | 1942 | /* This bit must be set on 855,865. */ |
| 652c393a JB |
1943 | # define SV_CLOCK_GATE_DISABLE (1 << 0) |
| 1944 | # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) | |
| 1945 | # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) | |
| 1946 | # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) | |
| 1947 | # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) | |
| 1948 | # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) | |
| 1949 | # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) | |
| 1950 | # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) | |
| 1951 | # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) | |
| 1952 | # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) | |
| 1953 | # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) | |
| 1954 | # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) | |
| 1955 | # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) | |
| 1956 | # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) | |
| 1957 | # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) | |
| 1958 | # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) | |
| 1959 | # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) | |
| 1960 | # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) | |
| 1961 | ||
| 1962 | # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) | |
| 646b4269 | 1963 | /* This bit must always be set on 965G/965GM */ |
| 652c393a JB |
1964 | # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) |
| 1965 | # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) | |
| 1966 | # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) | |
| 1967 | # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) | |
| 1968 | # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) | |
| 1969 | # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) | |
| 646b4269 | 1970 | /* This bit must always be set on 965G */ |
| 652c393a JB |
1971 | # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) |
| 1972 | # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) | |
| 1973 | # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) | |
| 1974 | # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) | |
| 1975 | # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) | |
| 1976 | # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) | |
| 1977 | # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) | |
| 1978 | # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) | |
| 1979 | # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) | |
| 1980 | # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) | |
| 1981 | # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) | |
| 1982 | # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) | |
| 1983 | # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) | |
| 1984 | # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) | |
| 1985 | # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) | |
| 1986 | # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) | |
| 1987 | # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) | |
| 1988 | # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) | |
| 1989 | # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) | |
| 1990 | ||
| 1991 | #define RENCLK_GATE_D2 0x6208 | |
| 1992 | #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) | |
| 1993 | #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) | |
| 1994 | #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) | |
| fa4f53c4 VS |
1995 | |
| 1996 | #define VDECCLK_GATE_D 0x620C /* g4x only */ | |
| 1997 | #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) | |
| 1998 | ||
| 652c393a JB |
1999 | #define RAMCLK_GATE_D 0x6210 /* CRL only */ |
| 2000 | #define DEUC 0x6214 /* CRL only */ | |
| 585fb111 | 2001 | |
| d88b2270 | 2002 | #define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) |
| ceb04246 JB |
2003 | #define FW_CSPWRDWNEN (1<<15) |
| 2004 | ||
| e0d8d59b VS |
2005 | #define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) |
| 2006 | ||
| 24eb2d59 CML |
2007 | #define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) |
| 2008 | #define CDCLK_FREQ_SHIFT 4 | |
| 2009 | #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) | |
| 2010 | #define CZCLK_FREQ_MASK 0xf | |
| 2011 | #define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) | |
| 2012 | ||
| 585fb111 JB |
2013 | /* |
| 2014 | * Palette regs | |
| 2015 | */ | |
| a57c774a AK |
2016 | #define PALETTE_A_OFFSET 0xa000 |
| 2017 | #define PALETTE_B_OFFSET 0xa800 | |
| 84fd4f4e | 2018 | #define CHV_PALETTE_C_OFFSET 0xc000 |
| 5c969aa7 DL |
2019 | #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ |
| 2020 | dev_priv->info.display_mmio_offset) | |
| 585fb111 | 2021 | |
| 673a394b EA |
2022 | /* MCH MMIO space */ |
| 2023 | ||
| 2024 | /* | |
| 2025 | * MCHBAR mirror. | |
| 2026 | * | |
| 2027 | * This mirrors the MCHBAR MMIO space whose location is determined by | |
| 2028 | * device 0 function 0's pci config register 0x44 or 0x48 and matches it in | |
| 2029 | * every way. It is not accessible from the CP register read instructions. | |
| 2030 | * | |
| 515b2392 PZ |
2031 | * Starting from Haswell, you can't write registers using the MCHBAR mirror, |
| 2032 | * just read. | |
| 673a394b EA |
2033 | */ |
| 2034 | #define MCHBAR_MIRROR_BASE 0x10000 | |
| 2035 | ||
| 1398261a YL |
2036 | #define MCHBAR_MIRROR_BASE_SNB 0x140000 |
| 2037 | ||
| 3ebecd07 | 2038 | /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ |
| 153b4b95 | 2039 | #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) |
| 3ebecd07 | 2040 | |
| 646b4269 | 2041 | /* 915-945 and GM965 MCH register controlling DRAM channel access */ |
| 673a394b EA |
2042 | #define DCC 0x10200 |
| 2043 | #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) | |
| 2044 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) | |
| 2045 | #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) | |
| 2046 | #define DCC_ADDRESSING_MODE_MASK (3 << 0) | |
| 2047 | #define DCC_CHANNEL_XOR_DISABLE (1 << 10) | |
| a7f014f2 | 2048 | #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) |
| 656bfa3a DV |
2049 | #define DCC2 0x10204 |
| 2050 | #define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) | |
| 673a394b | 2051 | |
| 646b4269 | 2052 | /* Pineview MCH register contains DDR3 setting */ |
| 95534263 LP |
2053 | #define CSHRDDR3CTL 0x101a8 |
| 2054 | #define CSHRDDR3CTL_DDR3 (1 << 2) | |
| 2055 | ||
| 646b4269 | 2056 | /* 965 MCH register controlling DRAM channel configuration */ |
| 673a394b EA |
2057 | #define C0DRB3 0x10206 |
| 2058 | #define C1DRB3 0x10606 | |
| 2059 | ||
| 646b4269 | 2060 | /* snb MCH registers for reading the DRAM channel configuration */ |
| f691e2f4 DV |
2061 | #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) |
| 2062 | #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) | |
| 2063 | #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) | |
| 2064 | #define MAD_DIMM_ECC_MASK (0x3 << 24) | |
| 2065 | #define MAD_DIMM_ECC_OFF (0x0 << 24) | |
| 2066 | #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) | |
| 2067 | #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) | |
| 2068 | #define MAD_DIMM_ECC_ON (0x3 << 24) | |
| 2069 | #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) | |
| 2070 | #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) | |
| 2071 | #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ | |
| 2072 | #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ | |
| 2073 | #define MAD_DIMM_B_DUAL_RANK (0x1 << 18) | |
| 2074 | #define MAD_DIMM_A_DUAL_RANK (0x1 << 17) | |
| 2075 | #define MAD_DIMM_A_SELECT (0x1 << 16) | |
| 2076 | /* DIMM sizes are in multiples of 256mb. */ | |
| 2077 | #define MAD_DIMM_B_SIZE_SHIFT 8 | |
| 2078 | #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) | |
| 2079 | #define MAD_DIMM_A_SIZE_SHIFT 0 | |
| 2080 | #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) | |
| 2081 | ||
| 646b4269 | 2082 | /* snb MCH registers for priority tuning */ |
| 1d7aaa0c DV |
2083 | #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) |
| 2084 | #define MCH_SSKPD_WM0_MASK 0x3f | |
| 2085 | #define MCH_SSKPD_WM0_VAL 0xc | |
| f691e2f4 | 2086 | |
| ec013e7f JB |
2087 | #define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) |
| 2088 | ||
| b11248df KP |
2089 | /* Clocking configuration register */ |
| 2090 | #define CLKCFG 0x10c00 | |
| 7662c8bd | 2091 | #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ |
| b11248df KP |
2092 | #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ |
| 2093 | #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ | |
| 2094 | #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ | |
| 2095 | #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ | |
| 2096 | #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ | |
| 7662c8bd | 2097 | /* Note, below two are guess */ |
| b11248df | 2098 | #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ |
| 7662c8bd | 2099 | #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ |
| b11248df | 2100 | #define CLKCFG_FSB_MASK (7 << 0) |
| 7662c8bd SL |
2101 | #define CLKCFG_MEM_533 (1 << 4) |
| 2102 | #define CLKCFG_MEM_667 (2 << 4) | |
| 2103 | #define CLKCFG_MEM_800 (3 << 4) | |
| 2104 | #define CLKCFG_MEM_MASK (7 << 4) | |
| 2105 | ||
| ea056c14 JB |
2106 | #define TSC1 0x11001 |
| 2107 | #define TSE (1<<0) | |
| 7648fa99 JB |
2108 | #define TR1 0x11006 |
| 2109 | #define TSFS 0x11020 | |
| 2110 | #define TSFS_SLOPE_MASK 0x0000ff00 | |
| 2111 | #define TSFS_SLOPE_SHIFT 8 | |
| 2112 | #define TSFS_INTR_MASK 0x000000ff | |
| 2113 | ||
| f97108d1 JB |
2114 | #define CRSTANDVID 0x11100 |
| 2115 | #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ | |
| 2116 | #define PXVFREQ_PX_MASK 0x7f000000 | |
| 2117 | #define PXVFREQ_PX_SHIFT 24 | |
| 2118 | #define VIDFREQ_BASE 0x11110 | |
| 2119 | #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ | |
| 2120 | #define VIDFREQ2 0x11114 | |
| 2121 | #define VIDFREQ3 0x11118 | |
| 2122 | #define VIDFREQ4 0x1111c | |
| 2123 | #define VIDFREQ_P0_MASK 0x1f000000 | |
| 2124 | #define VIDFREQ_P0_SHIFT 24 | |
| 2125 | #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 | |
| 2126 | #define VIDFREQ_P0_CSCLK_SHIFT 20 | |
| 2127 | #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 | |
| 2128 | #define VIDFREQ_P0_CRCLK_SHIFT 16 | |
| 2129 | #define VIDFREQ_P1_MASK 0x00001f00 | |
| 2130 | #define VIDFREQ_P1_SHIFT 8 | |
| 2131 | #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 | |
| 2132 | #define VIDFREQ_P1_CSCLK_SHIFT 4 | |
| 2133 | #define VIDFREQ_P1_CRCLK_MASK 0x0000000f | |
| 2134 | #define INTTOEXT_BASE_ILK 0x11300 | |
| 2135 | #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ | |
| 2136 | #define INTTOEXT_MAP3_SHIFT 24 | |
| 2137 | #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) | |
| 2138 | #define INTTOEXT_MAP2_SHIFT 16 | |
| 2139 | #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) | |
| 2140 | #define INTTOEXT_MAP1_SHIFT 8 | |
| 2141 | #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) | |
| 2142 | #define INTTOEXT_MAP0_SHIFT 0 | |
| 2143 | #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) | |
| 2144 | #define MEMSWCTL 0x11170 /* Ironlake only */ | |
| 2145 | #define MEMCTL_CMD_MASK 0xe000 | |
| 2146 | #define MEMCTL_CMD_SHIFT 13 | |
| 2147 | #define MEMCTL_CMD_RCLK_OFF 0 | |
| 2148 | #define MEMCTL_CMD_RCLK_ON 1 | |
| 2149 | #define MEMCTL_CMD_CHFREQ 2 | |
| 2150 | #define MEMCTL_CMD_CHVID 3 | |
| 2151 | #define MEMCTL_CMD_VMMOFF 4 | |
| 2152 | #define MEMCTL_CMD_VMMON 5 | |
| 2153 | #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears | |
| 2154 | when command complete */ | |
| 2155 | #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ | |
| 2156 | #define MEMCTL_FREQ_SHIFT 8 | |
| 2157 | #define MEMCTL_SFCAVM (1<<7) | |
| 2158 | #define MEMCTL_TGT_VID_MASK 0x007f | |
| 2159 | #define MEMIHYST 0x1117c | |
| 2160 | #define MEMINTREN 0x11180 /* 16 bits */ | |
| 2161 | #define MEMINT_RSEXIT_EN (1<<8) | |
| 2162 | #define MEMINT_CX_SUPR_EN (1<<7) | |
| 2163 | #define MEMINT_CONT_BUSY_EN (1<<6) | |
| 2164 | #define MEMINT_AVG_BUSY_EN (1<<5) | |
| 2165 | #define MEMINT_EVAL_CHG_EN (1<<4) | |
| 2166 | #define MEMINT_MON_IDLE_EN (1<<3) | |
| 2167 | #define MEMINT_UP_EVAL_EN (1<<2) | |
| 2168 | #define MEMINT_DOWN_EVAL_EN (1<<1) | |
| 2169 | #define MEMINT_SW_CMD_EN (1<<0) | |
| 2170 | #define MEMINTRSTR 0x11182 /* 16 bits */ | |
| 2171 | #define MEM_RSEXIT_MASK 0xc000 | |
| 2172 | #define MEM_RSEXIT_SHIFT 14 | |
| 2173 | #define MEM_CONT_BUSY_MASK 0x3000 | |
| 2174 | #define MEM_CONT_BUSY_SHIFT 12 | |
| 2175 | #define MEM_AVG_BUSY_MASK 0x0c00 | |
| 2176 | #define MEM_AVG_BUSY_SHIFT 10 | |
| 2177 | #define MEM_EVAL_CHG_MASK 0x0300 | |
| 2178 | #define MEM_EVAL_BUSY_SHIFT 8 | |
| 2179 | #define MEM_MON_IDLE_MASK 0x00c0 | |
| 2180 | #define MEM_MON_IDLE_SHIFT 6 | |
| 2181 | #define MEM_UP_EVAL_MASK 0x0030 | |
| 2182 | #define MEM_UP_EVAL_SHIFT 4 | |
| 2183 | #define MEM_DOWN_EVAL_MASK 0x000c | |
| 2184 | #define MEM_DOWN_EVAL_SHIFT 2 | |
| 2185 | #define MEM_SW_CMD_MASK 0x0003 | |
| 2186 | #define MEM_INT_STEER_GFX 0 | |
| 2187 | #define MEM_INT_STEER_CMR 1 | |
| 2188 | #define MEM_INT_STEER_SMI 2 | |
| 2189 | #define MEM_INT_STEER_SCI 3 | |
| 2190 | #define MEMINTRSTS 0x11184 | |
| 2191 | #define MEMINT_RSEXIT (1<<7) | |
| 2192 | #define MEMINT_CONT_BUSY (1<<6) | |
| 2193 | #define MEMINT_AVG_BUSY (1<<5) | |
| 2194 | #define MEMINT_EVAL_CHG (1<<4) | |
| 2195 | #define MEMINT_MON_IDLE (1<<3) | |
| 2196 | #define MEMINT_UP_EVAL (1<<2) | |
| 2197 | #define MEMINT_DOWN_EVAL (1<<1) | |
| 2198 | #define MEMINT_SW_CMD (1<<0) | |
| 2199 | #define MEMMODECTL 0x11190 | |
| 2200 | #define MEMMODE_BOOST_EN (1<<31) | |
| 2201 | #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ | |
| 2202 | #define MEMMODE_BOOST_FREQ_SHIFT 24 | |
| 2203 | #define MEMMODE_IDLE_MODE_MASK 0x00030000 | |
| 2204 | #define MEMMODE_IDLE_MODE_SHIFT 16 | |
| 2205 | #define MEMMODE_IDLE_MODE_EVAL 0 | |
| 2206 | #define MEMMODE_IDLE_MODE_CONT 1 | |
| 2207 | #define MEMMODE_HWIDLE_EN (1<<15) | |
| 2208 | #define MEMMODE_SWMODE_EN (1<<14) | |
| 2209 | #define MEMMODE_RCLK_GATE (1<<13) | |
| 2210 | #define MEMMODE_HW_UPDATE (1<<12) | |
| 2211 | #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ | |
| 2212 | #define MEMMODE_FSTART_SHIFT 8 | |
| 2213 | #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ | |
| 2214 | #define MEMMODE_FMAX_SHIFT 4 | |
| 2215 | #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ | |
| 2216 | #define RCBMAXAVG 0x1119c | |
| 2217 | #define MEMSWCTL2 0x1119e /* Cantiga only */ | |
| 2218 | #define SWMEMCMD_RENDER_OFF (0 << 13) | |
| 2219 | #define SWMEMCMD_RENDER_ON (1 << 13) | |
| 2220 | #define SWMEMCMD_SWFREQ (2 << 13) | |
| 2221 | #define SWMEMCMD_TARVID (3 << 13) | |
| 2222 | #define SWMEMCMD_VRM_OFF (4 << 13) | |
| 2223 | #define SWMEMCMD_VRM_ON (5 << 13) | |
| 2224 | #define CMDSTS (1<<12) | |
| 2225 | #define SFCAVM (1<<11) | |
| 2226 | #define SWFREQ_MASK 0x0380 /* P0-7 */ | |
| 2227 | #define SWFREQ_SHIFT 7 | |
| 2228 | #define TARVID_MASK 0x001f | |
| 2229 | #define MEMSTAT_CTG 0x111a0 | |
| 2230 | #define RCBMINAVG 0x111a0 | |
| 2231 | #define RCUPEI 0x111b0 | |
| 2232 | #define RCDNEI 0x111b4 | |
| 88271da3 JB |
2233 | #define RSTDBYCTL 0x111b8 |
| 2234 | #define RS1EN (1<<31) | |
| 2235 | #define RS2EN (1<<30) | |
| 2236 | #define RS3EN (1<<29) | |
| 2237 | #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ | |
| 2238 | #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ | |
| 2239 | #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ | |
| 2240 | #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ | |
| 2241 | #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ | |
| 2242 | #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ | |
| 2243 | #define RSX_STATUS_MASK (7<<20) | |
| 2244 | #define RSX_STATUS_ON (0<<20) | |
| 2245 | #define RSX_STATUS_RC1 (1<<20) | |
| 2246 | #define RSX_STATUS_RC1E (2<<20) | |
| 2247 | #define RSX_STATUS_RS1 (3<<20) | |
| 2248 | #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ | |
| 2249 | #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ | |
| 2250 | #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ | |
| 2251 | #define RSX_STATUS_RSVD2 (7<<20) | |
| 2252 | #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ | |
| 2253 | #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ | |
| 2254 | #define JRSC (1<<17) /* rsx coupled to cpu c-state */ | |
| 2255 | #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ | |
| 2256 | #define RS1CONTSAV_MASK (3<<14) | |
| 2257 | #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ | |
| 2258 | #define RS1CONTSAV_RSVD (1<<14) | |
| 2259 | #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ | |
| 2260 | #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ | |
| 2261 | #define NORMSLEXLAT_MASK (3<<12) | |
| 2262 | #define SLOW_RS123 (0<<12) | |
| 2263 | #define SLOW_RS23 (1<<12) | |
| 2264 | #define SLOW_RS3 (2<<12) | |
| 2265 | #define NORMAL_RS123 (3<<12) | |
| 2266 | #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ | |
| 2267 | #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ | |
| 2268 | #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ | |
| 2269 | #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ | |
| 2270 | #define RS_CSTATE_MASK (3<<4) | |
| 2271 | #define RS_CSTATE_C367_RS1 (0<<4) | |
| 2272 | #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) | |
| 2273 | #define RS_CSTATE_RSVD (2<<4) | |
| 2274 | #define RS_CSTATE_C367_RS2 (3<<4) | |
| 2275 | #define REDSAVES (1<<3) /* no context save if was idle during rs0 */ | |
| 2276 | #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ | |
| f97108d1 JB |
2277 | #define VIDCTL 0x111c0 |
| 2278 | #define VIDSTS 0x111c8 | |
| 2279 | #define VIDSTART 0x111cc /* 8 bits */ | |
| 2280 | #define MEMSTAT_ILK 0x111f8 | |
| 2281 | #define MEMSTAT_VID_MASK 0x7f00 | |
| 2282 | #define MEMSTAT_VID_SHIFT 8 | |
| 2283 | #define MEMSTAT_PSTATE_MASK 0x00f8 | |
| 2284 | #define MEMSTAT_PSTATE_SHIFT 3 | |
| 2285 | #define MEMSTAT_MON_ACTV (1<<2) | |
| 2286 | #define MEMSTAT_SRC_CTL_MASK 0x0003 | |
| 2287 | #define MEMSTAT_SRC_CTL_CORE 0 | |
| 2288 | #define MEMSTAT_SRC_CTL_TRB 1 | |
| 2289 | #define MEMSTAT_SRC_CTL_THM 2 | |
| 2290 | #define MEMSTAT_SRC_CTL_STDBY 3 | |
| 2291 | #define RCPREVBSYTUPAVG 0x113b8 | |
| 2292 | #define RCPREVBSYTDNAVG 0x113bc | |
| ea056c14 JB |
2293 | #define PMMISC 0x11214 |
| 2294 | #define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ | |
| 7648fa99 JB |
2295 | #define SDEW 0x1124c |
| 2296 | #define CSIEW0 0x11250 | |
| 2297 | #define CSIEW1 0x11254 | |
| 2298 | #define CSIEW2 0x11258 | |
| 2299 | #define PEW 0x1125c | |
| 2300 | #define DEW 0x11270 | |
| 2301 | #define MCHAFE 0x112c0 | |
| 2302 | #define CSIEC 0x112e0 | |
| 2303 | #define DMIEC 0x112e4 | |
| 2304 | #define DDREC 0x112e8 | |
| 2305 | #define PEG0EC 0x112ec | |
| 2306 | #define PEG1EC 0x112f0 | |
| 2307 | #define GFXEC 0x112f4 | |
| 2308 | #define RPPREVBSYTUPAVG 0x113b8 | |
| 2309 | #define RPPREVBSYTDNAVG 0x113bc | |
| 2310 | #define ECR 0x11600 | |
| 2311 | #define ECR_GPFE (1<<31) | |
| 2312 | #define ECR_IMONE (1<<30) | |
| 2313 | #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ | |
| 2314 | #define OGW0 0x11608 | |
| 2315 | #define OGW1 0x1160c | |
| 2316 | #define EG0 0x11610 | |
| 2317 | #define EG1 0x11614 | |
| 2318 | #define EG2 0x11618 | |
| 2319 | #define EG3 0x1161c | |
| 2320 | #define EG4 0x11620 | |
| 2321 | #define EG5 0x11624 | |
| 2322 | #define EG6 0x11628 | |
| 2323 | #define EG7 0x1162c | |
| 2324 | #define PXW 0x11664 | |
| 2325 | #define PXWL 0x11680 | |
| 2326 | #define LCFUSE02 0x116c0 | |
| 2327 | #define LCFUSE_HIV_MASK 0x000000ff | |
| 2328 | #define CSIPLL0 0x12c10 | |
| 2329 | #define DDRMPLL1 0X12c20 | |
| 7d57382e EA |
2330 | #define PEG_BAND_GAP_DATA 0x14d68 |
| 2331 | ||
| c4de7b0f CW |
2332 | #define GEN6_GT_THREAD_STATUS_REG 0x13805c |
| 2333 | #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 | |
| c4de7b0f | 2334 | |
| 153b4b95 BW |
2335 | #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) |
| 2336 | #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) | |
| 2337 | #define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) | |
| 3b8d8d91 | 2338 | |
| aa40d6bb ZN |
2339 | /* |
| 2340 | * Logical Context regs | |
| 2341 | */ | |
| 2342 | #define CCID 0x2180 | |
| 2343 | #define CCID_EN (1<<0) | |
| e8016055 VS |
2344 | /* |
| 2345 | * Notes on SNB/IVB/VLV context size: | |
| 2346 | * - Power context is saved elsewhere (LLC or stolen) | |
| 2347 | * - Ring/execlist context is saved on SNB, not on IVB | |
| 2348 | * - Extended context size already includes render context size | |
| 2349 | * - We always need to follow the extended context size. | |
| 2350 | * SNB BSpec has comments indicating that we should use the | |
| 2351 | * render context size instead if execlists are disabled, but | |
| 2352 | * based on empirical testing that's just nonsense. | |
| 2353 | * - Pipelined/VF state is saved on SNB/IVB respectively | |
| 2354 | * - GT1 size just indicates how much of render context | |
| 2355 | * doesn't need saving on GT1 | |
| 2356 | */ | |
| fe1cc68f BW |
2357 | #define CXT_SIZE 0x21a0 |
| 2358 | #define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) | |
| 2359 | #define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) | |
| 2360 | #define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) | |
| 2361 | #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) | |
| 2362 | #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) | |
| e8016055 | 2363 | #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ |
| fe1cc68f BW |
2364 | GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ |
| 2365 | GEN6_CXT_PIPELINE_SIZE(cxt_reg)) | |
| 4f91dd6f | 2366 | #define GEN7_CXT_SIZE 0x21a8 |
| 6a4ea124 BW |
2367 | #define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) |
| 2368 | #define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) | |
| 4f91dd6f BW |
2369 | #define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) |
| 2370 | #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) | |
| 2371 | #define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) | |
| 2372 | #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) | |
| e8016055 | 2373 | #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ |
| 4f91dd6f | 2374 | GEN7_CXT_VFSTATE_SIZE(ctx_reg)) |
| a0de80a0 BW |
2375 | /* Haswell does have the CXT_SIZE register however it does not appear to be |
| 2376 | * valid. Now, docs explain in dwords what is in the context object. The full | |
| 2377 | * size is 70720 bytes, however, the power context and execlist context will | |
| 2378 | * never be saved (power context is stored elsewhere, and execlists don't work | |
| 2379 | * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. | |
| 2380 | */ | |
| 2381 | #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) | |
| 8897644a BW |
2382 | /* Same as Haswell, but 72064 bytes now. */ |
| 2383 | #define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) | |
| 2384 | ||
| 542a6b20 | 2385 | #define CHV_CLK_CTL1 0x101100 |
| e454a05d JB |
2386 | #define VLV_CLK_CTL2 0x101104 |
| 2387 | #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 | |
| 2388 | ||
| 585fb111 JB |
2389 | /* |
| 2390 | * Overlay regs | |
| 2391 | */ | |
| 2392 | ||
| 2393 | #define OVADD 0x30000 | |
| 2394 | #define DOVSTA 0x30008 | |
| 2395 | #define OC_BUF (0x3<<20) | |
| 2396 | #define OGAMC5 0x30010 | |
| 2397 | #define OGAMC4 0x30014 | |
| 2398 | #define OGAMC3 0x30018 | |
| 2399 | #define OGAMC2 0x3001c | |
| 2400 | #define OGAMC1 0x30020 | |
| 2401 | #define OGAMC0 0x30024 | |
| 2402 | ||
| 2403 | /* | |
| 2404 | * Display engine regs | |
| 2405 | */ | |
| 2406 | ||
| 8bf1e9f1 | 2407 | /* Pipe A CRC regs */ |
| a57c774a | 2408 | #define _PIPE_CRC_CTL_A 0x60050 |
| 8bf1e9f1 | 2409 | #define PIPE_CRC_ENABLE (1 << 31) |
| b4437a41 | 2410 | /* ivb+ source selection */ |
| 8bf1e9f1 SH |
2411 | #define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) |
| 2412 | #define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) | |
| 2413 | #define PIPE_CRC_SOURCE_PF_IVB (2 << 29) | |
| b4437a41 | 2414 | /* ilk+ source selection */ |
| 5a6b5c84 DV |
2415 | #define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) |
| 2416 | #define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) | |
| 2417 | #define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) | |
| 2418 | /* embedded DP port on the north display block, reserved on ivb */ | |
| 2419 | #define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) | |
| 2420 | #define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ | |
| b4437a41 DV |
2421 | /* vlv source selection */ |
| 2422 | #define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) | |
| 2423 | #define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) | |
| 2424 | #define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) | |
| 2425 | /* with DP port the pipe source is invalid */ | |
| 2426 | #define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) | |
| 2427 | #define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) | |
| 2428 | #define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) | |
| 2429 | /* gen3+ source selection */ | |
| 2430 | #define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) | |
| 2431 | #define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) | |
| 2432 | #define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) | |
| 2433 | /* with DP/TV port the pipe source is invalid */ | |
| 2434 | #define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) | |
| 2435 | #define PIPE_CRC_SOURCE_TV_PRE (4 << 28) | |
| 2436 | #define PIPE_CRC_SOURCE_TV_POST (5 << 28) | |
| 2437 | #define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) | |
| 2438 | #define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) | |
| 2439 | /* gen2 doesn't have source selection bits */ | |
| 52f843f6 | 2440 | #define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) |
| b4437a41 | 2441 | |
| 5a6b5c84 DV |
2442 | #define _PIPE_CRC_RES_1_A_IVB 0x60064 |
| 2443 | #define _PIPE_CRC_RES_2_A_IVB 0x60068 | |
| 2444 | #define _PIPE_CRC_RES_3_A_IVB 0x6006c | |
| 2445 | #define _PIPE_CRC_RES_4_A_IVB 0x60070 | |
| 2446 | #define _PIPE_CRC_RES_5_A_IVB 0x60074 | |
| 2447 | ||
| a57c774a AK |
2448 | #define _PIPE_CRC_RES_RED_A 0x60060 |
| 2449 | #define _PIPE_CRC_RES_GREEN_A 0x60064 | |
| 2450 | #define _PIPE_CRC_RES_BLUE_A 0x60068 | |
| 2451 | #define _PIPE_CRC_RES_RES1_A_I915 0x6006c | |
| 2452 | #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 | |
| 8bf1e9f1 SH |
2453 | |
| 2454 | /* Pipe B CRC regs */ | |
| 5a6b5c84 DV |
2455 | #define _PIPE_CRC_RES_1_B_IVB 0x61064 |
| 2456 | #define _PIPE_CRC_RES_2_B_IVB 0x61068 | |
| 2457 | #define _PIPE_CRC_RES_3_B_IVB 0x6106c | |
| 2458 | #define _PIPE_CRC_RES_4_B_IVB 0x61070 | |
| 2459 | #define _PIPE_CRC_RES_5_B_IVB 0x61074 | |
| 8bf1e9f1 | 2460 | |
| a57c774a | 2461 | #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) |
| 8bf1e9f1 | 2462 | #define PIPE_CRC_RES_1_IVB(pipe) \ |
| a57c774a | 2463 | _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) |
| 8bf1e9f1 | 2464 | #define PIPE_CRC_RES_2_IVB(pipe) \ |
| a57c774a | 2465 | _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) |
| 8bf1e9f1 | 2466 | #define PIPE_CRC_RES_3_IVB(pipe) \ |
| a57c774a | 2467 | _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) |
| 8bf1e9f1 | 2468 | #define PIPE_CRC_RES_4_IVB(pipe) \ |
| a57c774a | 2469 | _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) |
| 8bf1e9f1 | 2470 | #define PIPE_CRC_RES_5_IVB(pipe) \ |
| a57c774a | 2471 | _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) |
| 8bf1e9f1 | 2472 | |
| 0b5c5ed0 | 2473 | #define PIPE_CRC_RES_RED(pipe) \ |
| a57c774a | 2474 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) |
| 0b5c5ed0 | 2475 | #define PIPE_CRC_RES_GREEN(pipe) \ |
| a57c774a | 2476 | _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) |
| 0b5c5ed0 | 2477 | #define PIPE_CRC_RES_BLUE(pipe) \ |
| a57c774a | 2478 | _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) |
| 0b5c5ed0 | 2479 | #define PIPE_CRC_RES_RES1_I915(pipe) \ |
| a57c774a | 2480 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) |
| 0b5c5ed0 | 2481 | #define PIPE_CRC_RES_RES2_G4X(pipe) \ |
| a57c774a | 2482 | _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) |
| 5a6b5c84 | 2483 | |
| 585fb111 | 2484 | /* Pipe A timing regs */ |
| a57c774a AK |
2485 | #define _HTOTAL_A 0x60000 |
| 2486 | #define _HBLANK_A 0x60004 | |
| 2487 | #define _HSYNC_A 0x60008 | |
| 2488 | #define _VTOTAL_A 0x6000c | |
| 2489 | #define _VBLANK_A 0x60010 | |
| 2490 | #define _VSYNC_A 0x60014 | |
| 2491 | #define _PIPEASRC 0x6001c | |
| 2492 | #define _BCLRPAT_A 0x60020 | |
| 2493 | #define _VSYNCSHIFT_A 0x60028 | |
| ebb69c95 | 2494 | #define _PIPE_MULT_A 0x6002c |
| 585fb111 JB |
2495 | |
| 2496 | /* Pipe B timing regs */ | |
| a57c774a AK |
2497 | #define _HTOTAL_B 0x61000 |
| 2498 | #define _HBLANK_B 0x61004 | |
| 2499 | #define _HSYNC_B 0x61008 | |
| 2500 | #define _VTOTAL_B 0x6100c | |
| 2501 | #define _VBLANK_B 0x61010 | |
| 2502 | #define _VSYNC_B 0x61014 | |
| 2503 | #define _PIPEBSRC 0x6101c | |
| 2504 | #define _BCLRPAT_B 0x61020 | |
| 2505 | #define _VSYNCSHIFT_B 0x61028 | |
| ebb69c95 | 2506 | #define _PIPE_MULT_B 0x6102c |
| a57c774a AK |
2507 | |
| 2508 | #define TRANSCODER_A_OFFSET 0x60000 | |
| 2509 | #define TRANSCODER_B_OFFSET 0x61000 | |
| 2510 | #define TRANSCODER_C_OFFSET 0x62000 | |
| 84fd4f4e | 2511 | #define CHV_TRANSCODER_C_OFFSET 0x63000 |
| a57c774a AK |
2512 | #define TRANSCODER_EDP_OFFSET 0x6f000 |
| 2513 | ||
| 5c969aa7 DL |
2514 | #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ |
| 2515 | dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ | |
| 2516 | dev_priv->info.display_mmio_offset) | |
| a57c774a AK |
2517 | |
| 2518 | #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) | |
| 2519 | #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) | |
| 2520 | #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) | |
| 2521 | #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) | |
| 2522 | #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) | |
| 2523 | #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) | |
| 2524 | #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) | |
| 2525 | #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) | |
| 2526 | #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) | |
| ebb69c95 | 2527 | #define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) |
| 5eddb70b | 2528 | |
| c8f7df58 RV |
2529 | /* VLV eDP PSR registers */ |
| 2530 | #define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090) | |
| 2531 | #define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090) | |
| 2532 | #define VLV_EDP_PSR_ENABLE (1<<0) | |
| 2533 | #define VLV_EDP_PSR_RESET (1<<1) | |
| 2534 | #define VLV_EDP_PSR_MODE_MASK (7<<2) | |
| 2535 | #define VLV_EDP_PSR_MODE_HW_TIMER (1<<3) | |
| 2536 | #define VLV_EDP_PSR_MODE_SW_TIMER (1<<2) | |
| 2537 | #define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7) | |
| 2538 | #define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8) | |
| 2539 | #define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9) | |
| 2540 | #define VLV_EDP_PSR_DBL_FRAME (1<<10) | |
| 2541 | #define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16) | |
| 2542 | #define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16 | |
| 2543 | #define VLV_PSRCTL(pipe) _PIPE(pipe, _PSRCTLA, _PSRCTLB) | |
| 2544 | ||
| 2545 | #define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0) | |
| 2546 | #define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0) | |
| 2547 | #define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30) | |
| 2548 | #define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31) | |
| 2549 | #define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30) | |
| 2550 | #define VLV_VSCSDP(pipe) _PIPE(pipe, _VSCSDPA, _VSCSDPB) | |
| 2551 | ||
| 2552 | #define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094) | |
| 2553 | #define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094) | |
| 2554 | #define VLV_EDP_PSR_LAST_STATE_MASK (7<<3) | |
| 2555 | #define VLV_EDP_PSR_CURR_STATE_MASK 7 | |
| 2556 | #define VLV_EDP_PSR_DISABLED (0<<0) | |
| 2557 | #define VLV_EDP_PSR_INACTIVE (1<<0) | |
| 2558 | #define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0) | |
| 2559 | #define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0) | |
| 2560 | #define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0) | |
| 2561 | #define VLV_EDP_PSR_EXIT (5<<0) | |
| 2562 | #define VLV_EDP_PSR_IN_TRANS (1<<7) | |
| 2563 | #define VLV_PSRSTAT(pipe) _PIPE(pipe, _PSRSTATA, _PSRSTATB) | |
| 2564 | ||
| ed8546ac BW |
2565 | /* HSW+ eDP PSR registers */ |
| 2566 | #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) | |
| 18b5992c | 2567 | #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) |
| 2b28bb1b | 2568 | #define EDP_PSR_ENABLE (1<<31) |
| 82c56254 | 2569 | #define BDW_PSR_SINGLE_FRAME (1<<30) |
| 2b28bb1b RV |
2570 | #define EDP_PSR_LINK_DISABLE (0<<27) |
| 2571 | #define EDP_PSR_LINK_STANDBY (1<<27) | |
| 2572 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) | |
| 2573 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) | |
| 2574 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) | |
| 2575 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) | |
| 2576 | #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) | |
| 2577 | #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 | |
| 2578 | #define EDP_PSR_SKIP_AUX_EXIT (1<<12) | |
| 2579 | #define EDP_PSR_TP1_TP2_SEL (0<<11) | |
| 2580 | #define EDP_PSR_TP1_TP3_SEL (1<<11) | |
| 2581 | #define EDP_PSR_TP2_TP3_TIME_500us (0<<8) | |
| 2582 | #define EDP_PSR_TP2_TP3_TIME_100us (1<<8) | |
| 2583 | #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) | |
| 2584 | #define EDP_PSR_TP2_TP3_TIME_0us (3<<8) | |
| 2585 | #define EDP_PSR_TP1_TIME_500us (0<<4) | |
| 2586 | #define EDP_PSR_TP1_TIME_100us (1<<4) | |
| 2587 | #define EDP_PSR_TP1_TIME_2500us (2<<4) | |
| 2588 | #define EDP_PSR_TP1_TIME_0us (3<<4) | |
| 2589 | #define EDP_PSR_IDLE_FRAME_SHIFT 0 | |
| 2590 | ||
| 18b5992c BW |
2591 | #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) |
| 2592 | #define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) | |
| 18b5992c | 2593 | #define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) |
| 18b5992c BW |
2594 | #define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) |
| 2595 | #define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) | |
| 2596 | #define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) | |
| 2b28bb1b | 2597 | |
| 18b5992c | 2598 | #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) |
| 2b28bb1b | 2599 | #define EDP_PSR_STATUS_STATE_MASK (7<<29) |
| e91fd8c6 RV |
2600 | #define EDP_PSR_STATUS_STATE_IDLE (0<<29) |
| 2601 | #define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) | |
| 2602 | #define EDP_PSR_STATUS_STATE_SRDENT (2<<29) | |
| 2603 | #define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) | |
| 2604 | #define EDP_PSR_STATUS_STATE_BUFON (4<<29) | |
| 2605 | #define EDP_PSR_STATUS_STATE_AUXACK (5<<29) | |
| 2606 | #define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) | |
| 2607 | #define EDP_PSR_STATUS_LINK_MASK (3<<26) | |
| 2608 | #define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) | |
| 2609 | #define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) | |
| 2610 | #define EDP_PSR_STATUS_LINK_STANDBY (2<<26) | |
| 2611 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 | |
| 2612 | #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f | |
| 2613 | #define EDP_PSR_STATUS_COUNT_SHIFT 16 | |
| 2614 | #define EDP_PSR_STATUS_COUNT_MASK 0xf | |
| 2615 | #define EDP_PSR_STATUS_AUX_ERROR (1<<15) | |
| 2616 | #define EDP_PSR_STATUS_AUX_SENDING (1<<12) | |
| 2617 | #define EDP_PSR_STATUS_SENDING_IDLE (1<<9) | |
| 2618 | #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) | |
| 2619 | #define EDP_PSR_STATUS_SENDING_TP1 (1<<4) | |
| 2620 | #define EDP_PSR_STATUS_IDLE_MASK 0xf | |
| 2621 | ||
| 18b5992c | 2622 | #define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) |
| e91fd8c6 | 2623 | #define EDP_PSR_PERF_CNT_MASK 0xffffff |
| 2b28bb1b | 2624 | |
| 18b5992c | 2625 | #define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) |
| 2b28bb1b RV |
2626 | #define EDP_PSR_DEBUG_MASK_LPSP (1<<27) |
| 2627 | #define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) | |
| 2628 | #define EDP_PSR_DEBUG_MASK_HPD (1<<25) | |
| 2629 | ||
| 585fb111 JB |
2630 | /* VGA port control */ |
| 2631 | #define ADPA 0x61100 | |
| ebc0fd88 | 2632 | #define PCH_ADPA 0xe1100 |
| 540a8950 | 2633 | #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) |
| ebc0fd88 | 2634 | |
| 585fb111 JB |
2635 | #define ADPA_DAC_ENABLE (1<<31) |
| 2636 | #define ADPA_DAC_DISABLE 0 | |
| 2637 | #define ADPA_PIPE_SELECT_MASK (1<<30) | |
| 2638 | #define ADPA_PIPE_A_SELECT 0 | |
| 2639 | #define ADPA_PIPE_B_SELECT (1<<30) | |
| 1519b995 | 2640 | #define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) |
| ebc0fd88 DV |
2641 | /* CPT uses bits 29:30 for pch transcoder select */ |
| 2642 | #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ | |
| 2643 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) | |
| 2644 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) | |
| 2645 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) | |
| 2646 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) | |
| 2647 | #define ADPA_CRT_HOTPLUG_ENABLE (1<<23) | |
| 2648 | #define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) | |
| 2649 | #define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) | |
| 2650 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) | |
| 2651 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) | |
| 2652 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) | |
| 2653 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) | |
| 2654 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) | |
| 2655 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) | |
| 2656 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) | |
| 2657 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) | |
| 2658 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) | |
| 2659 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) | |
| 2660 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) | |
| 585fb111 JB |
2661 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) |
| 2662 | #define ADPA_SETS_HVPOLARITY 0 | |
| 60222c0c | 2663 | #define ADPA_VSYNC_CNTL_DISABLE (1<<10) |
| 585fb111 | 2664 | #define ADPA_VSYNC_CNTL_ENABLE 0 |
| 60222c0c | 2665 | #define ADPA_HSYNC_CNTL_DISABLE (1<<11) |
| 585fb111 JB |
2666 | #define ADPA_HSYNC_CNTL_ENABLE 0 |
| 2667 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) | |
| 2668 | #define ADPA_VSYNC_ACTIVE_LOW 0 | |
| 2669 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) | |
| 2670 | #define ADPA_HSYNC_ACTIVE_LOW 0 | |
| 2671 | #define ADPA_DPMS_MASK (~(3<<10)) | |
| 2672 | #define ADPA_DPMS_ON (0<<10) | |
| 2673 | #define ADPA_DPMS_SUSPEND (1<<10) | |
| 2674 | #define ADPA_DPMS_STANDBY (2<<10) | |
| 2675 | #define ADPA_DPMS_OFF (3<<10) | |
| 2676 | ||
| 939fe4d7 | 2677 | |
| 585fb111 | 2678 | /* Hotplug control (945+ only) */ |
| 5c969aa7 | 2679 | #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) |
| 26739f12 DV |
2680 | #define PORTB_HOTPLUG_INT_EN (1 << 29) |
| 2681 | #define PORTC_HOTPLUG_INT_EN (1 << 28) | |
| 2682 | #define PORTD_HOTPLUG_INT_EN (1 << 27) | |
| 585fb111 JB |
2683 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
| 2684 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
| 2685 | #define TV_HOTPLUG_INT_EN (1 << 18) | |
| 2686 | #define CRT_HOTPLUG_INT_EN (1 << 9) | |
| e5868a31 EE |
2687 | #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ |
| 2688 | PORTC_HOTPLUG_INT_EN | \ | |
| 2689 | PORTD_HOTPLUG_INT_EN | \ | |
| 2690 | SDVOC_HOTPLUG_INT_EN | \ | |
| 2691 | SDVOB_HOTPLUG_INT_EN | \ | |
| 2692 | CRT_HOTPLUG_INT_EN) | |
| 585fb111 | 2693 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) |
| 771cb081 ZY |
2694 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) |
| 2695 | /* must use period 64 on GM45 according to docs */ | |
| 2696 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) | |
| 2697 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) | |
| 2698 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) | |
| 2699 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) | |
| 2700 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) | |
| 2701 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) | |
| 2702 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) | |
| 2703 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) | |
| 2704 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) | |
| 2705 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) | |
| 2706 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) | |
| 2707 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | |
| 585fb111 | 2708 | |
| 5c969aa7 | 2709 | #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) |
| 0ce99f74 DV |
2710 | /* |
| 2711 | * HDMI/DP bits are gen4+ | |
| 2712 | * | |
| 2713 | * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. | |
| 2714 | * Please check the detailed lore in the commit message for for experimental | |
| 2715 | * evidence. | |
| 2716 | */ | |
| 232a6ee9 TP |
2717 | #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) |
| 2718 | #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) | |
| 2719 | #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) | |
| 2720 | /* VLV DP/HDMI bits again match Bspec */ | |
| 2721 | #define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) | |
| 2722 | #define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) | |
| 2723 | #define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) | |
| 26739f12 | 2724 | #define PORTD_HOTPLUG_INT_STATUS (3 << 21) |
| a211b497 DV |
2725 | #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) |
| 2726 | #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) | |
| 26739f12 | 2727 | #define PORTC_HOTPLUG_INT_STATUS (3 << 19) |
| a211b497 DV |
2728 | #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) |
| 2729 | #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) | |
| 26739f12 | 2730 | #define PORTB_HOTPLUG_INT_STATUS (3 << 17) |
| a211b497 DV |
2731 | #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) |
| 2732 | #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) | |
| 084b612e | 2733 | /* CRT/TV common between gen3+ */ |
| 585fb111 JB |
2734 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) |
| 2735 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | |
| 2736 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
| 2737 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
| 2738 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
| 2739 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
| 4aeebd74 DV |
2740 | #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) |
| 2741 | #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) | |
| 2742 | #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) | |
| bfbdb420 ID |
2743 | #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) |
| 2744 | ||
| 084b612e CW |
2745 | /* SDVO is different across gen3/4 */ |
| 2746 | #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) | |
| 2747 | #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) | |
| 4f7fd709 DV |
2748 | /* |
| 2749 | * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, | |
| 2750 | * since reality corrobates that they're the same as on gen3. But keep these | |
| 2751 | * bits here (and the comment!) to help any other lost wanderers back onto the | |
| 2752 | * right tracks. | |
| 2753 | */ | |
| 084b612e CW |
2754 | #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) |
| 2755 | #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) | |
| 2756 | #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) | |
| 2757 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) | |
| e5868a31 EE |
2758 | #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ |
| 2759 | SDVOB_HOTPLUG_INT_STATUS_G4X | \ | |
| 2760 | SDVOC_HOTPLUG_INT_STATUS_G4X | \ | |
| 2761 | PORTB_HOTPLUG_INT_STATUS | \ | |
| 2762 | PORTC_HOTPLUG_INT_STATUS | \ | |
| 2763 | PORTD_HOTPLUG_INT_STATUS) | |
| e5868a31 EE |
2764 | |
| 2765 | #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ | |
| 2766 | SDVOB_HOTPLUG_INT_STATUS_I915 | \ | |
| 2767 | SDVOC_HOTPLUG_INT_STATUS_I915 | \ | |
| 2768 | PORTB_HOTPLUG_INT_STATUS | \ | |
| 2769 | PORTC_HOTPLUG_INT_STATUS | \ | |
| 2770 | PORTD_HOTPLUG_INT_STATUS) | |
| 585fb111 | 2771 | |
| c20cd312 PZ |
2772 | /* SDVO and HDMI port control. |
| 2773 | * The same register may be used for SDVO or HDMI */ | |
| 2774 | #define GEN3_SDVOB 0x61140 | |
| 2775 | #define GEN3_SDVOC 0x61160 | |
| 2776 | #define GEN4_HDMIB GEN3_SDVOB | |
| 2777 | #define GEN4_HDMIC GEN3_SDVOC | |
| 9418c1f1 | 2778 | #define CHV_HDMID 0x6116C |
| c20cd312 PZ |
2779 | #define PCH_SDVOB 0xe1140 |
| 2780 | #define PCH_HDMIB PCH_SDVOB | |
| 2781 | #define PCH_HDMIC 0xe1150 | |
| 2782 | #define PCH_HDMID 0xe1160 | |
| 2783 | ||
| 84093603 DV |
2784 | #define PORT_DFT_I9XX 0x61150 |
| 2785 | #define DC_BALANCE_RESET (1 << 25) | |
| a8aab8bd | 2786 | #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) |
| 84093603 DV |
2787 | #define DC_BALANCE_RESET_VLV (1 << 31) |
| 2788 | #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) | |
| 2789 | #define PIPE_B_SCRAMBLE_RESET (1 << 1) | |
| 2790 | #define PIPE_A_SCRAMBLE_RESET (1 << 0) | |
| 2791 | ||
| c20cd312 PZ |
2792 | /* Gen 3 SDVO bits: */ |
| 2793 | #define SDVO_ENABLE (1 << 31) | |
| dc0fa718 PZ |
2794 | #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) |
| 2795 | #define SDVO_PIPE_SEL_MASK (1 << 30) | |
| c20cd312 PZ |
2796 | #define SDVO_PIPE_B_SELECT (1 << 30) |
| 2797 | #define SDVO_STALL_SELECT (1 << 29) | |
| 2798 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
| 646b4269 | 2799 | /* |
| 585fb111 | 2800 | * 915G/GM SDVO pixel multiplier. |
| 585fb111 | 2801 | * Programmed value is multiplier - 1, up to 5x. |
| 585fb111 JB |
2802 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK |
| 2803 | */ | |
| c20cd312 | 2804 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) |
| 585fb111 | 2805 | #define SDVO_PORT_MULTIPLY_SHIFT 23 |
| c20cd312 PZ |
2806 | #define SDVO_PHASE_SELECT_MASK (15 << 19) |
| 2807 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
| 2808 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
| 2809 | #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ | |
| 2810 | #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ | |
| 2811 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ | |
| 2812 | #define SDVO_DETECTED (1 << 2) | |
| 585fb111 | 2813 | /* Bits to be preserved when writing */ |
| c20cd312 PZ |
2814 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ |
| 2815 | SDVO_INTERRUPT_ENABLE) | |
| 2816 | #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) | |
| 2817 | ||
| 2818 | /* Gen 4 SDVO/HDMI bits: */ | |
| 4f3a8bc7 | 2819 | #define SDVO_COLOR_FORMAT_8bpc (0 << 26) |
| 18442d08 | 2820 | #define SDVO_COLOR_FORMAT_MASK (7 << 26) |
| c20cd312 PZ |
2821 | #define SDVO_ENCODING_SDVO (0 << 10) |
| 2822 | #define SDVO_ENCODING_HDMI (2 << 10) | |
| dc0fa718 PZ |
2823 | #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ |
| 2824 | #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ | |
| 4f3a8bc7 | 2825 | #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ |
| c20cd312 PZ |
2826 | #define SDVO_AUDIO_ENABLE (1 << 6) |
| 2827 | /* VSYNC/HSYNC bits new with 965, default is to be set */ | |
| 2828 | #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
| 2829 | #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
| 2830 | ||
| 2831 | /* Gen 5 (IBX) SDVO/HDMI bits: */ | |
| 4f3a8bc7 | 2832 | #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ |
| c20cd312 PZ |
2833 | #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ |
| 2834 | ||
| 2835 | /* Gen 6 (CPT) SDVO/HDMI bits: */ | |
| dc0fa718 PZ |
2836 | #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) |
| 2837 | #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) | |
| c20cd312 | 2838 | |
| 44f37d1f CML |
2839 | /* CHV SDVO/HDMI bits: */ |
| 2840 | #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) | |
| 2841 | #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) | |
| 2842 | ||
| 585fb111 JB |
2843 | |
| 2844 | /* DVO port control */ | |
| 2845 | #define DVOA 0x61120 | |
| 2846 | #define DVOB 0x61140 | |
| 2847 | #define DVOC 0x61160 | |
| 2848 | #define DVO_ENABLE (1 << 31) | |
| 2849 | #define DVO_PIPE_B_SELECT (1 << 30) | |
| 2850 | #define DVO_PIPE_STALL_UNUSED (0 << 28) | |
| 2851 | #define DVO_PIPE_STALL (1 << 28) | |
| 2852 | #define DVO_PIPE_STALL_TV (2 << 28) | |
| 2853 | #define DVO_PIPE_STALL_MASK (3 << 28) | |
| 2854 | #define DVO_USE_VGA_SYNC (1 << 15) | |
| 2855 | #define DVO_DATA_ORDER_I740 (0 << 14) | |
| 2856 | #define DVO_DATA_ORDER_FP (1 << 14) | |
| 2857 | #define DVO_VSYNC_DISABLE (1 << 11) | |
| 2858 | #define DVO_HSYNC_DISABLE (1 << 10) | |
| 2859 | #define DVO_VSYNC_TRISTATE (1 << 9) | |
| 2860 | #define DVO_HSYNC_TRISTATE (1 << 8) | |
| 2861 | #define DVO_BORDER_ENABLE (1 << 7) | |
| 2862 | #define DVO_DATA_ORDER_GBRG (1 << 6) | |
| 2863 | #define DVO_DATA_ORDER_RGGB (0 << 6) | |
| 2864 | #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) | |
| 2865 | #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) | |
| 2866 | #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) | |
| 2867 | #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) | |
| 2868 | #define DVO_BLANK_ACTIVE_HIGH (1 << 2) | |
| 2869 | #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ | |
| 2870 | #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ | |
| 2871 | #define DVO_PRESERVE_MASK (0x7<<24) | |
| 2872 | #define DVOA_SRCDIM 0x61124 | |
| 2873 | #define DVOB_SRCDIM 0x61144 | |
| 2874 | #define DVOC_SRCDIM 0x61164 | |
| 2875 | #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 | |
| 2876 | #define DVO_SRCDIM_VERTICAL_SHIFT 0 | |
| 2877 | ||
| 2878 | /* LVDS port control */ | |
| 2879 | #define LVDS 0x61180 | |
| 2880 | /* | |
| 2881 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
| 2882 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
| 2883 | */ | |
| 2884 | #define LVDS_PORT_EN (1 << 31) | |
| 2885 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | |
| 2886 | #define LVDS_PIPEB_SELECT (1 << 30) | |
| 47a05eca | 2887 | #define LVDS_PIPE_MASK (1 << 30) |
| 1519b995 | 2888 | #define LVDS_PIPE(pipe) ((pipe) << 30) |
| 898822ce ZY |
2889 | /* LVDS dithering flag on 965/g4x platform */ |
| 2890 | #define LVDS_ENABLE_DITHER (1 << 25) | |
| aa9b500d BF |
2891 | /* LVDS sync polarity flags. Set to invert (i.e. negative) */ |
| 2892 | #define LVDS_VSYNC_POLARITY (1 << 21) | |
| 2893 | #define LVDS_HSYNC_POLARITY (1 << 20) | |
| 2894 | ||
| a3e17eb8 ZY |
2895 | /* Enable border for unscaled (or aspect-scaled) display */ |
| 2896 | #define LVDS_BORDER_ENABLE (1 << 15) | |
| 585fb111 JB |
2897 | /* |
| 2898 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
| 2899 | * pixel. | |
| 2900 | */ | |
| 2901 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
| 2902 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
| 2903 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
| 2904 | /* | |
| 2905 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
| 2906 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
| 2907 | * on. | |
| 2908 | */ | |
| 2909 | #define LVDS_A3_POWER_MASK (3 << 6) | |
| 2910 | #define LVDS_A3_POWER_DOWN (0 << 6) | |
| 2911 | #define LVDS_A3_POWER_UP (3 << 6) | |
| 2912 | /* | |
| 2913 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
| 2914 | * is set. | |
| 2915 | */ | |
| 2916 | #define LVDS_CLKB_POWER_MASK (3 << 4) | |
| 2917 | #define LVDS_CLKB_POWER_DOWN (0 << 4) | |
| 2918 | #define LVDS_CLKB_POWER_UP (3 << 4) | |
| 2919 | /* | |
| 2920 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
| 2921 | * setting for whether we are in dual-channel mode. The B3 pair will | |
| 2922 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
| 2923 | */ | |
| 2924 | #define LVDS_B0B3_POWER_MASK (3 << 2) | |
| 2925 | #define LVDS_B0B3_POWER_DOWN (0 << 2) | |
| 2926 | #define LVDS_B0B3_POWER_UP (3 << 2) | |
| 2927 | ||
| 3c17fe4b DH |
2928 | /* Video Data Island Packet control */ |
| 2929 | #define VIDEO_DIP_DATA 0x61178 | |
| adf00b26 PZ |
2930 | /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC |
| 2931 | * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte | |
| 2932 | * of the infoframe structure specified by CEA-861. */ | |
| 2933 | #define VIDEO_DIP_DATA_SIZE 32 | |
| 2b28bb1b | 2934 | #define VIDEO_DIP_VSC_DATA_SIZE 36 |
| 3c17fe4b | 2935 | #define VIDEO_DIP_CTL 0x61170 |
| 2da8af54 | 2936 | /* Pre HSW: */ |
| 3c17fe4b | 2937 | #define VIDEO_DIP_ENABLE (1 << 31) |
| 822cdc52 | 2938 | #define VIDEO_DIP_PORT(port) ((port) << 29) |
| 3e6e6395 | 2939 | #define VIDEO_DIP_PORT_MASK (3 << 29) |
| 0dd87d20 | 2940 | #define VIDEO_DIP_ENABLE_GCP (1 << 25) |
| 3c17fe4b DH |
2941 | #define VIDEO_DIP_ENABLE_AVI (1 << 21) |
| 2942 | #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) | |
| 0dd87d20 | 2943 | #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) |
| 3c17fe4b DH |
2944 | #define VIDEO_DIP_ENABLE_SPD (8 << 21) |
| 2945 | #define VIDEO_DIP_SELECT_AVI (0 << 19) | |
| 2946 | #define VIDEO_DIP_SELECT_VENDOR (1 << 19) | |
| 2947 | #define VIDEO_DIP_SELECT_SPD (3 << 19) | |
| 45187ace | 2948 | #define VIDEO_DIP_SELECT_MASK (3 << 19) |
| 3c17fe4b DH |
2949 | #define VIDEO_DIP_FREQ_ONCE (0 << 16) |
| 2950 | #define VIDEO_DIP_FREQ_VSYNC (1 << 16) | |
| 2951 | #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) | |
| 60c5ea2d | 2952 | #define VIDEO_DIP_FREQ_MASK (3 << 16) |
| 2da8af54 | 2953 | /* HSW and later: */ |
| 0dd87d20 PZ |
2954 | #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) |
| 2955 | #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) | |
| 2da8af54 | 2956 | #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) |
| 0dd87d20 PZ |
2957 | #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) |
| 2958 | #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) | |
| 2da8af54 | 2959 | #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) |
| 3c17fe4b | 2960 | |
| 585fb111 JB |
2961 | /* Panel power sequencing */ |
| 2962 | #define PP_STATUS 0x61200 | |
| 2963 | #define PP_ON (1 << 31) | |
| 2964 | /* | |
| 2965 | * Indicates that all dependencies of the panel are on: | |
| 2966 | * | |
| 2967 | * - PLL enabled | |
| 2968 | * - pipe enabled | |
| 2969 | * - LVDS/DVOB/DVOC on | |
| 2970 | */ | |
| 2971 | #define PP_READY (1 << 30) | |
| 2972 | #define PP_SEQUENCE_NONE (0 << 28) | |
| 99ea7127 KP |
2973 | #define PP_SEQUENCE_POWER_UP (1 << 28) |
| 2974 | #define PP_SEQUENCE_POWER_DOWN (2 << 28) | |
| 2975 | #define PP_SEQUENCE_MASK (3 << 28) | |
| 2976 | #define PP_SEQUENCE_SHIFT 28 | |
| 01cb9ea6 | 2977 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) |
| 01cb9ea6 | 2978 | #define PP_SEQUENCE_STATE_MASK 0x0000000f |
| 99ea7127 KP |
2979 | #define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) |
| 2980 | #define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) | |
| 2981 | #define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) | |
| 2982 | #define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) | |
| 2983 | #define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) | |
| 2984 | #define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) | |
| 2985 | #define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) | |
| 2986 | #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) | |
| 2987 | #define PP_SEQUENCE_STATE_RESET (0xf << 0) | |
| 585fb111 JB |
2988 | #define PP_CONTROL 0x61204 |
| 2989 | #define POWER_TARGET_ON (1 << 0) | |
| 2990 | #define PP_ON_DELAYS 0x61208 | |
| 2991 | #define PP_OFF_DELAYS 0x6120c | |
| 2992 | #define PP_DIVISOR 0x61210 | |
| 2993 | ||
| 2994 | /* Panel fitting */ | |
| 5c969aa7 | 2995 | #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) |
| 585fb111 JB |
2996 | #define PFIT_ENABLE (1 << 31) |
| 2997 | #define PFIT_PIPE_MASK (3 << 29) | |
| 2998 | #define PFIT_PIPE_SHIFT 29 | |
| 2999 | #define VERT_INTERP_DISABLE (0 << 10) | |
| 3000 | #define VERT_INTERP_BILINEAR (1 << 10) | |
| 3001 | #define VERT_INTERP_MASK (3 << 10) | |
| 3002 | #define VERT_AUTO_SCALE (1 << 9) | |
| 3003 | #define HORIZ_INTERP_DISABLE (0 << 6) | |
| 3004 | #define HORIZ_INTERP_BILINEAR (1 << 6) | |
| 3005 | #define HORIZ_INTERP_MASK (3 << 6) | |
| 3006 | #define HORIZ_AUTO_SCALE (1 << 5) | |
| 3007 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
| 3fbe18d6 ZY |
3008 | #define PFIT_FILTER_FUZZY (0 << 24) |
| 3009 | #define PFIT_SCALING_AUTO (0 << 26) | |
| 3010 | #define PFIT_SCALING_PROGRAMMED (1 << 26) | |
| 3011 | #define PFIT_SCALING_PILLAR (2 << 26) | |
| 3012 | #define PFIT_SCALING_LETTER (3 << 26) | |
| 5c969aa7 | 3013 | #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) |
| 3fbe18d6 ZY |
3014 | /* Pre-965 */ |
| 3015 | #define PFIT_VERT_SCALE_SHIFT 20 | |
| 3016 | #define PFIT_VERT_SCALE_MASK 0xfff00000 | |
| 3017 | #define PFIT_HORIZ_SCALE_SHIFT 4 | |
| 3018 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
| 3019 | /* 965+ */ | |
| 3020 | #define PFIT_VERT_SCALE_SHIFT_965 16 | |
| 3021 | #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 | |
| 3022 | #define PFIT_HORIZ_SCALE_SHIFT_965 0 | |
| 3023 | #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff | |
| 3024 | ||
| 5c969aa7 | 3025 | #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) |
| 585fb111 | 3026 | |
| 5c969aa7 DL |
3027 | #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) |
| 3028 | #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) | |
| 07bf139b JB |
3029 | #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ |
| 3030 | _VLV_BLC_PWM_CTL2_B) | |
| 3031 | ||
| 5c969aa7 DL |
3032 | #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) |
| 3033 | #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) | |
| 07bf139b JB |
3034 | #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ |
| 3035 | _VLV_BLC_PWM_CTL_B) | |
| 3036 | ||
| 5c969aa7 DL |
3037 | #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) |
| 3038 | #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) | |
| 07bf139b JB |
3039 | #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ |
| 3040 | _VLV_BLC_HIST_CTL_B) | |
| 3041 | ||
| 585fb111 | 3042 | /* Backlight control */ |
| 5c969aa7 | 3043 | #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ |
| 7cf41601 DV |
3044 | #define BLM_PWM_ENABLE (1 << 31) |
| 3045 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ | |
| 3046 | #define BLM_PIPE_SELECT (1 << 29) | |
| 3047 | #define BLM_PIPE_SELECT_IVB (3 << 29) | |
| 3048 | #define BLM_PIPE_A (0 << 29) | |
| 3049 | #define BLM_PIPE_B (1 << 29) | |
| 3050 | #define BLM_PIPE_C (2 << 29) /* ivb + */ | |
| 35ffda48 JN |
3051 | #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ |
| 3052 | #define BLM_TRANSCODER_B BLM_PIPE_B | |
| 3053 | #define BLM_TRANSCODER_C BLM_PIPE_C | |
| 3054 | #define BLM_TRANSCODER_EDP (3 << 29) | |
| 7cf41601 DV |
3055 | #define BLM_PIPE(pipe) ((pipe) << 29) |
| 3056 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ | |
| 3057 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) | |
| 3058 | #define BLM_PHASE_IN_ENABLE (1 << 25) | |
| 3059 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) | |
| 3060 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) | |
| 3061 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) | |
| 3062 | #define BLM_PHASE_IN_COUNT_SHIFT (8) | |
| 3063 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) | |
| 3064 | #define BLM_PHASE_IN_INCR_SHIFT (0) | |
| 3065 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) | |
| 5c969aa7 | 3066 | #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) |
| ba3820ad TI |
3067 | /* |
| 3068 | * This is the most significant 15 bits of the number of backlight cycles in a | |
| 3069 | * complete cycle of the modulated backlight control. | |
| 3070 | * | |
| 3071 | * The actual value is this field multiplied by two. | |
| 3072 | */ | |
| 7cf41601 DV |
3073 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
| 3074 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
| 3075 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ | |
| 585fb111 JB |
3076 | /* |
| 3077 | * This is the number of cycles out of the backlight modulation cycle for which | |
| 3078 | * the backlight is on. | |
| 3079 | * | |
| 3080 | * This field must be no greater than the number of cycles in the complete | |
| 3081 | * backlight modulation cycle. | |
| 3082 | */ | |
| 3083 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
| 3084 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
| 534b5a53 DV |
3085 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
| 3086 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ | |
| 585fb111 | 3087 | |
| 5c969aa7 | 3088 | #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) |
| 0eb96d6e | 3089 | |
| 7cf41601 DV |
3090 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
| 3091 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ | |
| 3092 | #define BLC_PWM_CPU_CTL2 0x48250 | |
| 3093 | #define BLC_PWM_CPU_CTL 0x48254 | |
| 3094 | ||
| be256dc7 PZ |
3095 | #define HSW_BLC_PWM2_CTL 0x48350 |
| 3096 | ||
| 7cf41601 DV |
3097 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is |
| 3098 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ | |
| 3099 | #define BLC_PWM_PCH_CTL1 0xc8250 | |
| 4b4147c3 | 3100 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
| 7cf41601 DV |
3101 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
| 3102 | #define BLM_PCH_POLARITY (1 << 29) | |
| 3103 | #define BLC_PWM_PCH_CTL2 0xc8254 | |
| 3104 | ||
| be256dc7 PZ |
3105 | #define UTIL_PIN_CTL 0x48400 |
| 3106 | #define UTIL_PIN_ENABLE (1 << 31) | |
| 3107 | ||
| 3108 | #define PCH_GTC_CTL 0xe7000 | |
| 3109 | #define PCH_GTC_ENABLE (1 << 31) | |
| 3110 | ||
| 585fb111 JB |
3111 | /* TV port control */ |
| 3112 | #define TV_CTL 0x68000 | |
| 646b4269 | 3113 | /* Enables the TV encoder */ |
| 585fb111 | 3114 | # define TV_ENC_ENABLE (1 << 31) |
| 646b4269 | 3115 | /* Sources the TV encoder input from pipe B instead of A. */ |
| 585fb111 | 3116 | # define TV_ENC_PIPEB_SELECT (1 << 30) |
| 646b4269 | 3117 | /* Outputs composite video (DAC A only) */ |
| 585fb111 | 3118 | # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) |
| 646b4269 | 3119 | /* Outputs SVideo video (DAC B/C) */ |
| 585fb111 | 3120 | # define TV_ENC_OUTPUT_SVIDEO (1 << 28) |
| 646b4269 | 3121 | /* Outputs Component video (DAC A/B/C) */ |
| 585fb111 | 3122 | # define TV_ENC_OUTPUT_COMPONENT (2 << 28) |
| 646b4269 | 3123 | /* Outputs Composite and SVideo (DAC A/B/C) */ |
| 585fb111 JB |
3124 | # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) |
| 3125 | # define TV_TRILEVEL_SYNC (1 << 21) | |
| 646b4269 | 3126 | /* Enables slow sync generation (945GM only) */ |
| 585fb111 | 3127 | # define TV_SLOW_SYNC (1 << 20) |
| 646b4269 | 3128 | /* Selects 4x oversampling for 480i and 576p */ |
| 585fb111 | 3129 | # define TV_OVERSAMPLE_4X (0 << 18) |
| 646b4269 | 3130 | /* Selects 2x oversampling for 720p and 1080i */ |
| 585fb111 | 3131 | # define TV_OVERSAMPLE_2X (1 << 18) |
| 646b4269 | 3132 | /* Selects no oversampling for 1080p */ |
| 585fb111 | 3133 | # define TV_OVERSAMPLE_NONE (2 << 18) |
| 646b4269 | 3134 | /* Selects 8x oversampling */ |
| 585fb111 | 3135 | # define TV_OVERSAMPLE_8X (3 << 18) |
| 646b4269 | 3136 | /* Selects progressive mode rather than interlaced */ |
| 585fb111 | 3137 | # define TV_PROGRESSIVE (1 << 17) |
| 646b4269 | 3138 | /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ |
| 585fb111 | 3139 | # define TV_PAL_BURST (1 << 16) |
| 646b4269 | 3140 | /* Field for setting delay of Y compared to C */ |
| 585fb111 | 3141 | # define TV_YC_SKEW_MASK (7 << 12) |
| 646b4269 | 3142 | /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ |
| 585fb111 | 3143 | # define TV_ENC_SDP_FIX (1 << 11) |
| 646b4269 | 3144 | /* |
| 585fb111 JB |
3145 | * Enables a fix for the 915GM only. |
| 3146 | * | |
| 3147 | * Not sure what it does. | |
| 3148 | */ | |
| 3149 | # define TV_ENC_C0_FIX (1 << 10) | |
| 646b4269 | 3150 | /* Bits that must be preserved by software */ |
| d2d9f232 | 3151 | # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) |
| 585fb111 | 3152 | # define TV_FUSE_STATE_MASK (3 << 4) |
| 646b4269 | 3153 | /* Read-only state that reports all features enabled */ |
| 585fb111 | 3154 | # define TV_FUSE_STATE_ENABLED (0 << 4) |
| 646b4269 | 3155 | /* Read-only state that reports that Macrovision is disabled in hardware*/ |
| 585fb111 | 3156 | # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) |
| 646b4269 | 3157 | /* Read-only state that reports that TV-out is disabled in hardware. */ |
| 585fb111 | 3158 | # define TV_FUSE_STATE_DISABLED (2 << 4) |
| 646b4269 | 3159 | /* Normal operation */ |
| 585fb111 | 3160 | # define TV_TEST_MODE_NORMAL (0 << 0) |
| 646b4269 | 3161 | /* Encoder test pattern 1 - combo pattern */ |
| 585fb111 | 3162 | # define TV_TEST_MODE_PATTERN_1 (1 << 0) |
| 646b4269 | 3163 | /* Encoder test pattern 2 - full screen vertical 75% color bars */ |
| 585fb111 | 3164 | # define TV_TEST_MODE_PATTERN_2 (2 << 0) |
| 646b4269 | 3165 | /* Encoder test pattern 3 - full screen horizontal 75% color bars */ |
| 585fb111 | 3166 | # define TV_TEST_MODE_PATTERN_3 (3 << 0) |
| 646b4269 | 3167 | /* Encoder test pattern 4 - random noise */ |
| 585fb111 | 3168 | # define TV_TEST_MODE_PATTERN_4 (4 << 0) |
| 646b4269 | 3169 | /* Encoder test pattern 5 - linear color ramps */ |
| 585fb111 | 3170 | # define TV_TEST_MODE_PATTERN_5 (5 << 0) |
| 646b4269 | 3171 | /* |
| 585fb111 JB |
3172 | * This test mode forces the DACs to 50% of full output. |
| 3173 | * | |
| 3174 | * This is used for load detection in combination with TVDAC_SENSE_MASK | |
| 3175 | */ | |
| 3176 | # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) | |
| 3177 | # define TV_TEST_MODE_MASK (7 << 0) | |
| 3178 | ||
| 3179 | #define TV_DAC 0x68004 | |
| b8ed2a4f | 3180 | # define TV_DAC_SAVE 0x00ffff00 |
| 646b4269 | 3181 | /* |
| 585fb111 JB |
3182 | * Reports that DAC state change logic has reported change (RO). |
| 3183 | * | |
| 3184 | * This gets cleared when TV_DAC_STATE_EN is cleared | |
| 3185 | */ | |
| 3186 | # define TVDAC_STATE_CHG (1 << 31) | |
| 3187 | # define TVDAC_SENSE_MASK (7 << 28) | |
| 646b4269 | 3188 | /* Reports that DAC A voltage is above the detect threshold */ |
| 585fb111 | 3189 | # define TVDAC_A_SENSE (1 << 30) |
| 646b4269 | 3190 | /* Reports that DAC B voltage is above the detect threshold */ |
| 585fb111 | 3191 | # define TVDAC_B_SENSE (1 << 29) |
| 646b4269 | 3192 | /* Reports that DAC C voltage is above the detect threshold */ |
| 585fb111 | 3193 | # define TVDAC_C_SENSE (1 << 28) |
| 646b4269 | 3194 | /* |
| 585fb111 JB |
3195 | * Enables DAC state detection logic, for load-based TV detection. |
| 3196 | * | |
| 3197 | * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set | |
| 3198 | * to off, for load detection to work. | |
| 3199 | */ | |
| 3200 | # define TVDAC_STATE_CHG_EN (1 << 27) | |
| 646b4269 | 3201 | /* Sets the DAC A sense value to high */ |
| 585fb111 | 3202 | # define TVDAC_A_SENSE_CTL (1 << 26) |
| 646b4269 | 3203 | /* Sets the DAC B sense value to high */ |
| 585fb111 | 3204 | # define TVDAC_B_SENSE_CTL (1 << 25) |
| 646b4269 | 3205 | /* Sets the DAC C sense value to high */ |
| 585fb111 | 3206 | # define TVDAC_C_SENSE_CTL (1 << 24) |
| 646b4269 | 3207 | /* Overrides the ENC_ENABLE and DAC voltage levels */ |
| 585fb111 | 3208 | # define DAC_CTL_OVERRIDE (1 << 7) |
| 646b4269 | 3209 | /* Sets the slew rate. Must be preserved in software */ |
| 585fb111 JB |
3210 | # define ENC_TVDAC_SLEW_FAST (1 << 6) |
| 3211 | # define DAC_A_1_3_V (0 << 4) | |
| 3212 | # define DAC_A_1_1_V (1 << 4) | |
| 3213 | # define DAC_A_0_7_V (2 << 4) | |
| cb66c692 | 3214 | # define DAC_A_MASK (3 << 4) |
| 585fb111 JB |
3215 | # define DAC_B_1_3_V (0 << 2) |
| 3216 | # define DAC_B_1_1_V (1 << 2) | |
| 3217 | # define DAC_B_0_7_V (2 << 2) | |
| cb66c692 | 3218 | # define DAC_B_MASK (3 << 2) |
| 585fb111 JB |
3219 | # define DAC_C_1_3_V (0 << 0) |
| 3220 | # define DAC_C_1_1_V (1 << 0) | |
| 3221 | # define DAC_C_0_7_V (2 << 0) | |
| cb66c692 | 3222 | # define DAC_C_MASK (3 << 0) |
| 585fb111 | 3223 | |
| 646b4269 | 3224 | /* |
| 585fb111 JB |
3225 | * CSC coefficients are stored in a floating point format with 9 bits of |
| 3226 | * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, | |
| 3227 | * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with | |
| 3228 | * -1 (0x3) being the only legal negative value. | |
| 3229 | */ | |
| 3230 | #define TV_CSC_Y 0x68010 | |
| 3231 | # define TV_RY_MASK 0x07ff0000 | |
| 3232 | # define TV_RY_SHIFT 16 | |
| 3233 | # define TV_GY_MASK 0x00000fff | |
| 3234 | # define TV_GY_SHIFT 0 | |
| 3235 | ||
| 3236 | #define TV_CSC_Y2 0x68014 | |
| 3237 | # define TV_BY_MASK 0x07ff0000 | |
| 3238 | # define TV_BY_SHIFT 16 | |
| 646b4269 | 3239 | /* |
| 585fb111 JB |
3240 | * Y attenuation for component video. |
| 3241 | * | |
| 3242 | * Stored in 1.9 fixed point. | |
| 3243 | */ | |
| 3244 | # define TV_AY_MASK 0x000003ff | |
| 3245 | # define TV_AY_SHIFT 0 | |
| 3246 | ||
| 3247 | #define TV_CSC_U 0x68018 | |
| 3248 | # define TV_RU_MASK 0x07ff0000 | |
| 3249 | # define TV_RU_SHIFT 16 | |
| 3250 | # define TV_GU_MASK 0x000007ff | |
| 3251 | # define TV_GU_SHIFT 0 | |
| 3252 | ||
| 3253 | #define TV_CSC_U2 0x6801c | |
| 3254 | # define TV_BU_MASK 0x07ff0000 | |
| 3255 | # define TV_BU_SHIFT 16 | |
| 646b4269 | 3256 | /* |
| 585fb111 JB |
3257 | * U attenuation for component video. |
| 3258 | * | |
| 3259 | * Stored in 1.9 fixed point. | |
| 3260 | */ | |
| 3261 | # define TV_AU_MASK 0x000003ff | |
| 3262 | # define TV_AU_SHIFT 0 | |
| 3263 | ||
| 3264 | #define TV_CSC_V 0x68020 | |
| 3265 | # define TV_RV_MASK 0x0fff0000 | |
| 3266 | # define TV_RV_SHIFT 16 | |
| 3267 | # define TV_GV_MASK 0x000007ff | |
| 3268 | # define TV_GV_SHIFT 0 | |
| 3269 | ||
| 3270 | #define TV_CSC_V2 0x68024 | |
| 3271 | # define TV_BV_MASK 0x07ff0000 | |
| 3272 | # define TV_BV_SHIFT 16 | |
| 646b4269 | 3273 | /* |
| 585fb111 JB |
3274 | * V attenuation for component video. |
| 3275 | * | |
| 3276 | * Stored in 1.9 fixed point. | |
| 3277 | */ | |
| 3278 | # define TV_AV_MASK 0x000007ff | |
| 3279 | # define TV_AV_SHIFT 0 | |
| 3280 | ||
| 3281 | #define TV_CLR_KNOBS 0x68028 | |
| 646b4269 | 3282 | /* 2s-complement brightness adjustment */ |
| 585fb111 JB |
3283 | # define TV_BRIGHTNESS_MASK 0xff000000 |
| 3284 | # define TV_BRIGHTNESS_SHIFT 24 | |
| 646b4269 | 3285 | /* Contrast adjustment, as a 2.6 unsigned floating point number */ |
| 585fb111 JB |
3286 | # define TV_CONTRAST_MASK 0x00ff0000 |
| 3287 | # define TV_CONTRAST_SHIFT 16 | |
| 646b4269 | 3288 | /* Saturation adjustment, as a 2.6 unsigned floating point number */ |
| 585fb111 JB |
3289 | # define TV_SATURATION_MASK 0x0000ff00 |
| 3290 | # define TV_SATURATION_SHIFT 8 | |
| 646b4269 | 3291 | /* Hue adjustment, as an integer phase angle in degrees */ |
| 585fb111 JB |
3292 | # define TV_HUE_MASK 0x000000ff |
| 3293 | # define TV_HUE_SHIFT 0 | |
| 3294 | ||
| 3295 | #define TV_CLR_LEVEL 0x6802c | |
| 646b4269 | 3296 | /* Controls the DAC level for black */ |
| 585fb111 JB |
3297 | # define TV_BLACK_LEVEL_MASK 0x01ff0000 |
| 3298 | # define TV_BLACK_LEVEL_SHIFT 16 | |
| 646b4269 | 3299 | /* Controls the DAC level for blanking */ |
| 585fb111 JB |
3300 | # define TV_BLANK_LEVEL_MASK 0x000001ff |
| 3301 | # define TV_BLANK_LEVEL_SHIFT 0 | |
| 3302 | ||
| 3303 | #define TV_H_CTL_1 0x68030 | |
| 646b4269 | 3304 | /* Number of pixels in the hsync. */ |
| 585fb111 JB |
3305 | # define TV_HSYNC_END_MASK 0x1fff0000 |
| 3306 | # define TV_HSYNC_END_SHIFT 16 | |
| 646b4269 | 3307 | /* Total number of pixels minus one in the line (display and blanking). */ |
| 585fb111 JB |
3308 | # define TV_HTOTAL_MASK 0x00001fff |
| 3309 | # define TV_HTOTAL_SHIFT 0 | |
| 3310 | ||
| 3311 | #define TV_H_CTL_2 0x68034 | |
| 646b4269 | 3312 | /* Enables the colorburst (needed for non-component color) */ |
| 585fb111 | 3313 | # define TV_BURST_ENA (1 << 31) |
| 646b4269 | 3314 | /* Offset of the colorburst from the start of hsync, in pixels minus one. */ |
| 585fb111 JB |
3315 | # define TV_HBURST_START_SHIFT 16 |
| 3316 | # define TV_HBURST_START_MASK 0x1fff0000 | |
| 646b4269 | 3317 | /* Length of the colorburst */ |
| 585fb111 JB |
3318 | # define TV_HBURST_LEN_SHIFT 0 |
| 3319 | # define TV_HBURST_LEN_MASK 0x0001fff | |
| 3320 | ||
| 3321 | #define TV_H_CTL_3 0x68038 | |
| 646b4269 | 3322 | /* End of hblank, measured in pixels minus one from start of hsync */ |
| 585fb111 JB |
3323 | # define TV_HBLANK_END_SHIFT 16 |
| 3324 | # define TV_HBLANK_END_MASK 0x1fff0000 | |
| 646b4269 | 3325 | /* Start of hblank, measured in pixels minus one from start of hsync */ |
| 585fb111 JB |
3326 | # define TV_HBLANK_START_SHIFT 0 |
| 3327 | # define TV_HBLANK_START_MASK 0x0001fff | |
| 3328 | ||
| 3329 | #define TV_V_CTL_1 0x6803c | |
| 646b4269 | 3330 | /* XXX */ |
| 585fb111 JB |
3331 | # define TV_NBR_END_SHIFT 16 |
| 3332 | # define TV_NBR_END_MASK 0x07ff0000 | |
| 646b4269 | 3333 | /* XXX */ |
| 585fb111 JB |
3334 | # define TV_VI_END_F1_SHIFT 8 |
| 3335 | # define TV_VI_END_F1_MASK 0x00003f00 | |
| 646b4269 | 3336 | /* XXX */ |
| 585fb111 JB |
3337 | # define TV_VI_END_F2_SHIFT 0 |
| 3338 | # define TV_VI_END_F2_MASK 0x0000003f | |
| 3339 | ||
| 3340 | #define TV_V_CTL_2 0x68040 | |
| 646b4269 | 3341 | /* Length of vsync, in half lines */ |
| 585fb111 JB |
3342 | # define TV_VSYNC_LEN_MASK 0x07ff0000 |
| 3343 | # define TV_VSYNC_LEN_SHIFT 16 | |
| 646b4269 | 3344 | /* Offset of the start of vsync in field 1, measured in one less than the |
| 585fb111 JB |
3345 | * number of half lines. |
| 3346 | */ | |
| 3347 | # define TV_VSYNC_START_F1_MASK 0x00007f00 | |
| 3348 | # define TV_VSYNC_START_F1_SHIFT 8 | |
| 646b4269 | 3349 | /* |
| 585fb111 JB |
3350 | * Offset of the start of vsync in field 2, measured in one less than the |
| 3351 | * number of half lines. | |
| 3352 | */ | |
| 3353 | # define TV_VSYNC_START_F2_MASK 0x0000007f | |
| 3354 | # define TV_VSYNC_START_F2_SHIFT 0 | |
| 3355 | ||
| 3356 | #define TV_V_CTL_3 0x68044 | |
| 646b4269 | 3357 | /* Enables generation of the equalization signal */ |
| 585fb111 | 3358 | # define TV_EQUAL_ENA (1 << 31) |
| 646b4269 | 3359 | /* Length of vsync, in half lines */ |
| 585fb111 JB |
3360 | # define TV_VEQ_LEN_MASK 0x007f0000 |
| 3361 | # define TV_VEQ_LEN_SHIFT 16 | |
| 646b4269 | 3362 | /* Offset of the start of equalization in field 1, measured in one less than |
| 585fb111 JB |
3363 | * the number of half lines. |
| 3364 | */ | |
| 3365 | # define TV_VEQ_START_F1_MASK 0x0007f00 | |
| 3366 | # define TV_VEQ_START_F1_SHIFT 8 | |
| 646b4269 | 3367 | /* |
| 585fb111 JB |
3368 | * Offset of the start of equalization in field 2, measured in one less than |
| 3369 | * the number of half lines. | |
| 3370 | */ | |
| 3371 | # define TV_VEQ_START_F2_MASK 0x000007f | |
| 3372 | # define TV_VEQ_START_F2_SHIFT 0 | |
| 3373 | ||
| 3374 | #define TV_V_CTL_4 0x68048 | |
| 646b4269 | 3375 | /* |
| 585fb111 JB |
3376 | * Offset to start of vertical colorburst, measured in one less than the |
| 3377 | * number of lines from vertical start. | |
| 3378 | */ | |
| 3379 | # define TV_VBURST_START_F1_MASK 0x003f0000 | |
| 3380 | # define TV_VBURST_START_F1_SHIFT 16 | |
| 646b4269 | 3381 | /* |
| 585fb111 JB |
3382 | * Offset to the end of vertical colorburst, measured in one less than the |
| 3383 | * number of lines from the start of NBR. | |
| 3384 | */ | |
| 3385 | # define TV_VBURST_END_F1_MASK 0x000000ff | |
| 3386 | # define TV_VBURST_END_F1_SHIFT 0 | |
| 3387 | ||
| 3388 | #define TV_V_CTL_5 0x6804c | |
| 646b4269 | 3389 | /* |
| 585fb111 JB |
3390 | * Offset to start of vertical colorburst, measured in one less than the |
| 3391 | * number of lines from vertical start. | |
| 3392 | */ | |
| 3393 | # define TV_VBURST_START_F2_MASK 0x003f0000 | |
| 3394 | # define TV_VBURST_START_F2_SHIFT 16 | |
| 646b4269 | 3395 | /* |
| 585fb111 JB |
3396 | * Offset to the end of vertical colorburst, measured in one less than the |
| 3397 | * number of lines from the start of NBR. | |
| 3398 | */ | |
| 3399 | # define TV_VBURST_END_F2_MASK 0x000000ff | |
| 3400 | # define TV_VBURST_END_F2_SHIFT 0 | |
| 3401 | ||
| 3402 | #define TV_V_CTL_6 0x68050 | |
| 646b4269 | 3403 | /* |
| 585fb111 JB |
3404 | * Offset to start of vertical colorburst, measured in one less than the |
| 3405 | * number of lines from vertical start. | |
| 3406 | */ | |
| 3407 | # define TV_VBURST_START_F3_MASK 0x003f0000 | |
| 3408 | # define TV_VBURST_START_F3_SHIFT 16 | |
| 646b4269 | 3409 | /* |
| 585fb111 JB |
3410 | * Offset to the end of vertical colorburst, measured in one less than the |
| 3411 | * number of lines from the start of NBR. | |
| 3412 | */ | |
| 3413 | # define TV_VBURST_END_F3_MASK 0x000000ff | |
| 3414 | # define TV_VBURST_END_F3_SHIFT 0 | |
| 3415 | ||
| 3416 | #define TV_V_CTL_7 0x68054 | |
| 646b4269 | 3417 | /* |
| 585fb111 JB |
3418 | * Offset to start of vertical colorburst, measured in one less than the |
| 3419 | * number of lines from vertical start. | |
| 3420 | */ | |
| 3421 | # define TV_VBURST_START_F4_MASK 0x003f0000 | |
| 3422 | # define TV_VBURST_START_F4_SHIFT 16 | |
| 646b4269 | 3423 | /* |
| 585fb111 JB |
3424 | * Offset to the end of vertical colorburst, measured in one less than the |
| 3425 | * number of lines from the start of NBR. | |
| 3426 | */ | |
| 3427 | # define TV_VBURST_END_F4_MASK 0x000000ff | |
| 3428 | # define TV_VBURST_END_F4_SHIFT 0 | |
| 3429 | ||
| 3430 | #define TV_SC_CTL_1 0x68060 | |
| 646b4269 | 3431 | /* Turns on the first subcarrier phase generation DDA */ |
| 585fb111 | 3432 | # define TV_SC_DDA1_EN (1 << 31) |
| 646b4269 | 3433 | /* Turns on the first subcarrier phase generation DDA */ |
| 585fb111 | 3434 | # define TV_SC_DDA2_EN (1 << 30) |
| 646b4269 | 3435 | /* Turns on the first subcarrier phase generation DDA */ |
| 585fb111 | 3436 | # define TV_SC_DDA3_EN (1 << 29) |
| 646b4269 | 3437 | /* Sets the subcarrier DDA to reset frequency every other field */ |
| 585fb111 | 3438 | # define TV_SC_RESET_EVERY_2 (0 << 24) |
| 646b4269 | 3439 | /* Sets the subcarrier DDA to reset frequency every fourth field */ |
| 585fb111 | 3440 | # define TV_SC_RESET_EVERY_4 (1 << 24) |
| 646b4269 | 3441 | /* Sets the subcarrier DDA to reset frequency every eighth field */ |
| 585fb111 | 3442 | # define TV_SC_RESET_EVERY_8 (2 << 24) |
| 646b4269 | 3443 | /* Sets the subcarrier DDA to never reset the frequency */ |
| 585fb111 | 3444 | # define TV_SC_RESET_NEVER (3 << 24) |
| 646b4269 | 3445 | /* Sets the peak amplitude of the colorburst.*/ |
| 585fb111 JB |
3446 | # define TV_BURST_LEVEL_MASK 0x00ff0000 |
| 3447 | # define TV_BURST_LEVEL_SHIFT 16 | |
| 646b4269 | 3448 | /* Sets the increment of the first subcarrier phase generation DDA */ |
| 585fb111 JB |
3449 | # define TV_SCDDA1_INC_MASK 0x00000fff |
| 3450 | # define TV_SCDDA1_INC_SHIFT 0 | |
| 3451 | ||
| 3452 | #define TV_SC_CTL_2 0x68064 | |
| 646b4269 | 3453 | /* Sets the rollover for the second subcarrier phase generation DDA */ |
| 585fb111 JB |
3454 | # define TV_SCDDA2_SIZE_MASK 0x7fff0000 |
| 3455 | # define TV_SCDDA2_SIZE_SHIFT 16 | |
| 646b4269 | 3456 | /* Sets the increent of the second subcarrier phase generation DDA */ |
| 585fb111 JB |
3457 | # define TV_SCDDA2_INC_MASK 0x00007fff |
| 3458 | # define TV_SCDDA2_INC_SHIFT 0 | |
| 3459 | ||
| 3460 | #define TV_SC_CTL_3 0x68068 | |
| 646b4269 | 3461 | /* Sets the rollover for the third subcarrier phase generation DDA */ |
| 585fb111 JB |
3462 | # define TV_SCDDA3_SIZE_MASK 0x7fff0000 |
| 3463 | # define TV_SCDDA3_SIZE_SHIFT 16 | |
| 646b4269 | 3464 | /* Sets the increent of the third subcarrier phase generation DDA */ |
| 585fb111 JB |
3465 | # define TV_SCDDA3_INC_MASK 0x00007fff |
| 3466 | # define TV_SCDDA3_INC_SHIFT 0 | |
| 3467 | ||
| 3468 | #define TV_WIN_POS 0x68070 | |
| 646b4269 | 3469 | /* X coordinate of the display from the start of horizontal active */ |
| 585fb111 JB |
3470 | # define TV_XPOS_MASK 0x1fff0000 |
| 3471 | # define TV_XPOS_SHIFT 16 | |
| 646b4269 | 3472 | /* Y coordinate of the display from the start of vertical active (NBR) */ |
| 585fb111 JB |
3473 | # define TV_YPOS_MASK 0x00000fff |
| 3474 | # define TV_YPOS_SHIFT 0 | |
| 3475 | ||
| 3476 | #define TV_WIN_SIZE 0x68074 | |
| 646b4269 | 3477 | /* Horizontal size of the display window, measured in pixels*/ |
| 585fb111 JB |
3478 | # define TV_XSIZE_MASK 0x1fff0000 |
| 3479 | # define TV_XSIZE_SHIFT 16 | |
| 646b4269 | 3480 | /* |
| 585fb111 JB |
3481 | * Vertical size of the display window, measured in pixels. |
| 3482 | * | |
| 3483 | * Must be even for interlaced modes. | |
| 3484 | */ | |
| 3485 | # define TV_YSIZE_MASK 0x00000fff | |
| 3486 | # define TV_YSIZE_SHIFT 0 | |
| 3487 | ||
| 3488 | #define TV_FILTER_CTL_1 0x68080 | |
| 646b4269 | 3489 | /* |
| 585fb111 JB |
3490 | * Enables automatic scaling calculation. |
| 3491 | * | |
| 3492 | * If set, the rest of the registers are ignored, and the calculated values can | |
| 3493 | * be read back from the register. | |
| 3494 | */ | |
| 3495 | # define TV_AUTO_SCALE (1 << 31) | |
| 646b4269 | 3496 | /* |
| 585fb111 JB |
3497 | * Disables the vertical filter. |
| 3498 | * | |
| 3499 | * This is required on modes more than 1024 pixels wide */ | |
| 3500 | # define TV_V_FILTER_BYPASS (1 << 29) | |
| 646b4269 | 3501 | /* Enables adaptive vertical filtering */ |
| 585fb111 JB |
3502 | # define TV_VADAPT (1 << 28) |
| 3503 | # define TV_VADAPT_MODE_MASK (3 << 26) | |
| 646b4269 | 3504 | /* Selects the least adaptive vertical filtering mode */ |
| 585fb111 | 3505 | # define TV_VADAPT_MODE_LEAST (0 << 26) |
| 646b4269 | 3506 | /* Selects the moderately adaptive vertical filtering mode */ |
| 585fb111 | 3507 | # define TV_VADAPT_MODE_MODERATE (1 << 26) |
| 646b4269 | 3508 | /* Selects the most adaptive vertical filtering mode */ |
| 585fb111 | 3509 | # define TV_VADAPT_MODE_MOST (3 << 26) |
| 646b4269 | 3510 | /* |
| 585fb111 JB |
3511 | * Sets the horizontal scaling factor. |
| 3512 | * | |
| 3513 | * This should be the fractional part of the horizontal scaling factor divided | |
| 3514 | * by the oversampling rate. TV_HSCALE should be less than 1, and set to: | |
| 3515 | * | |
| 3516 | * (src width - 1) / ((oversample * dest width) - 1) | |
| 3517 | */ | |
| 3518 | # define TV_HSCALE_FRAC_MASK 0x00003fff | |
| 3519 | # define TV_HSCALE_FRAC_SHIFT 0 | |
| 3520 | ||
| 3521 | #define TV_FILTER_CTL_2 0x68084 | |
| 646b4269 | 3522 | /* |
| 585fb111 JB |
3523 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
| 3524 | * | |
| 3525 | * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) | |
| 3526 | */ | |
| 3527 | # define TV_VSCALE_INT_MASK 0x00038000 | |
| 3528 | # define TV_VSCALE_INT_SHIFT 15 | |
| 646b4269 | 3529 | /* |
| 585fb111 JB |
3530 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
| 3531 | * | |
| 3532 | * \sa TV_VSCALE_INT_MASK | |
| 3533 | */ | |
| 3534 | # define TV_VSCALE_FRAC_MASK 0x00007fff | |
| 3535 | # define TV_VSCALE_FRAC_SHIFT 0 | |
| 3536 | ||
| 3537 | #define TV_FILTER_CTL_3 0x68088 | |
| 646b4269 | 3538 | /* |
| 585fb111 JB |
3539 | * Sets the integer part of the 3.15 fixed-point vertical scaling factor. |
| 3540 | * | |
| 3541 | * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) | |
| 3542 | * | |
| 3543 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
| 3544 | */ | |
| 3545 | # define TV_VSCALE_IP_INT_MASK 0x00038000 | |
| 3546 | # define TV_VSCALE_IP_INT_SHIFT 15 | |
| 646b4269 | 3547 | /* |
| 585fb111 JB |
3548 | * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. |
| 3549 | * | |
| 3550 | * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. | |
| 3551 | * | |
| 3552 | * \sa TV_VSCALE_IP_INT_MASK | |
| 3553 | */ | |
| 3554 | # define TV_VSCALE_IP_FRAC_MASK 0x00007fff | |
| 3555 | # define TV_VSCALE_IP_FRAC_SHIFT 0 | |
| 3556 | ||
| 3557 | #define TV_CC_CONTROL 0x68090 | |
| 3558 | # define TV_CC_ENABLE (1 << 31) | |
| 646b4269 | 3559 | /* |
| 585fb111 JB |
3560 | * Specifies which field to send the CC data in. |
| 3561 | * | |
| 3562 | * CC data is usually sent in field 0. | |
| 3563 | */ | |
| 3564 | # define TV_CC_FID_MASK (1 << 27) | |
| 3565 | # define TV_CC_FID_SHIFT 27 | |
| 646b4269 | 3566 | /* Sets the horizontal position of the CC data. Usually 135. */ |
| 585fb111 JB |
3567 | # define TV_CC_HOFF_MASK 0x03ff0000 |
| 3568 | # define TV_CC_HOFF_SHIFT 16 | |
| 646b4269 | 3569 | /* Sets the vertical position of the CC data. Usually 21 */ |
| 585fb111 JB |
3570 | # define TV_CC_LINE_MASK 0x0000003f |
| 3571 | # define TV_CC_LINE_SHIFT 0 | |
| 3572 | ||
| 3573 | #define TV_CC_DATA 0x68094 | |
| 3574 | # define TV_CC_RDY (1 << 31) | |
| 646b4269 | 3575 | /* Second word of CC data to be transmitted. */ |
| 585fb111 JB |
3576 | # define TV_CC_DATA_2_MASK 0x007f0000 |
| 3577 | # define TV_CC_DATA_2_SHIFT 16 | |
| 646b4269 | 3578 | /* First word of CC data to be transmitted. */ |
| 585fb111 JB |
3579 | # define TV_CC_DATA_1_MASK 0x0000007f |
| 3580 | # define TV_CC_DATA_1_SHIFT 0 | |
| 3581 | ||
| 3582 | #define TV_H_LUMA_0 0x68100 | |
| 3583 | #define TV_H_LUMA_59 0x681ec | |
| 3584 | #define TV_H_CHROMA_0 0x68200 | |
| 3585 | #define TV_H_CHROMA_59 0x682ec | |
| 3586 | #define TV_V_LUMA_0 0x68300 | |
| 3587 | #define TV_V_LUMA_42 0x683a8 | |
| 3588 | #define TV_V_CHROMA_0 0x68400 | |
| 3589 | #define TV_V_CHROMA_42 0x684a8 | |
| 3590 | ||
| 040d87f1 | 3591 | /* Display Port */ |
| 32f9d658 | 3592 | #define DP_A 0x64000 /* eDP */ |
| 040d87f1 KP |
3593 | #define DP_B 0x64100 |
| 3594 | #define DP_C 0x64200 | |
| 3595 | #define DP_D 0x64300 | |
| 3596 | ||
| 3597 | #define DP_PORT_EN (1 << 31) | |
| 3598 | #define DP_PIPEB_SELECT (1 << 30) | |
| 47a05eca | 3599 | #define DP_PIPE_MASK (1 << 30) |
| 44f37d1f CML |
3600 | #define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) |
| 3601 | #define DP_PIPE_MASK_CHV (3 << 16) | |
| 47a05eca | 3602 | |
| 040d87f1 KP |
3603 | /* Link training mode - select a suitable mode for each stage */ |
| 3604 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) | |
| 3605 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) | |
| 3606 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) | |
| 3607 | #define DP_LINK_TRAIN_OFF (3 << 28) | |
| 3608 | #define DP_LINK_TRAIN_MASK (3 << 28) | |
| 3609 | #define DP_LINK_TRAIN_SHIFT 28 | |
| aad3d14d VS |
3610 | #define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) |
| 3611 | #define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) | |
| 040d87f1 | 3612 | |
| 8db9d77b ZW |
3613 | /* CPT Link training mode */ |
| 3614 | #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) | |
| 3615 | #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) | |
| 3616 | #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) | |
| 3617 | #define DP_LINK_TRAIN_OFF_CPT (3 << 8) | |
| 3618 | #define DP_LINK_TRAIN_MASK_CPT (7 << 8) | |
| 3619 | #define DP_LINK_TRAIN_SHIFT_CPT 8 | |
| 3620 | ||
| 040d87f1 KP |
3621 | /* Signal voltages. These are mostly controlled by the other end */ |
| 3622 | #define DP_VOLTAGE_0_4 (0 << 25) | |
| 3623 | #define DP_VOLTAGE_0_6 (1 << 25) | |
| 3624 | #define DP_VOLTAGE_0_8 (2 << 25) | |
| 3625 | #define DP_VOLTAGE_1_2 (3 << 25) | |
| 3626 | #define DP_VOLTAGE_MASK (7 << 25) | |
| 3627 | #define DP_VOLTAGE_SHIFT 25 | |
| 3628 | ||
| 3629 | /* Signal pre-emphasis levels, like voltages, the other end tells us what | |
| 3630 | * they want | |
| 3631 | */ | |
| 3632 | #define DP_PRE_EMPHASIS_0 (0 << 22) | |
| 3633 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) | |
| 3634 | #define DP_PRE_EMPHASIS_6 (2 << 22) | |
| 3635 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) | |
| 3636 | #define DP_PRE_EMPHASIS_MASK (7 << 22) | |
| 3637 | #define DP_PRE_EMPHASIS_SHIFT 22 | |
| 3638 | ||
| 3639 | /* How many wires to use. I guess 3 was too hard */ | |
| 17aa6be9 | 3640 | #define DP_PORT_WIDTH(width) (((width) - 1) << 19) |
| 040d87f1 KP |
3641 | #define DP_PORT_WIDTH_MASK (7 << 19) |
| 3642 | ||
| 3643 | /* Mystic DPCD version 1.1 special mode */ | |
| 3644 | #define DP_ENHANCED_FRAMING (1 << 18) | |
| 3645 | ||
| 32f9d658 ZW |
3646 | /* eDP */ |
| 3647 | #define DP_PLL_FREQ_270MHZ (0 << 16) | |
| 3648 | #define DP_PLL_FREQ_160MHZ (1 << 16) | |
| 3649 | #define DP_PLL_FREQ_MASK (3 << 16) | |
| 3650 | ||
| 646b4269 | 3651 | /* locked once port is enabled */ |
| 040d87f1 KP |
3652 | #define DP_PORT_REVERSAL (1 << 15) |
| 3653 | ||
| 32f9d658 ZW |
3654 | /* eDP */ |
| 3655 | #define DP_PLL_ENABLE (1 << 14) | |
| 3656 | ||
| 646b4269 | 3657 | /* sends the clock on lane 15 of the PEG for debug */ |
| 040d87f1 KP |
3658 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) |
| 3659 | ||
| 3660 | #define DP_SCRAMBLING_DISABLE (1 << 12) | |
| f2b115e6 | 3661 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) |
| 040d87f1 | 3662 | |
| 646b4269 | 3663 | /* limit RGB values to avoid confusing TVs */ |
| 040d87f1 KP |
3664 | #define DP_COLOR_RANGE_16_235 (1 << 8) |
| 3665 | ||
| 646b4269 | 3666 | /* Turn on the audio link */ |
| 040d87f1 KP |
3667 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) |
| 3668 | ||
| 646b4269 | 3669 | /* vs and hs sync polarity */ |
| 040d87f1 KP |
3670 | #define DP_SYNC_VS_HIGH (1 << 4) |
| 3671 | #define DP_SYNC_HS_HIGH (1 << 3) | |
| 3672 | ||
| 646b4269 | 3673 | /* A fantasy */ |
| 040d87f1 KP |
3674 | #define DP_DETECTED (1 << 2) |
| 3675 | ||
| 646b4269 | 3676 | /* The aux channel provides a way to talk to the |
| 040d87f1 KP |
3677 | * signal sink for DDC etc. Max packet size supported |
| 3678 | * is 20 bytes in each direction, hence the 5 fixed | |
| 3679 | * data registers | |
| 3680 | */ | |
| 32f9d658 ZW |
3681 | #define DPA_AUX_CH_CTL 0x64010 |
| 3682 | #define DPA_AUX_CH_DATA1 0x64014 | |
| 3683 | #define DPA_AUX_CH_DATA2 0x64018 | |
| 3684 | #define DPA_AUX_CH_DATA3 0x6401c | |
| 3685 | #define DPA_AUX_CH_DATA4 0x64020 | |
| 3686 | #define DPA_AUX_CH_DATA5 0x64024 | |
| 3687 | ||
| 040d87f1 KP |
3688 | #define DPB_AUX_CH_CTL 0x64110 |
| 3689 | #define DPB_AUX_CH_DATA1 0x64114 | |
| 3690 | #define DPB_AUX_CH_DATA2 0x64118 | |
| 3691 | #define DPB_AUX_CH_DATA3 0x6411c | |
| 3692 | #define DPB_AUX_CH_DATA4 0x64120 | |
| 3693 | #define DPB_AUX_CH_DATA5 0x64124 | |
| 3694 | ||
| 3695 | #define DPC_AUX_CH_CTL 0x64210 | |
| 3696 | #define DPC_AUX_CH_DATA1 0x64214 | |
| 3697 | #define DPC_AUX_CH_DATA2 0x64218 | |
| 3698 | #define DPC_AUX_CH_DATA3 0x6421c | |
| 3699 | #define DPC_AUX_CH_DATA4 0x64220 | |
| 3700 | #define DPC_AUX_CH_DATA5 0x64224 | |
| 3701 | ||
| 3702 | #define DPD_AUX_CH_CTL 0x64310 | |
| 3703 | #define DPD_AUX_CH_DATA1 0x64314 | |
| 3704 | #define DPD_AUX_CH_DATA2 0x64318 | |
| 3705 | #define DPD_AUX_CH_DATA3 0x6431c | |
| 3706 | #define DPD_AUX_CH_DATA4 0x64320 | |
| 3707 | #define DPD_AUX_CH_DATA5 0x64324 | |
| 3708 | ||
| 3709 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) | |
| 3710 | #define DP_AUX_CH_CTL_DONE (1 << 30) | |
| 3711 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) | |
| 3712 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) | |
| 3713 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) | |
| 3714 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) | |
| 3715 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) | |
| 3716 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) | |
| 3717 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) | |
| 3718 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) | |
| 3719 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) | |
| 3720 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 | |
| 3721 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) | |
| 3722 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 | |
| 3723 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) | |
| 3724 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) | |
| 3725 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) | |
| 3726 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) | |
| 3727 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) | |
| 3728 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) | |
| 3729 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 | |
| b9ca5fad | 3730 | #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) |
| 040d87f1 KP |
3731 | |
| 3732 | /* | |
| 3733 | * Computing GMCH M and N values for the Display Port link | |
| 3734 | * | |
| 3735 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes | |
| 3736 | * | |
| 3737 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) | |
| 3738 | * | |
| 3739 | * The GMCH value is used internally | |
| 3740 | * | |
| 3741 | * bytes_per_pixel is the number of bytes coming out of the plane, | |
| 3742 | * which is after the LUTs, so we want the bytes for our color format. | |
| 3743 | * For our current usage, this is always 3, one byte for R, G and B. | |
| 3744 | */ | |
| e3b95f1e DV |
3745 | #define _PIPEA_DATA_M_G4X 0x70050 |
| 3746 | #define _PIPEB_DATA_M_G4X 0x71050 | |
| 040d87f1 KP |
3747 | |
| 3748 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ | |
| a65851af | 3749 | #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ |
| 72419203 | 3750 | #define TU_SIZE_SHIFT 25 |
| a65851af | 3751 | #define TU_SIZE_MASK (0x3f << 25) |
| 040d87f1 | 3752 | |
| a65851af VS |
3753 | #define DATA_LINK_M_N_MASK (0xffffff) |
| 3754 | #define DATA_LINK_N_MAX (0x800000) | |
| 040d87f1 | 3755 | |
| e3b95f1e DV |
3756 | #define _PIPEA_DATA_N_G4X 0x70054 |
| 3757 | #define _PIPEB_DATA_N_G4X 0x71054 | |
| 040d87f1 KP |
3758 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) |
| 3759 | ||
| 3760 | /* | |
| 3761 | * Computing Link M and N values for the Display Port link | |
| 3762 | * | |
| 3763 | * Link M / N = pixel_clock / ls_clk | |
| 3764 | * | |
| 3765 | * (the DP spec calls pixel_clock the 'strm_clk') | |
| 3766 | * | |
| 3767 | * The Link value is transmitted in the Main Stream | |
| 3768 | * Attributes and VB-ID. | |
| 3769 | */ | |
| 3770 | ||
| e3b95f1e DV |
3771 | #define _PIPEA_LINK_M_G4X 0x70060 |
| 3772 | #define _PIPEB_LINK_M_G4X 0x71060 | |
| 040d87f1 KP |
3773 | #define PIPEA_DP_LINK_M_MASK (0xffffff) |
| 3774 | ||
| e3b95f1e DV |
3775 | #define _PIPEA_LINK_N_G4X 0x70064 |
| 3776 | #define _PIPEB_LINK_N_G4X 0x71064 | |
| 040d87f1 KP |
3777 | #define PIPEA_DP_LINK_N_MASK (0xffffff) |
| 3778 | ||
| e3b95f1e DV |
3779 | #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) |
| 3780 | #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) | |
| 3781 | #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) | |
| 3782 | #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) | |
| 9db4a9c7 | 3783 | |
| 585fb111 JB |
3784 | /* Display & cursor control */ |
| 3785 | ||
| 3786 | /* Pipe A */ | |
| a57c774a | 3787 | #define _PIPEADSL 0x70000 |
| 837ba00f PZ |
3788 | #define DSL_LINEMASK_GEN2 0x00000fff |
| 3789 | #define DSL_LINEMASK_GEN3 0x00001fff | |
| a57c774a | 3790 | #define _PIPEACONF 0x70008 |
| 5eddb70b CW |
3791 | #define PIPECONF_ENABLE (1<<31) |
| 3792 | #define PIPECONF_DISABLE 0 | |
| 3793 | #define PIPECONF_DOUBLE_WIDE (1<<30) | |
| 585fb111 | 3794 | #define I965_PIPECONF_ACTIVE (1<<30) |
| b6ec10b3 | 3795 | #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ |
| f47166d2 | 3796 | #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) |
| 5eddb70b CW |
3797 | #define PIPECONF_SINGLE_WIDE 0 |
| 3798 | #define PIPECONF_PIPE_UNLOCKED 0 | |
| 3799 | #define PIPECONF_PIPE_LOCKED (1<<25) | |
| 3800 | #define PIPECONF_PALETTE 0 | |
| 3801 | #define PIPECONF_GAMMA (1<<24) | |
| 585fb111 | 3802 | #define PIPECONF_FORCE_BORDER (1<<25) |
| 59df7b17 | 3803 | #define PIPECONF_INTERLACE_MASK (7 << 21) |
| ee2b0b38 | 3804 | #define PIPECONF_INTERLACE_MASK_HSW (3 << 21) |
| d442ae18 DV |
3805 | /* Note that pre-gen3 does not support interlaced display directly. Panel |
| 3806 | * fitting must be disabled on pre-ilk for interlaced. */ | |
| 3807 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
| 3808 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ | |
| 3809 | #define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ | |
| 3810 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
| 3811 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ | |
| 3812 | /* Ironlake and later have a complete new set of values for interlaced. PFIT | |
| 3813 | * means panel fitter required, PF means progressive fetch, DBL means power | |
| 3814 | * saving pixel doubling. */ | |
| 3815 | #define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) | |
| 3816 | #define PIPECONF_INTERLACED_ILK (3 << 21) | |
| 3817 | #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ | |
| 3818 | #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ | |
| 1bd1bd80 | 3819 | #define PIPECONF_INTERLACE_MODE_MASK (7 << 21) |
| 439d7ac0 | 3820 | #define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) |
| 652c393a | 3821 | #define PIPECONF_CXSR_DOWNCLOCK (1<<16) |
| 3685a8f3 | 3822 | #define PIPECONF_COLOR_RANGE_SELECT (1 << 13) |
| dfd07d72 DV |
3823 | #define PIPECONF_BPC_MASK (0x7 << 5) |
| 3824 | #define PIPECONF_8BPC (0<<5) | |
| 3825 | #define PIPECONF_10BPC (1<<5) | |
| 3826 | #define PIPECONF_6BPC (2<<5) | |
| 3827 | #define PIPECONF_12BPC (3<<5) | |
| 4f0d1aff JB |
3828 | #define PIPECONF_DITHER_EN (1<<4) |
| 3829 | #define PIPECONF_DITHER_TYPE_MASK (0x0000000c) | |
| 3830 | #define PIPECONF_DITHER_TYPE_SP (0<<2) | |
| 3831 | #define PIPECONF_DITHER_TYPE_ST1 (1<<2) | |
| 3832 | #define PIPECONF_DITHER_TYPE_ST2 (2<<2) | |
| 3833 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) | |
| a57c774a | 3834 | #define _PIPEASTAT 0x70024 |
| 585fb111 | 3835 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
| 579a9b0e | 3836 | #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) |
| 585fb111 JB |
3837 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
| 3838 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) | |
| 8cc96e7c | 3839 | #define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) |
| 585fb111 | 3840 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
| c46ce4d7 | 3841 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) |
| 585fb111 JB |
3842 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
| 3843 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | |
| 3844 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | |
| 3845 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | |
| c70af1e4 | 3846 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) |
| 585fb111 JB |
3847 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
| 3848 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | |
| 3849 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | |
| 10c59c51 | 3850 | #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) |
| 8cc96e7c | 3851 | #define PERF_COUNTER_INTERRUPT_EN (1UL<<19) |
| 585fb111 JB |
3852 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
| 3853 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | |
| 8cc96e7c | 3854 | #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) |
| 585fb111 | 3855 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
| c46ce4d7 | 3856 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) |
| 585fb111 | 3857 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
| 579a9b0e ID |
3858 | #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) |
| 3859 | #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) | |
| 585fb111 JB |
3860 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
| 3861 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | |
| 8cc96e7c | 3862 | #define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) |
| 585fb111 | 3863 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
| 579a9b0e | 3864 | #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) |
| 585fb111 JB |
3865 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
| 3866 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) | |
| 3867 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | |
| 3868 | #define PIPE_DPST_EVENT_STATUS (1UL<<7) | |
| 10c59c51 | 3869 | #define PIPE_A_PSR_STATUS_VLV (1UL<<6) |
| 8cc96e7c | 3870 | #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) |
| 585fb111 JB |
3871 | #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) |
| 3872 | #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | |
| 10c59c51 | 3873 | #define PIPE_B_PSR_STATUS_VLV (1UL<<3) |
| 8cc96e7c | 3874 | #define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) |
| 585fb111 JB |
3875 | #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ |
| 3876 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | |
| 8cc96e7c | 3877 | #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) |
| 585fb111 | 3878 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) |
| 8cc96e7c | 3879 | #define PIPE_HBLANK_INT_STATUS (1UL<<0) |
| 585fb111 JB |
3880 | #define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) |
| 3881 | ||
| 755e9019 ID |
3882 | #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 |
| 3883 | #define PIPESTAT_INT_STATUS_MASK 0x0000ffff | |
| 3884 | ||
| 84fd4f4e RB |
3885 | #define PIPE_A_OFFSET 0x70000 |
| 3886 | #define PIPE_B_OFFSET 0x71000 | |
| 3887 | #define PIPE_C_OFFSET 0x72000 | |
| 3888 | #define CHV_PIPE_C_OFFSET 0x74000 | |
| a57c774a AK |
3889 | /* |
| 3890 | * There's actually no pipe EDP. Some pipe registers have | |
| 3891 | * simply shifted from the pipe to the transcoder, while | |
| 3892 | * keeping their original offset. Thus we need PIPE_EDP_OFFSET | |
| 3893 | * to access such registers in transcoder EDP. | |
| 3894 | */ | |
| 3895 | #define PIPE_EDP_OFFSET 0x7f000 | |
| 3896 | ||
| 5c969aa7 DL |
3897 | #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ |
| 3898 | dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ | |
| 3899 | dev_priv->info.display_mmio_offset) | |
| a57c774a AK |
3900 | |
| 3901 | #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) | |
| 3902 | #define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) | |
| 3903 | #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) | |
| 3904 | #define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) | |
| 3905 | #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) | |
| 5eddb70b | 3906 | |
| 756f85cf PZ |
3907 | #define _PIPE_MISC_A 0x70030 |
| 3908 | #define _PIPE_MISC_B 0x71030 | |
| 3909 | #define PIPEMISC_DITHER_BPC_MASK (7<<5) | |
| 3910 | #define PIPEMISC_DITHER_8_BPC (0<<5) | |
| 3911 | #define PIPEMISC_DITHER_10_BPC (1<<5) | |
| 3912 | #define PIPEMISC_DITHER_6_BPC (2<<5) | |
| 3913 | #define PIPEMISC_DITHER_12_BPC (3<<5) | |
| 3914 | #define PIPEMISC_DITHER_ENABLE (1<<4) | |
| 3915 | #define PIPEMISC_DITHER_TYPE_MASK (3<<2) | |
| 3916 | #define PIPEMISC_DITHER_TYPE_SP (0<<2) | |
| a57c774a | 3917 | #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) |
| 756f85cf | 3918 | |
| b41fbda1 | 3919 | #define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) |
| 7983117f | 3920 | #define PIPEB_LINE_COMPARE_INT_EN (1<<29) |
| c46ce4d7 JB |
3921 | #define PIPEB_HLINE_INT_EN (1<<28) |
| 3922 | #define PIPEB_VBLANK_INT_EN (1<<27) | |
| 579a9b0e ID |
3923 | #define SPRITED_FLIP_DONE_INT_EN (1<<26) |
| 3924 | #define SPRITEC_FLIP_DONE_INT_EN (1<<25) | |
| 3925 | #define PLANEB_FLIP_DONE_INT_EN (1<<24) | |
| f3c67fdd | 3926 | #define PIPE_PSR_INT_EN (1<<22) |
| 7983117f | 3927 | #define PIPEA_LINE_COMPARE_INT_EN (1<<21) |
| c46ce4d7 JB |
3928 | #define PIPEA_HLINE_INT_EN (1<<20) |
| 3929 | #define PIPEA_VBLANK_INT_EN (1<<19) | |
| 579a9b0e ID |
3930 | #define SPRITEB_FLIP_DONE_INT_EN (1<<18) |
| 3931 | #define SPRITEA_FLIP_DONE_INT_EN (1<<17) | |
| c46ce4d7 | 3932 | #define PLANEA_FLIPDONE_INT_EN (1<<16) |
| f3c67fdd VS |
3933 | #define PIPEC_LINE_COMPARE_INT_EN (1<<13) |
| 3934 | #define PIPEC_HLINE_INT_EN (1<<12) | |
| 3935 | #define PIPEC_VBLANK_INT_EN (1<<11) | |
| 3936 | #define SPRITEF_FLIPDONE_INT_EN (1<<10) | |
| 3937 | #define SPRITEE_FLIPDONE_INT_EN (1<<9) | |
| 3938 | #define PLANEC_FLIPDONE_INT_EN (1<<8) | |
| c46ce4d7 | 3939 | |
| bf67a6fd VS |
3940 | #define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ |
| 3941 | #define SPRITEF_INVALID_GTT_INT_EN (1<<27) | |
| 3942 | #define SPRITEE_INVALID_GTT_INT_EN (1<<26) | |
| 3943 | #define PLANEC_INVALID_GTT_INT_EN (1<<25) | |
| 3944 | #define CURSORC_INVALID_GTT_INT_EN (1<<24) | |
| c46ce4d7 JB |
3945 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) |
| 3946 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) | |
| 3947 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) | |
| 3948 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) | |
| 3949 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) | |
| 3950 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) | |
| 3951 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) | |
| 3952 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) | |
| 3953 | #define DPINVGTT_EN_MASK 0xff0000 | |
| bf67a6fd VS |
3954 | #define DPINVGTT_EN_MASK_CHV 0xfff0000 |
| 3955 | #define SPRITEF_INVALID_GTT_STATUS (1<<11) | |
| 3956 | #define SPRITEE_INVALID_GTT_STATUS (1<<10) | |
| 3957 | #define PLANEC_INVALID_GTT_STATUS (1<<9) | |
| 3958 | #define CURSORC_INVALID_GTT_STATUS (1<<8) | |
| c46ce4d7 JB |
3959 | #define CURSORB_INVALID_GTT_STATUS (1<<7) |
| 3960 | #define CURSORA_INVALID_GTT_STATUS (1<<6) | |
| 3961 | #define SPRITED_INVALID_GTT_STATUS (1<<5) | |
| 3962 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) | |
| 3963 | #define PLANEB_INVALID_GTT_STATUS (1<<3) | |
| 3964 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) | |
| 3965 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) | |
| 3966 | #define PLANEA_INVALID_GTT_STATUS (1<<0) | |
| 3967 | #define DPINVGTT_STATUS_MASK 0xff | |
| bf67a6fd | 3968 | #define DPINVGTT_STATUS_MASK_CHV 0xfff |
| c46ce4d7 | 3969 | |
| 585fb111 JB |
3970 | #define DSPARB 0x70030 |
| 3971 | #define DSPARB_CSTART_MASK (0x7f << 7) | |
| 3972 | #define DSPARB_CSTART_SHIFT 7 | |
| 3973 | #define DSPARB_BSTART_MASK (0x7f) | |
| 3974 | #define DSPARB_BSTART_SHIFT 0 | |
| 7662c8bd SL |
3975 | #define DSPARB_BEND_SHIFT 9 /* on 855 */ |
| 3976 | #define DSPARB_AEND_SHIFT 0 | |
| 3977 | ||
| 0a560674 | 3978 | /* pnv/gen4/g4x/vlv/chv */ |
| 5c969aa7 | 3979 | #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) |
| 0a560674 VS |
3980 | #define DSPFW_SR_SHIFT 23 |
| 3981 | #define DSPFW_SR_MASK (0x1ff<<23) | |
| 3982 | #define DSPFW_CURSORB_SHIFT 16 | |
| 3983 | #define DSPFW_CURSORB_MASK (0x3f<<16) | |
| 3984 | #define DSPFW_PLANEB_SHIFT 8 | |
| 3985 | #define DSPFW_PLANEB_MASK (0x7f<<8) | |
| 3986 | #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ | |
| 3987 | #define DSPFW_PLANEA_SHIFT 0 | |
| 3988 | #define DSPFW_PLANEA_MASK (0x7f<<0) | |
| 3989 | #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ | |
| 5c969aa7 | 3990 | #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) |
| 0a560674 VS |
3991 | #define DSPFW_FBC_SR_EN (1<<31) /* g4x */ |
| 3992 | #define DSPFW_FBC_SR_SHIFT 28 | |
| 3993 | #define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ | |
| 3994 | #define DSPFW_FBC_HPLL_SR_SHIFT 24 | |
| 3995 | #define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ | |
| 3996 | #define DSPFW_SPRITEB_SHIFT (16) | |
| 3997 | #define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ | |
| 3998 | #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ | |
| 3999 | #define DSPFW_CURSORA_SHIFT 8 | |
| 4000 | #define DSPFW_CURSORA_MASK (0x3f<<8) | |
| 4001 | #define DSPFW_PLANEC_SHIFT_OLD 0 | |
| 4002 | #define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */ | |
| 4003 | #define DSPFW_SPRITEA_SHIFT 0 | |
| 4004 | #define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ | |
| 4005 | #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ | |
| 5c969aa7 | 4006 | #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) |
| 0a560674 | 4007 | #define DSPFW_HPLL_SR_EN (1<<31) |
| f2b115e6 | 4008 | #define PINEVIEW_SELF_REFRESH_EN (1<<30) |
| 0a560674 | 4009 | #define DSPFW_CURSOR_SR_SHIFT 24 |
| d4294342 ZY |
4010 | #define DSPFW_CURSOR_SR_MASK (0x3f<<24) |
| 4011 | #define DSPFW_HPLL_CURSOR_SHIFT 16 | |
| 4012 | #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) | |
| 0a560674 VS |
4013 | #define DSPFW_HPLL_SR_SHIFT 0 |
| 4014 | #define DSPFW_HPLL_SR_MASK (0x1ff<<0) | |
| 4015 | ||
| 4016 | /* vlv/chv */ | |
| 4017 | #define DSPFW4 (VLV_DISPLAY_BASE + 0x70070) | |
| 4018 | #define DSPFW_SPRITEB_WM1_SHIFT 16 | |
| 4019 | #define DSPFW_SPRITEB_WM1_MASK (0xff<<16) | |
| 4020 | #define DSPFW_CURSORA_WM1_SHIFT 8 | |
| 4021 | #define DSPFW_CURSORA_WM1_MASK (0x3f<<8) | |
| 4022 | #define DSPFW_SPRITEA_WM1_SHIFT 0 | |
| 4023 | #define DSPFW_SPRITEA_WM1_MASK (0xff<<0) | |
| 4024 | #define DSPFW5 (VLV_DISPLAY_BASE + 0x70074) | |
| 4025 | #define DSPFW_PLANEB_WM1_SHIFT 24 | |
| 4026 | #define DSPFW_PLANEB_WM1_MASK (0xff<<24) | |
| 4027 | #define DSPFW_PLANEA_WM1_SHIFT 16 | |
| 4028 | #define DSPFW_PLANEA_WM1_MASK (0xff<<16) | |
| 4029 | #define DSPFW_CURSORB_WM1_SHIFT 8 | |
| 4030 | #define DSPFW_CURSORB_WM1_MASK (0x3f<<8) | |
| 4031 | #define DSPFW_CURSOR_SR_WM1_SHIFT 0 | |
| 4032 | #define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) | |
| 4033 | #define DSPFW6 (VLV_DISPLAY_BASE + 0x70078) | |
| 4034 | #define DSPFW_SR_WM1_SHIFT 0 | |
| 4035 | #define DSPFW_SR_WM1_MASK (0x1ff<<0) | |
| 4036 | #define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) | |
| 4037 | #define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ | |
| 4038 | #define DSPFW_SPRITED_WM1_SHIFT 24 | |
| 4039 | #define DSPFW_SPRITED_WM1_MASK (0xff<<24) | |
| 4040 | #define DSPFW_SPRITED_SHIFT 16 | |
| 4041 | #define DSPFW_SPRITED_MASK (0xff<<16) | |
| 4042 | #define DSPFW_SPRITEC_WM1_SHIFT 8 | |
| 4043 | #define DSPFW_SPRITEC_WM1_MASK (0xff<<8) | |
| 4044 | #define DSPFW_SPRITEC_SHIFT 0 | |
| 4045 | #define DSPFW_SPRITEC_MASK (0xff<<0) | |
| 4046 | #define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) | |
| 4047 | #define DSPFW_SPRITEF_WM1_SHIFT 24 | |
| 4048 | #define DSPFW_SPRITEF_WM1_MASK (0xff<<24) | |
| 4049 | #define DSPFW_SPRITEF_SHIFT 16 | |
| 4050 | #define DSPFW_SPRITEF_MASK (0xff<<16) | |
| 4051 | #define DSPFW_SPRITEE_WM1_SHIFT 8 | |
| 4052 | #define DSPFW_SPRITEE_WM1_MASK (0xff<<8) | |
| 4053 | #define DSPFW_SPRITEE_SHIFT 0 | |
| 4054 | #define DSPFW_SPRITEE_MASK (0xff<<0) | |
| 4055 | #define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ | |
| 4056 | #define DSPFW_PLANEC_WM1_SHIFT 24 | |
| 4057 | #define DSPFW_PLANEC_WM1_MASK (0xff<<24) | |
| 4058 | #define DSPFW_PLANEC_SHIFT 16 | |
| 4059 | #define DSPFW_PLANEC_MASK (0xff<<16) | |
| 4060 | #define DSPFW_CURSORC_WM1_SHIFT 8 | |
| 4061 | #define DSPFW_CURSORC_WM1_MASK (0x3f<<16) | |
| 4062 | #define DSPFW_CURSORC_SHIFT 0 | |
| 4063 | #define DSPFW_CURSORC_MASK (0x3f<<0) | |
| 4064 | ||
| 4065 | /* vlv/chv high order bits */ | |
| 4066 | #define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) | |
| 4067 | #define DSPFW_SR_HI_SHIFT 24 | |
| 4068 | #define DSPFW_SR_HI_MASK (1<<24) | |
| 4069 | #define DSPFW_SPRITEF_HI_SHIFT 23 | |
| 4070 | #define DSPFW_SPRITEF_HI_MASK (1<<23) | |
| 4071 | #define DSPFW_SPRITEE_HI_SHIFT 22 | |
| 4072 | #define DSPFW_SPRITEE_HI_MASK (1<<22) | |
| 4073 | #define DSPFW_PLANEC_HI_SHIFT 21 | |
| 4074 | #define DSPFW_PLANEC_HI_MASK (1<<21) | |
| 4075 | #define DSPFW_SPRITED_HI_SHIFT 20 | |
| 4076 | #define DSPFW_SPRITED_HI_MASK (1<<20) | |
| 4077 | #define DSPFW_SPRITEC_HI_SHIFT 16 | |
| 4078 | #define DSPFW_SPRITEC_HI_MASK (1<<16) | |
| 4079 | #define DSPFW_PLANEB_HI_SHIFT 12 | |
| 4080 | #define DSPFW_PLANEB_HI_MASK (1<<12) | |
| 4081 | #define DSPFW_SPRITEB_HI_SHIFT 8 | |
| 4082 | #define DSPFW_SPRITEB_HI_MASK (1<<8) | |
| 4083 | #define DSPFW_SPRITEA_HI_SHIFT 4 | |
| 4084 | #define DSPFW_SPRITEA_HI_MASK (1<<4) | |
| 4085 | #define DSPFW_PLANEA_HI_SHIFT 0 | |
| 4086 | #define DSPFW_PLANEA_HI_MASK (1<<0) | |
| 4087 | #define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) | |
| 4088 | #define DSPFW_SR_WM1_HI_SHIFT 24 | |
| 4089 | #define DSPFW_SR_WM1_HI_MASK (1<<24) | |
| 4090 | #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 | |
| 4091 | #define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) | |
| 4092 | #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 | |
| 4093 | #define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) | |
| 4094 | #define DSPFW_PLANEC_WM1_HI_SHIFT 21 | |
| 4095 | #define DSPFW_PLANEC_WM1_HI_MASK (1<<21) | |
| 4096 | #define DSPFW_SPRITED_WM1_HI_SHIFT 20 | |
| 4097 | #define DSPFW_SPRITED_WM1_HI_MASK (1<<20) | |
| 4098 | #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 | |
| 4099 | #define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) | |
| 4100 | #define DSPFW_PLANEB_WM1_HI_SHIFT 12 | |
| 4101 | #define DSPFW_PLANEB_WM1_HI_MASK (1<<12) | |
| 4102 | #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 | |
| 4103 | #define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) | |
| 4104 | #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 | |
| 4105 | #define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) | |
| 4106 | #define DSPFW_PLANEA_WM1_HI_SHIFT 0 | |
| 4107 | #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) | |
| 7662c8bd | 4108 | |
| 12a3c055 | 4109 | /* drain latency register values*/ |
| 5e56ba45 | 4110 | #define DRAIN_LATENCY_PRECISION_16 16 |
| 12a3c055 | 4111 | #define DRAIN_LATENCY_PRECISION_32 32 |
| 22c5aee3 | 4112 | #define DRAIN_LATENCY_PRECISION_64 64 |
| 1abc4dc7 | 4113 | #define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) |
| 5e56ba45 RV |
4114 | #define DDL_CURSOR_PRECISION_HIGH (1<<31) |
| 4115 | #define DDL_CURSOR_PRECISION_LOW (0<<31) | |
| 1abc4dc7 | 4116 | #define DDL_CURSOR_SHIFT 24 |
| 5e56ba45 RV |
4117 | #define DDL_SPRITE_PRECISION_HIGH(sprite) (1<<(15+8*(sprite))) |
| 4118 | #define DDL_SPRITE_PRECISION_LOW(sprite) (0<<(15+8*(sprite))) | |
| 01e184cc | 4119 | #define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) |
| 5e56ba45 RV |
4120 | #define DDL_PLANE_PRECISION_HIGH (1<<7) |
| 4121 | #define DDL_PLANE_PRECISION_LOW (0<<7) | |
| 1abc4dc7 | 4122 | #define DDL_PLANE_SHIFT 0 |
| 0948c265 | 4123 | #define DRAIN_LATENCY_MASK 0x7f |
| 12a3c055 | 4124 | |
| 7662c8bd | 4125 | /* FIFO watermark sizes etc */ |
| 0e442c60 | 4126 | #define G4X_FIFO_LINE_SIZE 64 |
| 7662c8bd SL |
4127 | #define I915_FIFO_LINE_SIZE 64 |
| 4128 | #define I830_FIFO_LINE_SIZE 32 | |
| 0e442c60 | 4129 | |
| ceb04246 | 4130 | #define VALLEYVIEW_FIFO_SIZE 255 |
| 0e442c60 | 4131 | #define G4X_FIFO_SIZE 127 |
| 1b07e04e ZY |
4132 | #define I965_FIFO_SIZE 512 |
| 4133 | #define I945_FIFO_SIZE 127 | |
| 7662c8bd | 4134 | #define I915_FIFO_SIZE 95 |
| dff33cfc | 4135 | #define I855GM_FIFO_SIZE 127 /* In cachelines */ |
| 7662c8bd | 4136 | #define I830_FIFO_SIZE 95 |
| 0e442c60 | 4137 | |
| ceb04246 | 4138 | #define VALLEYVIEW_MAX_WM 0xff |
| 0e442c60 | 4139 | #define G4X_MAX_WM 0x3f |
| 7662c8bd SL |
4140 | #define I915_MAX_WM 0x3f |
| 4141 | ||
| f2b115e6 AJ |
4142 | #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ |
| 4143 | #define PINEVIEW_FIFO_LINE_SIZE 64 | |
| 4144 | #define PINEVIEW_MAX_WM 0x1ff | |
| 4145 | #define PINEVIEW_DFT_WM 0x3f | |
| 4146 | #define PINEVIEW_DFT_HPLLOFF_WM 0 | |
| 4147 | #define PINEVIEW_GUARD_WM 10 | |
| 4148 | #define PINEVIEW_CURSOR_FIFO 64 | |
| 4149 | #define PINEVIEW_CURSOR_MAX_WM 0x3f | |
| 4150 | #define PINEVIEW_CURSOR_DFT_WM 0 | |
| 4151 | #define PINEVIEW_CURSOR_GUARD_WM 5 | |
| 7662c8bd | 4152 | |
| ceb04246 | 4153 | #define VALLEYVIEW_CURSOR_MAX_WM 64 |
| 4fe5e611 ZY |
4154 | #define I965_CURSOR_FIFO 64 |
| 4155 | #define I965_CURSOR_MAX_WM 32 | |
| 4156 | #define I965_CURSOR_DFT_WM 8 | |
| 7f8a8569 | 4157 | |
| fae1267d PB |
4158 | /* Watermark register definitions for SKL */ |
| 4159 | #define CUR_WM_A_0 0x70140 | |
| 4160 | #define CUR_WM_B_0 0x71140 | |
| 4161 | #define PLANE_WM_1_A_0 0x70240 | |
| 4162 | #define PLANE_WM_1_B_0 0x71240 | |
| 4163 | #define PLANE_WM_2_A_0 0x70340 | |
| 4164 | #define PLANE_WM_2_B_0 0x71340 | |
| 4165 | #define PLANE_WM_TRANS_1_A_0 0x70268 | |
| 4166 | #define PLANE_WM_TRANS_1_B_0 0x71268 | |
| 4167 | #define PLANE_WM_TRANS_2_A_0 0x70368 | |
| 4168 | #define PLANE_WM_TRANS_2_B_0 0x71368 | |
| 4169 | #define CUR_WM_TRANS_A_0 0x70168 | |
| 4170 | #define CUR_WM_TRANS_B_0 0x71168 | |
| 4171 | #define PLANE_WM_EN (1 << 31) | |
| 4172 | #define PLANE_WM_LINES_SHIFT 14 | |
| 4173 | #define PLANE_WM_LINES_MASK 0x1f | |
| 4174 | #define PLANE_WM_BLOCKS_MASK 0x3ff | |
| 4175 | ||
| 4176 | #define CUR_WM_0(pipe) _PIPE(pipe, CUR_WM_A_0, CUR_WM_B_0) | |
| 4177 | #define CUR_WM(pipe, level) (CUR_WM_0(pipe) + ((4) * (level))) | |
| 4178 | #define CUR_WM_TRANS(pipe) _PIPE(pipe, CUR_WM_TRANS_A_0, CUR_WM_TRANS_B_0) | |
| 4179 | ||
| 4180 | #define _PLANE_WM_1(pipe) _PIPE(pipe, PLANE_WM_1_A_0, PLANE_WM_1_B_0) | |
| 4181 | #define _PLANE_WM_2(pipe) _PIPE(pipe, PLANE_WM_2_A_0, PLANE_WM_2_B_0) | |
| 4182 | #define _PLANE_WM_BASE(pipe, plane) \ | |
| 4183 | _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) | |
| 4184 | #define PLANE_WM(pipe, plane, level) \ | |
| 4185 | (_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) | |
| 4186 | #define _PLANE_WM_TRANS_1(pipe) \ | |
| 4187 | _PIPE(pipe, PLANE_WM_TRANS_1_A_0, PLANE_WM_TRANS_1_B_0) | |
| 4188 | #define _PLANE_WM_TRANS_2(pipe) \ | |
| 4189 | _PIPE(pipe, PLANE_WM_TRANS_2_A_0, PLANE_WM_TRANS_2_B_0) | |
| 4190 | #define PLANE_WM_TRANS(pipe, plane) \ | |
| 4191 | _PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)) | |
| 4192 | ||
| 7f8a8569 ZW |
4193 | /* define the Watermark register on Ironlake */ |
| 4194 | #define WM0_PIPEA_ILK 0x45100 | |
| 1996d624 | 4195 | #define WM0_PIPE_PLANE_MASK (0xffff<<16) |
| 7f8a8569 | 4196 | #define WM0_PIPE_PLANE_SHIFT 16 |
| 1996d624 | 4197 | #define WM0_PIPE_SPRITE_MASK (0xff<<8) |
| 7f8a8569 | 4198 | #define WM0_PIPE_SPRITE_SHIFT 8 |
| 1996d624 | 4199 | #define WM0_PIPE_CURSOR_MASK (0xff) |
| 7f8a8569 ZW |
4200 | |
| 4201 | #define WM0_PIPEB_ILK 0x45104 | |
| d6c892df | 4202 | #define WM0_PIPEC_IVB 0x45200 |
| 7f8a8569 ZW |
4203 | #define WM1_LP_ILK 0x45108 |
| 4204 | #define WM1_LP_SR_EN (1<<31) | |
| 4205 | #define WM1_LP_LATENCY_SHIFT 24 | |
| 4206 | #define WM1_LP_LATENCY_MASK (0x7f<<24) | |
| 4ed765f9 CW |
4207 | #define WM1_LP_FBC_MASK (0xf<<20) |
| 4208 | #define WM1_LP_FBC_SHIFT 20 | |
| 416f4727 | 4209 | #define WM1_LP_FBC_SHIFT_BDW 19 |
| 1996d624 | 4210 | #define WM1_LP_SR_MASK (0x7ff<<8) |
| 7f8a8569 | 4211 | #define WM1_LP_SR_SHIFT 8 |
| 1996d624 | 4212 | #define WM1_LP_CURSOR_MASK (0xff) |
| dd8849c8 JB |
4213 | #define WM2_LP_ILK 0x4510c |
| 4214 | #define WM2_LP_EN (1<<31) | |
| 4215 | #define WM3_LP_ILK 0x45110 | |
| 4216 | #define WM3_LP_EN (1<<31) | |
| 4217 | #define WM1S_LP_ILK 0x45120 | |
| b840d907 JB |
4218 | #define WM2S_LP_IVB 0x45124 |
| 4219 | #define WM3S_LP_IVB 0x45128 | |
| dd8849c8 | 4220 | #define WM1S_LP_EN (1<<31) |
| 7f8a8569 | 4221 | |
| cca32e9a PZ |
4222 | #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ |
| 4223 | (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ | |
| 4224 | ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) | |
| 4225 | ||
| 7f8a8569 ZW |
4226 | /* Memory latency timer register */ |
| 4227 | #define MLTR_ILK 0x11222 | |
| b79d4990 JB |
4228 | #define MLTR_WM1_SHIFT 0 |
| 4229 | #define MLTR_WM2_SHIFT 8 | |
| 7f8a8569 ZW |
4230 | /* the unit of memory self-refresh latency time is 0.5us */ |
| 4231 | #define ILK_SRLT_MASK 0x3f | |
| 4232 | ||
| 1398261a YL |
4233 | |
| 4234 | /* the address where we get all kinds of latency value */ | |
| 4235 | #define SSKPD 0x5d10 | |
| 4236 | #define SSKPD_WM_MASK 0x3f | |
| 4237 | #define SSKPD_WM0_SHIFT 0 | |
| 4238 | #define SSKPD_WM1_SHIFT 8 | |
| 4239 | #define SSKPD_WM2_SHIFT 16 | |
| 4240 | #define SSKPD_WM3_SHIFT 24 | |
| 4241 | ||
| 585fb111 JB |
4242 | /* |
| 4243 | * The two pipe frame counter registers are not synchronized, so | |
| 4244 | * reading a stable value is somewhat tricky. The following code | |
| 4245 | * should work: | |
| 4246 | * | |
| 4247 | * do { | |
| 4248 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
| 4249 | * PIPE_FRAME_HIGH_SHIFT; | |
| 4250 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | |
| 4251 | * PIPE_FRAME_LOW_SHIFT); | |
| 4252 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
| 4253 | * PIPE_FRAME_HIGH_SHIFT); | |
| 4254 | * } while (high1 != high2); | |
| 4255 | * frame = (high1 << 8) | low1; | |
| 4256 | */ | |
| 25a2e2d0 | 4257 | #define _PIPEAFRAMEHIGH 0x70040 |
| 585fb111 JB |
4258 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff |
| 4259 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
| 25a2e2d0 | 4260 | #define _PIPEAFRAMEPIXEL 0x70044 |
| 585fb111 JB |
4261 | #define PIPE_FRAME_LOW_MASK 0xff000000 |
| 4262 | #define PIPE_FRAME_LOW_SHIFT 24 | |
| 4263 | #define PIPE_PIXEL_MASK 0x00ffffff | |
| 4264 | #define PIPE_PIXEL_SHIFT 0 | |
| 9880b7a5 | 4265 | /* GM45+ just has to be different */ |
| eb6008ad RB |
4266 | #define _PIPEA_FRMCOUNT_GM45 0x70040 |
| 4267 | #define _PIPEA_FLIPCOUNT_GM45 0x70044 | |
| 4268 | #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) | |
| 75f7f3ec | 4269 | #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) |
| 585fb111 JB |
4270 | |
| 4271 | /* Cursor A & B regs */ | |
| 5efb3e28 | 4272 | #define _CURACNTR 0x70080 |
| 14b60391 JB |
4273 | /* Old style CUR*CNTR flags (desktop 8xx) */ |
| 4274 | #define CURSOR_ENABLE 0x80000000 | |
| 4275 | #define CURSOR_GAMMA_ENABLE 0x40000000 | |
| dc41c154 VS |
4276 | #define CURSOR_STRIDE_SHIFT 28 |
| 4277 | #define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ | |
| 86d3efce | 4278 | #define CURSOR_PIPE_CSC_ENABLE (1<<24) |
| 14b60391 JB |
4279 | #define CURSOR_FORMAT_SHIFT 24 |
| 4280 | #define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) | |
| 4281 | #define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) | |
| 4282 | #define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) | |
| 4283 | #define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) | |
| 4284 | #define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) | |
| 4285 | #define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) | |
| 4286 | /* New style CUR*CNTR flags */ | |
| 4287 | #define CURSOR_MODE 0x27 | |
| 585fb111 | 4288 | #define CURSOR_MODE_DISABLE 0x00 |
| 4726e0b0 SK |
4289 | #define CURSOR_MODE_128_32B_AX 0x02 |
| 4290 | #define CURSOR_MODE_256_32B_AX 0x03 | |
| 585fb111 | 4291 | #define CURSOR_MODE_64_32B_AX 0x07 |
| 4726e0b0 SK |
4292 | #define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) |
| 4293 | #define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) | |
| 585fb111 | 4294 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) |
| 14b60391 JB |
4295 | #define MCURSOR_PIPE_SELECT (1 << 28) |
| 4296 | #define MCURSOR_PIPE_A 0x00 | |
| 4297 | #define MCURSOR_PIPE_B (1 << 28) | |
| 585fb111 | 4298 | #define MCURSOR_GAMMA_ENABLE (1 << 26) |
| 4398ad45 | 4299 | #define CURSOR_ROTATE_180 (1<<15) |
| 1f5d76db | 4300 | #define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) |
| 5efb3e28 VS |
4301 | #define _CURABASE 0x70084 |
| 4302 | #define _CURAPOS 0x70088 | |
| 585fb111 JB |
4303 | #define CURSOR_POS_MASK 0x007FF |
| 4304 | #define CURSOR_POS_SIGN 0x8000 | |
| 4305 | #define CURSOR_X_SHIFT 0 | |
| 4306 | #define CURSOR_Y_SHIFT 16 | |
| 14b60391 | 4307 | #define CURSIZE 0x700a0 |
| 5efb3e28 VS |
4308 | #define _CURBCNTR 0x700c0 |
| 4309 | #define _CURBBASE 0x700c4 | |
| 4310 | #define _CURBPOS 0x700c8 | |
| 585fb111 | 4311 | |
| 65a21cd6 JB |
4312 | #define _CURBCNTR_IVB 0x71080 |
| 4313 | #define _CURBBASE_IVB 0x71084 | |
| 4314 | #define _CURBPOS_IVB 0x71088 | |
| 4315 | ||
| 5efb3e28 VS |
4316 | #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ |
| 4317 | dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ | |
| 4318 | dev_priv->info.display_mmio_offset) | |
| 4319 | ||
| 4320 | #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) | |
| 4321 | #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) | |
| 4322 | #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) | |
| c4a1d9e4 | 4323 | |
| 5efb3e28 VS |
4324 | #define CURSOR_A_OFFSET 0x70080 |
| 4325 | #define CURSOR_B_OFFSET 0x700c0 | |
| 4326 | #define CHV_CURSOR_C_OFFSET 0x700e0 | |
| 4327 | #define IVB_CURSOR_B_OFFSET 0x71080 | |
| 4328 | #define IVB_CURSOR_C_OFFSET 0x72080 | |
| 65a21cd6 | 4329 | |
| 585fb111 | 4330 | /* Display A control */ |
| a57c774a | 4331 | #define _DSPACNTR 0x70180 |
| 585fb111 JB |
4332 | #define DISPLAY_PLANE_ENABLE (1<<31) |
| 4333 | #define DISPLAY_PLANE_DISABLE 0 | |
| 4334 | #define DISPPLANE_GAMMA_ENABLE (1<<30) | |
| 4335 | #define DISPPLANE_GAMMA_DISABLE 0 | |
| 4336 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) | |
| 57779d06 | 4337 | #define DISPPLANE_YUV422 (0x0<<26) |
| 585fb111 | 4338 | #define DISPPLANE_8BPP (0x2<<26) |
| 57779d06 VS |
4339 | #define DISPPLANE_BGRA555 (0x3<<26) |
| 4340 | #define DISPPLANE_BGRX555 (0x4<<26) | |
| 4341 | #define DISPPLANE_BGRX565 (0x5<<26) | |
| 4342 | #define DISPPLANE_BGRX888 (0x6<<26) | |
| 4343 | #define DISPPLANE_BGRA888 (0x7<<26) | |
| 4344 | #define DISPPLANE_RGBX101010 (0x8<<26) | |
| 4345 | #define DISPPLANE_RGBA101010 (0x9<<26) | |
| 4346 | #define DISPPLANE_BGRX101010 (0xa<<26) | |
| 4347 | #define DISPPLANE_RGBX161616 (0xc<<26) | |
| 4348 | #define DISPPLANE_RGBX888 (0xe<<26) | |
| 4349 | #define DISPPLANE_RGBA888 (0xf<<26) | |
| 585fb111 JB |
4350 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
| 4351 | #define DISPPLANE_STEREO_DISABLE 0 | |
| 86d3efce | 4352 | #define DISPPLANE_PIPE_CSC_ENABLE (1<<24) |
| b24e7179 JB |
4353 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |
| 4354 | #define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) | |
| 585fb111 | 4355 | #define DISPPLANE_SEL_PIPE_A 0 |
| b24e7179 | 4356 | #define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) |
| 585fb111 JB |
4357 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) |
| 4358 | #define DISPPLANE_SRC_KEY_DISABLE 0 | |
| 4359 | #define DISPPLANE_LINE_DOUBLE (1<<20) | |
| 4360 | #define DISPPLANE_NO_LINE_DOUBLE 0 | |
| 4361 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
| 4362 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) | |
| c14b0485 VS |
4363 | #define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */ |
| 4364 | #define DISPPLANE_ROTATE_180 (1<<15) | |
| f2b115e6 | 4365 | #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ |
| f544847f | 4366 | #define DISPPLANE_TILED (1<<10) |
| c14b0485 | 4367 | #define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */ |
| a57c774a AK |
4368 | #define _DSPAADDR 0x70184 |
| 4369 | #define _DSPASTRIDE 0x70188 | |
| 4370 | #define _DSPAPOS 0x7018C /* reserved */ | |
| 4371 | #define _DSPASIZE 0x70190 | |
| 4372 | #define _DSPASURF 0x7019C /* 965+ only */ | |
| 4373 | #define _DSPATILEOFF 0x701A4 /* 965+ only */ | |
| 4374 | #define _DSPAOFFSET 0x701A4 /* HSW */ | |
| 4375 | #define _DSPASURFLIVE 0x701AC | |
| 4376 | ||
| 4377 | #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) | |
| 4378 | #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) | |
| 4379 | #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) | |
| 4380 | #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) | |
| 4381 | #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) | |
| 4382 | #define DSPSURF(plane) _PIPE2(plane, _DSPASURF) | |
| 4383 | #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) | |
| e506a0c6 | 4384 | #define DSPLINOFF(plane) DSPADDR(plane) |
| a57c774a AK |
4385 | #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) |
| 4386 | #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) | |
| 5eddb70b | 4387 | |
| c14b0485 VS |
4388 | /* CHV pipe B blender and primary plane */ |
| 4389 | #define _CHV_BLEND_A 0x60a00 | |
| 4390 | #define CHV_BLEND_LEGACY (0<<30) | |
| 4391 | #define CHV_BLEND_ANDROID (1<<30) | |
| 4392 | #define CHV_BLEND_MPO (2<<30) | |
| 4393 | #define CHV_BLEND_MASK (3<<30) | |
| 4394 | #define _CHV_CANVAS_A 0x60a04 | |
| 4395 | #define _PRIMPOS_A 0x60a08 | |
| 4396 | #define _PRIMSIZE_A 0x60a0c | |
| 4397 | #define _PRIMCNSTALPHA_A 0x60a10 | |
| 4398 | #define PRIM_CONST_ALPHA_ENABLE (1<<31) | |
| 4399 | ||
| 4400 | #define CHV_BLEND(pipe) _TRANSCODER2(pipe, _CHV_BLEND_A) | |
| 4401 | #define CHV_CANVAS(pipe) _TRANSCODER2(pipe, _CHV_CANVAS_A) | |
| 4402 | #define PRIMPOS(plane) _TRANSCODER2(plane, _PRIMPOS_A) | |
| 4403 | #define PRIMSIZE(plane) _TRANSCODER2(plane, _PRIMSIZE_A) | |
| 4404 | #define PRIMCNSTALPHA(plane) _TRANSCODER2(plane, _PRIMCNSTALPHA_A) | |
| 4405 | ||
| 446f2545 AR |
4406 | /* Display/Sprite base address macros */ |
| 4407 | #define DISP_BASEADDR_MASK (0xfffff000) | |
| 4408 | #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) | |
| 4409 | #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) | |
| 446f2545 | 4410 | |
| 585fb111 | 4411 | /* VBIOS flags */ |
| 5c969aa7 DL |
4412 | #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) |
| 4413 | #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) | |
| 4414 | #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) | |
| 4415 | #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) | |
| 4416 | #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) | |
| 4417 | #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) | |
| 4418 | #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) | |
| 4419 | #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) | |
| 4420 | #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) | |
| 4421 | #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) | |
| 4422 | #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) | |
| 4423 | #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) | |
| 4424 | #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) | |
| 585fb111 JB |
4425 | |
| 4426 | /* Pipe B */ | |
| 5c969aa7 DL |
4427 | #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) |
| 4428 | #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) | |
| 4429 | #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) | |
| 25a2e2d0 VS |
4430 | #define _PIPEBFRAMEHIGH 0x71040 |
| 4431 | #define _PIPEBFRAMEPIXEL 0x71044 | |
| 5c969aa7 DL |
4432 | #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) |
| 4433 | #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) | |
| 9880b7a5 | 4434 | |
| 585fb111 JB |
4435 | |
| 4436 | /* Display B control */ | |
| 5c969aa7 | 4437 | #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) |
| 585fb111 JB |
4438 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) |
| 4439 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 | |
| 4440 | #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 | |
| 4441 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
| 5c969aa7 DL |
4442 | #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) |
| 4443 | #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) | |
| 4444 | #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) | |
| 4445 | #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) | |
| 4446 | #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) | |
| 4447 | #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) | |
| 4448 | #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) | |
| 4449 | #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) | |
| 585fb111 | 4450 | |
| b840d907 JB |
4451 | /* Sprite A control */ |
| 4452 | #define _DVSACNTR 0x72180 | |
| 4453 | #define DVS_ENABLE (1<<31) | |
| 4454 | #define DVS_GAMMA_ENABLE (1<<30) | |
| 4455 | #define DVS_PIXFORMAT_MASK (3<<25) | |
| 4456 | #define DVS_FORMAT_YUV422 (0<<25) | |
| 4457 | #define DVS_FORMAT_RGBX101010 (1<<25) | |
| 4458 | #define DVS_FORMAT_RGBX888 (2<<25) | |
| 4459 | #define DVS_FORMAT_RGBX161616 (3<<25) | |
| 86d3efce | 4460 | #define DVS_PIPE_CSC_ENABLE (1<<24) |
| b840d907 | 4461 | #define DVS_SOURCE_KEY (1<<22) |
| ab2f9df1 | 4462 | #define DVS_RGB_ORDER_XBGR (1<<20) |
| b840d907 JB |
4463 | #define DVS_YUV_BYTE_ORDER_MASK (3<<16) |
| 4464 | #define DVS_YUV_ORDER_YUYV (0<<16) | |
| 4465 | #define DVS_YUV_ORDER_UYVY (1<<16) | |
| 4466 | #define DVS_YUV_ORDER_YVYU (2<<16) | |
| 4467 | #define DVS_YUV_ORDER_VYUY (3<<16) | |
| 76eebda7 | 4468 | #define DVS_ROTATE_180 (1<<15) |
| b840d907 JB |
4469 | #define DVS_DEST_KEY (1<<2) |
| 4470 | #define DVS_TRICKLE_FEED_DISABLE (1<<14) | |
| 4471 | #define DVS_TILED (1<<10) | |
| 4472 | #define _DVSALINOFF 0x72184 | |
| 4473 | #define _DVSASTRIDE 0x72188 | |
| 4474 | #define _DVSAPOS 0x7218c | |
| 4475 | #define _DVSASIZE 0x72190 | |
| 4476 | #define _DVSAKEYVAL 0x72194 | |
| 4477 | #define _DVSAKEYMSK 0x72198 | |
| 4478 | #define _DVSASURF 0x7219c | |
| 4479 | #define _DVSAKEYMAXVAL 0x721a0 | |
| 4480 | #define _DVSATILEOFF 0x721a4 | |
| 4481 | #define _DVSASURFLIVE 0x721ac | |
| 4482 | #define _DVSASCALE 0x72204 | |
| 4483 | #define DVS_SCALE_ENABLE (1<<31) | |
| 4484 | #define DVS_FILTER_MASK (3<<29) | |
| 4485 | #define DVS_FILTER_MEDIUM (0<<29) | |
| 4486 | #define DVS_FILTER_ENHANCING (1<<29) | |
| 4487 | #define DVS_FILTER_SOFTENING (2<<29) | |
| 4488 | #define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
| 4489 | #define DVS_VERTICAL_OFFSET_ENABLE (1<<27) | |
| 4490 | #define _DVSAGAMC 0x72300 | |
| 4491 | ||
| 4492 | #define _DVSBCNTR 0x73180 | |
| 4493 | #define _DVSBLINOFF 0x73184 | |
| 4494 | #define _DVSBSTRIDE 0x73188 | |
| 4495 | #define _DVSBPOS 0x7318c | |
| 4496 | #define _DVSBSIZE 0x73190 | |
| 4497 | #define _DVSBKEYVAL 0x73194 | |
| 4498 | #define _DVSBKEYMSK 0x73198 | |
| 4499 | #define _DVSBSURF 0x7319c | |
| 4500 | #define _DVSBKEYMAXVAL 0x731a0 | |
| 4501 | #define _DVSBTILEOFF 0x731a4 | |
| 4502 | #define _DVSBSURFLIVE 0x731ac | |
| 4503 | #define _DVSBSCALE 0x73204 | |
| 4504 | #define _DVSBGAMC 0x73300 | |
| 4505 | ||
| 4506 | #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) | |
| 4507 | #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) | |
| 4508 | #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) | |
| 4509 | #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) | |
| 4510 | #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) | |
| 8ea30864 | 4511 | #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) |
| b840d907 JB |
4512 | #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) |
| 4513 | #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) | |
| 4514 | #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) | |
| 8ea30864 JB |
4515 | #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) |
| 4516 | #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) | |
| 32ae46bf | 4517 | #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) |
| b840d907 JB |
4518 | |
| 4519 | #define _SPRA_CTL 0x70280 | |
| 4520 | #define SPRITE_ENABLE (1<<31) | |
| 4521 | #define SPRITE_GAMMA_ENABLE (1<<30) | |
| 4522 | #define SPRITE_PIXFORMAT_MASK (7<<25) | |
| 4523 | #define SPRITE_FORMAT_YUV422 (0<<25) | |
| 4524 | #define SPRITE_FORMAT_RGBX101010 (1<<25) | |
| 4525 | #define SPRITE_FORMAT_RGBX888 (2<<25) | |
| 4526 | #define SPRITE_FORMAT_RGBX161616 (3<<25) | |
| 4527 | #define SPRITE_FORMAT_YUV444 (4<<25) | |
| 4528 | #define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ | |
| 86d3efce | 4529 | #define SPRITE_PIPE_CSC_ENABLE (1<<24) |
| b840d907 JB |
4530 | #define SPRITE_SOURCE_KEY (1<<22) |
| 4531 | #define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ | |
| 4532 | #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) | |
| 4533 | #define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ | |
| 4534 | #define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) | |
| 4535 | #define SPRITE_YUV_ORDER_YUYV (0<<16) | |
| 4536 | #define SPRITE_YUV_ORDER_UYVY (1<<16) | |
| 4537 | #define SPRITE_YUV_ORDER_YVYU (2<<16) | |
| 4538 | #define SPRITE_YUV_ORDER_VYUY (3<<16) | |
| 76eebda7 | 4539 | #define SPRITE_ROTATE_180 (1<<15) |
| b840d907 JB |
4540 | #define SPRITE_TRICKLE_FEED_DISABLE (1<<14) |
| 4541 | #define SPRITE_INT_GAMMA_ENABLE (1<<13) | |
| 4542 | #define SPRITE_TILED (1<<10) | |
| 4543 | #define SPRITE_DEST_KEY (1<<2) | |
| 4544 | #define _SPRA_LINOFF 0x70284 | |
| 4545 | #define _SPRA_STRIDE 0x70288 | |
| 4546 | #define _SPRA_POS 0x7028c | |
| 4547 | #define _SPRA_SIZE 0x70290 | |
| 4548 | #define _SPRA_KEYVAL 0x70294 | |
| 4549 | #define _SPRA_KEYMSK 0x70298 | |
| 4550 | #define _SPRA_SURF 0x7029c | |
| 4551 | #define _SPRA_KEYMAX 0x702a0 | |
| 4552 | #define _SPRA_TILEOFF 0x702a4 | |
| c54173a8 | 4553 | #define _SPRA_OFFSET 0x702a4 |
| 32ae46bf | 4554 | #define _SPRA_SURFLIVE 0x702ac |
| b840d907 JB |
4555 | #define _SPRA_SCALE 0x70304 |
| 4556 | #define SPRITE_SCALE_ENABLE (1<<31) | |
| 4557 | #define SPRITE_FILTER_MASK (3<<29) | |
| 4558 | #define SPRITE_FILTER_MEDIUM (0<<29) | |
| 4559 | #define SPRITE_FILTER_ENHANCING (1<<29) | |
| 4560 | #define SPRITE_FILTER_SOFTENING (2<<29) | |
| 4561 | #define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ | |
| 4562 | #define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) | |
| 4563 | #define _SPRA_GAMC 0x70400 | |
| 4564 | ||
| 4565 | #define _SPRB_CTL 0x71280 | |
| 4566 | #define _SPRB_LINOFF 0x71284 | |
| 4567 | #define _SPRB_STRIDE 0x71288 | |
| 4568 | #define _SPRB_POS 0x7128c | |
| 4569 | #define _SPRB_SIZE 0x71290 | |
| 4570 | #define _SPRB_KEYVAL 0x71294 | |
| 4571 | #define _SPRB_KEYMSK 0x71298 | |
| 4572 | #define _SPRB_SURF 0x7129c | |
| 4573 | #define _SPRB_KEYMAX 0x712a0 | |
| 4574 | #define _SPRB_TILEOFF 0x712a4 | |
| c54173a8 | 4575 | #define _SPRB_OFFSET 0x712a4 |
| 32ae46bf | 4576 | #define _SPRB_SURFLIVE 0x712ac |
| b840d907 JB |
4577 | #define _SPRB_SCALE 0x71304 |
| 4578 | #define _SPRB_GAMC 0x71400 | |
| 4579 | ||
| 4580 | #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) | |
| 4581 | #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) | |
| 4582 | #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) | |
| 4583 | #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) | |
| 4584 | #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) | |
| 4585 | #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) | |
| 4586 | #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) | |
| 4587 | #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) | |
| 4588 | #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) | |
| 4589 | #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) | |
| c54173a8 | 4590 | #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) |
| b840d907 JB |
4591 | #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) |
| 4592 | #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) | |
| 32ae46bf | 4593 | #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) |
| b840d907 | 4594 | |
| 921c3b67 | 4595 | #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) |
| 7f1f3851 | 4596 | #define SP_ENABLE (1<<31) |
| 4ea67bc7 | 4597 | #define SP_GAMMA_ENABLE (1<<30) |
| 7f1f3851 JB |
4598 | #define SP_PIXFORMAT_MASK (0xf<<26) |
| 4599 | #define SP_FORMAT_YUV422 (0<<26) | |
| 4600 | #define SP_FORMAT_BGR565 (5<<26) | |
| 4601 | #define SP_FORMAT_BGRX8888 (6<<26) | |
| 4602 | #define SP_FORMAT_BGRA8888 (7<<26) | |
| 4603 | #define SP_FORMAT_RGBX1010102 (8<<26) | |
| 4604 | #define SP_FORMAT_RGBA1010102 (9<<26) | |
| 4605 | #define SP_FORMAT_RGBX8888 (0xe<<26) | |
| 4606 | #define SP_FORMAT_RGBA8888 (0xf<<26) | |
| c14b0485 | 4607 | #define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */ |
| 7f1f3851 JB |
4608 | #define SP_SOURCE_KEY (1<<22) |
| 4609 | #define SP_YUV_BYTE_ORDER_MASK (3<<16) | |
| 4610 | #define SP_YUV_ORDER_YUYV (0<<16) | |
| 4611 | #define SP_YUV_ORDER_UYVY (1<<16) | |
| 4612 | #define SP_YUV_ORDER_YVYU (2<<16) | |
| 4613 | #define SP_YUV_ORDER_VYUY (3<<16) | |
| 76eebda7 | 4614 | #define SP_ROTATE_180 (1<<15) |
| 7f1f3851 | 4615 | #define SP_TILED (1<<10) |
| c14b0485 | 4616 | #define SP_MIRROR (1<<8) /* CHV pipe B */ |
| 921c3b67 VS |
4617 | #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) |
| 4618 | #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) | |
| 4619 | #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) | |
| 4620 | #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) | |
| 4621 | #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) | |
| 4622 | #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) | |
| 4623 | #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) | |
| 4624 | #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) | |
| 4625 | #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) | |
| 4626 | #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) | |
| c14b0485 | 4627 | #define SP_CONST_ALPHA_ENABLE (1<<31) |
| 921c3b67 VS |
4628 | #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) |
| 4629 | ||
| 4630 | #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) | |
| 4631 | #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) | |
| 4632 | #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) | |
| 4633 | #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) | |
| 4634 | #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) | |
| 4635 | #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) | |
| 4636 | #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) | |
| 4637 | #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) | |
| 4638 | #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) | |
| 4639 | #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) | |
| 4640 | #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) | |
| 4641 | #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) | |
| 7f1f3851 JB |
4642 | |
| 4643 | #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) | |
| 4644 | #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) | |
| 4645 | #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) | |
| 4646 | #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) | |
| 4647 | #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) | |
| 4648 | #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) | |
| 4649 | #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) | |
| 4650 | #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) | |
| 4651 | #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) | |
| 4652 | #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) | |
| 4653 | #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) | |
| 4654 | #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) | |
| 4655 | ||
| 6ca2aeb2 VS |
4656 | /* |
| 4657 | * CHV pipe B sprite CSC | |
| 4658 | * | |
| 4659 | * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| | |
| 4660 | * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| | |
| 4661 | * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| | |
| 4662 | */ | |
| 4663 | #define SPCSCYGOFF(sprite) (VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000) | |
| 4664 | #define SPCSCCBOFF(sprite) (VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000) | |
| 4665 | #define SPCSCCROFF(sprite) (VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000) | |
| 4666 | #define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ | |
| 4667 | #define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ | |
| 4668 | ||
| 4669 | #define SPCSCC01(sprite) (VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000) | |
| 4670 | #define SPCSCC23(sprite) (VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000) | |
| 4671 | #define SPCSCC45(sprite) (VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000) | |
| 4672 | #define SPCSCC67(sprite) (VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000) | |
| 4673 | #define SPCSCC8(sprite) (VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000) | |
| 4674 | #define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ | |
| 4675 | #define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ | |
| 4676 | ||
| 4677 | #define SPCSCYGICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000) | |
| 4678 | #define SPCSCCBICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000) | |
| 4679 | #define SPCSCCRICLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000) | |
| 4680 | #define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ | |
| 4681 | #define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ | |
| 4682 | ||
| 4683 | #define SPCSCYGOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000) | |
| 4684 | #define SPCSCCBOCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000) | |
| 4685 | #define SPCSCCROCLAMP(sprite) (VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000) | |
| 4686 | #define SPCSC_OMAX(x) ((x) << 16) /* u10 */ | |
| 4687 | #define SPCSC_OMIN(x) ((x) << 0) /* u10 */ | |
| 4688 | ||
| 70d21f0e DL |
4689 | /* Skylake plane registers */ |
| 4690 | ||
| 4691 | #define _PLANE_CTL_1_A 0x70180 | |
| 4692 | #define _PLANE_CTL_2_A 0x70280 | |
| 4693 | #define _PLANE_CTL_3_A 0x70380 | |
| 4694 | #define PLANE_CTL_ENABLE (1 << 31) | |
| 4695 | #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) | |
| 4696 | #define PLANE_CTL_FORMAT_MASK (0xf << 24) | |
| 4697 | #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24) | |
| 4698 | #define PLANE_CTL_FORMAT_NV12 ( 1 << 24) | |
| 4699 | #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24) | |
| 4700 | #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24) | |
| 4701 | #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24) | |
| 4702 | #define PLANE_CTL_FORMAT_AYUV ( 8 << 24) | |
| 4703 | #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) | |
| 4704 | #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) | |
| 4705 | #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) | |
| dc2a41b4 DL |
4706 | #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) |
| 4707 | #define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) | |
| 4708 | #define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) | |
| 70d21f0e DL |
4709 | #define PLANE_CTL_ORDER_BGRX (0 << 20) |
| 4710 | #define PLANE_CTL_ORDER_RGBX (1 << 20) | |
| 4711 | #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) | |
| 4712 | #define PLANE_CTL_YUV422_YUYV ( 0 << 16) | |
| 4713 | #define PLANE_CTL_YUV422_UYVY ( 1 << 16) | |
| 4714 | #define PLANE_CTL_YUV422_YVYU ( 2 << 16) | |
| 4715 | #define PLANE_CTL_YUV422_VYUY ( 3 << 16) | |
| 4716 | #define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15) | |
| 4717 | #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) | |
| 4718 | #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) | |
| 4719 | #define PLANE_CTL_TILED_MASK (0x7 << 10) | |
| 4720 | #define PLANE_CTL_TILED_LINEAR ( 0 << 10) | |
| 4721 | #define PLANE_CTL_TILED_X ( 1 << 10) | |
| 4722 | #define PLANE_CTL_TILED_Y ( 4 << 10) | |
| 4723 | #define PLANE_CTL_TILED_YF ( 5 << 10) | |
| 4724 | #define PLANE_CTL_ALPHA_MASK (0x3 << 4) | |
| 4725 | #define PLANE_CTL_ALPHA_DISABLE ( 0 << 4) | |
| 4726 | #define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4) | |
| 4727 | #define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4) | |
| 1447dde0 SJ |
4728 | #define PLANE_CTL_ROTATE_MASK 0x3 |
| 4729 | #define PLANE_CTL_ROTATE_0 0x0 | |
| 4730 | #define PLANE_CTL_ROTATE_180 0x2 | |
| 70d21f0e DL |
4731 | #define _PLANE_STRIDE_1_A 0x70188 |
| 4732 | #define _PLANE_STRIDE_2_A 0x70288 | |
| 4733 | #define _PLANE_STRIDE_3_A 0x70388 | |
| 4734 | #define _PLANE_POS_1_A 0x7018c | |
| 4735 | #define _PLANE_POS_2_A 0x7028c | |
| 4736 | #define _PLANE_POS_3_A 0x7038c | |
| 4737 | #define _PLANE_SIZE_1_A 0x70190 | |
| 4738 | #define _PLANE_SIZE_2_A 0x70290 | |
| 4739 | #define _PLANE_SIZE_3_A 0x70390 | |
| 4740 | #define _PLANE_SURF_1_A 0x7019c | |
| 4741 | #define _PLANE_SURF_2_A 0x7029c | |
| 4742 | #define _PLANE_SURF_3_A 0x7039c | |
| 4743 | #define _PLANE_OFFSET_1_A 0x701a4 | |
| 4744 | #define _PLANE_OFFSET_2_A 0x702a4 | |
| 4745 | #define _PLANE_OFFSET_3_A 0x703a4 | |
| dc2a41b4 DL |
4746 | #define _PLANE_KEYVAL_1_A 0x70194 |
| 4747 | #define _PLANE_KEYVAL_2_A 0x70294 | |
| 4748 | #define _PLANE_KEYMSK_1_A 0x70198 | |
| 4749 | #define _PLANE_KEYMSK_2_A 0x70298 | |
| 4750 | #define _PLANE_KEYMAX_1_A 0x701a0 | |
| 4751 | #define _PLANE_KEYMAX_2_A 0x702a0 | |
| 8211bd5b DL |
4752 | #define _PLANE_BUF_CFG_1_A 0x7027c |
| 4753 | #define _PLANE_BUF_CFG_2_A 0x7037c | |
| 70d21f0e DL |
4754 | |
| 4755 | #define _PLANE_CTL_1_B 0x71180 | |
| 4756 | #define _PLANE_CTL_2_B 0x71280 | |
| 4757 | #define _PLANE_CTL_3_B 0x71380 | |
| 4758 | #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) | |
| 4759 | #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) | |
| 4760 | #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) | |
| 4761 | #define PLANE_CTL(pipe, plane) \ | |
| 4762 | _PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) | |
| 4763 | ||
| 4764 | #define _PLANE_STRIDE_1_B 0x71188 | |
| 4765 | #define _PLANE_STRIDE_2_B 0x71288 | |
| 4766 | #define _PLANE_STRIDE_3_B 0x71388 | |
| 4767 | #define _PLANE_STRIDE_1(pipe) \ | |
| 4768 | _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) | |
| 4769 | #define _PLANE_STRIDE_2(pipe) \ | |
| 4770 | _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) | |
| 4771 | #define _PLANE_STRIDE_3(pipe) \ | |
| 4772 | _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) | |
| 4773 | #define PLANE_STRIDE(pipe, plane) \ | |
| 4774 | _PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) | |
| 4775 | ||
| 4776 | #define _PLANE_POS_1_B 0x7118c | |
| 4777 | #define _PLANE_POS_2_B 0x7128c | |
| 4778 | #define _PLANE_POS_3_B 0x7138c | |
| 4779 | #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) | |
| 4780 | #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) | |
| 4781 | #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) | |
| 4782 | #define PLANE_POS(pipe, plane) \ | |
| 4783 | _PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) | |
| 4784 | ||
| 4785 | #define _PLANE_SIZE_1_B 0x71190 | |
| 4786 | #define _PLANE_SIZE_2_B 0x71290 | |
| 4787 | #define _PLANE_SIZE_3_B 0x71390 | |
| 4788 | #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) | |
| 4789 | #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) | |
| 4790 | #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) | |
| 4791 | #define PLANE_SIZE(pipe, plane) \ | |
| 4792 | _PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) | |
| 4793 | ||
| 4794 | #define _PLANE_SURF_1_B 0x7119c | |
| 4795 | #define _PLANE_SURF_2_B 0x7129c | |
| 4796 | #define _PLANE_SURF_3_B 0x7139c | |
| 4797 | #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) | |
| 4798 | #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) | |
| 4799 | #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) | |
| 4800 | #define PLANE_SURF(pipe, plane) \ | |
| 4801 | _PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) | |
| 4802 | ||
| 4803 | #define _PLANE_OFFSET_1_B 0x711a4 | |
| 4804 | #define _PLANE_OFFSET_2_B 0x712a4 | |
| 4805 | #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) | |
| 4806 | #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) | |
| 4807 | #define PLANE_OFFSET(pipe, plane) \ | |
| 4808 | _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) | |
| 4809 | ||
| dc2a41b4 DL |
4810 | #define _PLANE_KEYVAL_1_B 0x71194 |
| 4811 | #define _PLANE_KEYVAL_2_B 0x71294 | |
| 4812 | #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) | |
| 4813 | #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) | |
| 4814 | #define PLANE_KEYVAL(pipe, plane) \ | |
| 4815 | _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) | |
| 4816 | ||
| 4817 | #define _PLANE_KEYMSK_1_B 0x71198 | |
| 4818 | #define _PLANE_KEYMSK_2_B 0x71298 | |
| 4819 | #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) | |
| 4820 | #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) | |
| 4821 | #define PLANE_KEYMSK(pipe, plane) \ | |
| 4822 | _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) | |
| 4823 | ||
| 4824 | #define _PLANE_KEYMAX_1_B 0x711a0 | |
| 4825 | #define _PLANE_KEYMAX_2_B 0x712a0 | |
| 4826 | #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) | |
| 4827 | #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) | |
| 4828 | #define PLANE_KEYMAX(pipe, plane) \ | |
| 4829 | _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) | |
| 4830 | ||
| 8211bd5b DL |
4831 | #define _PLANE_BUF_CFG_1_B 0x7127c |
| 4832 | #define _PLANE_BUF_CFG_2_B 0x7137c | |
| 4833 | #define _PLANE_BUF_CFG_1(pipe) \ | |
| 4834 | _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) | |
| 4835 | #define _PLANE_BUF_CFG_2(pipe) \ | |
| 4836 | _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) | |
| 4837 | #define PLANE_BUF_CFG(pipe, plane) \ | |
| 4838 | _PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) | |
| 4839 | ||
| 4840 | /* SKL new cursor registers */ | |
| 4841 | #define _CUR_BUF_CFG_A 0x7017c | |
| 4842 | #define _CUR_BUF_CFG_B 0x7117c | |
| 4843 | #define CUR_BUF_CFG(pipe) _PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) | |
| 4844 | ||
| 585fb111 JB |
4845 | /* VBIOS regs */ |
| 4846 | #define VGACNTRL 0x71400 | |
| 4847 | # define VGA_DISP_DISABLE (1 << 31) | |
| 4848 | # define VGA_2X_MODE (1 << 30) | |
| 4849 | # define VGA_PIPE_B_SELECT (1 << 29) | |
| 4850 | ||
| 766aa1c4 VS |
4851 | #define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) |
| 4852 | ||
| f2b115e6 | 4853 | /* Ironlake */ |
| b9055052 ZW |
4854 | |
| 4855 | #define CPU_VGACNTRL 0x41000 | |
| 4856 | ||
| 4857 | #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 | |
| 4858 | #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) | |
| 4859 | #define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) | |
| 4860 | #define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) | |
| 4861 | #define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) | |
| 4862 | #define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) | |
| 4863 | #define DIGITAL_PORTA_NO_DETECT (0 << 0) | |
| 4864 | #define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) | |
| 4865 | #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) | |
| 4866 | ||
| 4867 | /* refresh rate hardware control */ | |
| 4868 | #define RR_HW_CTL 0x45300 | |
| 4869 | #define RR_HW_LOW_POWER_FRAMES_MASK 0xff | |
| 4870 | #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 | |
| 4871 | ||
| 4872 | #define FDI_PLL_BIOS_0 0x46000 | |
| 021357ac | 4873 | #define FDI_PLL_FB_CLOCK_MASK 0xff |
| b9055052 ZW |
4874 | #define FDI_PLL_BIOS_1 0x46004 |
| 4875 | #define FDI_PLL_BIOS_2 0x46008 | |
| 4876 | #define DISPLAY_PORT_PLL_BIOS_0 0x4600c | |
| 4877 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 | |
| 4878 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 | |
| 4879 | ||
| 8956c8bb EA |
4880 | #define PCH_3DCGDIS0 0x46020 |
| 4881 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) | |
| 4882 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | |
| 4883 | ||
| 06f37751 EA |
4884 | #define PCH_3DCGDIS1 0x46024 |
| 4885 | # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
| 4886 | ||
| b9055052 ZW |
4887 | #define FDI_PLL_FREQ_CTL 0x46030 |
| 4888 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) | |
| 4889 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 | |
| 4890 | #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff | |
| 4891 | ||
| 4892 | ||
| a57c774a | 4893 | #define _PIPEA_DATA_M1 0x60030 |
| 5eddb70b | 4894 | #define PIPE_DATA_M1_OFFSET 0 |
| a57c774a | 4895 | #define _PIPEA_DATA_N1 0x60034 |
| 5eddb70b | 4896 | #define PIPE_DATA_N1_OFFSET 0 |
| b9055052 | 4897 | |
| a57c774a | 4898 | #define _PIPEA_DATA_M2 0x60038 |
| 5eddb70b | 4899 | #define PIPE_DATA_M2_OFFSET 0 |
| a57c774a | 4900 | #define _PIPEA_DATA_N2 0x6003c |
| 5eddb70b | 4901 | #define PIPE_DATA_N2_OFFSET 0 |
| b9055052 | 4902 | |
| a57c774a | 4903 | #define _PIPEA_LINK_M1 0x60040 |
| 5eddb70b | 4904 | #define PIPE_LINK_M1_OFFSET 0 |
| a57c774a | 4905 | #define _PIPEA_LINK_N1 0x60044 |
| 5eddb70b | 4906 | #define PIPE_LINK_N1_OFFSET 0 |
| b9055052 | 4907 | |
| a57c774a | 4908 | #define _PIPEA_LINK_M2 0x60048 |
| 5eddb70b | 4909 | #define PIPE_LINK_M2_OFFSET 0 |
| a57c774a | 4910 | #define _PIPEA_LINK_N2 0x6004c |
| 5eddb70b | 4911 | #define PIPE_LINK_N2_OFFSET 0 |
| b9055052 ZW |
4912 | |
| 4913 | /* PIPEB timing regs are same start from 0x61000 */ | |
| 4914 | ||
| a57c774a AK |
4915 | #define _PIPEB_DATA_M1 0x61030 |
| 4916 | #define _PIPEB_DATA_N1 0x61034 | |
| 4917 | #define _PIPEB_DATA_M2 0x61038 | |
| 4918 | #define _PIPEB_DATA_N2 0x6103c | |
| 4919 | #define _PIPEB_LINK_M1 0x61040 | |
| 4920 | #define _PIPEB_LINK_N1 0x61044 | |
| 4921 | #define _PIPEB_LINK_M2 0x61048 | |
| 4922 | #define _PIPEB_LINK_N2 0x6104c | |
| 4923 | ||
| 4924 | #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) | |
| 4925 | #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) | |
| 4926 | #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) | |
| 4927 | #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) | |
| 4928 | #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) | |
| 4929 | #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) | |
| 4930 | #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) | |
| 4931 | #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) | |
| b9055052 ZW |
4932 | |
| 4933 | /* CPU panel fitter */ | |
| 9db4a9c7 JB |
4934 | /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ |
| 4935 | #define _PFA_CTL_1 0x68080 | |
| 4936 | #define _PFB_CTL_1 0x68880 | |
| b9055052 | 4937 | #define PF_ENABLE (1<<31) |
| 13888d78 PZ |
4938 | #define PF_PIPE_SEL_MASK_IVB (3<<29) |
| 4939 | #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) | |
| b1f60b70 ZW |
4940 | #define PF_FILTER_MASK (3<<23) |
| 4941 | #define PF_FILTER_PROGRAMMED (0<<23) | |
| 4942 | #define PF_FILTER_MED_3x3 (1<<23) | |
| 4943 | #define PF_FILTER_EDGE_ENHANCE (2<<23) | |
| 4944 | #define PF_FILTER_EDGE_SOFTEN (3<<23) | |
| 9db4a9c7 JB |
4945 | #define _PFA_WIN_SZ 0x68074 |
| 4946 | #define _PFB_WIN_SZ 0x68874 | |
| 4947 | #define _PFA_WIN_POS 0x68070 | |
| 4948 | #define _PFB_WIN_POS 0x68870 | |
| 4949 | #define _PFA_VSCALE 0x68084 | |
| 4950 | #define _PFB_VSCALE 0x68884 | |
| 4951 | #define _PFA_HSCALE 0x68090 | |
| 4952 | #define _PFB_HSCALE 0x68890 | |
| 4953 | ||
| 4954 | #define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) | |
| 4955 | #define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) | |
| 4956 | #define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) | |
| 4957 | #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) | |
| 4958 | #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) | |
| b9055052 | 4959 | |
| bd2e244f JB |
4960 | #define _PSA_CTL 0x68180 |
| 4961 | #define _PSB_CTL 0x68980 | |
| 4962 | #define PS_ENABLE (1<<31) | |
| 4963 | #define _PSA_WIN_SZ 0x68174 | |
| 4964 | #define _PSB_WIN_SZ 0x68974 | |
| 4965 | #define _PSA_WIN_POS 0x68170 | |
| 4966 | #define _PSB_WIN_POS 0x68970 | |
| 4967 | ||
| 4968 | #define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL) | |
| 4969 | #define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) | |
| 4970 | #define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) | |
| 4971 | ||
| b9055052 | 4972 | /* legacy palette */ |
| 9db4a9c7 JB |
4973 | #define _LGC_PALETTE_A 0x4a000 |
| 4974 | #define _LGC_PALETTE_B 0x4a800 | |
| 4975 | #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) | |
| b9055052 | 4976 | |
| 42db64ef PZ |
4977 | #define _GAMMA_MODE_A 0x4a480 |
| 4978 | #define _GAMMA_MODE_B 0x4ac80 | |
| 4979 | #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) | |
| 4980 | #define GAMMA_MODE_MODE_MASK (3 << 0) | |
| 3eff4faa DV |
4981 | #define GAMMA_MODE_MODE_8BIT (0 << 0) |
| 4982 | #define GAMMA_MODE_MODE_10BIT (1 << 0) | |
| 4983 | #define GAMMA_MODE_MODE_12BIT (2 << 0) | |
| 42db64ef PZ |
4984 | #define GAMMA_MODE_MODE_SPLIT (3 << 0) |
| 4985 | ||
| b9055052 ZW |
4986 | /* interrupts */ |
| 4987 | #define DE_MASTER_IRQ_CONTROL (1 << 31) | |
| 4988 | #define DE_SPRITEB_FLIP_DONE (1 << 29) | |
| 4989 | #define DE_SPRITEA_FLIP_DONE (1 << 28) | |
| 4990 | #define DE_PLANEB_FLIP_DONE (1 << 27) | |
| 4991 | #define DE_PLANEA_FLIP_DONE (1 << 26) | |
| 40da17c2 | 4992 | #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) |
| b9055052 ZW |
4993 | #define DE_PCU_EVENT (1 << 25) |
| 4994 | #define DE_GTT_FAULT (1 << 24) | |
| 4995 | #define DE_POISON (1 << 23) | |
| 4996 | #define DE_PERFORM_COUNTER (1 << 22) | |
| 4997 | #define DE_PCH_EVENT (1 << 21) | |
| 4998 | #define DE_AUX_CHANNEL_A (1 << 20) | |
| 4999 | #define DE_DP_A_HOTPLUG (1 << 19) | |
| 5000 | #define DE_GSE (1 << 18) | |
| 5001 | #define DE_PIPEB_VBLANK (1 << 15) | |
| 5002 | #define DE_PIPEB_EVEN_FIELD (1 << 14) | |
| 5003 | #define DE_PIPEB_ODD_FIELD (1 << 13) | |
| 5004 | #define DE_PIPEB_LINE_COMPARE (1 << 12) | |
| 5005 | #define DE_PIPEB_VSYNC (1 << 11) | |
| 5b3a856b | 5006 | #define DE_PIPEB_CRC_DONE (1 << 10) |
| b9055052 ZW |
5007 | #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) |
| 5008 | #define DE_PIPEA_VBLANK (1 << 7) | |
| 40da17c2 | 5009 | #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) |
| b9055052 ZW |
5010 | #define DE_PIPEA_EVEN_FIELD (1 << 6) |
| 5011 | #define DE_PIPEA_ODD_FIELD (1 << 5) | |
| 5012 | #define DE_PIPEA_LINE_COMPARE (1 << 4) | |
| 5013 | #define DE_PIPEA_VSYNC (1 << 3) | |
| 5b3a856b | 5014 | #define DE_PIPEA_CRC_DONE (1 << 2) |
| 40da17c2 | 5015 | #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) |
| b9055052 | 5016 | #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) |
| 40da17c2 | 5017 | #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) |
| b9055052 | 5018 | |
| b1f14ad0 | 5019 | /* More Ivybridge lolz */ |
| 8664281b | 5020 | #define DE_ERR_INT_IVB (1<<30) |
| b1f14ad0 JB |
5021 | #define DE_GSE_IVB (1<<29) |
| 5022 | #define DE_PCH_EVENT_IVB (1<<28) | |
| 5023 | #define DE_DP_A_HOTPLUG_IVB (1<<27) | |
| 5024 | #define DE_AUX_CHANNEL_A_IVB (1<<26) | |
| b615b57a CW |
5025 | #define DE_SPRITEC_FLIP_DONE_IVB (1<<14) |
| 5026 | #define DE_PLANEC_FLIP_DONE_IVB (1<<13) | |
| 5027 | #define DE_PIPEC_VBLANK_IVB (1<<10) | |
| b1f14ad0 | 5028 | #define DE_SPRITEB_FLIP_DONE_IVB (1<<9) |
| b1f14ad0 | 5029 | #define DE_PLANEB_FLIP_DONE_IVB (1<<8) |
| b1f14ad0 | 5030 | #define DE_PIPEB_VBLANK_IVB (1<<5) |
| b615b57a CW |
5031 | #define DE_SPRITEA_FLIP_DONE_IVB (1<<4) |
| 5032 | #define DE_PLANEA_FLIP_DONE_IVB (1<<3) | |
| 40da17c2 | 5033 | #define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) |
| b1f14ad0 | 5034 | #define DE_PIPEA_VBLANK_IVB (1<<0) |
| b518421f PZ |
5035 | #define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) |
| 5036 | ||
| 7eea1ddf JB |
5037 | #define VLV_MASTER_IER 0x4400c /* Gunit master IER */ |
| 5038 | #define MASTER_INTERRUPT_ENABLE (1<<31) | |
| 5039 | ||
| b9055052 ZW |
5040 | #define DEISR 0x44000 |
| 5041 | #define DEIMR 0x44004 | |
| 5042 | #define DEIIR 0x44008 | |
| 5043 | #define DEIER 0x4400c | |
| 5044 | ||
| b9055052 ZW |
5045 | #define GTISR 0x44010 |
| 5046 | #define GTIMR 0x44014 | |
| 5047 | #define GTIIR 0x44018 | |
| 5048 | #define GTIER 0x4401c | |
| 5049 | ||
| abd58f01 BW |
5050 | #define GEN8_MASTER_IRQ 0x44200 |
| 5051 | #define GEN8_MASTER_IRQ_CONTROL (1<<31) | |
| 5052 | #define GEN8_PCU_IRQ (1<<30) | |
| 5053 | #define GEN8_DE_PCH_IRQ (1<<23) | |
| 5054 | #define GEN8_DE_MISC_IRQ (1<<22) | |
| 5055 | #define GEN8_DE_PORT_IRQ (1<<20) | |
| 5056 | #define GEN8_DE_PIPE_C_IRQ (1<<18) | |
| 5057 | #define GEN8_DE_PIPE_B_IRQ (1<<17) | |
| 5058 | #define GEN8_DE_PIPE_A_IRQ (1<<16) | |
| c42664cc | 5059 | #define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) |
| abd58f01 | 5060 | #define GEN8_GT_VECS_IRQ (1<<6) |
| 0961021a | 5061 | #define GEN8_GT_PM_IRQ (1<<4) |
| abd58f01 BW |
5062 | #define GEN8_GT_VCS2_IRQ (1<<3) |
| 5063 | #define GEN8_GT_VCS1_IRQ (1<<2) | |
| 5064 | #define GEN8_GT_BCS_IRQ (1<<1) | |
| 5065 | #define GEN8_GT_RCS_IRQ (1<<0) | |
| abd58f01 BW |
5066 | |
| 5067 | #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) | |
| 5068 | #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) | |
| 5069 | #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) | |
| 5070 | #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) | |
| 5071 | ||
| 5072 | #define GEN8_BCS_IRQ_SHIFT 16 | |
| 5073 | #define GEN8_RCS_IRQ_SHIFT 0 | |
| 5074 | #define GEN8_VCS2_IRQ_SHIFT 16 | |
| 5075 | #define GEN8_VCS1_IRQ_SHIFT 0 | |
| 5076 | #define GEN8_VECS_IRQ_SHIFT 0 | |
| 5077 | ||
| 5078 | #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) | |
| 5079 | #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) | |
| 5080 | #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) | |
| 5081 | #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) | |
| 38d83c96 | 5082 | #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) |
| abd58f01 BW |
5083 | #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) |
| 5084 | #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) | |
| 5085 | #define GEN8_PIPE_CURSOR_FAULT (1 << 10) | |
| 5086 | #define GEN8_PIPE_SPRITE_FAULT (1 << 9) | |
| 5087 | #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) | |
| 5088 | #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) | |
| d0e1f1cb | 5089 | #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) |
| abd58f01 BW |
5090 | #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) |
| 5091 | #define GEN8_PIPE_VSYNC (1 << 1) | |
| 5092 | #define GEN8_PIPE_VBLANK (1 << 0) | |
| 770de83d DL |
5093 | #define GEN9_PIPE_CURSOR_FAULT (1 << 11) |
| 5094 | #define GEN9_PIPE_PLANE3_FAULT (1 << 9) | |
| 5095 | #define GEN9_PIPE_PLANE2_FAULT (1 << 8) | |
| 5096 | #define GEN9_PIPE_PLANE1_FAULT (1 << 7) | |
| 5097 | #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) | |
| 5098 | #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) | |
| 5099 | #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) | |
| 5100 | #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p)) | |
| 30100f2b DV |
5101 | #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ |
| 5102 | (GEN8_PIPE_CURSOR_FAULT | \ | |
| 5103 | GEN8_PIPE_SPRITE_FAULT | \ | |
| 5104 | GEN8_PIPE_PRIMARY_FAULT) | |
| 770de83d DL |
5105 | #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ |
| 5106 | (GEN9_PIPE_CURSOR_FAULT | \ | |
| 5107 | GEN9_PIPE_PLANE3_FAULT | \ | |
| 5108 | GEN9_PIPE_PLANE2_FAULT | \ | |
| 5109 | GEN9_PIPE_PLANE1_FAULT) | |
| abd58f01 BW |
5110 | |
| 5111 | #define GEN8_DE_PORT_ISR 0x44440 | |
| 5112 | #define GEN8_DE_PORT_IMR 0x44444 | |
| 5113 | #define GEN8_DE_PORT_IIR 0x44448 | |
| 5114 | #define GEN8_DE_PORT_IER 0x4444c | |
| 6d766f02 | 5115 | #define GEN8_PORT_DP_A_HOTPLUG (1 << 3) |
| 88e04703 JB |
5116 | #define GEN9_AUX_CHANNEL_D (1 << 27) |
| 5117 | #define GEN9_AUX_CHANNEL_C (1 << 26) | |
| 5118 | #define GEN9_AUX_CHANNEL_B (1 << 25) | |
| 6d766f02 | 5119 | #define GEN8_AUX_CHANNEL_A (1 << 0) |
| abd58f01 BW |
5120 | |
| 5121 | #define GEN8_DE_MISC_ISR 0x44460 | |
| 5122 | #define GEN8_DE_MISC_IMR 0x44464 | |
| 5123 | #define GEN8_DE_MISC_IIR 0x44468 | |
| 5124 | #define GEN8_DE_MISC_IER 0x4446c | |
| 5125 | #define GEN8_DE_MISC_GSE (1 << 27) | |
| 5126 | ||
| 5127 | #define GEN8_PCU_ISR 0x444e0 | |
| 5128 | #define GEN8_PCU_IMR 0x444e4 | |
| 5129 | #define GEN8_PCU_IIR 0x444e8 | |
| 5130 | #define GEN8_PCU_IER 0x444ec | |
| 5131 | ||
| 7f8a8569 | 5132 | #define ILK_DISPLAY_CHICKEN2 0x42004 |
| 67e92af0 EA |
5133 | /* Required on all Ironlake and Sandybridge according to the B-Spec. */ |
| 5134 | #define ILK_ELPIN_409_SELECT (1 << 25) | |
| 7f8a8569 ZW |
5135 | #define ILK_DPARB_GATE (1<<22) |
| 5136 | #define ILK_VSDPFD_FULL (1<<21) | |
| e3589908 DL |
5137 | #define FUSE_STRAP 0x42014 |
| 5138 | #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) | |
| 5139 | #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) | |
| 5140 | #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) | |
| 5141 | #define ILK_HDCP_DISABLE (1 << 25) | |
| 5142 | #define ILK_eDP_A_DISABLE (1 << 24) | |
| 5143 | #define HSW_CDCLK_LIMIT (1 << 24) | |
| 5144 | #define ILK_DESKTOP (1 << 23) | |
| 231e54f6 DL |
5145 | |
| 5146 | #define ILK_DSPCLK_GATE_D 0x42020 | |
| 5147 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) | |
| 5148 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) | |
| 5149 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
| 5150 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) | |
| 5151 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) | |
| 7f8a8569 | 5152 | |
| 116ac8d2 EA |
5153 | #define IVB_CHICKEN3 0x4200c |
| 5154 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) | |
| 5155 | # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) | |
| 5156 | ||
| 90a88643 | 5157 | #define CHICKEN_PAR1_1 0x42080 |
| fe4ab3ce | 5158 | #define DPA_MASK_VBLANK_SRD (1 << 15) |
| 90a88643 PZ |
5159 | #define FORCE_ARB_IDLE_PLANES (1 << 14) |
| 5160 | ||
| fe4ab3ce BW |
5161 | #define _CHICKEN_PIPESL_1_A 0x420b0 |
| 5162 | #define _CHICKEN_PIPESL_1_B 0x420b4 | |
| 8f670bb1 VS |
5163 | #define HSW_FBCQ_DIS (1 << 22) |
| 5164 | #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) | |
| fe4ab3ce BW |
5165 | #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) |
| 5166 | ||
| 553bd149 ZW |
5167 | #define DISP_ARB_CTL 0x45000 |
| 5168 | #define DISP_TILE_SURFACE_SWIZZLING (1<<13) | |
| 7f8a8569 | 5169 | #define DISP_FBC_WM_DIS (1<<15) |
| ac9545fd VS |
5170 | #define DISP_ARB_CTL2 0x45004 |
| 5171 | #define DISP_DATA_PARTITION_5_6 (1<<6) | |
| 88a2b2a3 BW |
5172 | #define GEN7_MSG_CTL 0x45010 |
| 5173 | #define WAIT_FOR_PCH_RESET_ACK (1<<1) | |
| 5174 | #define WAIT_FOR_PCH_FLR_ACK (1<<0) | |
| 6ba844b0 DV |
5175 | #define HSW_NDE_RSTWRN_OPT 0x46408 |
| 5176 | #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) | |
| 553bd149 | 5177 | |
| e4e0c058 | 5178 | /* GEN7 chicken */ |
| d71de14d KG |
5179 | #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 |
| 5180 | # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) | |
| a75f3628 BW |
5181 | #define COMMON_SLICE_CHICKEN2 0x7014 |
| 5182 | # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) | |
| d71de14d | 5183 | |
| 031994ee VS |
5184 | #define GEN7_L3SQCREG1 0xB010 |
| 5185 | #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 | |
| 5186 | ||
| e4e0c058 | 5187 | #define GEN7_L3CNTLREG1 0xB01C |
| 1af8452f | 5188 | #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C |
| d0cf5ead | 5189 | #define GEN7_L3AGDIS (1<<19) |
| c9224faa BV |
5190 | #define GEN7_L3CNTLREG2 0xB020 |
| 5191 | #define GEN7_L3CNTLREG3 0xB024 | |
| e4e0c058 ED |
5192 | |
| 5193 | #define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 | |
| 5194 | #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 | |
| 5195 | ||
| 61939d97 JB |
5196 | #define GEN7_L3SQCREG4 0xb034 |
| 5197 | #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) | |
| 5198 | ||
| 63801f21 BW |
5199 | /* GEN8 chicken */ |
| 5200 | #define HDC_CHICKEN0 0x7300 | |
| 5201 | #define HDC_FORCE_NON_COHERENT (1<<4) | |
| 95289009 | 5202 | #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) |
| da09654d | 5203 | #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) |
| 63801f21 | 5204 | |
| db099c8f ED |
5205 | /* WaCatErrorRejectionIssue */ |
| 5206 | #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 | |
| 5207 | #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) | |
| 5208 | ||
| f3fc4884 FJ |
5209 | #define HSW_SCRATCH1 0xb038 |
| 5210 | #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) | |
| 5211 | ||
| b9055052 ZW |
5212 | /* PCH */ |
| 5213 | ||
| 23e81d69 | 5214 | /* south display engine interrupt: IBX */ |
| 776ad806 JB |
5215 | #define SDE_AUDIO_POWER_D (1 << 27) |
| 5216 | #define SDE_AUDIO_POWER_C (1 << 26) | |
| 5217 | #define SDE_AUDIO_POWER_B (1 << 25) | |
| 5218 | #define SDE_AUDIO_POWER_SHIFT (25) | |
| 5219 | #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) | |
| 5220 | #define SDE_GMBUS (1 << 24) | |
| 5221 | #define SDE_AUDIO_HDCP_TRANSB (1 << 23) | |
| 5222 | #define SDE_AUDIO_HDCP_TRANSA (1 << 22) | |
| 5223 | #define SDE_AUDIO_HDCP_MASK (3 << 22) | |
| 5224 | #define SDE_AUDIO_TRANSB (1 << 21) | |
| 5225 | #define SDE_AUDIO_TRANSA (1 << 20) | |
| 5226 | #define SDE_AUDIO_TRANS_MASK (3 << 20) | |
| 5227 | #define SDE_POISON (1 << 19) | |
| 5228 | /* 18 reserved */ | |
| 5229 | #define SDE_FDI_RXB (1 << 17) | |
| 5230 | #define SDE_FDI_RXA (1 << 16) | |
| 5231 | #define SDE_FDI_MASK (3 << 16) | |
| 5232 | #define SDE_AUXD (1 << 15) | |
| 5233 | #define SDE_AUXC (1 << 14) | |
| 5234 | #define SDE_AUXB (1 << 13) | |
| 5235 | #define SDE_AUX_MASK (7 << 13) | |
| 5236 | /* 12 reserved */ | |
| b9055052 ZW |
5237 | #define SDE_CRT_HOTPLUG (1 << 11) |
| 5238 | #define SDE_PORTD_HOTPLUG (1 << 10) | |
| 5239 | #define SDE_PORTC_HOTPLUG (1 << 9) | |
| 5240 | #define SDE_PORTB_HOTPLUG (1 << 8) | |
| 5241 | #define SDE_SDVOB_HOTPLUG (1 << 6) | |
| e5868a31 EE |
5242 | #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ |
| 5243 | SDE_SDVOB_HOTPLUG | \ | |
| 5244 | SDE_PORTB_HOTPLUG | \ | |
| 5245 | SDE_PORTC_HOTPLUG | \ | |
| 5246 | SDE_PORTD_HOTPLUG) | |
| 776ad806 JB |
5247 | #define SDE_TRANSB_CRC_DONE (1 << 5) |
| 5248 | #define SDE_TRANSB_CRC_ERR (1 << 4) | |
| 5249 | #define SDE_TRANSB_FIFO_UNDER (1 << 3) | |
| 5250 | #define SDE_TRANSA_CRC_DONE (1 << 2) | |
| 5251 | #define SDE_TRANSA_CRC_ERR (1 << 1) | |
| 5252 | #define SDE_TRANSA_FIFO_UNDER (1 << 0) | |
| 5253 | #define SDE_TRANS_MASK (0x3f) | |
| 23e81d69 AJ |
5254 | |
| 5255 | /* south display engine interrupt: CPT/PPT */ | |
| 5256 | #define SDE_AUDIO_POWER_D_CPT (1 << 31) | |
| 5257 | #define SDE_AUDIO_POWER_C_CPT (1 << 30) | |
| 5258 | #define SDE_AUDIO_POWER_B_CPT (1 << 29) | |
| 5259 | #define SDE_AUDIO_POWER_SHIFT_CPT 29 | |
| 5260 | #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) | |
| 5261 | #define SDE_AUXD_CPT (1 << 27) | |
| 5262 | #define SDE_AUXC_CPT (1 << 26) | |
| 5263 | #define SDE_AUXB_CPT (1 << 25) | |
| 5264 | #define SDE_AUX_MASK_CPT (7 << 25) | |
| 8db9d77b ZW |
5265 | #define SDE_PORTD_HOTPLUG_CPT (1 << 23) |
| 5266 | #define SDE_PORTC_HOTPLUG_CPT (1 << 22) | |
| 5267 | #define SDE_PORTB_HOTPLUG_CPT (1 << 21) | |
| 23e81d69 | 5268 | #define SDE_CRT_HOTPLUG_CPT (1 << 19) |
| 73c352a2 | 5269 | #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) |
| 2d7b8366 | 5270 | #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ |
| 73c352a2 | 5271 | SDE_SDVOB_HOTPLUG_CPT | \ |
| 2d7b8366 YL |
5272 | SDE_PORTD_HOTPLUG_CPT | \ |
| 5273 | SDE_PORTC_HOTPLUG_CPT | \ | |
| 5274 | SDE_PORTB_HOTPLUG_CPT) | |
| 23e81d69 | 5275 | #define SDE_GMBUS_CPT (1 << 17) |
| 8664281b | 5276 | #define SDE_ERROR_CPT (1 << 16) |
| 23e81d69 AJ |
5277 | #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) |
| 5278 | #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) | |
| 5279 | #define SDE_FDI_RXC_CPT (1 << 8) | |
| 5280 | #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) | |
| 5281 | #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) | |
| 5282 | #define SDE_FDI_RXB_CPT (1 << 4) | |
| 5283 | #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) | |
| 5284 | #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) | |
| 5285 | #define SDE_FDI_RXA_CPT (1 << 0) | |
| 5286 | #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ | |
| 5287 | SDE_AUDIO_CP_REQ_B_CPT | \ | |
| 5288 | SDE_AUDIO_CP_REQ_A_CPT) | |
| 5289 | #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ | |
| 5290 | SDE_AUDIO_CP_CHG_B_CPT | \ | |
| 5291 | SDE_AUDIO_CP_CHG_A_CPT) | |
| 5292 | #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ | |
| 5293 | SDE_FDI_RXB_CPT | \ | |
| 5294 | SDE_FDI_RXA_CPT) | |
| b9055052 ZW |
5295 | |
| 5296 | #define SDEISR 0xc4000 | |
| 5297 | #define SDEIMR 0xc4004 | |
| 5298 | #define SDEIIR 0xc4008 | |
| 5299 | #define SDEIER 0xc400c | |
| 5300 | ||
| 8664281b | 5301 | #define SERR_INT 0xc4040 |
| de032bf4 | 5302 | #define SERR_INT_POISON (1<<31) |
| 8664281b PZ |
5303 | #define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) |
| 5304 | #define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) | |
| 5305 | #define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) | |
| 1dd246fb | 5306 | #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) |
| 8664281b | 5307 | |
| b9055052 | 5308 | /* digital port hotplug */ |
| 7fe0b973 | 5309 | #define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ |
| b9055052 ZW |
5310 | #define PORTD_HOTPLUG_ENABLE (1 << 20) |
| 5311 | #define PORTD_PULSE_DURATION_2ms (0) | |
| 5312 | #define PORTD_PULSE_DURATION_4_5ms (1 << 18) | |
| 5313 | #define PORTD_PULSE_DURATION_6ms (2 << 18) | |
| 5314 | #define PORTD_PULSE_DURATION_100ms (3 << 18) | |
| 7fe0b973 | 5315 | #define PORTD_PULSE_DURATION_MASK (3 << 18) |
| b696519e DL |
5316 | #define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) |
| 5317 | #define PORTD_HOTPLUG_NO_DETECT (0 << 16) | |
| 5318 | #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) | |
| 5319 | #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) | |
| b9055052 ZW |
5320 | #define PORTC_HOTPLUG_ENABLE (1 << 12) |
| 5321 | #define PORTC_PULSE_DURATION_2ms (0) | |
| 5322 | #define PORTC_PULSE_DURATION_4_5ms (1 << 10) | |
| 5323 | #define PORTC_PULSE_DURATION_6ms (2 << 10) | |
| 5324 | #define PORTC_PULSE_DURATION_100ms (3 << 10) | |
| 7fe0b973 | 5325 | #define PORTC_PULSE_DURATION_MASK (3 << 10) |
| b696519e DL |
5326 | #define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) |
| 5327 | #define PORTC_HOTPLUG_NO_DETECT (0 << 8) | |
| 5328 | #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) | |
| 5329 | #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) | |
| b9055052 ZW |
5330 | #define PORTB_HOTPLUG_ENABLE (1 << 4) |
| 5331 | #define PORTB_PULSE_DURATION_2ms (0) | |
| 5332 | #define PORTB_PULSE_DURATION_4_5ms (1 << 2) | |
| 5333 | #define PORTB_PULSE_DURATION_6ms (2 << 2) | |
| 5334 | #define PORTB_PULSE_DURATION_100ms (3 << 2) | |
| 7fe0b973 | 5335 | #define PORTB_PULSE_DURATION_MASK (3 << 2) |
| b696519e DL |
5336 | #define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) |
| 5337 | #define PORTB_HOTPLUG_NO_DETECT (0 << 0) | |
| 5338 | #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) | |
| 5339 | #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) | |
| b9055052 ZW |
5340 | |
| 5341 | #define PCH_GPIOA 0xc5010 | |
| 5342 | #define PCH_GPIOB 0xc5014 | |
| 5343 | #define PCH_GPIOC 0xc5018 | |
| 5344 | #define PCH_GPIOD 0xc501c | |
| 5345 | #define PCH_GPIOE 0xc5020 | |
| 5346 | #define PCH_GPIOF 0xc5024 | |
| 5347 | ||
| f0217c42 EA |
5348 | #define PCH_GMBUS0 0xc5100 |
| 5349 | #define PCH_GMBUS1 0xc5104 | |
| 5350 | #define PCH_GMBUS2 0xc5108 | |
| 5351 | #define PCH_GMBUS3 0xc510c | |
| 5352 | #define PCH_GMBUS4 0xc5110 | |
| 5353 | #define PCH_GMBUS5 0xc5120 | |
| 5354 | ||
| 9db4a9c7 JB |
5355 | #define _PCH_DPLL_A 0xc6014 |
| 5356 | #define _PCH_DPLL_B 0xc6018 | |
| e9a632a5 | 5357 | #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) |
| b9055052 | 5358 | |
| 9db4a9c7 | 5359 | #define _PCH_FPA0 0xc6040 |
| c1858123 | 5360 | #define FP_CB_TUNE (0x3<<22) |
| 9db4a9c7 JB |
5361 | #define _PCH_FPA1 0xc6044 |
| 5362 | #define _PCH_FPB0 0xc6048 | |
| 5363 | #define _PCH_FPB1 0xc604c | |
| e9a632a5 DV |
5364 | #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) |
| 5365 | #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) | |
| b9055052 ZW |
5366 | |
| 5367 | #define PCH_DPLL_TEST 0xc606c | |
| 5368 | ||
| 5369 | #define PCH_DREF_CONTROL 0xC6200 | |
| 5370 | #define DREF_CONTROL_MASK 0x7fc3 | |
| 5371 | #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) | |
| 5372 | #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) | |
| 5373 | #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) | |
| 5374 | #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) | |
| 5375 | #define DREF_SSC_SOURCE_DISABLE (0<<11) | |
| 5376 | #define DREF_SSC_SOURCE_ENABLE (2<<11) | |
| c038e51e | 5377 | #define DREF_SSC_SOURCE_MASK (3<<11) |
| b9055052 ZW |
5378 | #define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) |
| 5379 | #define DREF_NONSPREAD_CK505_ENABLE (1<<9) | |
| 5380 | #define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) | |
| c038e51e | 5381 | #define DREF_NONSPREAD_SOURCE_MASK (3<<9) |
| b9055052 ZW |
5382 | #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) |
| 5383 | #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) | |
| 92f2584a | 5384 | #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) |
| b9055052 ZW |
5385 | #define DREF_SSC4_DOWNSPREAD (0<<6) |
| 5386 | #define DREF_SSC4_CENTERSPREAD (1<<6) | |
| 5387 | #define DREF_SSC1_DISABLE (0<<1) | |
| 5388 | #define DREF_SSC1_ENABLE (1<<1) | |
| 5389 | #define DREF_SSC4_DISABLE (0) | |
| 5390 | #define DREF_SSC4_ENABLE (1) | |
| 5391 | ||
| 5392 | #define PCH_RAWCLK_FREQ 0xc6204 | |
| 5393 | #define FDL_TP1_TIMER_SHIFT 12 | |
| 5394 | #define FDL_TP1_TIMER_MASK (3<<12) | |
| 5395 | #define FDL_TP2_TIMER_SHIFT 10 | |
| 5396 | #define FDL_TP2_TIMER_MASK (3<<10) | |
| 5397 | #define RAWCLK_FREQ_MASK 0x3ff | |
| 5398 | ||
| 5399 | #define PCH_DPLL_TMR_CFG 0xc6208 | |
| 5400 | ||
| 5401 | #define PCH_SSC4_PARMS 0xc6210 | |
| 5402 | #define PCH_SSC4_AUX_PARMS 0xc6214 | |
| 5403 | ||
| 8db9d77b | 5404 | #define PCH_DPLL_SEL 0xc7000 |
| 11887397 DV |
5405 | #define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) |
| 5406 | #define TRANS_DPLLA_SEL(pipe) 0 | |
| 5407 | #define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) | |
| 8db9d77b | 5408 | |
| b9055052 ZW |
5409 | /* transcoder */ |
| 5410 | ||
| 275f01b2 DV |
5411 | #define _PCH_TRANS_HTOTAL_A 0xe0000 |
| 5412 | #define TRANS_HTOTAL_SHIFT 16 | |
| 5413 | #define TRANS_HACTIVE_SHIFT 0 | |
| 5414 | #define _PCH_TRANS_HBLANK_A 0xe0004 | |
| 5415 | #define TRANS_HBLANK_END_SHIFT 16 | |
| 5416 | #define TRANS_HBLANK_START_SHIFT 0 | |
| 5417 | #define _PCH_TRANS_HSYNC_A 0xe0008 | |
| 5418 | #define TRANS_HSYNC_END_SHIFT 16 | |
| 5419 | #define TRANS_HSYNC_START_SHIFT 0 | |
| 5420 | #define _PCH_TRANS_VTOTAL_A 0xe000c | |
| 5421 | #define TRANS_VTOTAL_SHIFT 16 | |
| 5422 | #define TRANS_VACTIVE_SHIFT 0 | |
| 5423 | #define _PCH_TRANS_VBLANK_A 0xe0010 | |
| 5424 | #define TRANS_VBLANK_END_SHIFT 16 | |
| 5425 | #define TRANS_VBLANK_START_SHIFT 0 | |
| 5426 | #define _PCH_TRANS_VSYNC_A 0xe0014 | |
| 5427 | #define TRANS_VSYNC_END_SHIFT 16 | |
| 5428 | #define TRANS_VSYNC_START_SHIFT 0 | |
| 5429 | #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 | |
| b9055052 | 5430 | |
| e3b95f1e DV |
5431 | #define _PCH_TRANSA_DATA_M1 0xe0030 |
| 5432 | #define _PCH_TRANSA_DATA_N1 0xe0034 | |
| 5433 | #define _PCH_TRANSA_DATA_M2 0xe0038 | |
| 5434 | #define _PCH_TRANSA_DATA_N2 0xe003c | |
| 5435 | #define _PCH_TRANSA_LINK_M1 0xe0040 | |
| 5436 | #define _PCH_TRANSA_LINK_N1 0xe0044 | |
| 5437 | #define _PCH_TRANSA_LINK_M2 0xe0048 | |
| 5438 | #define _PCH_TRANSA_LINK_N2 0xe004c | |
| 9db4a9c7 | 5439 | |
| 2dcbc34d | 5440 | /* Per-transcoder DIP controls (PCH) */ |
| b055c8f3 JB |
5441 | #define _VIDEO_DIP_CTL_A 0xe0200 |
| 5442 | #define _VIDEO_DIP_DATA_A 0xe0208 | |
| 5443 | #define _VIDEO_DIP_GCP_A 0xe0210 | |
| 5444 | ||
| 5445 | #define _VIDEO_DIP_CTL_B 0xe1200 | |
| 5446 | #define _VIDEO_DIP_DATA_B 0xe1208 | |
| 5447 | #define _VIDEO_DIP_GCP_B 0xe1210 | |
| 5448 | ||
| 5449 | #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) | |
| 5450 | #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) | |
| 5451 | #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) | |
| 5452 | ||
| 2dcbc34d | 5453 | /* Per-transcoder DIP controls (VLV) */ |
| b906487c VS |
5454 | #define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) |
| 5455 | #define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) | |
| 5456 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) | |
| 90b107c8 | 5457 | |
| b906487c VS |
5458 | #define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) |
| 5459 | #define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) | |
| 5460 | #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) | |
| 90b107c8 | 5461 | |
| 2dcbc34d VS |
5462 | #define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) |
| 5463 | #define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) | |
| 5464 | #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) | |
| 5465 | ||
| 90b107c8 | 5466 | #define VLV_TVIDEO_DIP_CTL(pipe) \ |
| 2dcbc34d VS |
5467 | _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ |
| 5468 | VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) | |
| 90b107c8 | 5469 | #define VLV_TVIDEO_DIP_DATA(pipe) \ |
| 2dcbc34d VS |
5470 | _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ |
| 5471 | VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) | |
| 90b107c8 | 5472 | #define VLV_TVIDEO_DIP_GCP(pipe) \ |
| 2dcbc34d VS |
5473 | _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ |
| 5474 | VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) | |
| 90b107c8 | 5475 | |
| 8c5f5f7c ED |
5476 | /* Haswell DIP controls */ |
| 5477 | #define HSW_VIDEO_DIP_CTL_A 0x60200 | |
| 5478 | #define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 | |
| 5479 | #define HSW_VIDEO_DIP_VS_DATA_A 0x60260 | |
| 5480 | #define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 | |
| 5481 | #define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 | |
| 5482 | #define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 | |
| 5483 | #define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 | |
| 5484 | #define HSW_VIDEO_DIP_VS_ECC_A 0x60280 | |
| 5485 | #define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 | |
| 5486 | #define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 | |
| 5487 | #define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 | |
| 5488 | #define HSW_VIDEO_DIP_GCP_A 0x60210 | |
| 5489 | ||
| 5490 | #define HSW_VIDEO_DIP_CTL_B 0x61200 | |
| 5491 | #define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 | |
| 5492 | #define HSW_VIDEO_DIP_VS_DATA_B 0x61260 | |
| 5493 | #define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 | |
| 5494 | #define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 | |
| 5495 | #define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 | |
| 5496 | #define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 | |
| 5497 | #define HSW_VIDEO_DIP_VS_ECC_B 0x61280 | |
| 5498 | #define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 | |
| 5499 | #define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 | |
| 5500 | #define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 | |
| 5501 | #define HSW_VIDEO_DIP_GCP_B 0x61210 | |
| 5502 | ||
| 7d9bcebe | 5503 | #define HSW_TVIDEO_DIP_CTL(trans) \ |
| a57c774a | 5504 | _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) |
| 7d9bcebe | 5505 | #define HSW_TVIDEO_DIP_AVI_DATA(trans) \ |
| a57c774a | 5506 | _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) |
| c8bb75af | 5507 | #define HSW_TVIDEO_DIP_VS_DATA(trans) \ |
| a57c774a | 5508 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) |
| 7d9bcebe | 5509 | #define HSW_TVIDEO_DIP_SPD_DATA(trans) \ |
| a57c774a | 5510 | _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) |
| 7d9bcebe | 5511 | #define HSW_TVIDEO_DIP_GCP(trans) \ |
| a57c774a | 5512 | _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) |
| 7d9bcebe | 5513 | #define HSW_TVIDEO_DIP_VSC_DATA(trans) \ |
| a57c774a | 5514 | _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) |
| 8c5f5f7c | 5515 | |
| 3f51e471 RV |
5516 | #define HSW_STEREO_3D_CTL_A 0x70020 |
| 5517 | #define S3D_ENABLE (1<<31) | |
| 5518 | #define HSW_STEREO_3D_CTL_B 0x71020 | |
| 5519 | ||
| 5520 | #define HSW_STEREO_3D_CTL(trans) \ | |
| a57c774a | 5521 | _PIPE2(trans, HSW_STEREO_3D_CTL_A) |
| 3f51e471 | 5522 | |
| 275f01b2 DV |
5523 | #define _PCH_TRANS_HTOTAL_B 0xe1000 |
| 5524 | #define _PCH_TRANS_HBLANK_B 0xe1004 | |
| 5525 | #define _PCH_TRANS_HSYNC_B 0xe1008 | |
| 5526 | #define _PCH_TRANS_VTOTAL_B 0xe100c | |
| 5527 | #define _PCH_TRANS_VBLANK_B 0xe1010 | |
| 5528 | #define _PCH_TRANS_VSYNC_B 0xe1014 | |
| 5529 | #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 | |
| 5530 | ||
| 5531 | #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) | |
| 5532 | #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) | |
| 5533 | #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) | |
| 5534 | #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) | |
| 5535 | #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) | |
| 5536 | #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) | |
| 5537 | #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ | |
| 5538 | _PCH_TRANS_VSYNCSHIFT_B) | |
| 9db4a9c7 | 5539 | |
| e3b95f1e DV |
5540 | #define _PCH_TRANSB_DATA_M1 0xe1030 |
| 5541 | #define _PCH_TRANSB_DATA_N1 0xe1034 | |
| 5542 | #define _PCH_TRANSB_DATA_M2 0xe1038 | |
| 5543 | #define _PCH_TRANSB_DATA_N2 0xe103c | |
| 5544 | #define _PCH_TRANSB_LINK_M1 0xe1040 | |
| 5545 | #define _PCH_TRANSB_LINK_N1 0xe1044 | |
| 5546 | #define _PCH_TRANSB_LINK_M2 0xe1048 | |
| 5547 | #define _PCH_TRANSB_LINK_N2 0xe104c | |
| 5548 | ||
| 5549 | #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) | |
| 5550 | #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) | |
| 5551 | #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) | |
| 5552 | #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) | |
| 5553 | #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) | |
| 5554 | #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) | |
| 5555 | #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) | |
| 5556 | #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) | |
| 9db4a9c7 | 5557 | |
| ab9412ba DV |
5558 | #define _PCH_TRANSACONF 0xf0008 |
| 5559 | #define _PCH_TRANSBCONF 0xf1008 | |
| 5560 | #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) | |
| 5561 | #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ | |
| b9055052 ZW |
5562 | #define TRANS_DISABLE (0<<31) |
| 5563 | #define TRANS_ENABLE (1<<31) | |
| 5564 | #define TRANS_STATE_MASK (1<<30) | |
| 5565 | #define TRANS_STATE_DISABLE (0<<30) | |
| 5566 | #define TRANS_STATE_ENABLE (1<<30) | |
| 5567 | #define TRANS_FSYNC_DELAY_HB1 (0<<27) | |
| 5568 | #define TRANS_FSYNC_DELAY_HB2 (1<<27) | |
| 5569 | #define TRANS_FSYNC_DELAY_HB3 (2<<27) | |
| 5570 | #define TRANS_FSYNC_DELAY_HB4 (3<<27) | |
| 5f7f726d | 5571 | #define TRANS_INTERLACE_MASK (7<<21) |
| b9055052 | 5572 | #define TRANS_PROGRESSIVE (0<<21) |
| 5f7f726d | 5573 | #define TRANS_INTERLACED (3<<21) |
| 7c26e5c6 | 5574 | #define TRANS_LEGACY_INTERLACED_ILK (2<<21) |
| b9055052 ZW |
5575 | #define TRANS_8BPC (0<<5) |
| 5576 | #define TRANS_10BPC (1<<5) | |
| 5577 | #define TRANS_6BPC (2<<5) | |
| 5578 | #define TRANS_12BPC (3<<5) | |
| 5579 | ||
| ce40141f DV |
5580 | #define _TRANSA_CHICKEN1 0xf0060 |
| 5581 | #define _TRANSB_CHICKEN1 0xf1060 | |
| 5582 | #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) | |
| 5583 | #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) | |
| 3bcf603f JB |
5584 | #define _TRANSA_CHICKEN2 0xf0064 |
| 5585 | #define _TRANSB_CHICKEN2 0xf1064 | |
| 5586 | #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) | |
| dc4bd2d1 PZ |
5587 | #define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) |
| 5588 | #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) | |
| 5589 | #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) | |
| 5590 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) | |
| 5591 | #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) | |
| 3bcf603f | 5592 | |
| 291427f5 JB |
5593 | #define SOUTH_CHICKEN1 0xc2000 |
| 5594 | #define FDIA_PHASE_SYNC_SHIFT_OVR 19 | |
| 5595 | #define FDIA_PHASE_SYNC_SHIFT_EN 18 | |
| 01a415fd DV |
5596 | #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) |
| 5597 | #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) | |
| 5598 | #define FDI_BC_BIFURCATION_SELECT (1 << 12) | |
| 645c62a5 | 5599 | #define SOUTH_CHICKEN2 0xc2004 |
| dde86e2d PZ |
5600 | #define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) |
| 5601 | #define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) | |
| 5602 | #define DPLS_EDP_PPS_FIX_DIS (1<<0) | |
| 645c62a5 | 5603 | |
| 9db4a9c7 JB |
5604 | #define _FDI_RXA_CHICKEN 0xc200c |
| 5605 | #define _FDI_RXB_CHICKEN 0xc2010 | |
| 6f06ce18 JB |
5606 | #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) |
| 5607 | #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) | |
| 9db4a9c7 | 5608 | #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) |
| b9055052 | 5609 | |
| 382b0936 | 5610 | #define SOUTH_DSPCLK_GATE_D 0xc2020 |
| cd664078 | 5611 | #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) |
| 382b0936 | 5612 | #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) |
| cd664078 | 5613 | #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) |
| 17a303ec | 5614 | #define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) |
| 382b0936 | 5615 | |
| b9055052 | 5616 | /* CPU: FDI_TX */ |
| 9db4a9c7 JB |
5617 | #define _FDI_TXA_CTL 0x60100 |
| 5618 | #define _FDI_TXB_CTL 0x61100 | |
| 5619 | #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) | |
| b9055052 ZW |
5620 | #define FDI_TX_DISABLE (0<<31) |
| 5621 | #define FDI_TX_ENABLE (1<<31) | |
| 5622 | #define FDI_LINK_TRAIN_PATTERN_1 (0<<28) | |
| 5623 | #define FDI_LINK_TRAIN_PATTERN_2 (1<<28) | |
| 5624 | #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) | |
| 5625 | #define FDI_LINK_TRAIN_NONE (3<<28) | |
| 5626 | #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) | |
| 5627 | #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) | |
| 5628 | #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) | |
| 5629 | #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) | |
| 5630 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) | |
| 5631 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) | |
| 5632 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) | |
| 5633 | #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) | |
| 8db9d77b ZW |
5634 | /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. |
| 5635 | SNB has different settings. */ | |
| 5636 | /* SNB A-stepping */ | |
| 5637 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
| 5638 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
| 5639 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
| 5640 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
| 5641 | /* SNB B-stepping */ | |
| 5642 | #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) | |
| 5643 | #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) | |
| 5644 | #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) | |
| 5645 | #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) | |
| 5646 | #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) | |
| 627eb5a3 DV |
5647 | #define FDI_DP_PORT_WIDTH_SHIFT 19 |
| 5648 | #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) | |
| 5649 | #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) | |
| b9055052 | 5650 | #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) |
| f2b115e6 | 5651 | /* Ironlake: hardwired to 1 */ |
| b9055052 | 5652 | #define FDI_TX_PLL_ENABLE (1<<14) |
| 357555c0 JB |
5653 | |
| 5654 | /* Ivybridge has different bits for lolz */ | |
| 5655 | #define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) | |
| 5656 | #define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) | |
| 5657 | #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) | |
| 5658 | #define FDI_LINK_TRAIN_NONE_IVB (3<<8) | |
| 5659 | ||
| b9055052 | 5660 | /* both Tx and Rx */ |
| c4f9c4c2 | 5661 | #define FDI_COMPOSITE_SYNC (1<<11) |
| 357555c0 | 5662 | #define FDI_LINK_TRAIN_AUTO (1<<10) |
| b9055052 ZW |
5663 | #define FDI_SCRAMBLING_ENABLE (0<<7) |
| 5664 | #define FDI_SCRAMBLING_DISABLE (1<<7) | |
| 5665 | ||
| 5666 | /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ | |
| 9db4a9c7 JB |
5667 | #define _FDI_RXA_CTL 0xf000c |
| 5668 | #define _FDI_RXB_CTL 0xf100c | |
| 5669 | #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) | |
| b9055052 | 5670 | #define FDI_RX_ENABLE (1<<31) |
| b9055052 | 5671 | /* train, dp width same as FDI_TX */ |
| 357555c0 JB |
5672 | #define FDI_FS_ERRC_ENABLE (1<<27) |
| 5673 | #define FDI_FE_ERRC_ENABLE (1<<26) | |
| 68d18ad7 | 5674 | #define FDI_RX_POLARITY_REVERSED_LPT (1<<16) |
| b9055052 ZW |
5675 | #define FDI_8BPC (0<<16) |
| 5676 | #define FDI_10BPC (1<<16) | |
| 5677 | #define FDI_6BPC (2<<16) | |
| 5678 | #define FDI_12BPC (3<<16) | |
| 3e68320e | 5679 | #define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) |
| b9055052 ZW |
5680 | #define FDI_DMI_LINK_REVERSE_MASK (1<<14) |
| 5681 | #define FDI_RX_PLL_ENABLE (1<<13) | |
| 5682 | #define FDI_FS_ERR_CORRECT_ENABLE (1<<11) | |
| 5683 | #define FDI_FE_ERR_CORRECT_ENABLE (1<<10) | |
| 5684 | #define FDI_FS_ERR_REPORT_ENABLE (1<<9) | |
| 5685 | #define FDI_FE_ERR_REPORT_ENABLE (1<<8) | |
| 5686 | #define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) | |
| 5eddb70b | 5687 | #define FDI_PCDCLK (1<<4) |
| 8db9d77b ZW |
5688 | /* CPT */ |
| 5689 | #define FDI_AUTO_TRAINING (1<<10) | |
| 5690 | #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) | |
| 5691 | #define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) | |
| 5692 | #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) | |
| 5693 | #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) | |
| 5694 | #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) | |
| b9055052 | 5695 | |
| 04945641 PZ |
5696 | #define _FDI_RXA_MISC 0xf0010 |
| 5697 | #define _FDI_RXB_MISC 0xf1010 | |
| 5698 | #define FDI_RX_PWRDN_LANE1_MASK (3<<26) | |
| 5699 | #define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) | |
| 5700 | #define FDI_RX_PWRDN_LANE0_MASK (3<<24) | |
| 5701 | #define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) | |
| 5702 | #define FDI_RX_TP1_TO_TP2_48 (2<<20) | |
| 5703 | #define FDI_RX_TP1_TO_TP2_64 (3<<20) | |
| 5704 | #define FDI_RX_FDI_DELAY_90 (0x90<<0) | |
| 5705 | #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) | |
| 5706 | ||
| 9db4a9c7 JB |
5707 | #define _FDI_RXA_TUSIZE1 0xf0030 |
| 5708 | #define _FDI_RXA_TUSIZE2 0xf0038 | |
| 5709 | #define _FDI_RXB_TUSIZE1 0xf1030 | |
| 5710 | #define _FDI_RXB_TUSIZE2 0xf1038 | |
| 9db4a9c7 JB |
5711 | #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) |
| 5712 | #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) | |
| b9055052 ZW |
5713 | |
| 5714 | /* FDI_RX interrupt register format */ | |
| 5715 | #define FDI_RX_INTER_LANE_ALIGN (1<<10) | |
| 5716 | #define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ | |
| 5717 | #define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ | |
| 5718 | #define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) | |
| 5719 | #define FDI_RX_FS_CODE_ERR (1<<6) | |
| 5720 | #define FDI_RX_FE_CODE_ERR (1<<5) | |
| 5721 | #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) | |
| 5722 | #define FDI_RX_HDCP_LINK_FAIL (1<<3) | |
| 5723 | #define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) | |
| 5724 | #define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) | |
| 5725 | #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) | |
| 5726 | ||
| 9db4a9c7 JB |
5727 | #define _FDI_RXA_IIR 0xf0014 |
| 5728 | #define _FDI_RXA_IMR 0xf0018 | |
| 5729 | #define _FDI_RXB_IIR 0xf1014 | |
| 5730 | #define _FDI_RXB_IMR 0xf1018 | |
| 5731 | #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) | |
| 5732 | #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) | |
| b9055052 ZW |
5733 | |
| 5734 | #define FDI_PLL_CTL_1 0xfe000 | |
| 5735 | #define FDI_PLL_CTL_2 0xfe004 | |
| 5736 | ||
| b9055052 ZW |
5737 | #define PCH_LVDS 0xe1180 |
| 5738 | #define LVDS_DETECTED (1 << 1) | |
| 5739 | ||
| 98364379 | 5740 | /* vlv has 2 sets of panel control regs. */ |
| f12c47b2 VS |
5741 | #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) |
| 5742 | #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) | |
| 5743 | #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) | |
| ad933b56 | 5744 | #define PANEL_PORT_SELECT_VLV(port) ((port) << 30) |
| f12c47b2 VS |
5745 | #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) |
| 5746 | #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) | |
| 5747 | ||
| 5748 | #define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) | |
| 5749 | #define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) | |
| 5750 | #define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) | |
| 5751 | #define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) | |
| 5752 | #define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) | |
| 98364379 | 5753 | |
| 453c5420 JB |
5754 | #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) |
| 5755 | #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) | |
| 5756 | #define VLV_PIPE_PP_ON_DELAYS(pipe) \ | |
| 5757 | _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) | |
| 5758 | #define VLV_PIPE_PP_OFF_DELAYS(pipe) \ | |
| 5759 | _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) | |
| 5760 | #define VLV_PIPE_PP_DIVISOR(pipe) \ | |
| 5761 | _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) | |
| 5762 | ||
| b9055052 ZW |
5763 | #define PCH_PP_STATUS 0xc7200 |
| 5764 | #define PCH_PP_CONTROL 0xc7204 | |
| 4a655f04 | 5765 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
| 1c0ae80a | 5766 | #define PANEL_UNLOCK_MASK (0xffff << 16) |
| b9055052 ZW |
5767 | #define EDP_FORCE_VDD (1 << 3) |
| 5768 | #define EDP_BLC_ENABLE (1 << 2) | |
| 5769 | #define PANEL_POWER_RESET (1 << 1) | |
| 5770 | #define PANEL_POWER_OFF (0 << 0) | |
| 5771 | #define PANEL_POWER_ON (1 << 0) | |
| 5772 | #define PCH_PP_ON_DELAYS 0xc7208 | |
| f01eca2e KP |
5773 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
| 5774 | #define PANEL_PORT_SELECT_LVDS (0 << 30) | |
| 5775 | #define PANEL_PORT_SELECT_DPA (1 << 30) | |
| f01eca2e KP |
5776 | #define PANEL_PORT_SELECT_DPC (2 << 30) |
| 5777 | #define PANEL_PORT_SELECT_DPD (3 << 30) | |
| 5778 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) | |
| 5779 | #define PANEL_POWER_UP_DELAY_SHIFT 16 | |
| 5780 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) | |
| 5781 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 | |
| 5782 | ||
| b9055052 | 5783 | #define PCH_PP_OFF_DELAYS 0xc720c |
| f01eca2e KP |
5784 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
| 5785 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 | |
| 5786 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) | |
| 5787 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 | |
| 5788 | ||
| b9055052 | 5789 | #define PCH_PP_DIVISOR 0xc7210 |
| f01eca2e KP |
5790 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) |
| 5791 | #define PP_REFERENCE_DIVIDER_SHIFT 8 | |
| 5792 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) | |
| 5793 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 | |
| b9055052 | 5794 | |
| 5eb08b69 ZW |
5795 | #define PCH_DP_B 0xe4100 |
| 5796 | #define PCH_DPB_AUX_CH_CTL 0xe4110 | |
| 5797 | #define PCH_DPB_AUX_CH_DATA1 0xe4114 | |
| 5798 | #define PCH_DPB_AUX_CH_DATA2 0xe4118 | |
| 5799 | #define PCH_DPB_AUX_CH_DATA3 0xe411c | |
| 5800 | #define PCH_DPB_AUX_CH_DATA4 0xe4120 | |
| 5801 | #define PCH_DPB_AUX_CH_DATA5 0xe4124 | |
| 5802 | ||
| 5803 | #define PCH_DP_C 0xe4200 | |
| 5804 | #define PCH_DPC_AUX_CH_CTL 0xe4210 | |
| 5805 | #define PCH_DPC_AUX_CH_DATA1 0xe4214 | |
| 5806 | #define PCH_DPC_AUX_CH_DATA2 0xe4218 | |
| 5807 | #define PCH_DPC_AUX_CH_DATA3 0xe421c | |
| 5808 | #define PCH_DPC_AUX_CH_DATA4 0xe4220 | |
| 5809 | #define PCH_DPC_AUX_CH_DATA5 0xe4224 | |
| 5810 | ||
| 5811 | #define PCH_DP_D 0xe4300 | |
| 5812 | #define PCH_DPD_AUX_CH_CTL 0xe4310 | |
| 5813 | #define PCH_DPD_AUX_CH_DATA1 0xe4314 | |
| 5814 | #define PCH_DPD_AUX_CH_DATA2 0xe4318 | |
| 5815 | #define PCH_DPD_AUX_CH_DATA3 0xe431c | |
| 5816 | #define PCH_DPD_AUX_CH_DATA4 0xe4320 | |
| 5817 | #define PCH_DPD_AUX_CH_DATA5 0xe4324 | |
| 5818 | ||
| 8db9d77b ZW |
5819 | /* CPT */ |
| 5820 | #define PORT_TRANS_A_SEL_CPT 0 | |
| 5821 | #define PORT_TRANS_B_SEL_CPT (1<<29) | |
| 5822 | #define PORT_TRANS_C_SEL_CPT (2<<29) | |
| 5823 | #define PORT_TRANS_SEL_MASK (3<<29) | |
| 1519b995 | 5824 | #define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) |
| 19d8fe15 DV |
5825 | #define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) |
| 5826 | #define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) | |
| 71485e0a VS |
5827 | #define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) |
| 5828 | #define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) | |
| 8db9d77b ZW |
5829 | |
| 5830 | #define TRANS_DP_CTL_A 0xe0300 | |
| 5831 | #define TRANS_DP_CTL_B 0xe1300 | |
| 5832 | #define TRANS_DP_CTL_C 0xe2300 | |
| 23670b32 | 5833 | #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) |
| 8db9d77b ZW |
5834 | #define TRANS_DP_OUTPUT_ENABLE (1<<31) |
| 5835 | #define TRANS_DP_PORT_SEL_B (0<<29) | |
| 5836 | #define TRANS_DP_PORT_SEL_C (1<<29) | |
| 5837 | #define TRANS_DP_PORT_SEL_D (2<<29) | |
| cb3543c6 | 5838 | #define TRANS_DP_PORT_SEL_NONE (3<<29) |
| 8db9d77b ZW |
5839 | #define TRANS_DP_PORT_SEL_MASK (3<<29) |
| 5840 | #define TRANS_DP_AUDIO_ONLY (1<<26) | |
| 5841 | #define TRANS_DP_ENH_FRAMING (1<<18) | |
| 5842 | #define TRANS_DP_8BPC (0<<9) | |
| 5843 | #define TRANS_DP_10BPC (1<<9) | |
| 5844 | #define TRANS_DP_6BPC (2<<9) | |
| 5845 | #define TRANS_DP_12BPC (3<<9) | |
| 220cad3c | 5846 | #define TRANS_DP_BPC_MASK (3<<9) |
| 8db9d77b ZW |
5847 | #define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) |
| 5848 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 | |
| 5849 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) | |
| 5850 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 | |
| 94113cec | 5851 | #define TRANS_DP_SYNC_MASK (3<<3) |
| 8db9d77b ZW |
5852 | |
| 5853 | /* SNB eDP training params */ | |
| 5854 | /* SNB A-stepping */ | |
| 5855 | #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) | |
| 5856 | #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) | |
| 5857 | #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) | |
| 5858 | #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) | |
| 5859 | /* SNB B-stepping */ | |
| 3c5a62b5 YL |
5860 | #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) |
| 5861 | #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) | |
| 5862 | #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) | |
| 5863 | #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) | |
| 5864 | #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) | |
| 8db9d77b ZW |
5865 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) |
| 5866 | ||
| 1a2eb460 KP |
5867 | /* IVB */ |
| 5868 | #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) | |
| 5869 | #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) | |
| 5870 | #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) | |
| 5871 | #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) | |
| 5872 | #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) | |
| 5873 | #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) | |
| 77fa4cbd | 5874 | #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) |
| 1a2eb460 KP |
5875 | |
| 5876 | /* legacy values */ | |
| 5877 | #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) | |
| 5878 | #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) | |
| 5879 | #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) | |
| 5880 | #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) | |
| 5881 | #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) | |
| 5882 | ||
| 5883 | #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) | |
| 5884 | ||
| 9e72b46c ID |
5885 | #define VLV_PMWGICZ 0x1300a4 |
| 5886 | ||
| cae5852d | 5887 | #define FORCEWAKE 0xA18C |
| 575155a9 JB |
5888 | #define FORCEWAKE_VLV 0x1300b0 |
| 5889 | #define FORCEWAKE_ACK_VLV 0x1300b4 | |
| ed5de399 JB |
5890 | #define FORCEWAKE_MEDIA_VLV 0x1300b8 |
| 5891 | #define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc | |
| e7911c48 | 5892 | #define FORCEWAKE_ACK_HSW 0x130044 |
| eb43f4af | 5893 | #define FORCEWAKE_ACK 0x130090 |
| d62b4892 | 5894 | #define VLV_GTLC_WAKE_CTRL 0x130090 |
| 981a5aea ID |
5895 | #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) |
| 5896 | #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) | |
| 5897 | #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) | |
| 5898 | ||
| d62b4892 | 5899 | #define VLV_GTLC_PW_STATUS 0x130094 |
| 981a5aea ID |
5900 | #define VLV_GTLC_ALLOWWAKEACK (1 << 0) |
| 5901 | #define VLV_GTLC_ALLOWWAKEERR (1 << 1) | |
| 5902 | #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) | |
| 5903 | #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) | |
| 8d715f00 | 5904 | #define FORCEWAKE_MT 0xa188 /* multi-threaded */ |
| 38cff0b1 ZW |
5905 | #define FORCEWAKE_MEDIA_GEN9 0xa270 |
| 5906 | #define FORCEWAKE_RENDER_GEN9 0xa278 | |
| 5907 | #define FORCEWAKE_BLITTER_GEN9 0xa188 | |
| 5908 | #define FORCEWAKE_ACK_MEDIA_GEN9 0x0D88 | |
| 5909 | #define FORCEWAKE_ACK_RENDER_GEN9 0x0D84 | |
| 5910 | #define FORCEWAKE_ACK_BLITTER_GEN9 0x130044 | |
| c5836c27 CW |
5911 | #define FORCEWAKE_KERNEL 0x1 |
| 5912 | #define FORCEWAKE_USER 0x2 | |
| 8d715f00 KP |
5913 | #define FORCEWAKE_MT_ACK 0x130040 |
| 5914 | #define ECOBUS 0xa180 | |
| 5915 | #define FORCEWAKE_MT_ENABLE (1<<5) | |
| 9e72b46c | 5916 | #define VLV_SPAREG2H 0xA194 |
| 8fd26859 | 5917 | |
| dd202c6d | 5918 | #define GTFIFODBG 0x120000 |
| 90f256b5 VS |
5919 | #define GT_FIFO_SBDROPERR (1<<6) |
| 5920 | #define GT_FIFO_BLOBDROPERR (1<<5) | |
| 5921 | #define GT_FIFO_SB_READ_ABORTERR (1<<4) | |
| 5922 | #define GT_FIFO_DROPERR (1<<3) | |
| dd202c6d BW |
5923 | #define GT_FIFO_OVFERR (1<<2) |
| 5924 | #define GT_FIFO_IAWRERR (1<<1) | |
| 5925 | #define GT_FIFO_IARDERR (1<<0) | |
| 5926 | ||
| 46520e2b VS |
5927 | #define GTFIFOCTL 0x120008 |
| 5928 | #define GT_FIFO_FREE_ENTRIES_MASK 0x7f | |
| 95736720 | 5929 | #define GT_FIFO_NUM_RESERVED_ENTRIES 20 |
| 91355834 | 5930 | |
| 05e21cc4 BW |
5931 | #define HSW_IDICR 0x9008 |
| 5932 | #define IDIHASHMSK(x) (((x) & 0x3f) << 16) | |
| 5933 | #define HSW_EDRAM_PRESENT 0x120010 | |
| 5934 | ||
| 80e829fa | 5935 | #define GEN6_UCGCTL1 0x9400 |
| e4443e45 | 5936 | # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) |
| 80e829fa | 5937 | # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
| de4a8bd1 | 5938 | # define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) |
| 80e829fa | 5939 | |
| 406478dc | 5940 | #define GEN6_UCGCTL2 0x9404 |
| 0f846f81 | 5941 | # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) |
| 6edaa7fc | 5942 | # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) |
| eae66b50 | 5943 | # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) |
| 406478dc | 5944 | # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) |
| 9ca1d10d | 5945 | # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) |
| 406478dc | 5946 | |
| 9e72b46c ID |
5947 | #define GEN6_UCGCTL3 0x9408 |
| 5948 | ||
| e3f33d46 JB |
5949 | #define GEN7_UCGCTL4 0x940c |
| 5950 | #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) | |
| 5951 | ||
| 9e72b46c ID |
5952 | #define GEN6_RCGCTL1 0x9410 |
| 5953 | #define GEN6_RCGCTL2 0x9414 | |
| 5954 | #define GEN6_RSTCTL 0x9420 | |
| 5955 | ||
| 4f1ca9e9 VS |
5956 | #define GEN8_UCGCTL6 0x9430 |
| 5957 | #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) | |
| 5958 | ||
| 9e72b46c | 5959 | #define GEN6_GFXPAUSE 0xA000 |
| 3b8d8d91 | 5960 | #define GEN6_RPNSWREQ 0xA008 |
| 8fd26859 CW |
5961 | #define GEN6_TURBO_DISABLE (1<<31) |
| 5962 | #define GEN6_FREQUENCY(x) ((x)<<25) | |
| 92bd1bf0 | 5963 | #define HSW_FREQUENCY(x) ((x)<<24) |
| 8fd26859 CW |
5964 | #define GEN6_OFFSET(x) ((x)<<19) |
| 5965 | #define GEN6_AGGRESSIVE_TURBO (0<<15) | |
| 5966 | #define GEN6_RC_VIDEO_FREQ 0xA00C | |
| 5967 | #define GEN6_RC_CONTROL 0xA090 | |
| 5968 | #define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) | |
| 5969 | #define GEN6_RC_CTL_RC6p_ENABLE (1<<17) | |
| 5970 | #define GEN6_RC_CTL_RC6_ENABLE (1<<18) | |
| 5971 | #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) | |
| 5972 | #define GEN6_RC_CTL_RC7_ENABLE (1<<22) | |
| 6b88f295 | 5973 | #define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) |
| 0a073b84 | 5974 | #define GEN7_RC_CTL_TO_MODE (1<<28) |
| 8fd26859 CW |
5975 | #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) |
| 5976 | #define GEN6_RC_CTL_HW_ENABLE (1<<31) | |
| 5977 | #define GEN6_RP_DOWN_TIMEOUT 0xA010 | |
| 5978 | #define GEN6_RP_INTERRUPT_LIMITS 0xA014 | |
| 3b8d8d91 | 5979 | #define GEN6_RPSTAT1 0xA01C |
| ccab5c82 | 5980 | #define GEN6_CAGF_SHIFT 8 |
| f82855d3 | 5981 | #define HSW_CAGF_SHIFT 7 |
| ccab5c82 | 5982 | #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) |
| f82855d3 | 5983 | #define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) |
| 8fd26859 CW |
5984 | #define GEN6_RP_CONTROL 0xA024 |
| 5985 | #define GEN6_RP_MEDIA_TURBO (1<<11) | |
| 6ed55ee7 BW |
5986 | #define GEN6_RP_MEDIA_MODE_MASK (3<<9) |
| 5987 | #define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) | |
| 5988 | #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) | |
| 5989 | #define GEN6_RP_MEDIA_HW_MODE (1<<9) | |
| 5990 | #define GEN6_RP_MEDIA_SW_MODE (0<<9) | |
| 8fd26859 CW |
5991 | #define GEN6_RP_MEDIA_IS_GFX (1<<8) |
| 5992 | #define GEN6_RP_ENABLE (1<<7) | |
| ccab5c82 JB |
5993 | #define GEN6_RP_UP_IDLE_MIN (0x1<<3) |
| 5994 | #define GEN6_RP_UP_BUSY_AVG (0x2<<3) | |
| 5995 | #define GEN6_RP_UP_BUSY_CONT (0x4<<3) | |
| dd75fdc8 | 5996 | #define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) |
| ccab5c82 | 5997 | #define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) |
| 8fd26859 CW |
5998 | #define GEN6_RP_UP_THRESHOLD 0xA02C |
| 5999 | #define GEN6_RP_DOWN_THRESHOLD 0xA030 | |
| ccab5c82 JB |
6000 | #define GEN6_RP_CUR_UP_EI 0xA050 |
| 6001 | #define GEN6_CURICONT_MASK 0xffffff | |
| 6002 | #define GEN6_RP_CUR_UP 0xA054 | |
| 6003 | #define GEN6_CURBSYTAVG_MASK 0xffffff | |
| 6004 | #define GEN6_RP_PREV_UP 0xA058 | |
| 6005 | #define GEN6_RP_CUR_DOWN_EI 0xA05C | |
| 6006 | #define GEN6_CURIAVG_MASK 0xffffff | |
| 6007 | #define GEN6_RP_CUR_DOWN 0xA060 | |
| 6008 | #define GEN6_RP_PREV_DOWN 0xA064 | |
| 8fd26859 CW |
6009 | #define GEN6_RP_UP_EI 0xA068 |
| 6010 | #define GEN6_RP_DOWN_EI 0xA06C | |
| 6011 | #define GEN6_RP_IDLE_HYSTERSIS 0xA070 | |
| 9e72b46c ID |
6012 | #define GEN6_RPDEUHWTC 0xA080 |
| 6013 | #define GEN6_RPDEUC 0xA084 | |
| 6014 | #define GEN6_RPDEUCSW 0xA088 | |
| 8fd26859 CW |
6015 | #define GEN6_RC_STATE 0xA094 |
| 6016 | #define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 | |
| 6017 | #define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C | |
| 6018 | #define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 | |
| 6019 | #define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 | |
| 6020 | #define GEN6_RC_IDLE_HYSTERSIS 0xA0AC | |
| 6021 | #define GEN6_RC_SLEEP 0xA0B0 | |
| 9e72b46c | 6022 | #define GEN6_RCUBMABDTMR 0xA0B0 |
| 8fd26859 CW |
6023 | #define GEN6_RC1e_THRESHOLD 0xA0B4 |
| 6024 | #define GEN6_RC6_THRESHOLD 0xA0B8 | |
| 6025 | #define GEN6_RC6p_THRESHOLD 0xA0BC | |
| 9e72b46c | 6026 | #define VLV_RCEDATA 0xA0BC |
| 8fd26859 | 6027 | #define GEN6_RC6pp_THRESHOLD 0xA0C0 |
| 3b8d8d91 | 6028 | #define GEN6_PMINTRMSK 0xA168 |
| baccd458 | 6029 | #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) |
| 9e72b46c | 6030 | #define VLV_PWRDWNUPCTL 0xA294 |
| 8fd26859 CW |
6031 | |
| 6032 | #define GEN6_PMISR 0x44020 | |
| 4912d041 | 6033 | #define GEN6_PMIMR 0x44024 /* rps_lock */ |
| 8fd26859 CW |
6034 | #define GEN6_PMIIR 0x44028 |
| 6035 | #define GEN6_PMIER 0x4402C | |
| 6036 | #define GEN6_PM_MBOX_EVENT (1<<25) | |
| 6037 | #define GEN6_PM_THERMAL_EVENT (1<<24) | |
| 6038 | #define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) | |
| 6039 | #define GEN6_PM_RP_UP_THRESHOLD (1<<5) | |
| 6040 | #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) | |
| 6041 | #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) | |
| 6042 | #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) | |
| 4848405c | 6043 | #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ |
| 4912d041 BW |
6044 | GEN6_PM_RP_DOWN_THRESHOLD | \ |
| 6045 | GEN6_PM_RP_DOWN_TIMEOUT) | |
| 8fd26859 | 6046 | |
| 9e72b46c ID |
6047 | #define GEN7_GT_SCRATCH_BASE 0x4F100 |
| 6048 | #define GEN7_GT_SCRATCH_REG_NUM 8 | |
| 6049 | ||
| 76c3552f D |
6050 | #define VLV_GTLC_SURVIVABILITY_REG 0x130098 |
| 6051 | #define VLV_GFX_CLK_STATUS_BIT (1<<3) | |
| 6052 | #define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) | |
| 6053 | ||
| cce66a28 | 6054 | #define GEN6_GT_GFX_RC6_LOCKED 0x138104 |
| 49798eb2 JB |
6055 | #define VLV_COUNTER_CONTROL 0x138104 |
| 6056 | #define VLV_COUNT_RANGE_HIGH (1<<15) | |
| 31685c25 D |
6057 | #define VLV_MEDIA_RC0_COUNT_EN (1<<5) |
| 6058 | #define VLV_RENDER_RC0_COUNT_EN (1<<4) | |
| 49798eb2 JB |
6059 | #define VLV_MEDIA_RC6_COUNT_EN (1<<1) |
| 6060 | #define VLV_RENDER_RC6_COUNT_EN (1<<0) | |
| cce66a28 | 6061 | #define GEN6_GT_GFX_RC6 0x138108 |
| 9cc19be5 ID |
6062 | #define VLV_GT_RENDER_RC6 0x138108 |
| 6063 | #define VLV_GT_MEDIA_RC6 0x13810C | |
| 6064 | ||
| cce66a28 BW |
6065 | #define GEN6_GT_GFX_RC6p 0x13810C |
| 6066 | #define GEN6_GT_GFX_RC6pp 0x138110 | |
| 31685c25 D |
6067 | #define VLV_RENDER_C0_COUNT_REG 0x138118 |
| 6068 | #define VLV_MEDIA_C0_COUNT_REG 0x13811C | |
| cce66a28 | 6069 | |
| 8fd26859 CW |
6070 | #define GEN6_PCODE_MAILBOX 0x138124 |
| 6071 | #define GEN6_PCODE_READY (1<<31) | |
| a6044e23 | 6072 | #define GEN6_READ_OC_PARAMS 0xc |
| 23b2f8bb JB |
6073 | #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 |
| 6074 | #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 | |
| 31643d54 BW |
6075 | #define GEN6_PCODE_WRITE_RC6VIDS 0x4 |
| 6076 | #define GEN6_PCODE_READ_RC6VIDS 0x5 | |
| 515b2392 PZ |
6077 | #define GEN6_PCODE_READ_D_COMP 0x10 |
| 6078 | #define GEN6_PCODE_WRITE_D_COMP 0x11 | |
| 7083e050 BW |
6079 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
| 6080 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) | |
| 2a114cc1 | 6081 | #define DISPLAY_IPS_CONTROL 0x19 |
| 93ee2920 | 6082 | #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A |
| 8fd26859 | 6083 | #define GEN6_PCODE_DATA 0x138128 |
| 23b2f8bb | 6084 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
| 3ebecd07 | 6085 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
| dddab346 | 6086 | #define GEN6_PCODE_DATA1 0x13812C |
| 8fd26859 | 6087 | |
| 2af30a5c PB |
6088 | #define GEN9_PCODE_READ_MEM_LATENCY 0x6 |
| 6089 | #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF | |
| 6090 | #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 | |
| 6091 | #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 | |
| 6092 | #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 | |
| 6093 | ||
| 4d85529d BW |
6094 | #define GEN6_GT_CORE_STATUS 0x138060 |
| 6095 | #define GEN6_CORE_CPD_STATE_MASK (7<<4) | |
| 6096 | #define GEN6_RCn_MASK 7 | |
| 6097 | #define GEN6_RC0 0 | |
| 6098 | #define GEN6_RC3 2 | |
| 6099 | #define GEN6_RC6 3 | |
| 6100 | #define GEN6_RC7 4 | |
| 6101 | ||
| e3689190 BW |
6102 | #define GEN7_MISCCPCTL (0x9424) |
| 6103 | #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) | |
| 6104 | ||
| 6105 | /* IVYBRIDGE DPF */ | |
| 6106 | #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ | |
| 35a85ac6 | 6107 | #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ |
| e3689190 BW |
6108 | #define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) |
| 6109 | #define GEN7_PARITY_ERROR_VALID (1<<13) | |
| 6110 | #define GEN7_L3CDERRST1_BANK_MASK (3<<11) | |
| 6111 | #define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) | |
| 6112 | #define GEN7_PARITY_ERROR_ROW(reg) \ | |
| 6113 | ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) | |
| 6114 | #define GEN7_PARITY_ERROR_BANK(reg) \ | |
| 6115 | ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) | |
| 6116 | #define GEN7_PARITY_ERROR_SUBBANK(reg) \ | |
| 6117 | ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) | |
| 6118 | #define GEN7_L3CDERRST1_ENABLE (1<<7) | |
| 6119 | ||
| b9524a1e | 6120 | #define GEN7_L3LOG_BASE 0xB070 |
| 35a85ac6 | 6121 | #define HSW_L3LOG_BASE_SLICE1 0xB270 |
| b9524a1e BW |
6122 | #define GEN7_L3LOG_SIZE 0x80 |
| 6123 | ||
| 12f3382b JB |
6124 | #define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ |
| 6125 | #define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 | |
| 6126 | #define GEN7_MAX_PS_THREAD_DEP (8<<12) | |
| 4c2e7a5f | 6127 | #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) |
| 12f3382b JB |
6128 | #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) |
| 6129 | ||
| 3ca5da43 DL |
6130 | #define GEN9_HALF_SLICE_CHICKEN5 0xe188 |
| 6131 | #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) | |
| 6132 | ||
| c8966e10 KG |
6133 | #define GEN8_ROW_CHICKEN 0xe4f0 |
| 6134 | #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) | |
| 1411e6a5 | 6135 | #define STALL_DOP_GATING_DISABLE (1<<5) |
| c8966e10 | 6136 | |
| 8ab43976 JB |
6137 | #define GEN7_ROW_CHICKEN2 0xe4f4 |
| 6138 | #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 | |
| 6139 | #define DOP_CLOCK_GATING_DISABLE (1<<0) | |
| 6140 | ||
| f3fc4884 FJ |
6141 | #define HSW_ROW_CHICKEN3 0xe49c |
| 6142 | #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) | |
| 6143 | ||
| fd392b60 BW |
6144 | #define HALF_SLICE_CHICKEN3 0xe184 |
| 6145 | #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) | |
| bf66347c | 6146 | #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) |
| fd392b60 | 6147 | |
| c46f111f | 6148 | /* Audio */ |
| 5c969aa7 | 6149 | #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) |
| c46f111f JN |
6150 | #define INTEL_AUDIO_DEVCL 0x808629FB |
| 6151 | #define INTEL_AUDIO_DEVBLC 0x80862801 | |
| 6152 | #define INTEL_AUDIO_DEVCTG 0x80862802 | |
| e0dac65e WF |
6153 | |
| 6154 | #define G4X_AUD_CNTL_ST 0x620B4 | |
| c46f111f JN |
6155 | #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) |
| 6156 | #define G4X_ELDV_DEVCTG (1 << 14) | |
| 6157 | #define G4X_ELD_ADDR_MASK (0xf << 5) | |
| 6158 | #define G4X_ELD_ACK (1 << 4) | |
| e0dac65e WF |
6159 | #define G4X_HDMIW_HDMIEDID 0x6210C |
| 6160 | ||
| c46f111f JN |
6161 | #define _IBX_HDMIW_HDMIEDID_A 0xE2050 |
| 6162 | #define _IBX_HDMIW_HDMIEDID_B 0xE2150 | |
| 9b138a83 | 6163 | #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6164 | _IBX_HDMIW_HDMIEDID_A, \ |
| 6165 | _IBX_HDMIW_HDMIEDID_B) | |
| 6166 | #define _IBX_AUD_CNTL_ST_A 0xE20B4 | |
| 6167 | #define _IBX_AUD_CNTL_ST_B 0xE21B4 | |
| 9b138a83 | 6168 | #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6169 | _IBX_AUD_CNTL_ST_A, \ |
| 6170 | _IBX_AUD_CNTL_ST_B) | |
| 6171 | #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) | |
| 6172 | #define IBX_ELD_ADDRESS_MASK (0x1f << 5) | |
| 6173 | #define IBX_ELD_ACK (1 << 4) | |
| 1202b4c6 | 6174 | #define IBX_AUD_CNTL_ST2 0xE20C0 |
| 82910ac6 JN |
6175 | #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) |
| 6176 | #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) | |
| 1202b4c6 | 6177 | |
| c46f111f JN |
6178 | #define _CPT_HDMIW_HDMIEDID_A 0xE5050 |
| 6179 | #define _CPT_HDMIW_HDMIEDID_B 0xE5150 | |
| 9b138a83 | 6180 | #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6181 | _CPT_HDMIW_HDMIEDID_A, \ |
| 6182 | _CPT_HDMIW_HDMIEDID_B) | |
| 6183 | #define _CPT_AUD_CNTL_ST_A 0xE50B4 | |
| 6184 | #define _CPT_AUD_CNTL_ST_B 0xE51B4 | |
| 9b138a83 | 6185 | #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6186 | _CPT_AUD_CNTL_ST_A, \ |
| 6187 | _CPT_AUD_CNTL_ST_B) | |
| 1202b4c6 | 6188 | #define CPT_AUD_CNTRL_ST2 0xE50C0 |
| e0dac65e | 6189 | |
| c46f111f JN |
6190 | #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) |
| 6191 | #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) | |
| 9ca2fe73 | 6192 | #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6193 | _VLV_HDMIW_HDMIEDID_A, \ |
| 6194 | _VLV_HDMIW_HDMIEDID_B) | |
| 6195 | #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) | |
| 6196 | #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) | |
| 9ca2fe73 | 6197 | #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6198 | _VLV_AUD_CNTL_ST_A, \ |
| 6199 | _VLV_AUD_CNTL_ST_B) | |
| 9ca2fe73 ML |
6200 | #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) |
| 6201 | ||
| ae662d31 EA |
6202 | /* These are the 4 32-bit write offset registers for each stream |
| 6203 | * output buffer. It determines the offset from the | |
| 6204 | * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. | |
| 6205 | */ | |
| 6206 | #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) | |
| 6207 | ||
| c46f111f JN |
6208 | #define _IBX_AUD_CONFIG_A 0xe2000 |
| 6209 | #define _IBX_AUD_CONFIG_B 0xe2100 | |
| 9b138a83 | 6210 | #define IBX_AUD_CFG(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6211 | _IBX_AUD_CONFIG_A, \ |
| 6212 | _IBX_AUD_CONFIG_B) | |
| 6213 | #define _CPT_AUD_CONFIG_A 0xe5000 | |
| 6214 | #define _CPT_AUD_CONFIG_B 0xe5100 | |
| 9b138a83 | 6215 | #define CPT_AUD_CFG(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6216 | _CPT_AUD_CONFIG_A, \ |
| 6217 | _CPT_AUD_CONFIG_B) | |
| 6218 | #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) | |
| 6219 | #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) | |
| 9ca2fe73 | 6220 | #define VLV_AUD_CFG(pipe) _PIPE(pipe, \ |
| c46f111f JN |
6221 | _VLV_AUD_CONFIG_A, \ |
| 6222 | _VLV_AUD_CONFIG_B) | |
| 9ca2fe73 | 6223 | |
| b6daa025 WF |
6224 | #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) |
| 6225 | #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) | |
| 6226 | #define AUD_CONFIG_UPPER_N_SHIFT 20 | |
| c46f111f | 6227 | #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) |
| b6daa025 | 6228 | #define AUD_CONFIG_LOWER_N_SHIFT 4 |
| c46f111f | 6229 | #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) |
| b6daa025 | 6230 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 |
| 1a91510d JN |
6231 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) |
| 6232 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) | |
| 6233 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) | |
| 6234 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) | |
| 6235 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) | |
| 6236 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) | |
| 6237 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) | |
| 6238 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) | |
| 6239 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) | |
| 6240 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) | |
| 6241 | #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) | |
| b6daa025 WF |
6242 | #define AUD_CONFIG_DISABLE_NCTS (1 << 3) |
| 6243 | ||
| 9a78b6cc | 6244 | /* HSW Audio */ |
| c46f111f JN |
6245 | #define _HSW_AUD_CONFIG_A 0x65000 |
| 6246 | #define _HSW_AUD_CONFIG_B 0x65100 | |
| 6247 | #define HSW_AUD_CFG(pipe) _PIPE(pipe, \ | |
| 6248 | _HSW_AUD_CONFIG_A, \ | |
| 6249 | _HSW_AUD_CONFIG_B) | |
| 6250 | ||
| 6251 | #define _HSW_AUD_MISC_CTRL_A 0x65010 | |
| 6252 | #define _HSW_AUD_MISC_CTRL_B 0x65110 | |
| 6253 | #define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ | |
| 6254 | _HSW_AUD_MISC_CTRL_A, \ | |
| 6255 | _HSW_AUD_MISC_CTRL_B) | |
| 6256 | ||
| 6257 | #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 | |
| 6258 | #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 | |
| 6259 | #define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ | |
| 6260 | _HSW_AUD_DIP_ELD_CTRL_ST_A, \ | |
| 6261 | _HSW_AUD_DIP_ELD_CTRL_ST_B) | |
| 9a78b6cc WX |
6262 | |
| 6263 | /* Audio Digital Converter */ | |
| c46f111f JN |
6264 | #define _HSW_AUD_DIG_CNVT_1 0x65080 |
| 6265 | #define _HSW_AUD_DIG_CNVT_2 0x65180 | |
| 6266 | #define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ | |
| 6267 | _HSW_AUD_DIG_CNVT_1, \ | |
| 6268 | _HSW_AUD_DIG_CNVT_2) | |
| 6269 | #define DIP_PORT_SEL_MASK 0x3 | |
| 6270 | ||
| 6271 | #define _HSW_AUD_EDID_DATA_A 0x65050 | |
| 6272 | #define _HSW_AUD_EDID_DATA_B 0x65150 | |
| 6273 | #define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ | |
| 6274 | _HSW_AUD_EDID_DATA_A, \ | |
| 6275 | _HSW_AUD_EDID_DATA_B) | |
| 6276 | ||
| 6277 | #define HSW_AUD_PIPE_CONV_CFG 0x6507c | |
| 6278 | #define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 | |
| 82910ac6 JN |
6279 | #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) |
| 6280 | #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) | |
| 6281 | #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) | |
| 6282 | #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) | |
| 9a78b6cc | 6283 | |
| 9eb3a752 | 6284 | /* HSW Power Wells */ |
| fa42e23c PZ |
6285 | #define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ |
| 6286 | #define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ | |
| 6287 | #define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ | |
| 6288 | #define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ | |
| 6aedd1f5 PZ |
6289 | #define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) |
| 6290 | #define HSW_PWR_WELL_STATE_ENABLED (1<<30) | |
| 5e49cea6 | 6291 | #define HSW_PWR_WELL_CTL5 0x45410 |
| 9eb3a752 ED |
6292 | #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) |
| 6293 | #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) | |
| 5e49cea6 PZ |
6294 | #define HSW_PWR_WELL_FORCE_ON (1<<19) |
| 6295 | #define HSW_PWR_WELL_CTL6 0x45414 | |
| 9eb3a752 | 6296 | |
| e7e104c3 | 6297 | /* Per-pipe DDI Function Control */ |
| ad80a810 PZ |
6298 | #define TRANS_DDI_FUNC_CTL_A 0x60400 |
| 6299 | #define TRANS_DDI_FUNC_CTL_B 0x61400 | |
| 6300 | #define TRANS_DDI_FUNC_CTL_C 0x62400 | |
| 6301 | #define TRANS_DDI_FUNC_CTL_EDP 0x6F400 | |
| a57c774a AK |
6302 | #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) |
| 6303 | ||
| ad80a810 | 6304 | #define TRANS_DDI_FUNC_ENABLE (1<<31) |
| e7e104c3 | 6305 | /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ |
| ad80a810 | 6306 | #define TRANS_DDI_PORT_MASK (7<<28) |
| 26804afd | 6307 | #define TRANS_DDI_PORT_SHIFT 28 |
| ad80a810 PZ |
6308 | #define TRANS_DDI_SELECT_PORT(x) ((x)<<28) |
| 6309 | #define TRANS_DDI_PORT_NONE (0<<28) | |
| 6310 | #define TRANS_DDI_MODE_SELECT_MASK (7<<24) | |
| 6311 | #define TRANS_DDI_MODE_SELECT_HDMI (0<<24) | |
| 6312 | #define TRANS_DDI_MODE_SELECT_DVI (1<<24) | |
| 6313 | #define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) | |
| 6314 | #define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) | |
| 6315 | #define TRANS_DDI_MODE_SELECT_FDI (4<<24) | |
| 6316 | #define TRANS_DDI_BPC_MASK (7<<20) | |
| 6317 | #define TRANS_DDI_BPC_8 (0<<20) | |
| 6318 | #define TRANS_DDI_BPC_10 (1<<20) | |
| 6319 | #define TRANS_DDI_BPC_6 (2<<20) | |
| 6320 | #define TRANS_DDI_BPC_12 (3<<20) | |
| 6321 | #define TRANS_DDI_PVSYNC (1<<17) | |
| 6322 | #define TRANS_DDI_PHSYNC (1<<16) | |
| 6323 | #define TRANS_DDI_EDP_INPUT_MASK (7<<12) | |
| 6324 | #define TRANS_DDI_EDP_INPUT_A_ON (0<<12) | |
| 6325 | #define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) | |
| 6326 | #define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) | |
| 6327 | #define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) | |
| 01b887c3 | 6328 | #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) |
| ad80a810 | 6329 | #define TRANS_DDI_BFI_ENABLE (1<<4) |
| e7e104c3 | 6330 | |
| 0e87f667 ED |
6331 | /* DisplayPort Transport Control */ |
| 6332 | #define DP_TP_CTL_A 0x64040 | |
| 6333 | #define DP_TP_CTL_B 0x64140 | |
| 5e49cea6 PZ |
6334 | #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) |
| 6335 | #define DP_TP_CTL_ENABLE (1<<31) | |
| 6336 | #define DP_TP_CTL_MODE_SST (0<<27) | |
| 6337 | #define DP_TP_CTL_MODE_MST (1<<27) | |
| 01b887c3 | 6338 | #define DP_TP_CTL_FORCE_ACT (1<<25) |
| 0e87f667 | 6339 | #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) |
| 5e49cea6 | 6340 | #define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) |
| 0e87f667 ED |
6341 | #define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) |
| 6342 | #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) | |
| 6343 | #define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) | |
| d6c0d722 PZ |
6344 | #define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) |
| 6345 | #define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) | |
| 5e49cea6 | 6346 | #define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) |
| d6c0d722 | 6347 | #define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) |
| 0e87f667 | 6348 | |
| e411b2c1 ED |
6349 | /* DisplayPort Transport Status */ |
| 6350 | #define DP_TP_STATUS_A 0x64044 | |
| 6351 | #define DP_TP_STATUS_B 0x64144 | |
| 5e49cea6 | 6352 | #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) |
| 01b887c3 DA |
6353 | #define DP_TP_STATUS_IDLE_DONE (1<<25) |
| 6354 | #define DP_TP_STATUS_ACT_SENT (1<<24) | |
| 6355 | #define DP_TP_STATUS_MODE_STATUS_MST (1<<23) | |
| 6356 | #define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) | |
| 6357 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) | |
| 6358 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) | |
| 6359 | #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) | |
| e411b2c1 | 6360 | |
| 03f896a1 ED |
6361 | /* DDI Buffer Control */ |
| 6362 | #define DDI_BUF_CTL_A 0x64000 | |
| 6363 | #define DDI_BUF_CTL_B 0x64100 | |
| 5e49cea6 PZ |
6364 | #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) |
| 6365 | #define DDI_BUF_CTL_ENABLE (1<<31) | |
| c5fe6a06 | 6366 | #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) |
| 5e49cea6 | 6367 | #define DDI_BUF_EMP_MASK (0xf<<24) |
| 876a8cdf | 6368 | #define DDI_BUF_PORT_REVERSAL (1<<16) |
| 5e49cea6 | 6369 | #define DDI_BUF_IS_IDLE (1<<7) |
| 79935fca | 6370 | #define DDI_A_4_LANES (1<<4) |
| 17aa6be9 | 6371 | #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) |
| 03f896a1 ED |
6372 | #define DDI_INIT_DISPLAY_DETECTED (1<<0) |
| 6373 | ||
| bb879a44 ED |
6374 | /* DDI Buffer Translations */ |
| 6375 | #define DDI_BUF_TRANS_A 0x64E00 | |
| 6376 | #define DDI_BUF_TRANS_B 0x64E60 | |
| 5e49cea6 | 6377 | #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) |
| bb879a44 | 6378 | |
| 7501a4d8 ED |
6379 | /* Sideband Interface (SBI) is programmed indirectly, via |
| 6380 | * SBI_ADDR, which contains the register offset; and SBI_DATA, | |
| 6381 | * which contains the payload */ | |
| 5e49cea6 PZ |
6382 | #define SBI_ADDR 0xC6000 |
| 6383 | #define SBI_DATA 0xC6004 | |
| 7501a4d8 | 6384 | #define SBI_CTL_STAT 0xC6008 |
| 988d6ee8 PZ |
6385 | #define SBI_CTL_DEST_ICLK (0x0<<16) |
| 6386 | #define SBI_CTL_DEST_MPHY (0x1<<16) | |
| 6387 | #define SBI_CTL_OP_IORD (0x2<<8) | |
| 6388 | #define SBI_CTL_OP_IOWR (0x3<<8) | |
| 7501a4d8 ED |
6389 | #define SBI_CTL_OP_CRRD (0x6<<8) |
| 6390 | #define SBI_CTL_OP_CRWR (0x7<<8) | |
| 6391 | #define SBI_RESPONSE_FAIL (0x1<<1) | |
| 5e49cea6 PZ |
6392 | #define SBI_RESPONSE_SUCCESS (0x0<<1) |
| 6393 | #define SBI_BUSY (0x1<<0) | |
| 6394 | #define SBI_READY (0x0<<0) | |
| 52f025ef | 6395 | |
| ccf1c867 | 6396 | /* SBI offsets */ |
| 5e49cea6 | 6397 | #define SBI_SSCDIVINTPHASE6 0x0600 |
| ccf1c867 ED |
6398 | #define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) |
| 6399 | #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) | |
| 6400 | #define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) | |
| 6401 | #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) | |
| 5e49cea6 | 6402 | #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) |
| ccf1c867 | 6403 | #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) |
| 5e49cea6 | 6404 | #define SBI_SSCCTL 0x020c |
| ccf1c867 | 6405 | #define SBI_SSCCTL6 0x060C |
| dde86e2d | 6406 | #define SBI_SSCCTL_PATHALT (1<<3) |
| 5e49cea6 | 6407 | #define SBI_SSCCTL_DISABLE (1<<0) |
| ccf1c867 ED |
6408 | #define SBI_SSCAUXDIV6 0x0610 |
| 6409 | #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) | |
| 5e49cea6 | 6410 | #define SBI_DBUFF0 0x2a00 |
| 2fa86a1f PZ |
6411 | #define SBI_GEN0 0x1f00 |
| 6412 | #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) | |
| ccf1c867 | 6413 | |
| 52f025ef | 6414 | /* LPT PIXCLK_GATE */ |
| 5e49cea6 | 6415 | #define PIXCLK_GATE 0xC6020 |
| 745ca3be PZ |
6416 | #define PIXCLK_GATE_UNGATE (1<<0) |
| 6417 | #define PIXCLK_GATE_GATE (0<<0) | |
| 52f025ef | 6418 | |
| e93ea06a | 6419 | /* SPLL */ |
| 5e49cea6 | 6420 | #define SPLL_CTL 0x46020 |
| e93ea06a | 6421 | #define SPLL_PLL_ENABLE (1<<31) |
| 39bc66c9 DL |
6422 | #define SPLL_PLL_SSC (1<<28) |
| 6423 | #define SPLL_PLL_NON_SSC (2<<28) | |
| 11578553 JB |
6424 | #define SPLL_PLL_LCPLL (3<<28) |
| 6425 | #define SPLL_PLL_REF_MASK (3<<28) | |
| 5e49cea6 PZ |
6426 | #define SPLL_PLL_FREQ_810MHz (0<<26) |
| 6427 | #define SPLL_PLL_FREQ_1350MHz (1<<26) | |
| 11578553 JB |
6428 | #define SPLL_PLL_FREQ_2700MHz (2<<26) |
| 6429 | #define SPLL_PLL_FREQ_MASK (3<<26) | |
| e93ea06a | 6430 | |
| 4dffc404 | 6431 | /* WRPLL */ |
| 5e49cea6 PZ |
6432 | #define WRPLL_CTL1 0x46040 |
| 6433 | #define WRPLL_CTL2 0x46060 | |
| d452c5b6 | 6434 | #define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) |
| 5e49cea6 | 6435 | #define WRPLL_PLL_ENABLE (1<<31) |
| 114fe488 DV |
6436 | #define WRPLL_PLL_SSC (1<<28) |
| 6437 | #define WRPLL_PLL_NON_SSC (2<<28) | |
| 6438 | #define WRPLL_PLL_LCPLL (3<<28) | |
| 6439 | #define WRPLL_PLL_REF_MASK (3<<28) | |
| ef4d084f | 6440 | /* WRPLL divider programming */ |
| 5e49cea6 | 6441 | #define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) |
| 11578553 | 6442 | #define WRPLL_DIVIDER_REF_MASK (0xff) |
| 5e49cea6 | 6443 | #define WRPLL_DIVIDER_POST(x) ((x)<<8) |
| 11578553 JB |
6444 | #define WRPLL_DIVIDER_POST_MASK (0x3f<<8) |
| 6445 | #define WRPLL_DIVIDER_POST_SHIFT 8 | |
| 5e49cea6 | 6446 | #define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) |
| 11578553 JB |
6447 | #define WRPLL_DIVIDER_FB_SHIFT 16 |
| 6448 | #define WRPLL_DIVIDER_FB_MASK (0xff<<16) | |
| 4dffc404 | 6449 | |
| fec9181c ED |
6450 | /* Port clock selection */ |
| 6451 | #define PORT_CLK_SEL_A 0x46100 | |
| 6452 | #define PORT_CLK_SEL_B 0x46104 | |
| 5e49cea6 | 6453 | #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) |
| fec9181c ED |
6454 | #define PORT_CLK_SEL_LCPLL_2700 (0<<29) |
| 6455 | #define PORT_CLK_SEL_LCPLL_1350 (1<<29) | |
| 6456 | #define PORT_CLK_SEL_LCPLL_810 (2<<29) | |
| 5e49cea6 | 6457 | #define PORT_CLK_SEL_SPLL (3<<29) |
| 716c2e55 | 6458 | #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) |
| fec9181c ED |
6459 | #define PORT_CLK_SEL_WRPLL1 (4<<29) |
| 6460 | #define PORT_CLK_SEL_WRPLL2 (5<<29) | |
| 6441ab5f | 6461 | #define PORT_CLK_SEL_NONE (7<<29) |
| 11578553 | 6462 | #define PORT_CLK_SEL_MASK (7<<29) |
| fec9181c | 6463 | |
| bb523fc0 PZ |
6464 | /* Transcoder clock selection */ |
| 6465 | #define TRANS_CLK_SEL_A 0x46140 | |
| 6466 | #define TRANS_CLK_SEL_B 0x46144 | |
| 6467 | #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) | |
| 6468 | /* For each transcoder, we need to select the corresponding port clock */ | |
| 6469 | #define TRANS_CLK_SEL_DISABLED (0x0<<29) | |
| 6470 | #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) | |
| fec9181c | 6471 | |
| a57c774a AK |
6472 | #define TRANSA_MSA_MISC 0x60410 |
| 6473 | #define TRANSB_MSA_MISC 0x61410 | |
| 6474 | #define TRANSC_MSA_MISC 0x62410 | |
| 6475 | #define TRANS_EDP_MSA_MISC 0x6f410 | |
| 6476 | #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) | |
| 6477 | ||
| c9809791 PZ |
6478 | #define TRANS_MSA_SYNC_CLK (1<<0) |
| 6479 | #define TRANS_MSA_6_BPC (0<<5) | |
| 6480 | #define TRANS_MSA_8_BPC (1<<5) | |
| 6481 | #define TRANS_MSA_10_BPC (2<<5) | |
| 6482 | #define TRANS_MSA_12_BPC (3<<5) | |
| 6483 | #define TRANS_MSA_16_BPC (4<<5) | |
| dae84799 | 6484 | |
| 90e8d31c | 6485 | /* LCPLL Control */ |
| 5e49cea6 | 6486 | #define LCPLL_CTL 0x130040 |
| 90e8d31c ED |
6487 | #define LCPLL_PLL_DISABLE (1<<31) |
| 6488 | #define LCPLL_PLL_LOCK (1<<30) | |
| 79f689aa PZ |
6489 | #define LCPLL_CLK_FREQ_MASK (3<<26) |
| 6490 | #define LCPLL_CLK_FREQ_450 (0<<26) | |
| e39bf98a PZ |
6491 | #define LCPLL_CLK_FREQ_54O_BDW (1<<26) |
| 6492 | #define LCPLL_CLK_FREQ_337_5_BDW (2<<26) | |
| 6493 | #define LCPLL_CLK_FREQ_675_BDW (3<<26) | |
| 5e49cea6 | 6494 | #define LCPLL_CD_CLOCK_DISABLE (1<<25) |
| 90e8d31c | 6495 | #define LCPLL_CD2X_CLOCK_DISABLE (1<<23) |
| be256dc7 | 6496 | #define LCPLL_POWER_DOWN_ALLOW (1<<22) |
| 79f689aa | 6497 | #define LCPLL_CD_SOURCE_FCLK (1<<21) |
| be256dc7 PZ |
6498 | #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) |
| 6499 | ||
| 326ac39b S |
6500 | /* |
| 6501 | * SKL Clocks | |
| 6502 | */ | |
| 6503 | ||
| 6504 | /* CDCLK_CTL */ | |
| 6505 | #define CDCLK_CTL 0x46000 | |
| 6506 | #define CDCLK_FREQ_SEL_MASK (3<<26) | |
| 6507 | #define CDCLK_FREQ_450_432 (0<<26) | |
| 6508 | #define CDCLK_FREQ_540 (1<<26) | |
| 6509 | #define CDCLK_FREQ_337_308 (2<<26) | |
| 6510 | #define CDCLK_FREQ_675_617 (3<<26) | |
| 6511 | #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) | |
| 6512 | ||
| 6513 | /* LCPLL_CTL */ | |
| 6514 | #define LCPLL1_CTL 0x46010 | |
| 6515 | #define LCPLL2_CTL 0x46014 | |
| 6516 | #define LCPLL_PLL_ENABLE (1<<31) | |
| 6517 | ||
| 6518 | /* DPLL control1 */ | |
| 6519 | #define DPLL_CTRL1 0x6C058 | |
| 6520 | #define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5)) | |
| 6521 | #define DPLL_CTRL1_SSC(id) (1<<((id)*6+4)) | |
| 6522 | #define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1)) | |
| 540e732c | 6523 | #define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1) |
| 326ac39b S |
6524 | #define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) |
| 6525 | #define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6)) | |
| 6526 | #define DPLL_CRTL1_LINK_RATE_2700 0 | |
| 6527 | #define DPLL_CRTL1_LINK_RATE_1350 1 | |
| 6528 | #define DPLL_CRTL1_LINK_RATE_810 2 | |
| 6529 | #define DPLL_CRTL1_LINK_RATE_1620 3 | |
| 6530 | #define DPLL_CRTL1_LINK_RATE_1080 4 | |
| 6531 | #define DPLL_CRTL1_LINK_RATE_2160 5 | |
| 6532 | ||
| 6533 | /* DPLL control2 */ | |
| 6534 | #define DPLL_CTRL2 0x6C05C | |
| 6535 | #define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15)) | |
| 6536 | #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1)) | |
| 540e732c | 6537 | #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1) |
| 326ac39b S |
6538 | #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1)) |
| 6539 | #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3)) | |
| 6540 | ||
| 6541 | /* DPLL Status */ | |
| 6542 | #define DPLL_STATUS 0x6C060 | |
| 6543 | #define DPLL_LOCK(id) (1<<((id)*8)) | |
| 6544 | ||
| 6545 | /* DPLL cfg */ | |
| 6546 | #define DPLL1_CFGCR1 0x6C040 | |
| 6547 | #define DPLL2_CFGCR1 0x6C048 | |
| 6548 | #define DPLL3_CFGCR1 0x6C050 | |
| 6549 | #define DPLL_CFGCR1_FREQ_ENABLE (1<<31) | |
| 6550 | #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9) | |
| 6551 | #define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9) | |
| 6552 | #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) | |
| 6553 | ||
| 6554 | #define DPLL1_CFGCR2 0x6C044 | |
| 6555 | #define DPLL2_CFGCR2 0x6C04C | |
| 6556 | #define DPLL3_CFGCR2 0x6C054 | |
| 6557 | #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8) | |
| 6558 | #define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8) | |
| 6559 | #define DPLL_CFGCR2_QDIV_MODE(x) (x<<7) | |
| 6560 | #define DPLL_CFGCR2_KDIV_MASK (3<<5) | |
| 6561 | #define DPLL_CFGCR2_KDIV(x) (x<<5) | |
| 6562 | #define DPLL_CFGCR2_KDIV_5 (0<<5) | |
| 6563 | #define DPLL_CFGCR2_KDIV_2 (1<<5) | |
| 6564 | #define DPLL_CFGCR2_KDIV_3 (2<<5) | |
| 6565 | #define DPLL_CFGCR2_KDIV_1 (3<<5) | |
| 6566 | #define DPLL_CFGCR2_PDIV_MASK (7<<2) | |
| 6567 | #define DPLL_CFGCR2_PDIV(x) (x<<2) | |
| 6568 | #define DPLL_CFGCR2_PDIV_1 (0<<2) | |
| 6569 | #define DPLL_CFGCR2_PDIV_2 (1<<2) | |
| 6570 | #define DPLL_CFGCR2_PDIV_3 (2<<2) | |
| 6571 | #define DPLL_CFGCR2_PDIV_7 (4<<2) | |
| 6572 | #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) | |
| 6573 | ||
| 540e732c S |
6574 | #define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8) |
| 6575 | #define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8) | |
| 6576 | ||
| 9ccd5aeb PZ |
6577 | /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, |
| 6578 | * since on HSW we can't write to it using I915_WRITE. */ | |
| 6579 | #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) | |
| 6580 | #define D_COMP_BDW 0x138144 | |
| be256dc7 PZ |
6581 | #define D_COMP_RCOMP_IN_PROGRESS (1<<9) |
| 6582 | #define D_COMP_COMP_FORCE (1<<8) | |
| 6583 | #define D_COMP_COMP_DISABLE (1<<0) | |
| 90e8d31c | 6584 | |
| 69e94b7e ED |
6585 | /* Pipe WM_LINETIME - watermark line time */ |
| 6586 | #define PIPE_WM_LINETIME_A 0x45270 | |
| 6587 | #define PIPE_WM_LINETIME_B 0x45274 | |
| 5e49cea6 PZ |
6588 | #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ |
| 6589 | PIPE_WM_LINETIME_B) | |
| 6590 | #define PIPE_WM_LINETIME_MASK (0x1ff) | |
| 6591 | #define PIPE_WM_LINETIME_TIME(x) ((x)) | |
| 69e94b7e | 6592 | #define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) |
| 5e49cea6 | 6593 | #define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) |
| 96d6e350 ED |
6594 | |
| 6595 | /* SFUSE_STRAP */ | |
| 5e49cea6 | 6596 | #define SFUSE_STRAP 0xc2014 |
| 658ac4c6 DL |
6597 | #define SFUSE_STRAP_FUSE_LOCK (1<<13) |
| 6598 | #define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) | |
| 96d6e350 ED |
6599 | #define SFUSE_STRAP_DDIB_DETECTED (1<<2) |
| 6600 | #define SFUSE_STRAP_DDIC_DETECTED (1<<1) | |
| 6601 | #define SFUSE_STRAP_DDID_DETECTED (1<<0) | |
| 6602 | ||
| 801bcfff PZ |
6603 | #define WM_MISC 0x45260 |
| 6604 | #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) | |
| 6605 | ||
| 1544d9d5 ED |
6606 | #define WM_DBG 0x45280 |
| 6607 | #define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) | |
| 6608 | #define WM_DBG_DISALLOW_MAXFIFO (1<<1) | |
| 6609 | #define WM_DBG_DISALLOW_SPRITE (1<<2) | |
| 6610 | ||
| 86d3efce VS |
6611 | /* pipe CSC */ |
| 6612 | #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 | |
| 6613 | #define _PIPE_A_CSC_COEFF_BY 0x49014 | |
| 6614 | #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 | |
| 6615 | #define _PIPE_A_CSC_COEFF_BU 0x4901c | |
| 6616 | #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 | |
| 6617 | #define _PIPE_A_CSC_COEFF_BV 0x49024 | |
| 6618 | #define _PIPE_A_CSC_MODE 0x49028 | |
| 29a397ba VS |
6619 | #define CSC_BLACK_SCREEN_OFFSET (1 << 2) |
| 6620 | #define CSC_POSITION_BEFORE_GAMMA (1 << 1) | |
| 6621 | #define CSC_MODE_YUV_TO_RGB (1 << 0) | |
| 86d3efce VS |
6622 | #define _PIPE_A_CSC_PREOFF_HI 0x49030 |
| 6623 | #define _PIPE_A_CSC_PREOFF_ME 0x49034 | |
| 6624 | #define _PIPE_A_CSC_PREOFF_LO 0x49038 | |
| 6625 | #define _PIPE_A_CSC_POSTOFF_HI 0x49040 | |
| 6626 | #define _PIPE_A_CSC_POSTOFF_ME 0x49044 | |
| 6627 | #define _PIPE_A_CSC_POSTOFF_LO 0x49048 | |
| 6628 | ||
| 6629 | #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 | |
| 6630 | #define _PIPE_B_CSC_COEFF_BY 0x49114 | |
| 6631 | #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 | |
| 6632 | #define _PIPE_B_CSC_COEFF_BU 0x4911c | |
| 6633 | #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 | |
| 6634 | #define _PIPE_B_CSC_COEFF_BV 0x49124 | |
| 6635 | #define _PIPE_B_CSC_MODE 0x49128 | |
| 6636 | #define _PIPE_B_CSC_PREOFF_HI 0x49130 | |
| 6637 | #define _PIPE_B_CSC_PREOFF_ME 0x49134 | |
| 6638 | #define _PIPE_B_CSC_PREOFF_LO 0x49138 | |
| 6639 | #define _PIPE_B_CSC_POSTOFF_HI 0x49140 | |
| 6640 | #define _PIPE_B_CSC_POSTOFF_ME 0x49144 | |
| 6641 | #define _PIPE_B_CSC_POSTOFF_LO 0x49148 | |
| 6642 | ||
| 86d3efce VS |
6643 | #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) |
| 6644 | #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) | |
| 6645 | #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) | |
| 6646 | #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) | |
| 6647 | #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) | |
| 6648 | #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) | |
| 6649 | #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) | |
| 6650 | #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) | |
| 6651 | #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) | |
| 6652 | #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) | |
| 6653 | #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) | |
| 6654 | #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) | |
| 6655 | #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) | |
| 6656 | ||
| e7d7cad0 JN |
6657 | /* MIPI DSI registers */ |
| 6658 | ||
| 6659 | #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */ | |
| 3230bf14 JN |
6660 | |
| 6661 | #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) | |
| e7d7cad0 JN |
6662 | #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) |
| 6663 | #define MIPI_PORT_CTRL(port) _MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) | |
| 6664 | #define DPI_ENABLE (1 << 31) /* A + C */ | |
| 3230bf14 JN |
6665 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 |
| 6666 | #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) | |
| 6667 | #define DUAL_LINK_MODE_MASK (1 << 26) | |
| 6668 | #define DUAL_LINK_MODE_FRONT_BACK (0 << 26) | |
| 6669 | #define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) | |
| e7d7cad0 | 6670 | #define DITHERING_ENABLE (1 << 25) /* A + C */ |
| 3230bf14 JN |
6671 | #define FLOPPED_HSTX (1 << 23) |
| 6672 | #define DE_INVERT (1 << 19) /* XXX */ | |
| 6673 | #define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 | |
| 6674 | #define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) | |
| 6675 | #define AFE_LATCHOUT (1 << 17) | |
| 6676 | #define LP_OUTPUT_HOLD (1 << 16) | |
| e7d7cad0 JN |
6677 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 |
| 6678 | #define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) | |
| 6679 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 | |
| 6680 | #define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) | |
| 3230bf14 JN |
6681 | #define CSB_SHIFT 9 |
| 6682 | #define CSB_MASK (3 << 9) | |
| 6683 | #define CSB_20MHZ (0 << 9) | |
| 6684 | #define CSB_10MHZ (1 << 9) | |
| 6685 | #define CSB_40MHZ (2 << 9) | |
| 6686 | #define BANDGAP_MASK (1 << 8) | |
| 6687 | #define BANDGAP_PNW_CIRCUIT (0 << 8) | |
| 6688 | #define BANDGAP_LNC_CIRCUIT (1 << 8) | |
| e7d7cad0 JN |
6689 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 |
| 6690 | #define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) | |
| 6691 | #define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ | |
| 6692 | #define TEARING_EFFECT_SHIFT 2 /* A + C */ | |
| 3230bf14 JN |
6693 | #define TEARING_EFFECT_MASK (3 << 2) |
| 6694 | #define TEARING_EFFECT_OFF (0 << 2) | |
| 6695 | #define TEARING_EFFECT_DSI (1 << 2) | |
| 6696 | #define TEARING_EFFECT_GPIO (2 << 2) | |
| 6697 | #define LANE_CONFIGURATION_SHIFT 0 | |
| 6698 | #define LANE_CONFIGURATION_MASK (3 << 0) | |
| 6699 | #define LANE_CONFIGURATION_4LANE (0 << 0) | |
| 6700 | #define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) | |
| 6701 | #define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) | |
| 6702 | ||
| 6703 | #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) | |
| e7d7cad0 JN |
6704 | #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) |
| 6705 | #define MIPI_TEARING_CTRL(port) _MIPI_PORT(port, \ | |
| 6706 | _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) | |
| 3230bf14 JN |
6707 | #define TEARING_EFFECT_DELAY_SHIFT 0 |
| 6708 | #define TEARING_EFFECT_DELAY_MASK (0xffff << 0) | |
| 6709 | ||
| 6710 | /* XXX: all bits reserved */ | |
| 4ad83e94 | 6711 | #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) |
| 3230bf14 JN |
6712 | |
| 6713 | /* MIPI DSI Controller and D-PHY registers */ | |
| 6714 | ||
| 4ad83e94 | 6715 | #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) |
| e7d7cad0 JN |
6716 | #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) |
| 6717 | #define MIPI_DEVICE_READY(port) _MIPI_PORT(port, _MIPIA_DEVICE_READY, \ | |
| 6718 | _MIPIC_DEVICE_READY) | |
| 3230bf14 JN |
6719 | #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ |
| 6720 | #define ULPS_STATE_MASK (3 << 1) | |
| 6721 | #define ULPS_STATE_ENTER (2 << 1) | |
| 6722 | #define ULPS_STATE_EXIT (1 << 1) | |
| 6723 | #define ULPS_STATE_NORMAL_OPERATION (0 << 1) | |
| 6724 | #define DEVICE_READY (1 << 0) | |
| 6725 | ||
| 4ad83e94 | 6726 | #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) |
| e7d7cad0 JN |
6727 | #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) |
| 6728 | #define MIPI_INTR_STAT(port) _MIPI_PORT(port, _MIPIA_INTR_STAT, \ | |
| 6729 | _MIPIC_INTR_STAT) | |
| 4ad83e94 | 6730 | #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) |
| e7d7cad0 JN |
6731 | #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) |
| 6732 | #define MIPI_INTR_EN(port) _MIPI_PORT(port, _MIPIA_INTR_EN, \ | |
| 6733 | _MIPIC_INTR_EN) | |
| 3230bf14 JN |
6734 | #define TEARING_EFFECT (1 << 31) |
| 6735 | #define SPL_PKT_SENT_INTERRUPT (1 << 30) | |
| 6736 | #define GEN_READ_DATA_AVAIL (1 << 29) | |
| 6737 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) | |
| 6738 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) | |
| 6739 | #define RX_PROT_VIOLATION (1 << 26) | |
| 6740 | #define RX_INVALID_TX_LENGTH (1 << 25) | |
| 6741 | #define ACK_WITH_NO_ERROR (1 << 24) | |
| 6742 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) | |
| 6743 | #define LP_RX_TIMEOUT (1 << 22) | |
| 6744 | #define HS_TX_TIMEOUT (1 << 21) | |
| 6745 | #define DPI_FIFO_UNDERRUN (1 << 20) | |
| 6746 | #define LOW_CONTENTION (1 << 19) | |
| 6747 | #define HIGH_CONTENTION (1 << 18) | |
| 6748 | #define TXDSI_VC_ID_INVALID (1 << 17) | |
| 6749 | #define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) | |
| 6750 | #define TXCHECKSUM_ERROR (1 << 15) | |
| 6751 | #define TXECC_MULTIBIT_ERROR (1 << 14) | |
| 6752 | #define TXECC_SINGLE_BIT_ERROR (1 << 13) | |
| 6753 | #define TXFALSE_CONTROL_ERROR (1 << 12) | |
| 6754 | #define RXDSI_VC_ID_INVALID (1 << 11) | |
| 6755 | #define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) | |
| 6756 | #define RXCHECKSUM_ERROR (1 << 9) | |
| 6757 | #define RXECC_MULTIBIT_ERROR (1 << 8) | |
| 6758 | #define RXECC_SINGLE_BIT_ERROR (1 << 7) | |
| 6759 | #define RXFALSE_CONTROL_ERROR (1 << 6) | |
| 6760 | #define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) | |
| 6761 | #define RX_LP_TX_SYNC_ERROR (1 << 4) | |
| 6762 | #define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) | |
| 6763 | #define RXEOT_SYNC_ERROR (1 << 2) | |
| 6764 | #define RXSOT_SYNC_ERROR (1 << 1) | |
| 6765 | #define RXSOT_ERROR (1 << 0) | |
| 6766 | ||
| 4ad83e94 | 6767 | #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) |
| e7d7cad0 JN |
6768 | #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) |
| 6769 | #define MIPI_DSI_FUNC_PRG(port) _MIPI_PORT(port, _MIPIA_DSI_FUNC_PRG, \ | |
| 6770 | _MIPIC_DSI_FUNC_PRG) | |
| 3230bf14 JN |
6771 | #define CMD_MODE_DATA_WIDTH_MASK (7 << 13) |
| 6772 | #define CMD_MODE_NOT_SUPPORTED (0 << 13) | |
| 6773 | #define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) | |
| 6774 | #define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) | |
| 6775 | #define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) | |
| 6776 | #define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) | |
| 6777 | #define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) | |
| 6778 | #define VID_MODE_FORMAT_MASK (0xf << 7) | |
| 6779 | #define VID_MODE_NOT_SUPPORTED (0 << 7) | |
| 6780 | #define VID_MODE_FORMAT_RGB565 (1 << 7) | |
| 6781 | #define VID_MODE_FORMAT_RGB666 (2 << 7) | |
| 6782 | #define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) | |
| 6783 | #define VID_MODE_FORMAT_RGB888 (4 << 7) | |
| 6784 | #define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 | |
| 6785 | #define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) | |
| 6786 | #define VID_MODE_CHANNEL_NUMBER_SHIFT 3 | |
| 6787 | #define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) | |
| 6788 | #define DATA_LANES_PRG_REG_SHIFT 0 | |
| 6789 | #define DATA_LANES_PRG_REG_MASK (7 << 0) | |
| 6790 | ||
| 4ad83e94 | 6791 | #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) |
| e7d7cad0 JN |
6792 | #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) |
| 6793 | #define MIPI_HS_TX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_HS_TX_TIMEOUT, \ | |
| 6794 | _MIPIC_HS_TX_TIMEOUT) | |
| 3230bf14 JN |
6795 | #define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff |
| 6796 | ||
| 4ad83e94 | 6797 | #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) |
| e7d7cad0 JN |
6798 | #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) |
| 6799 | #define MIPI_LP_RX_TIMEOUT(port) _MIPI_PORT(port, _MIPIA_LP_RX_TIMEOUT, \ | |
| 6800 | _MIPIC_LP_RX_TIMEOUT) | |
| 3230bf14 JN |
6801 | #define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff |
| 6802 | ||
| 4ad83e94 | 6803 | #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) |
| e7d7cad0 JN |
6804 | #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) |
| 6805 | #define MIPI_TURN_AROUND_TIMEOUT(port) _MIPI_PORT(port, \ | |
| 6806 | _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) | |
| 3230bf14 JN |
6807 | #define TURN_AROUND_TIMEOUT_MASK 0x3f |
| 6808 | ||
| 4ad83e94 | 6809 | #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) |
| e7d7cad0 JN |
6810 | #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) |
| 6811 | #define MIPI_DEVICE_RESET_TIMER(port) _MIPI_PORT(port, \ | |
| 6812 | _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) | |
| 3230bf14 JN |
6813 | #define DEVICE_RESET_TIMER_MASK 0xffff |
| 6814 | ||
| 4ad83e94 | 6815 | #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) |
| e7d7cad0 JN |
6816 | #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) |
| 6817 | #define MIPI_DPI_RESOLUTION(port) _MIPI_PORT(port, _MIPIA_DPI_RESOLUTION, \ | |
| 6818 | _MIPIC_DPI_RESOLUTION) | |
| 3230bf14 JN |
6819 | #define VERTICAL_ADDRESS_SHIFT 16 |
| 6820 | #define VERTICAL_ADDRESS_MASK (0xffff << 16) | |
| 6821 | #define HORIZONTAL_ADDRESS_SHIFT 0 | |
| 6822 | #define HORIZONTAL_ADDRESS_MASK 0xffff | |
| 6823 | ||
| 4ad83e94 | 6824 | #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) |
| e7d7cad0 JN |
6825 | #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) |
| 6826 | #define MIPI_DBI_FIFO_THROTTLE(port) _MIPI_PORT(port, \ | |
| 6827 | _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) | |
| 3230bf14 JN |
6828 | #define DBI_FIFO_EMPTY_HALF (0 << 0) |
| 6829 | #define DBI_FIFO_EMPTY_QUARTER (1 << 0) | |
| 6830 | #define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) | |
| 6831 | ||
| 6832 | /* regs below are bits 15:0 */ | |
| 4ad83e94 | 6833 | #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) |
| e7d7cad0 JN |
6834 | #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) |
| 6835 | #define MIPI_HSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ | |
| 6836 | _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) | |
| 3230bf14 | 6837 | |
| 4ad83e94 | 6838 | #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) |
| e7d7cad0 JN |
6839 | #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) |
| 6840 | #define MIPI_HBP_COUNT(port) _MIPI_PORT(port, _MIPIA_HBP_COUNT, \ | |
| 6841 | _MIPIC_HBP_COUNT) | |
| 3230bf14 | 6842 | |
| 4ad83e94 | 6843 | #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) |
| e7d7cad0 JN |
6844 | #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) |
| 6845 | #define MIPI_HFP_COUNT(port) _MIPI_PORT(port, _MIPIA_HFP_COUNT, \ | |
| 6846 | _MIPIC_HFP_COUNT) | |
| 3230bf14 | 6847 | |
| 4ad83e94 | 6848 | #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) |
| e7d7cad0 JN |
6849 | #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) |
| 6850 | #define MIPI_HACTIVE_AREA_COUNT(port) _MIPI_PORT(port, \ | |
| 6851 | _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) | |
| 3230bf14 | 6852 | |
| 4ad83e94 | 6853 | #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) |
| e7d7cad0 JN |
6854 | #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) |
| 6855 | #define MIPI_VSYNC_PADDING_COUNT(port) _MIPI_PORT(port, \ | |
| 6856 | _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) | |
| 3230bf14 | 6857 | |
| 4ad83e94 | 6858 | #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) |
| e7d7cad0 JN |
6859 | #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) |
| 6860 | #define MIPI_VBP_COUNT(port) _MIPI_PORT(port, _MIPIA_VBP_COUNT, \ | |
| 6861 | _MIPIC_VBP_COUNT) | |
| 3230bf14 | 6862 | |
| 4ad83e94 | 6863 | #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) |
| e7d7cad0 JN |
6864 | #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) |
| 6865 | #define MIPI_VFP_COUNT(port) _MIPI_PORT(port, _MIPIA_VFP_COUNT, \ | |
| 6866 | _MIPIC_VFP_COUNT) | |
| 3230bf14 | 6867 | |
| 4ad83e94 | 6868 | #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) |
| e7d7cad0 JN |
6869 | #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) |
| 6870 | #define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MIPI_PORT(port, \ | |
| 6871 | _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) | |
| 4ad83e94 | 6872 | |
| 3230bf14 JN |
6873 | /* regs above are bits 15:0 */ |
| 6874 | ||
| 4ad83e94 | 6875 | #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) |
| e7d7cad0 JN |
6876 | #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) |
| 6877 | #define MIPI_DPI_CONTROL(port) _MIPI_PORT(port, _MIPIA_DPI_CONTROL, \ | |
| 6878 | _MIPIC_DPI_CONTROL) | |
| 3230bf14 JN |
6879 | #define DPI_LP_MODE (1 << 6) |
| 6880 | #define BACKLIGHT_OFF (1 << 5) | |
| 6881 | #define BACKLIGHT_ON (1 << 4) | |
| 6882 | #define COLOR_MODE_OFF (1 << 3) | |
| 6883 | #define COLOR_MODE_ON (1 << 2) | |
| 6884 | #define TURN_ON (1 << 1) | |
| 6885 | #define SHUTDOWN (1 << 0) | |
| 6886 | ||
| 4ad83e94 | 6887 | #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) |
| e7d7cad0 JN |
6888 | #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) |
| 6889 | #define MIPI_DPI_DATA(port) _MIPI_PORT(port, _MIPIA_DPI_DATA, \ | |
| 6890 | _MIPIC_DPI_DATA) | |
| 3230bf14 JN |
6891 | #define COMMAND_BYTE_SHIFT 0 |
| 6892 | #define COMMAND_BYTE_MASK (0x3f << 0) | |
| 6893 | ||
| 4ad83e94 | 6894 | #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) |
| e7d7cad0 JN |
6895 | #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) |
| 6896 | #define MIPI_INIT_COUNT(port) _MIPI_PORT(port, _MIPIA_INIT_COUNT, \ | |
| 6897 | _MIPIC_INIT_COUNT) | |
| 3230bf14 JN |
6898 | #define MASTER_INIT_TIMER_SHIFT 0 |
| 6899 | #define MASTER_INIT_TIMER_MASK (0xffff << 0) | |
| 6900 | ||
| 4ad83e94 | 6901 | #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) |
| e7d7cad0 JN |
6902 | #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) |
| 6903 | #define MIPI_MAX_RETURN_PKT_SIZE(port) _MIPI_PORT(port, \ | |
| 6904 | _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) | |
| 3230bf14 JN |
6905 | #define MAX_RETURN_PKT_SIZE_SHIFT 0 |
| 6906 | #define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) | |
| 6907 | ||
| 4ad83e94 | 6908 | #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) |
| e7d7cad0 JN |
6909 | #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) |
| 6910 | #define MIPI_VIDEO_MODE_FORMAT(port) _MIPI_PORT(port, \ | |
| 6911 | _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) | |
| 3230bf14 JN |
6912 | #define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) |
| 6913 | #define DISABLE_VIDEO_BTA (1 << 3) | |
| 6914 | #define IP_TG_CONFIG (1 << 2) | |
| 6915 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) | |
| 6916 | #define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) | |
| 6917 | #define VIDEO_MODE_BURST (3 << 0) | |
| 6918 | ||
| 4ad83e94 | 6919 | #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) |
| e7d7cad0 JN |
6920 | #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) |
| 6921 | #define MIPI_EOT_DISABLE(port) _MIPI_PORT(port, _MIPIA_EOT_DISABLE, \ | |
| 6922 | _MIPIC_EOT_DISABLE) | |
| 3230bf14 JN |
6923 | #define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) |
| 6924 | #define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) | |
| 6925 | #define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) | |
| 6926 | #define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) | |
| 6927 | #define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) | |
| 6928 | #define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) | |
| 6929 | #define CLOCKSTOP (1 << 1) | |
| 6930 | #define EOT_DISABLE (1 << 0) | |
| 6931 | ||
| 4ad83e94 | 6932 | #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) |
| e7d7cad0 JN |
6933 | #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) |
| 6934 | #define MIPI_LP_BYTECLK(port) _MIPI_PORT(port, _MIPIA_LP_BYTECLK, \ | |
| 6935 | _MIPIC_LP_BYTECLK) | |
| 3230bf14 JN |
6936 | #define LP_BYTECLK_SHIFT 0 |
| 6937 | #define LP_BYTECLK_MASK (0xffff << 0) | |
| 6938 | ||
| 6939 | /* bits 31:0 */ | |
| 4ad83e94 | 6940 | #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) |
| e7d7cad0 JN |
6941 | #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) |
| 6942 | #define MIPI_LP_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_LP_GEN_DATA, \ | |
| 6943 | _MIPIC_LP_GEN_DATA) | |
| 3230bf14 JN |
6944 | |
| 6945 | /* bits 31:0 */ | |
| 4ad83e94 | 6946 | #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) |
| e7d7cad0 JN |
6947 | #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) |
| 6948 | #define MIPI_HS_GEN_DATA(port) _MIPI_PORT(port, _MIPIA_HS_GEN_DATA, \ | |
| 6949 | _MIPIC_HS_GEN_DATA) | |
| 3230bf14 | 6950 | |
| 4ad83e94 | 6951 | #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) |
| e7d7cad0 JN |
6952 | #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) |
| 6953 | #define MIPI_LP_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_LP_GEN_CTRL, \ | |
| 6954 | _MIPIC_LP_GEN_CTRL) | |
| 4ad83e94 | 6955 | #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) |
| e7d7cad0 JN |
6956 | #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) |
| 6957 | #define MIPI_HS_GEN_CTRL(port) _MIPI_PORT(port, _MIPIA_HS_GEN_CTRL, \ | |
| 6958 | _MIPIC_HS_GEN_CTRL) | |
| 3230bf14 JN |
6959 | #define LONG_PACKET_WORD_COUNT_SHIFT 8 |
| 6960 | #define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) | |
| 6961 | #define SHORT_PACKET_PARAM_SHIFT 8 | |
| 6962 | #define SHORT_PACKET_PARAM_MASK (0xffff << 8) | |
| 6963 | #define VIRTUAL_CHANNEL_SHIFT 6 | |
| 6964 | #define VIRTUAL_CHANNEL_MASK (3 << 6) | |
| 6965 | #define DATA_TYPE_SHIFT 0 | |
| 6966 | #define DATA_TYPE_MASK (3f << 0) | |
| 6967 | /* data type values, see include/video/mipi_display.h */ | |
| 6968 | ||
| 4ad83e94 | 6969 | #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) |
| e7d7cad0 JN |
6970 | #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) |
| 6971 | #define MIPI_GEN_FIFO_STAT(port) _MIPI_PORT(port, _MIPIA_GEN_FIFO_STAT, \ | |
| 6972 | _MIPIC_GEN_FIFO_STAT) | |
| 3230bf14 JN |
6973 | #define DPI_FIFO_EMPTY (1 << 28) |
| 6974 | #define DBI_FIFO_EMPTY (1 << 27) | |
| 6975 | #define LP_CTRL_FIFO_EMPTY (1 << 26) | |
| 6976 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) | |
| 6977 | #define LP_CTRL_FIFO_FULL (1 << 24) | |
| 6978 | #define HS_CTRL_FIFO_EMPTY (1 << 18) | |
| 6979 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) | |
| 6980 | #define HS_CTRL_FIFO_FULL (1 << 16) | |
| 6981 | #define LP_DATA_FIFO_EMPTY (1 << 10) | |
| 6982 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) | |
| 6983 | #define LP_DATA_FIFO_FULL (1 << 8) | |
| 6984 | #define HS_DATA_FIFO_EMPTY (1 << 2) | |
| 6985 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) | |
| 6986 | #define HS_DATA_FIFO_FULL (1 << 0) | |
| 6987 | ||
| 4ad83e94 | 6988 | #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) |
| e7d7cad0 JN |
6989 | #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) |
| 6990 | #define MIPI_HS_LP_DBI_ENABLE(port) _MIPI_PORT(port, \ | |
| 6991 | _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) | |
| 3230bf14 JN |
6992 | #define DBI_HS_LP_MODE_MASK (1 << 0) |
| 6993 | #define DBI_LP_MODE (1 << 0) | |
| 6994 | #define DBI_HS_MODE (0 << 0) | |
| 6995 | ||
| 4ad83e94 | 6996 | #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) |
| e7d7cad0 JN |
6997 | #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) |
| 6998 | #define MIPI_DPHY_PARAM(port) _MIPI_PORT(port, _MIPIA_DPHY_PARAM, \ | |
| 6999 | _MIPIC_DPHY_PARAM) | |
| 3230bf14 JN |
7000 | #define EXIT_ZERO_COUNT_SHIFT 24 |
| 7001 | #define EXIT_ZERO_COUNT_MASK (0x3f << 24) | |
| 7002 | #define TRAIL_COUNT_SHIFT 16 | |
| 7003 | #define TRAIL_COUNT_MASK (0x1f << 16) | |
| 7004 | #define CLK_ZERO_COUNT_SHIFT 8 | |
| 7005 | #define CLK_ZERO_COUNT_MASK (0xff << 8) | |
| 7006 | #define PREPARE_COUNT_SHIFT 0 | |
| 7007 | #define PREPARE_COUNT_MASK (0x3f << 0) | |
| 7008 | ||
| 7009 | /* bits 31:0 */ | |
| 4ad83e94 | 7010 | #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) |
| e7d7cad0 JN |
7011 | #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) |
| 7012 | #define MIPI_DBI_BW_CTRL(port) _MIPI_PORT(port, _MIPIA_DBI_BW_CTRL, \ | |
| 7013 | _MIPIC_DBI_BW_CTRL) | |
| 3230bf14 | 7014 | |
| 4ad83e94 SS |
7015 | #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
| 7016 | + 0xb088) | |
| e7d7cad0 | 7017 | #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ |
| 4ad83e94 | 7018 | + 0xb888) |
| e7d7cad0 JN |
7019 | #define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MIPI_PORT(port, \ |
| 7020 | _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) | |
| 3230bf14 JN |
7021 | #define LP_HS_SSW_CNT_SHIFT 16 |
| 7022 | #define LP_HS_SSW_CNT_MASK (0xffff << 16) | |
| 7023 | #define HS_LP_PWR_SW_CNT_SHIFT 0 | |
| 7024 | #define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) | |
| 7025 | ||
| 4ad83e94 | 7026 | #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) |
| e7d7cad0 JN |
7027 | #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) |
| 7028 | #define MIPI_STOP_STATE_STALL(port) _MIPI_PORT(port, \ | |
| 7029 | _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) | |
| 3230bf14 JN |
7030 | #define STOP_STATE_STALL_COUNTER_SHIFT 0 |
| 7031 | #define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) | |
| 7032 | ||
| 4ad83e94 | 7033 | #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) |
| e7d7cad0 JN |
7034 | #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) |
| 7035 | #define MIPI_INTR_STAT_REG_1(port) _MIPI_PORT(port, \ | |
| 7036 | _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) | |
| 4ad83e94 | 7037 | #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) |
| e7d7cad0 JN |
7038 | #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) |
| 7039 | #define MIPI_INTR_EN_REG_1(port) _MIPI_PORT(port, _MIPIA_INTR_EN_REG_1, \ | |
| 7040 | _MIPIC_INTR_EN_REG_1) | |
| 3230bf14 JN |
7041 | #define RX_CONTENTION_DETECTED (1 << 0) |
| 7042 | ||
| 7043 | /* XXX: only pipe A ?!? */ | |
| 4ad83e94 | 7044 | #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) |
| 3230bf14 JN |
7045 | #define DBI_TYPEC_ENABLE (1 << 31) |
| 7046 | #define DBI_TYPEC_WIP (1 << 30) | |
| 7047 | #define DBI_TYPEC_OPTION_SHIFT 28 | |
| 7048 | #define DBI_TYPEC_OPTION_MASK (3 << 28) | |
| 7049 | #define DBI_TYPEC_FREQ_SHIFT 24 | |
| 7050 | #define DBI_TYPEC_FREQ_MASK (0xf << 24) | |
| 7051 | #define DBI_TYPEC_OVERRIDE (1 << 8) | |
| 7052 | #define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 | |
| 7053 | #define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) | |
| 7054 | ||
| 7055 | ||
| 7056 | /* MIPI adapter registers */ | |
| 7057 | ||
| 4ad83e94 | 7058 | #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) |
| e7d7cad0 JN |
7059 | #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) |
| 7060 | #define MIPI_CTRL(port) _MIPI_PORT(port, _MIPIA_CTRL, \ | |
| 7061 | _MIPIC_CTRL) | |
| 3230bf14 JN |
7062 | #define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ |
| 7063 | #define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) | |
| 7064 | #define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) | |
| 7065 | #define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) | |
| 7066 | #define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) | |
| 7067 | #define READ_REQUEST_PRIORITY_SHIFT 3 | |
| 7068 | #define READ_REQUEST_PRIORITY_MASK (3 << 3) | |
| 7069 | #define READ_REQUEST_PRIORITY_LOW (0 << 3) | |
| 7070 | #define READ_REQUEST_PRIORITY_HIGH (3 << 3) | |
| 7071 | #define RGB_FLIP_TO_BGR (1 << 2) | |
| 7072 | ||
| 4ad83e94 | 7073 | #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) |
| e7d7cad0 JN |
7074 | #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) |
| 7075 | #define MIPI_DATA_ADDRESS(port) _MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \ | |
| 7076 | _MIPIC_DATA_ADDRESS) | |
| 3230bf14 JN |
7077 | #define DATA_MEM_ADDRESS_SHIFT 5 |
| 7078 | #define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
| 7079 | #define DATA_VALID (1 << 0) | |
| 7080 | ||
| 4ad83e94 | 7081 | #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) |
| e7d7cad0 JN |
7082 | #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) |
| 7083 | #define MIPI_DATA_LENGTH(port) _MIPI_PORT(port, _MIPIA_DATA_LENGTH, \ | |
| 7084 | _MIPIC_DATA_LENGTH) | |
| 3230bf14 JN |
7085 | #define DATA_LENGTH_SHIFT 0 |
| 7086 | #define DATA_LENGTH_MASK (0xfffff << 0) | |
| 7087 | ||
| 4ad83e94 | 7088 | #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) |
| e7d7cad0 JN |
7089 | #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) |
| 7090 | #define MIPI_COMMAND_ADDRESS(port) _MIPI_PORT(port, \ | |
| 7091 | _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) | |
| 3230bf14 JN |
7092 | #define COMMAND_MEM_ADDRESS_SHIFT 5 |
| 7093 | #define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) | |
| 7094 | #define AUTO_PWG_ENABLE (1 << 2) | |
| 7095 | #define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) | |
| 7096 | #define COMMAND_VALID (1 << 0) | |
| 7097 | ||
| 4ad83e94 | 7098 | #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) |
| e7d7cad0 JN |
7099 | #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) |
| 7100 | #define MIPI_COMMAND_LENGTH(port) _MIPI_PORT(port, _MIPIA_COMMAND_LENGTH, \ | |
| 7101 | _MIPIC_COMMAND_LENGTH) | |
| 3230bf14 JN |
7102 | #define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ |
| 7103 | #define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) | |
| 7104 | ||
| 4ad83e94 | 7105 | #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) |
| e7d7cad0 JN |
7106 | #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) |
| 7107 | #define MIPI_READ_DATA_RETURN(port, n) \ | |
| 7108 | (_MIPI_PORT(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) \ | |
| a2560a66 | 7109 | + 4 * (n)) /* n: 0...7 */ |
| 3230bf14 | 7110 | |
| 4ad83e94 | 7111 | #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) |
| e7d7cad0 JN |
7112 | #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) |
| 7113 | #define MIPI_READ_DATA_VALID(port) _MIPI_PORT(port, \ | |
| 7114 | _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) | |
| 3230bf14 JN |
7115 | #define READ_DATA_VALID(n) (1 << (n)) |
| 7116 | ||
| a57c774a | 7117 | /* For UMS only (deprecated): */ |
| 5c969aa7 DL |
7118 | #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) |
| 7119 | #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) | |
| a57c774a | 7120 | |
| 585fb111 | 7121 | #endif /* _I915_REG_H_ */ |