Merge remote-tracking branch 'omap_dss2/for-next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_suspend.c
CommitLineData
317c35d1
JB
1/*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
760285e7
DH
27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
f0217c42 29#include "intel_drv.h"
5e5b7fa2 30#include "i915_reg.h"
317c35d1 31
d70bed19 32static void i915_save_display(struct drm_device *dev)
fccdaba4 33{
fac5e23e 34 struct drm_i915_private *dev_priv = to_i915(dev);
fccdaba4
ZY
35
36 /* Display arbitration control */
8de0add7
PZ
37 if (INTEL_INFO(dev)->gen <= 4)
38 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
fccdaba4 39
768cf7f4
VS
40 /* save FBC interval */
41 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
42 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
317c35d1
JB
43}
44
d70bed19 45static void i915_restore_display(struct drm_device *dev)
317c35d1 46{
fac5e23e 47 struct drm_i915_private *dev_priv = to_i915(dev);
461cba2d 48
881ee988 49 /* Display arbitration */
8de0add7
PZ
50 if (INTEL_INFO(dev)->gen <= 4)
51 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
317c35d1 52
a2c459ee 53 /* only restore FBC info on the platform that supports FBC*/
c937ab3e 54 intel_fbc_global_disable(dev_priv);
768cf7f4
VS
55
56 /* restore FBC interval */
57 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
58 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
a65e827d 59
8634bd4a 60 i915_redisable_vga(dev);
1341d655
BG
61}
62
63int i915_save_state(struct drm_device *dev)
64{
fac5e23e 65 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 66 struct pci_dev *pdev = dev_priv->drm.pdev;
1341d655
BG
67 int i;
68
d70bed19
KP
69 mutex_lock(&dev->struct_mutex);
70
1341d655
BG
71 i915_save_display(dev);
72
9f49c376 73 if (IS_GEN4(dev))
52a05c30 74 pci_read_config_word(pdev, GCDGMBUS,
9f49c376
JB
75 &dev_priv->regfile.saveGCDGMBUS);
76
1341d655 77 /* Cache mode state */
e8cde23b
JB
78 if (INTEL_INFO(dev)->gen < 7)
79 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
1341d655
BG
80
81 /* Memory Arbitration state */
f4c956ad 82 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
1341d655
BG
83
84 /* Scratch space */
85fa792b
VS
85 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
86 for (i = 0; i < 7; i++) {
87 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
88 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
89 }
90 for (i = 0; i < 3; i++)
91 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
92 } else if (IS_GEN2(dev_priv)) {
93 for (i = 0; i < 7; i++)
94 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
95 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
96 for (i = 0; i < 16; i++) {
97 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
98 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
99 }
100 for (i = 0; i < 3; i++)
101 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
1341d655 102 }
1341d655 103
d70bed19
KP
104 mutex_unlock(&dev->struct_mutex);
105
1341d655
BG
106 return 0;
107}
108
109int i915_restore_state(struct drm_device *dev)
110{
fac5e23e 111 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 112 struct pci_dev *pdev = dev_priv->drm.pdev;
1341d655
BG
113 int i;
114
d70bed19
KP
115 mutex_lock(&dev->struct_mutex);
116
19b2dbde 117 i915_gem_restore_fences(dev);
9f49c376
JB
118
119 if (IS_GEN4(dev))
52a05c30 120 pci_write_config_word(pdev, GCDGMBUS,
9f49c376 121 dev_priv->regfile.saveGCDGMBUS);
1341d655
BG
122 i915_restore_display(dev);
123
317c35d1 124 /* Cache mode state */
e8cde23b
JB
125 if (INTEL_INFO(dev)->gen < 7)
126 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
127 0xffff0000);
317c35d1
JB
128
129 /* Memory arbitration state */
f4c956ad 130 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
317c35d1 131
85fa792b
VS
132 /* Scratch space */
133 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
134 for (i = 0; i < 7; i++) {
135 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
136 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
137 }
138 for (i = 0; i < 3; i++)
139 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
140 } else if (IS_GEN2(dev_priv)) {
141 for (i = 0; i < 7; i++)
142 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
143 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
144 for (i = 0; i < 16; i++) {
145 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
146 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
147 }
148 for (i = 0; i < 3; i++)
149 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
317c35d1 150 }
317c35d1 151
d70bed19
KP
152 mutex_unlock(&dev->struct_mutex);
153
f899fc64 154 intel_i2c_reset(dev);
f0217c42 155
317c35d1
JB
156 return 0;
157}
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