[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_color.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 */

#include "intel_drv.h"

#define CTM_COEFF_SIGN	(1ULL << 63)

#define CTM_COEFF_1_0	(1ULL << 32)
#define CTM_COEFF_2_0	(CTM_COEFF_1_0 << 1)
#define CTM_COEFF_4_0	(CTM_COEFF_2_0 << 1)
#define CTM_COEFF_8_0	(CTM_COEFF_4_0 << 1)
#define CTM_COEFF_0_5	(CTM_COEFF_1_0 >> 1)
#define CTM_COEFF_0_25	(CTM_COEFF_0_5 >> 1)
#define CTM_COEFF_0_125	(CTM_COEFF_0_25 >> 1)

#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)

#define CTM_COEFF_NEGATIVE(coeff)	(((coeff) & CTM_COEFF_SIGN) != 0)
#define CTM_COEFF_ABS(coeff)		((coeff) & (CTM_COEFF_SIGN - 1))

#define LEGACY_LUT_LENGTH		(sizeof(struct drm_color_lut) * 256)

/*
 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
 * format). This macro takes the coefficient we want transformed and the
 * number of fractional bits.
 *
 * We only have a 9 bits precision window which slides depending on the value
 * of the CTM coefficient and we write the value from bit 3. We also round the
 * value.
 */
#define I9XX_CSC_COEFF_FP(coeff, fbits)	\
	(clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)

#define I9XX_CSC_COEFF_LIMITED_RANGE	\
	I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
#define I9XX_CSC_COEFF_1_0		\
	((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))

static bool crtc_state_is_legacy(struct drm_crtc_state *state)
{
	return !state->degamma_lut &&
		!state->ctm &&
		state->gamma_lut &&
		state->gamma_lut->length == LEGACY_LUT_LENGTH;
}

/*
 * When using limited range, multiply the matrix given by userspace by
 * the matrix that we would use for the limited range. We do the
 * multiplication in U2.30 format.
 */
static void ctm_mult_by_limited(uint64_t *result, int64_t *input)
{
	int i;

	for (i = 0; i < 9; i++)
		result[i] = 0;

	for (i = 0; i < 3; i++) {
		int64_t user_coeff = input[i * 3 + i];
		uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2;
		uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff),
					       0,
					       CTM_COEFF_4_0 - 1) >> 2;

		result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27;
		if (CTM_COEFF_NEGATIVE(user_coeff))
			result[i * 3 + i] |= CTM_COEFF_SIGN;
	}
}

/* Set up the pipe CSC unit. */
static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
{
	struct drm_crtc *crtc = crtc_state->crtc;
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int i, pipe = intel_crtc->pipe;
	uint16_t coeffs[9] = { 0, };
	struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);

	if (crtc_state->ctm) {
		struct drm_color_ctm *ctm =
			(struct drm_color_ctm *)crtc_state->ctm->data;
		uint64_t input[9] = { 0, };

		if (intel_crtc_state->limited_color_range) {
			ctm_mult_by_limited(input, ctm->matrix);
		} else {
			for (i = 0; i < ARRAY_SIZE(input); i++)
				input[i] = ctm->matrix[i];
		}

		/*
		 * Convert fixed point S31.32 input to format supported by the
		 * hardware.
		 */
		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
			uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];

			/*
			 * Clamp input value to min/max supported by
			 * hardware.
			 */
			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);

			/* sign bit */
			if (CTM_COEFF_NEGATIVE(input[i]))
				coeffs[i] |= 1 << 15;

			if (abs_coeff < CTM_COEFF_0_125)
				coeffs[i] |= (3 << 12) |
					I9XX_CSC_COEFF_FP(abs_coeff, 12);
			else if (abs_coeff < CTM_COEFF_0_25)
				coeffs[i] |= (2 << 12) |
					I9XX_CSC_COEFF_FP(abs_coeff, 11);
			else if (abs_coeff < CTM_COEFF_0_5)
				coeffs[i] |= (1 << 12) |
					I9XX_CSC_COEFF_FP(abs_coeff, 10);
			else if (abs_coeff < CTM_COEFF_1_0)
				coeffs[i] |= I9XX_CSC_COEFF_FP(abs_coeff, 9);
			else if (abs_coeff < CTM_COEFF_2_0)
				coeffs[i] |= (7 << 12) |
					I9XX_CSC_COEFF_FP(abs_coeff, 8);
			else
				coeffs[i] |= (6 << 12) |
					I9XX_CSC_COEFF_FP(abs_coeff, 7);
		}
	} else {
		/*
		 * Load an identity matrix if no coefficients are provided.
		 *
		 * TODO: Check what kind of values actually come out of the
		 * pipe with these coeff/postoff values and adjust to get the
		 * best accuracy. Perhaps we even need to take the bpc value
		 * into consideration.
		 */
		for (i = 0; i < 3; i++) {
			if (intel_crtc_state->limited_color_range)
				coeffs[i * 3 + i] =
					I9XX_CSC_COEFF_LIMITED_RANGE;
			else
				coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0;
		}
	}

	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);

	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);

	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);

	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);

	if (INTEL_INFO(dev)->gen > 6) {
		uint16_t postoff = 0;

		if (intel_crtc_state->limited_color_range)
			postoff = (16 * (1 << 12) / 255) & 0x1fff;

		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);

		I915_WRITE(PIPE_CSC_MODE(pipe), 0);
	} else {
		uint32_t mode = CSC_MODE_YUV_TO_RGB;

		if (intel_crtc_state->limited_color_range)
			mode |= CSC_BLACK_SCREEN_OFFSET;

		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
	}
}

/*
 * Set up the pipe CSC unit on CherryView.
 */
static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
{
	struct drm_crtc *crtc = state->crtc;
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	int pipe = to_intel_crtc(crtc)->pipe;
	uint32_t mode;

	if (state->ctm) {
		struct drm_color_ctm *ctm =
			(struct drm_color_ctm *) state->ctm->data;
		uint16_t coeffs[9] = { 0, };
		int i;

		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
			uint64_t abs_coeff =
				((1ULL << 63) - 1) & ctm->matrix[i];

			/* Round coefficient. */
			abs_coeff += 1 << (32 - 13);
			/* Clamp to hardware limits. */
			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);

			/* Write coefficients in S3.12 format. */
			if (ctm->matrix[i] & (1ULL << 63))
				coeffs[i] = 1 << 15;
			coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
			coeffs[i] |= (abs_coeff >> 20) & 0xfff;
		}

		I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
			   coeffs[1] << 16 | coeffs[0]);
		I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
			   coeffs[3] << 16 | coeffs[2]);
		I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
			   coeffs[5] << 16 | coeffs[4]);
		I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
			   coeffs[7] << 16 | coeffs[6]);
		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
	}

	mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
	if (!crtc_state_is_legacy(state)) {
		mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
			(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
	}
	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
}

void intel_color_set_csc(struct drm_crtc_state *crtc_state)
{
	struct drm_device *dev = crtc_state->crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);

	if (dev_priv->display.load_csc_matrix)
		dev_priv->display.load_csc_matrix(crtc_state);
}

/* Loads the legacy palette/gamma unit for the CRTC. */
static void i9xx_load_luts_internal(struct drm_crtc *crtc,
				    struct drm_property_blob *blob,
				    struct intel_crtc_state *crtc_state)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	enum pipe pipe = intel_crtc->pipe;
	int i;

	if (HAS_GMCH_DISPLAY(dev)) {
		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
			assert_dsi_pll_enabled(dev_priv);
		else
			assert_pll_enabled(dev_priv, pipe);
	}

	if (blob) {
		struct drm_color_lut *lut = (struct drm_color_lut *) blob->data;
		for (i = 0; i < 256; i++) {
			uint32_t word =
				(drm_color_lut_extract(lut[i].red, 8) << 16) |
				(drm_color_lut_extract(lut[i].green, 8) << 8) |
				drm_color_lut_extract(lut[i].blue, 8);

			if (HAS_GMCH_DISPLAY(dev))
				I915_WRITE(PALETTE(pipe, i), word);
			else
				I915_WRITE(LGC_PALETTE(pipe, i), word);
		}
	} else {
		for (i = 0; i < 256; i++) {
			uint32_t word = (i << 16) | (i << 8) | i;

			if (HAS_GMCH_DISPLAY(dev))
				I915_WRITE(PALETTE(pipe, i), word);
			else
				I915_WRITE(LGC_PALETTE(pipe, i), word);
		}
	}
}

static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
{
	i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
				to_intel_crtc_state(crtc_state));
}

/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
static void haswell_load_luts(struct drm_crtc_state *crtc_state)
{
	struct drm_crtc *crtc = crtc_state->crtc;
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_crtc_state *intel_crtc_state =
		to_intel_crtc_state(crtc_state);
	bool reenable_ips = false;

	/*
	 * Workaround : Do not read or write the pipe palette/gamma data while
	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
	 */
	if (IS_HASWELL(dev) && intel_crtc_state->ips_enabled &&
	    (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
		hsw_disable_ips(intel_crtc);
		reenable_ips = true;
	}

	intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);

	i9xx_load_luts(crtc_state);

	if (reenable_ips)
		hsw_enable_ips(intel_crtc);
}

/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
static void broadwell_load_luts(struct drm_crtc_state *state)
{
	struct drm_crtc *crtc = state->crtc;
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;

	if (crtc_state_is_legacy(state)) {
		haswell_load_luts(state);
		return;
	}

	I915_WRITE(PREC_PAL_INDEX(pipe),
		   PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);

	if (state->degamma_lut) {
		struct drm_color_lut *lut =
			(struct drm_color_lut *) state->degamma_lut->data;

		for (i = 0; i < lut_size; i++) {
			uint32_t word =
			drm_color_lut_extract(lut[i].red, 10) << 20 |
			drm_color_lut_extract(lut[i].green, 10) << 10 |
			drm_color_lut_extract(lut[i].blue, 10);

			I915_WRITE(PREC_PAL_DATA(pipe), word);
		}
	} else {
		for (i = 0; i < lut_size; i++) {
			uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);

			I915_WRITE(PREC_PAL_DATA(pipe),
				   (v << 20) | (v << 10) | v);
		}
	}

	if (state->gamma_lut) {
		struct drm_color_lut *lut =
			(struct drm_color_lut *) state->gamma_lut->data;

		for (i = 0; i < lut_size; i++) {
			uint32_t word =
			(drm_color_lut_extract(lut[i].red, 10) << 20) |
			(drm_color_lut_extract(lut[i].green, 10) << 10) |
			drm_color_lut_extract(lut[i].blue, 10);

			I915_WRITE(PREC_PAL_DATA(pipe), word);
		}

		/* Program the max register to clamp values > 1.0. */
		I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
			   drm_color_lut_extract(lut[i].red, 16));
		I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
			   drm_color_lut_extract(lut[i].green, 16));
		I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
			   drm_color_lut_extract(lut[i].blue, 16));
	} else {
		for (i = 0; i < lut_size; i++) {
			uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);

			I915_WRITE(PREC_PAL_DATA(pipe),
				   (v << 20) | (v << 10) | v);
		}

		I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
		I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
		I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
	}

	intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
	POSTING_READ(GAMMA_MODE(pipe));

	/*
	 * Reset the index, otherwise it prevents the legacy palette to be
	 * written properly.
	 */
	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
}

/* Loads the palette/gamma unit for the CRTC on CherryView. */
static void cherryview_load_luts(struct drm_crtc_state *state)
{
	struct drm_crtc *crtc = state->crtc;
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	struct drm_color_lut *lut;
	uint32_t i, lut_size;
	uint32_t word0, word1;

	if (crtc_state_is_legacy(state)) {
		/* Turn off degamma/gamma on CGM block. */
		I915_WRITE(CGM_PIPE_MODE(pipe),
			   (state->ctm ? CGM_PIPE_MODE_CSC : 0));
		i9xx_load_luts_internal(crtc, state->gamma_lut,
					to_intel_crtc_state(state));
		return;
	}

	if (state->degamma_lut) {
		lut = (struct drm_color_lut *) state->degamma_lut->data;
		lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
		for (i = 0; i < lut_size; i++) {
			/* Write LUT in U0.14 format. */
			word0 =
			(drm_color_lut_extract(lut[i].green, 14) << 16) |
			drm_color_lut_extract(lut[i].blue, 14);
			word1 = drm_color_lut_extract(lut[i].red, 14);

			I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
			I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
		}
	}

	if (state->gamma_lut) {
		lut = (struct drm_color_lut *) state->gamma_lut->data;
		lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
		for (i = 0; i < lut_size; i++) {
			/* Write LUT in U0.10 format. */
			word0 =
			(drm_color_lut_extract(lut[i].green, 10) << 16) |
			drm_color_lut_extract(lut[i].blue, 10);
			word1 = drm_color_lut_extract(lut[i].red, 10);

			I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
			I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
		}
	}

	I915_WRITE(CGM_PIPE_MODE(pipe),
		   (state->ctm ? CGM_PIPE_MODE_CSC : 0) |
		   (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
		   (state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));

	/*
	 * Also program a linear LUT in the legacy block (behind the
	 * CGM block).
	 */
	i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
}

void intel_color_load_luts(struct drm_crtc_state *crtc_state)
{
	struct drm_device *dev = crtc_state->crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);

	dev_priv->display.load_luts(crtc_state);
}

int intel_color_check(struct drm_crtc *crtc,
		      struct drm_crtc_state *crtc_state)
{
	struct drm_device *dev = crtc->dev;
	size_t gamma_length, degamma_length;

	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
		sizeof(struct drm_color_lut);
	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
		sizeof(struct drm_color_lut);

	/*
	 * We allow both degamma & gamma luts at the right size or
	 * NULL.
	 */
	if ((!crtc_state->degamma_lut ||
	     crtc_state->degamma_lut->length == degamma_length) &&
	    (!crtc_state->gamma_lut ||
	     crtc_state->gamma_lut->length == gamma_length))
		return 0;

	/*
	 * We also allow no degamma lut and a gamma lut at the legacy
	 * size (256 entries).
	 */
	if (!crtc_state->degamma_lut &&
	    crtc_state->gamma_lut &&
	    crtc_state->gamma_lut->length == LEGACY_LUT_LENGTH)
		return 0;

	return -EINVAL;
}

void intel_color_init(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = to_i915(dev);

	drm_mode_crtc_set_gamma_size(crtc, 256);

	if (IS_CHERRYVIEW(dev)) {
		dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
		dev_priv->display.load_luts = cherryview_load_luts;
	} else if (IS_HASWELL(dev)) {
		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
		dev_priv->display.load_luts = haswell_load_luts;
	} else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
		   IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
		dev_priv->display.load_luts = broadwell_load_luts;
	} else {
		dev_priv->display.load_luts = i9xx_load_luts;
	}

	/* Enable color management support when we have degamma & gamma LUTs. */
	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
	    INTEL_INFO(dev)->color.gamma_lut_size != 0)
		drm_crtc_enable_color_mgmt(crtc,
					INTEL_INFO(dev)->color.degamma_lut_size,
					true,
					INTEL_INFO(dev)->color.gamma_lut_size);
}
Commit	Line	Data
8563b1e8 LL	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#include "intel_drv.h"
	26
82cf435b LL	27	#define CTM_COEFF_SIGN (1ULL << 63)
	28
	29	#define CTM_COEFF_1_0 (1ULL << 32)
	30	#define CTM_COEFF_2_0 (CTM_COEFF_1_0 << 1)
	31	#define CTM_COEFF_4_0 (CTM_COEFF_2_0 << 1)
29dc3739	32	#define CTM_COEFF_8_0 (CTM_COEFF_4_0 << 1)
82cf435b LL	33	#define CTM_COEFF_0_5 (CTM_COEFF_1_0 >> 1)
	34	#define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
	35	#define CTM_COEFF_0_125 (CTM_COEFF_0_25 >> 1)
	36
	37	#define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
	38
	39	#define CTM_COEFF_NEGATIVE(coeff) (((coeff) & CTM_COEFF_SIGN) != 0)
	40	#define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
	41
	42	#define LEGACY_LUT_LENGTH (sizeof(struct drm_color_lut) * 256)
	43
8563b1e8	44	/*
82cf435b LL	45	* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
	46	* format). This macro takes the coefficient we want transformed and the
	47	* number of fractional bits.
8563b1e8	48	*
82cf435b LL	49	* We only have a 9 bits precision window which slides depending on the value
	50	* of the CTM coefficient and we write the value from bit 3. We also round the
	51	* value.
8563b1e8	52	*/
82cf435b LL	53	#define I9XX_CSC_COEFF_FP(coeff, fbits) \
	54	(clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
	55
	56	#define I9XX_CSC_COEFF_LIMITED_RANGE \
	57	I9XX_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
	58	#define I9XX_CSC_COEFF_1_0 \
	59	((7 << 12) \| I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
	60
	61	static bool crtc_state_is_legacy(struct drm_crtc_state *state)
	62	{
	63	return !state->degamma_lut &&
	64	!state->ctm &&
	65	state->gamma_lut &&
	66	state->gamma_lut->length == LEGACY_LUT_LENGTH;
	67	}
	68
	69	/*
	70	* When using limited range, multiply the matrix given by userspace by
	71	* the matrix that we would use for the limited range. We do the
	72	* multiplication in U2.30 format.
	73	*/
	74	static void ctm_mult_by_limited(uint64_t result, int64_t input)
	75	{
	76	int i;
	77
	78	for (i = 0; i < 9; i++)
	79	result[i] = 0;
	80
	81	for (i = 0; i < 3; i++) {
	82	int64_t user_coeff = input[i * 3 + i];
	83	uint64_t limited_coeff = CTM_COEFF_LIMITED_RANGE >> 2;
	84	uint64_t abs_coeff = clamp_val(CTM_COEFF_ABS(user_coeff),
	85	0,
	86	CTM_COEFF_4_0 - 1) >> 2;
	87
	88	result[i * 3 + i] = (limited_coeff * abs_coeff) >> 27;
	89	if (CTM_COEFF_NEGATIVE(user_coeff))
	90	result[i * 3 + i] \|= CTM_COEFF_SIGN;
	91	}
	92	}
	93
	94	/* Set up the pipe CSC unit. */
b95c5321	95	static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
8563b1e8	96	{
b95c5321	97	struct drm_crtc *crtc = crtc_state->crtc;
8563b1e8	98	struct drm_device *dev = crtc->dev;
fac5e23e	99	struct drm_i915_private *dev_priv = to_i915(dev);
8563b1e8	100	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
82cf435b LL	101	int i, pipe = intel_crtc->pipe;
82cf435b LL	102	uint16_t coeffs[9] = { 0, };
1f0017f6	103	struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
82cf435b LL	104
	105	if (crtc_state->ctm) {
	106	struct drm_color_ctm *ctm =
	107	(struct drm_color_ctm *)crtc_state->ctm->data;
	108	uint64_t input[9] = { 0, };
	109
1f0017f6	110	if (intel_crtc_state->limited_color_range) {
82cf435b LL	111	ctm_mult_by_limited(input, ctm->matrix);
	112	} else {
	113	for (i = 0; i < ARRAY_SIZE(input); i++)
	114	input[i] = ctm->matrix[i];
	115	}
	116
	117	/*
	118	* Convert fixed point S31.32 input to format supported by the
	119	* hardware.
	120	*/
	121	for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
	122	uint64_t abs_coeff = ((1ULL << 63) - 1) & input[i];
	123
	124	/*
	125	* Clamp input value to min/max supported by
	126	* hardware.
	127	*/
	128	abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
	129
	130	/* sign bit */
	131	if (CTM_COEFF_NEGATIVE(input[i]))
	132	coeffs[i] \|= 1 << 15;
	133
	134	if (abs_coeff < CTM_COEFF_0_125)
	135	coeffs[i] \|= (3 << 12) \|
	136	I9XX_CSC_COEFF_FP(abs_coeff, 12);
	137	else if (abs_coeff < CTM_COEFF_0_25)
	138	coeffs[i] \|= (2 << 12) \|
	139	I9XX_CSC_COEFF_FP(abs_coeff, 11);
	140	else if (abs_coeff < CTM_COEFF_0_5)
	141	coeffs[i] \|= (1 << 12) \|
	142	I9XX_CSC_COEFF_FP(abs_coeff, 10);
	143	else if (abs_coeff < CTM_COEFF_1_0)
	144	coeffs[i] \|= I9XX_CSC_COEFF_FP(abs_coeff, 9);
	145	else if (abs_coeff < CTM_COEFF_2_0)
	146	coeffs[i] \|= (7 << 12) \|
	147	I9XX_CSC_COEFF_FP(abs_coeff, 8);
	148	else
	149	coeffs[i] \|= (6 << 12) \|
	150	I9XX_CSC_COEFF_FP(abs_coeff, 7);
	151	}
	152	} else {
	153	/*
	154	* Load an identity matrix if no coefficients are provided.
	155	*
	156	* TODO: Check what kind of values actually come out of the
	157	* pipe with these coeff/postoff values and adjust to get the
	158	* best accuracy. Perhaps we even need to take the bpc value
	159	* into consideration.
	160	*/
	161	for (i = 0; i < 3; i++) {
1f0017f6	162	if (intel_crtc_state->limited_color_range)
82cf435b LL	163	coeffs[i * 3 + i] =
	164	I9XX_CSC_COEFF_LIMITED_RANGE;
	165	else
	166	coeffs[i * 3 + i] = I9XX_CSC_COEFF_1_0;
	167	}
	168	}
8563b1e8	169
82cf435b LL	170	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 \| coeffs[1]);
82cf435b LL	171	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
8563b1e8	172
82cf435b LL	173	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 \| coeffs[4]);
82cf435b LL	174	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
8563b1e8	175
82cf435b LL	176	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 \| coeffs[7]);
82cf435b LL	177	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
8563b1e8 LL	178
	179	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
	180	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
	181	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
	182
	183	if (INTEL_INFO(dev)->gen > 6) {
	184	uint16_t postoff = 0;
	185
1f0017f6	186	if (intel_crtc_state->limited_color_range)
8563b1e8 LL	187	postoff = (16 * (1 << 12) / 255) & 0x1fff;
	188
	189	I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
	190	I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
	191	I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
	192
	193	I915_WRITE(PIPE_CSC_MODE(pipe), 0);
	194	} else {
	195	uint32_t mode = CSC_MODE_YUV_TO_RGB;
	196
1f0017f6	197	if (intel_crtc_state->limited_color_range)
8563b1e8 LL	198	mode \|= CSC_BLACK_SCREEN_OFFSET;
	199
	200	I915_WRITE(PIPE_CSC_MODE(pipe), mode);
	201	}
	202	}
	203
29dc3739 LL	204	/*
	205	* Set up the pipe CSC unit on CherryView.
	206	*/
b95c5321	207	static void cherryview_load_csc_matrix(struct drm_crtc_state *state)
29dc3739	208	{
b95c5321	209	struct drm_crtc *crtc = state->crtc;
29dc3739	210	struct drm_device *dev = crtc->dev;
fac5e23e	211	struct drm_i915_private *dev_priv = to_i915(dev);
29dc3739 LL	212	int pipe = to_intel_crtc(crtc)->pipe;
	213	uint32_t mode;
	214
	215	if (state->ctm) {
	216	struct drm_color_ctm *ctm =
	217	(struct drm_color_ctm *) state->ctm->data;
	218	uint16_t coeffs[9] = { 0, };
	219	int i;
	220
	221	for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
	222	uint64_t abs_coeff =
	223	((1ULL << 63) - 1) & ctm->matrix[i];
	224
	225	/* Round coefficient. */
	226	abs_coeff += 1 << (32 - 13);
	227	/* Clamp to hardware limits. */
	228	abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
	229
	230	/* Write coefficients in S3.12 format. */
	231	if (ctm->matrix[i] & (1ULL << 63))
	232	coeffs[i] = 1 << 15;
	233	coeffs[i] \|= ((abs_coeff >> 32) & 7) << 12;
	234	coeffs[i] \|= (abs_coeff >> 20) & 0xfff;
	235	}
	236
	237	I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe),
	238	coeffs[1] << 16 \| coeffs[0]);
	239	I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe),
	240	coeffs[3] << 16 \| coeffs[2]);
	241	I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe),
	242	coeffs[5] << 16 \| coeffs[4]);
	243	I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe),
	244	coeffs[7] << 16 \| coeffs[6]);
	245	I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
	246	}
	247
	248	mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
	249	if (!crtc_state_is_legacy(state)) {
	250	mode \|= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) \|
	251	(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
	252	}
	253	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
	254	}
	255
b95c5321	256	void intel_color_set_csc(struct drm_crtc_state *crtc_state)
8563b1e8	257	{
b95c5321	258	struct drm_device *dev = crtc_state->crtc->dev;
fac5e23e	259	struct drm_i915_private *dev_priv = to_i915(dev);
82cf435b LL	260
82cf435b LL	261	if (dev_priv->display.load_csc_matrix)
b95c5321	262	dev_priv->display.load_csc_matrix(crtc_state);
8563b1e8 LL	263	}
8563b1e8 LL	264
82cf435b	265	/* Loads the legacy palette/gamma unit for the CRTC. */
29dc3739	266	static void i9xx_load_luts_internal(struct drm_crtc *crtc,
1f0017f6 ML	267	struct drm_property_blob *blob,
1f0017f6 ML	268	struct intel_crtc_state *crtc_state)
8563b1e8 LL	269	{
8563b1e8 LL	270	struct drm_device *dev = crtc->dev;
fac5e23e	271	struct drm_i915_private *dev_priv = to_i915(dev);
8563b1e8 LL	272	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	273	enum pipe pipe = intel_crtc->pipe;
	274	int i;
	275
	276	if (HAS_GMCH_DISPLAY(dev)) {
1f0017f6	277	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
8563b1e8 LL	278	assert_dsi_pll_enabled(dev_priv);
	279	else
	280	assert_pll_enabled(dev_priv, pipe);
	281	}
	282
29dc3739 LL	283	if (blob) {
29dc3739 LL	284	struct drm_color_lut lut = (struct drm_color_lut ) blob->data;
82cf435b LL	285	for (i = 0; i < 256; i++) {
	286	uint32_t word =
	287	(drm_color_lut_extract(lut[i].red, 8) << 16) \|
	288	(drm_color_lut_extract(lut[i].green, 8) << 8) \|
	289	drm_color_lut_extract(lut[i].blue, 8);
	290
	291	if (HAS_GMCH_DISPLAY(dev))
	292	I915_WRITE(PALETTE(pipe, i), word);
	293	else
	294	I915_WRITE(LGC_PALETTE(pipe, i), word);
	295	}
	296	} else {
	297	for (i = 0; i < 256; i++) {
	298	uint32_t word = (i << 16) \| (i << 8) \| i;
	299
	300	if (HAS_GMCH_DISPLAY(dev))
	301	I915_WRITE(PALETTE(pipe, i), word);
	302	else
	303	I915_WRITE(LGC_PALETTE(pipe, i), word);
	304	}
8563b1e8 LL	305	}
	306	}
	307
b95c5321	308	static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
29dc3739	309	{
1f0017f6 ML	310	i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
1f0017f6 ML	311	to_intel_crtc_state(crtc_state));
29dc3739 LL	312	}
29dc3739 LL	313
82cf435b	314	/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
b95c5321	315	static void haswell_load_luts(struct drm_crtc_state *crtc_state)
8563b1e8	316	{
b95c5321	317	struct drm_crtc *crtc = crtc_state->crtc;
8563b1e8	318	struct drm_device *dev = crtc->dev;
fac5e23e	319	struct drm_i915_private *dev_priv = to_i915(dev);
8563b1e8	320	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05dc698c	321	struct intel_crtc_state *intel_crtc_state =
b95c5321	322	to_intel_crtc_state(crtc_state);
8563b1e8 LL	323	bool reenable_ips = false;
	324
	325	/*
	326	* Workaround : Do not read or write the pipe palette/gamma data while
	327	* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
	328	*/
1f0017f6	329	if (IS_HASWELL(dev) && intel_crtc_state->ips_enabled &&
05dc698c	330	(intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
8563b1e8 LL	331	hsw_disable_ips(intel_crtc);
	332	reenable_ips = true;
	333	}
05dc698c LL	334
05dc698c LL	335	intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
8563b1e8 LL	336	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8563b1e8 LL	337
b95c5321	338	i9xx_load_luts(crtc_state);
8563b1e8 LL	339
	340	if (reenable_ips)
	341	hsw_enable_ips(intel_crtc);
	342	}
	343
82cf435b	344	/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
b95c5321	345	static void broadwell_load_luts(struct drm_crtc_state *state)
82cf435b	346	{
b95c5321	347	struct drm_crtc *crtc = state->crtc;
82cf435b	348	struct drm_device *dev = crtc->dev;
fac5e23e	349	struct drm_i915_private *dev_priv = to_i915(dev);
82cf435b LL	350	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
	351	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	352	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
	353
	354	if (crtc_state_is_legacy(state)) {
b95c5321	355	haswell_load_luts(state);
82cf435b LL	356	return;
	357	}
	358
	359	I915_WRITE(PREC_PAL_INDEX(pipe),
	360	PAL_PREC_SPLIT_MODE \| PAL_PREC_AUTO_INCREMENT);
	361
	362	if (state->degamma_lut) {
	363	struct drm_color_lut *lut =
	364	(struct drm_color_lut *) state->degamma_lut->data;
	365
	366	for (i = 0; i < lut_size; i++) {
	367	uint32_t word =
	368	drm_color_lut_extract(lut[i].red, 10) << 20 \|
	369	drm_color_lut_extract(lut[i].green, 10) << 10 \|
	370	drm_color_lut_extract(lut[i].blue, 10);
	371
	372	I915_WRITE(PREC_PAL_DATA(pipe), word);
	373	}
	374	} else {
	375	for (i = 0; i < lut_size; i++) {
	376	uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
	377
	378	I915_WRITE(PREC_PAL_DATA(pipe),
	379	(v << 20) \| (v << 10) \| v);
	380	}
	381	}
	382
	383	if (state->gamma_lut) {
	384	struct drm_color_lut *lut =
	385	(struct drm_color_lut *) state->gamma_lut->data;
	386
	387	for (i = 0; i < lut_size; i++) {
	388	uint32_t word =
	389	(drm_color_lut_extract(lut[i].red, 10) << 20) \|
	390	(drm_color_lut_extract(lut[i].green, 10) << 10) \|
	391	drm_color_lut_extract(lut[i].blue, 10);
	392
	393	I915_WRITE(PREC_PAL_DATA(pipe), word);
	394	}
	395
	396	/* Program the max register to clamp values > 1.0. */
	397	I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
	398	drm_color_lut_extract(lut[i].red, 16));
	399	I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
	400	drm_color_lut_extract(lut[i].green, 16));
	401	I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
	402	drm_color_lut_extract(lut[i].blue, 16));
	403	} else {
	404	for (i = 0; i < lut_size; i++) {
	405	uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1);
	406
	407	I915_WRITE(PREC_PAL_DATA(pipe),
	408	(v << 20) \| (v << 10) \| v);
	409	}
	410
	411	I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
	412	I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
	413	I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
	414	}
	415
	416	intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
	417	I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
	418	POSTING_READ(GAMMA_MODE(pipe));
	419
420	/*
421	* Reset the index, otherwise it prevents the legacy palette to be
422	* written properly.
423	*/
424	I915_WRITE(PREC_PAL_INDEX(pipe), 0);
425	}
426
29dc3739	427	/* Loads the palette/gamma unit for the CRTC on CherryView. */
b95c5321	428	static void cherryview_load_luts(struct drm_crtc_state *state)
29dc3739	429	{
b95c5321	430	struct drm_crtc *crtc = state->crtc;
29dc3739	431	struct drm_device *dev = crtc->dev;
fac5e23e	432	struct drm_i915_private *dev_priv = to_i915(dev);
29dc3739 LL	433	enum pipe pipe = to_intel_crtc(crtc)->pipe;
	434	struct drm_color_lut *lut;
	435	uint32_t i, lut_size;
	436	uint32_t word0, word1;
	437
	438	if (crtc_state_is_legacy(state)) {
	439	/* Turn off degamma/gamma on CGM block. */
	440	I915_WRITE(CGM_PIPE_MODE(pipe),
	441	(state->ctm ? CGM_PIPE_MODE_CSC : 0));
1f0017f6 ML	442	i9xx_load_luts_internal(crtc, state->gamma_lut,
1f0017f6 ML	443	to_intel_crtc_state(state));
29dc3739 LL	444	return;
	445	}
	446
	447	if (state->degamma_lut) {
	448	lut = (struct drm_color_lut *) state->degamma_lut->data;
	449	lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
	450	for (i = 0; i < lut_size; i++) {
	451	/* Write LUT in U0.14 format. */
	452	word0 =
	453	(drm_color_lut_extract(lut[i].green, 14) << 16) \|
	454	drm_color_lut_extract(lut[i].blue, 14);
	455	word1 = drm_color_lut_extract(lut[i].red, 14);
	456
	457	I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), word0);
	458	I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), word1);
	459	}
	460	}
	461
	462	if (state->gamma_lut) {
	463	lut = (struct drm_color_lut *) state->gamma_lut->data;
	464	lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
	465	for (i = 0; i < lut_size; i++) {
	466	/* Write LUT in U0.10 format. */
	467	word0 =
	468	(drm_color_lut_extract(lut[i].green, 10) << 16) \|
	469	drm_color_lut_extract(lut[i].blue, 10);
	470	word1 = drm_color_lut_extract(lut[i].red, 10);
	471
	472	I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), word0);
	473	I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), word1);
	474	}
	475	}
	476
	477	I915_WRITE(CGM_PIPE_MODE(pipe),
	478	(state->ctm ? CGM_PIPE_MODE_CSC : 0) \|
	479	(state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) \|
	480	(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0));
	481
	482	/*
	483	* Also program a linear LUT in the legacy block (behind the
	484	* CGM block).
	485	*/
1f0017f6	486	i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
29dc3739 LL	487	}
29dc3739 LL	488
b95c5321	489	void intel_color_load_luts(struct drm_crtc_state *crtc_state)
8563b1e8	490	{
b95c5321	491	struct drm_device *dev = crtc_state->crtc->dev;
fac5e23e	492	struct drm_i915_private *dev_priv = to_i915(dev);
8563b1e8	493
b95c5321	494	dev_priv->display.load_luts(crtc_state);
8563b1e8 LL	495	}
8563b1e8 LL	496
82cf435b LL	497	int intel_color_check(struct drm_crtc *crtc,
82cf435b LL	498	struct drm_crtc_state *crtc_state)
8563b1e8	499	{
82cf435b LL	500	struct drm_device *dev = crtc->dev;
82cf435b LL	501	size_t gamma_length, degamma_length;
8563b1e8	502
82cf435b LL	503	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
	504	sizeof(struct drm_color_lut);
	505	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
	506	sizeof(struct drm_color_lut);
8563b1e8	507
82cf435b LL	508	/*
	509	* We allow both degamma & gamma luts at the right size or
	510	* NULL.
	511	*/
	512	if ((!crtc_state->degamma_lut \|\|
	513	crtc_state->degamma_lut->length == degamma_length) &&
	514	(!crtc_state->gamma_lut \|\|
	515	crtc_state->gamma_lut->length == gamma_length))
	516	return 0;
	517
	518	/*
	519	* We also allow no degamma lut and a gamma lut at the legacy
	520	* size (256 entries).
	521	*/
	522	if (!crtc_state->degamma_lut &&
	523	crtc_state->gamma_lut &&
	524	crtc_state->gamma_lut->length == LEGACY_LUT_LENGTH)
	525	return 0;
	526
	527	return -EINVAL;
8563b1e8 LL	528	}
	529
	530	void intel_color_init(struct drm_crtc *crtc)
	531	{
	532	struct drm_device *dev = crtc->dev;
fac5e23e	533	struct drm_i915_private *dev_priv = to_i915(dev);
8563b1e8 LL	534
8563b1e8 LL	535	drm_mode_crtc_set_gamma_size(crtc, 256);
8563b1e8	536
29dc3739 LL	537	if (IS_CHERRYVIEW(dev)) {
	538	dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
	539	dev_priv->display.load_luts = cherryview_load_luts;
	540	} else if (IS_HASWELL(dev)) {
82cf435b	541	dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
8563b1e8	542	dev_priv->display.load_luts = haswell_load_luts;
82cf435b LL	543	} else if (IS_BROADWELL(dev) \|\| IS_SKYLAKE(dev) \|\|
	544	IS_BROXTON(dev) \|\| IS_KABYLAKE(dev)) {
	545	dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
	546	dev_priv->display.load_luts = broadwell_load_luts;
8563b1e8 LL	547	} else {
	548	dev_priv->display.load_luts = i9xx_load_luts;
	549	}
82cf435b LL	550
	551	/* Enable color management support when we have degamma & gamma LUTs. */
	552	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
	553	INTEL_INFO(dev)->color.gamma_lut_size != 0)
f8ed34ac	554	drm_crtc_enable_color_mgmt(crtc,
82cf435b	555	INTEL_INFO(dev)->color.degamma_lut_size,
f8ed34ac	556	true,
82cf435b	557	INTEL_INFO(dev)->color.gamma_lut_size);
8563b1e8	558	}