projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Fix bogus dig_port_map[] assignment for pre-HSW
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
d1c0a001 136 { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
f8896f5d
DW		 137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
d1c0a001 139 { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
f8896f5d 140 { 0x00002016, 0x000000DF, 0x0 },
d1c0a001 141 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d
DW		 147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
d1c0a001 149 { 0x80009010, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
5f8b2531 150 { 0x0000201B, 0x0000009D, 0x0 },
d1c0a001 151 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
152 { 0x80007011, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
f8896f5d 153 { 0x00002016, 0x00000088, 0x0 },
d1c0a001 154 { 0x80005012, 0x000000C0, 0x1 }, /* Uses I_boost level 0x1 */
f8896f5d
DW		 155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
d1c0a001 162 { 0x80009010, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
f8896f5d 163 { 0x00000018, 0x0000009D, 0x0 },
d1c0a001 164 { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
165 { 0x80007011, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
f8896f5d 166 { 0x00000018, 0x00000088, 0x0 },
d1c0a001 167 { 0x80005012, 0x000000C0, 0x3 }, /* Uses I_boost level 0x3 */
f8896f5d
DW		 168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
5f8b2531 247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
f8896f5d 248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
f8896f5d
DW		 304static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
305 enum port port, int type);
306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 312
8cd21b7f
JN		 313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
8cd21b7f
JN		 317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
8cd21b7f
JN		 324 break;
325 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 326 *dig_port = NULL;
327 *port = PORT_E;
8cd21b7f
JN		 328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
fc914639
PZ		 332 }
333}
334
a1e6ad66
ID		 335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
ce3b7e9b
DL		 345static bool
346intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
347{
f0f59a00 348 return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg);
ce3b7e9b
DL		 349}
350
f8896f5d
DW		 351static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
352 int *n_entries)
353{
f8896f5d 354 const struct ddi_buf_trans *ddi_translations;
f8896f5d 355
a5b7991c 356 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
5f8b2531
RV		 357 ddi_translations = skl_y_ddi_translations_dp;
358 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
a5b7991c 359 } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
f8896f5d
DW		 360 ddi_translations = skl_u_ddi_translations_dp;
361 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
362 } else {
363 ddi_translations = skl_ddi_translations_dp;
364 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
365 }
366
367 return ddi_translations;
368}
369
370static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
371 int *n_entries)
372{
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 const struct ddi_buf_trans *ddi_translations;
f8896f5d 375
a5b7991c 376 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
f8896f5d 377 if (dev_priv->edp_low_vswing) {
5f8b2531
RV		 378 ddi_translations = skl_y_ddi_translations_edp;
379 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
f8896f5d 380 } else {
5f8b2531
RV		 381 ddi_translations = skl_y_ddi_translations_dp;
382 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d 383 }
a5b7991c 384 } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
f8896f5d
DW		 385 if (dev_priv->edp_low_vswing) {
386 ddi_translations = skl_u_ddi_translations_edp;
387 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
388 } else {
389 ddi_translations = skl_u_ddi_translations_dp;
390 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
391 }
392 } else {
393 if (dev_priv->edp_low_vswing) {
394 ddi_translations = skl_ddi_translations_edp;
395 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
396 } else {
397 ddi_translations = skl_ddi_translations_dp;
398 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
399 }
400 }
401
402 return ddi_translations;
403}
404
405static const struct ddi_buf_trans *
406skl_get_buf_trans_hdmi(struct drm_device *dev,
407 int *n_entries)
408{
f8896f5d 409 const struct ddi_buf_trans *ddi_translations;
f8896f5d 410
a5b7991c 411 if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
5f8b2531
RV		 412 ddi_translations = skl_y_ddi_translations_hdmi;
413 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
f8896f5d
DW		 414 } else {
415 ddi_translations = skl_ddi_translations_hdmi;
416 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
417 }
418
419 return ddi_translations;
420}
421
e58623cb
AR		 422/*
423 * Starting with Haswell, DDI port buffers must be programmed with correct
424 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 425 * but the HDMI/DVI fields are shared among those. So we program the DDI
426 * in either FDI or DP modes only, as HDMI connections will work with both
427 * of those
428 */
faa0cdbe
ID		 429static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
430 bool supports_hdmi)
45244b87
ED		 431{
432 struct drm_i915_private *dev_priv = dev->dev_private;
75067dde 433 u32 iboost_bit = 0;
7ff44670 434 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 435 size;
6acab15a 436 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 437 const struct ddi_buf_trans *ddi_translations_fdi;
438 const struct ddi_buf_trans *ddi_translations_dp;
439 const struct ddi_buf_trans *ddi_translations_edp;
440 const struct ddi_buf_trans *ddi_translations_hdmi;
441 const struct ddi_buf_trans *ddi_translations;
e58623cb 442
96fb9f9b 443 if (IS_BROXTON(dev)) {
faa0cdbe 444 if (!supports_hdmi)
96fb9f9b
VK		 445 return;
446
447 /* Vswing programming for HDMI */
448 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
449 INTEL_OUTPUT_HDMI);
450 return;
ef11bdb3 451 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c30400fc 452 ddi_translations_fdi = NULL;
f8896f5d
DW		 453 ddi_translations_dp =
454 skl_get_buf_trans_dp(dev, &n_dp_entries);
455 ddi_translations_edp =
456 skl_get_buf_trans_edp(dev, &n_edp_entries);
457 ddi_translations_hdmi =
458 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
459 hdmi_default_entry = 8;
75067dde
AK		 460 /* If we're boosting the current, set bit 31 of trans1 */
461 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
462 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
463 iboost_bit = 1<<31;
7f88e3af 464 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 465 ddi_translations_fdi = bdw_ddi_translations_fdi;
466 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 467 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 468 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 469 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
470 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 471 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 472 hdmi_default_entry = 7;
e58623cb
AR		 473 } else if (IS_HASWELL(dev)) {
474 ddi_translations_fdi = hsw_ddi_translations_fdi;
475 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 476 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 477 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 478 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 479 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 480 hdmi_default_entry = 6;
e58623cb
AR		 481 } else {
482 WARN(1, "ddi translation table missing\n");
300644c7 483 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 484 ddi_translations_fdi = bdw_ddi_translations_fdi;
485 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 486 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 487 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
488 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 489 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 490 hdmi_default_entry = 7;
e58623cb
AR		 491 }
492
300644c7
PZ		 493 switch (port) {
494 case PORT_A:
495 ddi_translations = ddi_translations_edp;
7ad14a29 496 size = n_edp_entries;
300644c7
PZ		 497 break;
498 case PORT_B:
499 case PORT_C:
300644c7 500 ddi_translations = ddi_translations_dp;
7ad14a29 501 size = n_dp_entries;
300644c7 502 break;
77d8d009 503 case PORT_D:
7ad14a29 504 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 505 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 506 size = n_edp_entries;
507 } else {
77d8d009 508 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 509 size = n_dp_entries;
510 }
77d8d009 511 break;
300644c7 512 case PORT_E:
7f88e3af
DL		 513 if (ddi_translations_fdi)
514 ddi_translations = ddi_translations_fdi;
515 else
516 ddi_translations = ddi_translations_dp;
7ad14a29 517 size = n_dp_entries;
300644c7
PZ		 518 break;
519 default:
520 BUG();
521 }
45244b87 522
9712e688
VS		 523 for (i = 0; i < size; i++) {
524 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
525 ddi_translations[i].trans1 | iboost_bit);
526 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
527 ddi_translations[i].trans2);
45244b87 528 }
ce4dd49e 529
faa0cdbe 530 if (!supports_hdmi)
ce3b7e9b
DL		 531 return;
532
ce4dd49e
DL		 533 /* Choose a good default if VBT is badly populated */
534 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
535 hdmi_level >= n_hdmi_entries)
7ff44670 536 hdmi_level = hdmi_default_entry;
ce4dd49e 537
6acab15a 538 /* Entry 9 is for HDMI: */
9712e688
VS		 539 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
540 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
541 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
542 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 543}
544
545/* Program DDI buffers translations for DP. By default, program ports A-D in DP
546 * mode and port E for FDI.
547 */
548void intel_prepare_ddi(struct drm_device *dev)
549{
faa0cdbe 550 struct intel_encoder *intel_encoder;
b403745c 551 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 552
0d536cb4
PZ		 553 if (!HAS_DDI(dev))
554 return;
45244b87 555
faa0cdbe
ID		 556 for_each_intel_encoder(dev, intel_encoder) {
557 struct intel_digital_port *intel_dig_port;
558 enum port port;
559 bool supports_hdmi;
560
7d4aefd0
SS		 561 if (intel_encoder->type == INTEL_OUTPUT_DSI)
562 continue;
faa0cdbe 563
7d4aefd0 564 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
faa0cdbe 565 if (visited[port])
b403745c
DL		 566 continue;
567
faa0cdbe
ID		 568 supports_hdmi = intel_dig_port &&
569 intel_dig_port_supports_hdmi(intel_dig_port);
570
571 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
572 visited[port] = true;
b403745c 573 }
45244b87 574}
c82e4d26 575
248138b5
PZ		 576static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
577 enum port port)
578{
f0f59a00 579 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 580 int i;
581
3449ca85 582 for (i = 0; i < 16; i++) {
248138b5
PZ		 583 udelay(1);
584 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
585 return;
586 }
587 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
588}
c82e4d26
ED		 589
590/* Starting with Haswell, different DDI ports can work in FDI mode for
591 * connection to the PCH-located connectors. For this, it is necessary to train
592 * both the DDI port and PCH receiver for the desired DDI buffer settings.
593 *
594 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
595 * please note that when FDI mode is active on DDI E, it shares 2 lines with
596 * DDI A (which is used for eDP)
597 */
598
599void hsw_fdi_link_train(struct drm_crtc *crtc)
600{
601 struct drm_device *dev = crtc->dev;
602 struct drm_i915_private *dev_priv = dev->dev_private;
603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 604 u32 temp, i, rx_ctl_val;
c82e4d26 605
04945641
PZ		 606 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
607 * mode set "sequence for CRT port" document:
608 * - TP1 to TP2 time with the default value
609 * - FDI delay to 90h
8693a824
DL		 610 *
611 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 612 */
eede3b53 613 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 614 FDI_RX_PWRDN_LANE0_VAL(2) |
615 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
616
617 /* Enable the PCH Receiver FDI PLL */
3e68320e 618 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 619 FDI_RX_PLL_ENABLE |
6e3c9717 620 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 621 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
622 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 623 udelay(220);
624
625 /* Switch from Rawclk to PCDclk */
626 rx_ctl_val |= FDI_PCDCLK;
eede3b53 627 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 628
629 /* Configure Port Clock Select */
6e3c9717
ACO		 630 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
631 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 632
633 /* Start the training iterating through available voltages and emphasis,
634 * testing each value twice. */
10122051 635 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 636 /* Configure DP_TP_CTL with auto-training */
637 I915_WRITE(DP_TP_CTL(PORT_E),
638 DP_TP_CTL_FDI_AUTOTRAIN |
639 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
640 DP_TP_CTL_LINK_TRAIN_PAT1 |
641 DP_TP_CTL_ENABLE);
642
876a8cdf
DL		 643 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
644 * DDI E does not support port reversal, the functionality is
645 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
646 * port reversal bit */
c82e4d26 647 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 648 DDI_BUF_CTL_ENABLE |
6e3c9717 649 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 650 DDI_BUF_TRANS_SELECT(i / 2));
04945641 651 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 652
653 udelay(600);
654
04945641 655 /* Program PCH FDI Receiver TU */
eede3b53 656 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 657
658 /* Enable PCH FDI Receiver with auto-training */
659 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 660 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
661 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 662
663 /* Wait for FDI receiver lane calibration */
664 udelay(30);
665
666 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 667 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 668 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 669 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
670 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 671
672 /* Wait for FDI auto training time */
673 udelay(5);
c82e4d26
ED		 674
675 temp = I915_READ(DP_TP_STATUS(PORT_E));
676 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 677 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 678 break;
679 }
c82e4d26 680
a308ccb3
VS		 681 /*
682 * Leave things enabled even if we failed to train FDI.
683 * Results in less fireworks from the state checker.
684 */
685 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
686 DRM_ERROR("FDI link training failed!\n");
687 break;
c82e4d26 688 }
04945641 689
248138b5
PZ		 690 temp = I915_READ(DDI_BUF_CTL(PORT_E));
691 temp &= ~DDI_BUF_CTL_ENABLE;
692 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
693 POSTING_READ(DDI_BUF_CTL(PORT_E));
694
04945641 695 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 696 temp = I915_READ(DP_TP_CTL(PORT_E));
697 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
698 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
699 I915_WRITE(DP_TP_CTL(PORT_E), temp);
700 POSTING_READ(DP_TP_CTL(PORT_E));
701
702 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 703
704 rx_ctl_val &= ~FDI_RX_ENABLE;
eede3b53
VS		 705 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
706 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 707
708 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 709 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 710 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
711 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 712 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
713 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 714 }
715
a308ccb3
VS		 716 /* Enable normal pixel sending for FDI */
717 I915_WRITE(DP_TP_CTL(PORT_E),
718 DP_TP_CTL_FDI_AUTOTRAIN |
719 DP_TP_CTL_LINK_TRAIN_NORMAL |
720 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
721 DP_TP_CTL_ENABLE);
c82e4d26 722}
0e72a5b5 723
44905a27
DA		 724void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
725{
726 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
727 struct intel_digital_port *intel_dig_port =
728 enc_to_dig_port(&encoder->base);
729
730 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 731 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 732 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 733}
734
8d9ddbcb
PZ		 735static struct intel_encoder *
736intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
737{
738 struct drm_device *dev = crtc->dev;
739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
740 struct intel_encoder *intel_encoder, *ret = NULL;
741 int num_encoders = 0;
742
743 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
744 ret = intel_encoder;
745 num_encoders++;
746 }
747
748 if (num_encoders != 1)
84f44ce7
VS		 749 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
750 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 751
752 BUG_ON(ret == NULL);
753 return ret;
754}
755
bcddf610 756struct intel_encoder *
3165c074 757intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 758{
3165c074
ACO		 759 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
760 struct intel_encoder *ret = NULL;
761 struct drm_atomic_state *state;
da3ced29
ACO		 762 struct drm_connector *connector;
763 struct drm_connector_state *connector_state;
d0737e1d 764 int num_encoders = 0;
3165c074 765 int i;
d0737e1d 766
3165c074
ACO		 767 state = crtc_state->base.state;
768
da3ced29
ACO		 769 for_each_connector_in_state(state, connector, connector_state, i) {
770 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 771 continue;
772
da3ced29 773 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 774 num_encoders++;
d0737e1d
ACO		 775 }
776
777 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
778 pipe_name(crtc->pipe));
779
780 BUG_ON(ret == NULL);
781 return ret;
782}
783
1c0b85c5 784#define LC_FREQ 2700
27893390 785#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 786
787#define P_MIN 2
788#define P_MAX 64
789#define P_INC 2
790
791/* Constraints for PLL good behavior */
792#define REF_MIN 48
793#define REF_MAX 400
794#define VCO_MIN 2400
795#define VCO_MAX 4800
796
27893390
DL		 797#define abs_diff(a, b) ({ \
798 typeof(a) __a = (a); \
799 typeof(b) __b = (b); \
800 (void) (&__a == &__b); \
801 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 802
63582983 803struct hsw_wrpll_rnp {
1c0b85c5
DL		 804 unsigned p, n2, r2;
805};
806
63582983 807static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 808{
1c0b85c5
DL		 809 unsigned budget;
810
811 switch (clock) {
812 case 25175000:
813 case 25200000:
814 case 27000000:
815 case 27027000:
816 case 37762500:
817 case 37800000:
818 case 40500000:
819 case 40541000:
820 case 54000000:
821 case 54054000:
822 case 59341000:
823 case 59400000:
824 case 72000000:
825 case 74176000:
826 case 74250000:
827 case 81000000:
828 case 81081000:
829 case 89012000:
830 case 89100000:
831 case 108000000:
832 case 108108000:
833 case 111264000:
834 case 111375000:
835 case 148352000:
836 case 148500000:
837 case 162000000:
838 case 162162000:
839 case 222525000:
840 case 222750000:
841 case 296703000:
842 case 297000000:
843 budget = 0;
844 break;
845 case 233500000:
846 case 245250000:
847 case 247750000:
848 case 253250000:
849 case 298000000:
850 budget = 1500;
851 break;
852 case 169128000:
853 case 169500000:
854 case 179500000:
855 case 202000000:
856 budget = 2000;
857 break;
858 case 256250000:
859 case 262500000:
860 case 270000000:
861 case 272500000:
862 case 273750000:
863 case 280750000:
864 case 281250000:
865 case 286000000:
866 case 291750000:
867 budget = 4000;
868 break;
869 case 267250000:
870 case 268500000:
871 budget = 5000;
872 break;
873 default:
874 budget = 1000;
875 break;
876 }
6441ab5f 877
1c0b85c5
DL		 878 return budget;
879}
880
63582983
DL		 881static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
882 unsigned r2, unsigned n2, unsigned p,
883 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 884{
885 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 886
1c0b85c5
DL		 887 /* No best (r,n,p) yet */
888 if (best->p == 0) {
889 best->p = p;
890 best->n2 = n2;
891 best->r2 = r2;
892 return;
893 }
6441ab5f 894
1c0b85c5
DL		 895 /*
896 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
897 * freq2k.
898 *
899 * delta = 1e6 *
900 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
901 * freq2k;
902 *
903 * and we would like delta <= budget.
904 *
905 * If the discrepancy is above the PPM-based budget, always prefer to
906 * improve upon the previous solution. However, if you're within the
907 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
908 */
909 a = freq2k * budget * p * r2;
910 b = freq2k * budget * best->p * best->r2;
27893390
DL		 911 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
912 diff_best = abs_diff(freq2k * best->p * best->r2,
913 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 914 c = 1000000 * diff;
915 d = 1000000 * diff_best;
916
917 if (a < c && b < d) {
918 /* If both are above the budget, pick the closer */
919 if (best->p * best->r2 * diff < p * r2 * diff_best) {
920 best->p = p;
921 best->n2 = n2;
922 best->r2 = r2;
923 }
924 } else if (a >= c && b < d) {
925 /* If A is below the threshold but B is above it? Update. */
926 best->p = p;
927 best->n2 = n2;
928 best->r2 = r2;
929 } else if (a >= c && b >= d) {
930 /* Both are below the limit, so pick the higher n2/(r2*r2) */
931 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
932 best->p = p;
933 best->n2 = n2;
934 best->r2 = r2;
935 }
936 }
937 /* Otherwise a < c && b >= d, do nothing */
938}
939
f0f59a00
VS		 940static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
941 i915_reg_t reg)
11578553
JB		 942{
943 int refclk = LC_FREQ;
944 int n, p, r;
945 u32 wrpll;
946
947 wrpll = I915_READ(reg);
114fe488
DV		 948 switch (wrpll & WRPLL_PLL_REF_MASK) {
949 case WRPLL_PLL_SSC:
950 case WRPLL_PLL_NON_SSC:
11578553
JB		 951 /*
952 * We could calculate spread here, but our checking
953 * code only cares about 5% accuracy, and spread is a max of
954 * 0.5% downspread.
955 */
956 refclk = 135;
957 break;
114fe488 958 case WRPLL_PLL_LCPLL:
11578553
JB		 959 refclk = LC_FREQ;
960 break;
961 default:
962 WARN(1, "bad wrpll refclk\n");
963 return 0;
964 }
965
966 r = wrpll & WRPLL_DIVIDER_REF_MASK;
967 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
968 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
969
20f0ec16
JB		 970 /* Convert to KHz, p & r have a fixed point portion */
971 return (refclk * n * 100) / (p * r);
11578553
JB		 972}
973
540e732c
S		 974static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
975 uint32_t dpll)
976{
f0f59a00 977 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 978 uint32_t cfgcr1_val, cfgcr2_val;
979 uint32_t p0, p1, p2, dco_freq;
980
923c1241
VS		 981 cfgcr1_reg = DPLL_CFGCR1(dpll);
982 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 983
984 cfgcr1_val = I915_READ(cfgcr1_reg);
985 cfgcr2_val = I915_READ(cfgcr2_reg);
986
987 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
988 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
989
990 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
991 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
992 else
993 p1 = 1;
994
995
996 switch (p0) {
997 case DPLL_CFGCR2_PDIV_1:
998 p0 = 1;
999 break;
1000 case DPLL_CFGCR2_PDIV_2:
1001 p0 = 2;
1002 break;
1003 case DPLL_CFGCR2_PDIV_3:
1004 p0 = 3;
1005 break;
1006 case DPLL_CFGCR2_PDIV_7:
1007 p0 = 7;
1008 break;
1009 }
1010
1011 switch (p2) {
1012 case DPLL_CFGCR2_KDIV_5:
1013 p2 = 5;
1014 break;
1015 case DPLL_CFGCR2_KDIV_2:
1016 p2 = 2;
1017 break;
1018 case DPLL_CFGCR2_KDIV_3:
1019 p2 = 3;
1020 break;
1021 case DPLL_CFGCR2_KDIV_1:
1022 p2 = 1;
1023 break;
1024 }
1025
1026 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1027
1028 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1029 1000) / 0x8000;
1030
1031 return dco_freq / (p0 * p1 * p2 * 5);
1032}
1033
398a017e
VS		 1034static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1035{
1036 int dotclock;
1037
1038 if (pipe_config->has_pch_encoder)
1039 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1040 &pipe_config->fdi_m_n);
1041 else if (pipe_config->has_dp_encoder)
1042 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1043 &pipe_config->dp_m_n);
1044 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1045 dotclock = pipe_config->port_clock * 2 / 3;
1046 else
1047 dotclock = pipe_config->port_clock;
1048
1049 if (pipe_config->pixel_multiplier)
1050 dotclock /= pipe_config->pixel_multiplier;
1051
1052 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1053}
540e732c
S		 1054
1055static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1056 struct intel_crtc_state *pipe_config)
540e732c
S		 1057{
1058 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1059 int link_clock = 0;
1060 uint32_t dpll_ctl1, dpll;
1061
134ffa44 1062 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1063
1064 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1065
1066 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1067 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1068 } else {
71cd8423
DL		 1069 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1070 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1071
1072 switch (link_clock) {
71cd8423 1073 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1074 link_clock = 81000;
1075 break;
71cd8423 1076 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1077 link_clock = 108000;
1078 break;
71cd8423 1079 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1080 link_clock = 135000;
1081 break;
71cd8423 1082 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1083 link_clock = 162000;
1084 break;
71cd8423 1085 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1086 link_clock = 216000;
1087 break;
71cd8423 1088 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1089 link_clock = 270000;
1090 break;
1091 default:
1092 WARN(1, "Unsupported link rate\n");
1093 break;
1094 }
1095 link_clock *= 2;
1096 }
1097
1098 pipe_config->port_clock = link_clock;
1099
398a017e 1100 ddi_dotclock_get(pipe_config);
540e732c
S		 1101}
1102
3d51278a 1103static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1104 struct intel_crtc_state *pipe_config)
11578553
JB		 1105{
1106 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1107 int link_clock = 0;
1108 u32 val, pll;
1109
26804afd 1110 val = pipe_config->ddi_pll_sel;
11578553
JB		 1111 switch (val & PORT_CLK_SEL_MASK) {
1112 case PORT_CLK_SEL_LCPLL_810:
1113 link_clock = 81000;
1114 break;
1115 case PORT_CLK_SEL_LCPLL_1350:
1116 link_clock = 135000;
1117 break;
1118 case PORT_CLK_SEL_LCPLL_2700:
1119 link_clock = 270000;
1120 break;
1121 case PORT_CLK_SEL_WRPLL1:
01403de3 1122 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1123 break;
1124 case PORT_CLK_SEL_WRPLL2:
01403de3 1125 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1126 break;
1127 case PORT_CLK_SEL_SPLL:
1128 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1129 if (pll == SPLL_PLL_FREQ_810MHz)
1130 link_clock = 81000;
1131 else if (pll == SPLL_PLL_FREQ_1350MHz)
1132 link_clock = 135000;
1133 else if (pll == SPLL_PLL_FREQ_2700MHz)
1134 link_clock = 270000;
1135 else {
1136 WARN(1, "bad spll freq\n");
1137 return;
1138 }
1139 break;
1140 default:
1141 WARN(1, "bad port clock sel\n");
1142 return;
1143 }
1144
1145 pipe_config->port_clock = link_clock * 2;
1146
398a017e 1147 ddi_dotclock_get(pipe_config);
11578553
JB		 1148}
1149
977bb38d
S		 1150static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1151 enum intel_dpll_id dpll)
1152{
aa610dcb
ID		 1153 struct intel_shared_dpll *pll;
1154 struct intel_dpll_hw_state *state;
1155 intel_clock_t clock;
1156
1157 /* For DDI ports we always use a shared PLL. */
1158 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1159 return 0;
1160
1161 pll = &dev_priv->shared_dplls[dpll];
1162 state = &pll->config.hw_state;
1163
1164 clock.m1 = 2;
1165 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1166 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1167 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1168 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1169 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1170 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1171
1172 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1173}
1174
1175static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1176 struct intel_crtc_state *pipe_config)
1177{
1178 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1179 enum port port = intel_ddi_get_encoder_port(encoder);
1180 uint32_t dpll = port;
1181
398a017e 1182 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1183
398a017e 1184 ddi_dotclock_get(pipe_config);
977bb38d
S		 1185}
1186
3d51278a 1187void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1188 struct intel_crtc_state *pipe_config)
3d51278a 1189{
22606a18
DL		 1190 struct drm_device *dev = encoder->base.dev;
1191
1192 if (INTEL_INFO(dev)->gen <= 8)
1193 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 1194 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 1195 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1196 else if (IS_BROXTON(dev))
1197 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1198}
1199
1c0b85c5 1200static void
d664c0ce
DL		 1201hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1202 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1203{
1204 uint64_t freq2k;
1205 unsigned p, n2, r2;
63582983 1206 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1207 unsigned budget;
1208
1209 freq2k = clock / 100;
1210
63582983 1211 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1212
1213 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1214 * and directly pass the LC PLL to it. */
1215 if (freq2k == 5400000) {
1216 *n2_out = 2;
1217 *p_out = 1;
1218 *r2_out = 2;
1219 return;
1220 }
1221
1222 /*
1223 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1224 * the WR PLL.
1225 *
1226 * We want R so that REF_MIN <= Ref <= REF_MAX.
1227 * Injecting R2 = 2 * R gives:
1228 * REF_MAX * r2 > LC_FREQ * 2 and
1229 * REF_MIN * r2 < LC_FREQ * 2
1230 *
1231 * Which means the desired boundaries for r2 are:
1232 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1233 *
1234 */
1235 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1236 r2 <= LC_FREQ * 2 / REF_MIN;
1237 r2++) {
1238
1239 /*
1240 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1241 *
1242 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1243 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1244 * VCO_MAX * r2 > n2 * LC_FREQ and
1245 * VCO_MIN * r2 < n2 * LC_FREQ)
1246 *
1247 * Which means the desired boundaries for n2 are:
1248 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1249 */
1250 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1251 n2 <= VCO_MAX * r2 / LC_FREQ;
1252 n2++) {
1253
1254 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1255 hsw_wrpll_update_rnp(freq2k, budget,
1256 r2, n2, p, &best);
1c0b85c5
DL		 1257 }
1258 }
6441ab5f 1259
1c0b85c5
DL		 1260 *n2_out = best.n2;
1261 *p_out = best.p;
1262 *r2_out = best.r2;
6441ab5f
PZ		 1263}
1264
0220ab6e 1265static bool
d664c0ce 1266hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1267 struct intel_crtc_state *crtc_state,
96f3f1f9 1268 struct intel_encoder *intel_encoder)
6441ab5f 1269{
96f3f1f9
VS		 1270 int clock = crtc_state->port_clock;
1271
d664c0ce 1272 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1273 struct intel_shared_dpll *pll;
716c2e55 1274 uint32_t val;
1c0b85c5 1275 unsigned p, n2, r2;
6441ab5f 1276
d664c0ce 1277 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1278
114fe488 1279 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1280 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1281 WRPLL_DIVIDER_POST(p);
1282
dd3cd74a
ACO		 1283 memset(&crtc_state->dpll_hw_state, 0,
1284 sizeof(crtc_state->dpll_hw_state));
1285
190f68c5 1286 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1287
190f68c5 1288 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1289 if (pll == NULL) {
1290 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1291 pipe_name(intel_crtc->pipe));
1292 return false;
0694001b 1293 }
d452c5b6 1294
190f68c5 1295 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
00490c22
ML		 1296 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1297 struct drm_atomic_state *state = crtc_state->base.state;
1298 struct intel_shared_dpll_config *spll =
1299 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1300
1301 if (spll->crtc_mask &&
1302 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1303 return false;
1304
1305 crtc_state->shared_dpll = DPLL_ID_SPLL;
1306 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1307 spll->crtc_mask |= 1 << intel_crtc->pipe;
6441ab5f
PZ		 1308 }
1309
6441ab5f
PZ		 1310 return true;
1311}
1312
dc253813
DL		 1313struct skl_wrpll_context {
1314 uint64_t min_deviation; /* current minimal deviation */
1315 uint64_t central_freq; /* chosen central freq */
1316 uint64_t dco_freq; /* chosen dco freq */
1317 unsigned int p; /* chosen divider */
1318};
1319
1320static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1321{
1322 memset(ctx, 0, sizeof(*ctx));
1323
1324 ctx->min_deviation = U64_MAX;
1325}
1326
1327/* DCO freq must be within +1%/-6% of the DCO central freq */
1328#define SKL_DCO_MAX_PDEVIATION 100
1329#define SKL_DCO_MAX_NDEVIATION 600
1330
1331static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1332 uint64_t central_freq,
1333 uint64_t dco_freq,
1334 unsigned int divider)
1335{
1336 uint64_t deviation;
1337
1338 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1339 central_freq);
1340
1341 /* positive deviation */
1342 if (dco_freq >= central_freq) {
1343 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1344 deviation < ctx->min_deviation) {
1345 ctx->min_deviation = deviation;
1346 ctx->central_freq = central_freq;
1347 ctx->dco_freq = dco_freq;
1348 ctx->p = divider;
1349 }
1350 /* negative deviation */
1351 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1352 deviation < ctx->min_deviation) {
1353 ctx->min_deviation = deviation;
1354 ctx->central_freq = central_freq;
1355 ctx->dco_freq = dco_freq;
1356 ctx->p = divider;
1357 }
dc253813
DL		 1358}
1359
1360static void skl_wrpll_get_multipliers(unsigned int p,
1361 unsigned int *p0 /* out */,
1362 unsigned int *p1 /* out */,
1363 unsigned int *p2 /* out */)
1364{
1365 /* even dividers */
1366 if (p % 2 == 0) {
1367 unsigned int half = p / 2;
1368
1369 if (half == 1 || half == 2 || half == 3 || half == 5) {
1370 *p0 = 2;
1371 *p1 = 1;
1372 *p2 = half;
1373 } else if (half % 2 == 0) {
1374 *p0 = 2;
1375 *p1 = half / 2;
1376 *p2 = 2;
1377 } else if (half % 3 == 0) {
1378 *p0 = 3;
1379 *p1 = half / 3;
1380 *p2 = 2;
1381 } else if (half % 7 == 0) {
1382 *p0 = 7;
1383 *p1 = half / 7;
1384 *p2 = 2;
1385 }
1386 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1387 *p0 = 3;
1388 *p1 = 1;
1389 *p2 = p / 3;
1390 } else if (p == 5 || p == 7) {
1391 *p0 = p;
1392 *p1 = 1;
1393 *p2 = 1;
1394 } else if (p == 15) {
1395 *p0 = 3;
1396 *p1 = 1;
1397 *p2 = 5;
1398 } else if (p == 21) {
1399 *p0 = 7;
1400 *p1 = 1;
1401 *p2 = 3;
1402 } else if (p == 35) {
1403 *p0 = 7;
1404 *p1 = 1;
1405 *p2 = 5;
1406 }
1407}
1408
82d35437
S		 1409struct skl_wrpll_params {
1410 uint32_t dco_fraction;
1411 uint32_t dco_integer;
1412 uint32_t qdiv_ratio;
1413 uint32_t qdiv_mode;
1414 uint32_t kdiv;
1415 uint32_t pdiv;
1416 uint32_t central_freq;
1417};
1418
76516fbc
DL		 1419static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1420 uint64_t afe_clock,
1421 uint64_t central_freq,
1422 uint32_t p0, uint32_t p1, uint32_t p2)
1423{
1424 uint64_t dco_freq;
1425
76516fbc
DL		 1426 switch (central_freq) {
1427 case 9600000000ULL:
1428 params->central_freq = 0;
1429 break;
1430 case 9000000000ULL:
1431 params->central_freq = 1;
1432 break;
1433 case 8400000000ULL:
1434 params->central_freq = 3;
1435 }
1436
1437 switch (p0) {
1438 case 1:
1439 params->pdiv = 0;
1440 break;
1441 case 2:
1442 params->pdiv = 1;
1443 break;
1444 case 3:
1445 params->pdiv = 2;
1446 break;
1447 case 7:
1448 params->pdiv = 4;
1449 break;
1450 default:
1451 WARN(1, "Incorrect PDiv\n");
1452 }
1453
1454 switch (p2) {
1455 case 5:
1456 params->kdiv = 0;
1457 break;
1458 case 2:
1459 params->kdiv = 1;
1460 break;
1461 case 3:
1462 params->kdiv = 2;
1463 break;
1464 case 1:
1465 params->kdiv = 3;
1466 break;
1467 default:
1468 WARN(1, "Incorrect KDiv\n");
1469 }
1470
1471 params->qdiv_ratio = p1;
1472 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1473
1474 dco_freq = p0 * p1 * p2 * afe_clock;
1475
1476 /*
1477 * Intermediate values are in Hz.
1478 * Divide by MHz to match bsepc
1479 */
30a7862d 1480 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1481 params->dco_fraction =
30a7862d
DL		 1482 div_u64((div_u64(dco_freq, 24) -
1483 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1484}
1485
318bd821 1486static bool
82d35437
S		 1487skl_ddi_calculate_wrpll(int clock /* in Hz */,
1488 struct skl_wrpll_params *wrpll_params)
1489{
1490 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1491 uint64_t dco_central_freq[3] = {8400000000ULL,
1492 9000000000ULL,
1493 9600000000ULL};
dc253813
DL		 1494 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1495 24, 28, 30, 32, 36, 40, 42, 44,
1496 48, 52, 54, 56, 60, 64, 66, 68,
1497 70, 72, 76, 78, 80, 84, 88, 90,
1498 92, 96, 98 };
1499 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1500 static const struct {
1501 const int *list;
1502 int n_dividers;
1503 } dividers[] = {
1504 { even_dividers, ARRAY_SIZE(even_dividers) },
1505 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1506 };
1507 struct skl_wrpll_context ctx;
1508 unsigned int dco, d, i;
1509 unsigned int p0, p1, p2;
1510
1511 skl_wrpll_context_init(&ctx);
1512
1513 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1514 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1515 for (i = 0; i < dividers[d].n_dividers; i++) {
1516 unsigned int p = dividers[d].list[i];
1517 uint64_t dco_freq = p * afe_clock;
1518
1519 skl_wrpll_try_divider(&ctx,
1520 dco_central_freq[dco],
1521 dco_freq,
1522 p);
e7ad9878
DL		 1523 /*
1524 * Skip the remaining dividers if we're sure to
1525 * have found the definitive divider, we can't
1526 * improve a 0 deviation.
1527 */
1528 if (ctx.min_deviation == 0)
1529 goto skip_remaining_dividers;
82d35437
S		 1530 }
1531 }
267db663 1532
e7ad9878 1533skip_remaining_dividers:
267db663
DL		 1534 /*
1535 * If a solution is found with an even divider, prefer
1536 * this one.
1537 */
1538 if (d == 0 && ctx.p)
1539 break;
82d35437
S		 1540 }
1541
dc253813
DL		 1542 if (!ctx.p) {
1543 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1544 return false;
dc253813 1545 }
82d35437 1546
dc253813
DL		 1547 /*
1548 * gcc incorrectly analyses that these can be used without being
1549 * initialized. To be fair, it's hard to guess.
1550 */
1551 p0 = p1 = p2 = 0;
1552 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1553 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1554 p0, p1, p2);
318bd821
DL		 1555
1556 return true;
82d35437
S		 1557}
1558
82d35437
S		 1559static bool
1560skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1561 struct intel_crtc_state *crtc_state,
96f3f1f9 1562 struct intel_encoder *intel_encoder)
82d35437
S		 1563{
1564 struct intel_shared_dpll *pll;
1565 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1566 int clock = crtc_state->port_clock;
82d35437
S		 1567
1568 /*
1569 * See comment in intel_dpll_hw_state to understand why we always use 0
1570 * as the DPLL id in this function.
1571 */
1572
1573 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1574
1575 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1576 struct skl_wrpll_params wrpll_params = { 0, };
1577
1578 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1579
318bd821
DL		 1580 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1581 return false;
82d35437
S		 1582
1583 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1584 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1585 wrpll_params.dco_integer;
1586
1587 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1588 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1589 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1590 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1591 wrpll_params.central_freq;
3d849b02
L		 1592 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1593 intel_encoder->type == INTEL_OUTPUT_DP_MST) {
840b32b7
VS		 1594 switch (crtc_state->port_clock / 2) {
1595 case 81000:
71cd8423 1596 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1597 break;
840b32b7 1598 case 135000:
71cd8423 1599 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1600 break;
840b32b7 1601 case 270000:
71cd8423 1602 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1603 break;
1604 }
1605
1606 cfgcr1 = cfgcr2 = 0;
1607 } else /* eDP */
1608 return true;
1609
dd3cd74a
ACO		 1610 memset(&crtc_state->dpll_hw_state, 0,
1611 sizeof(crtc_state->dpll_hw_state));
1612
190f68c5
ACO		 1613 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1614 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1615 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1616
190f68c5 1617 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1618 if (pll == NULL) {
1619 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1620 pipe_name(intel_crtc->pipe));
1621 return false;
1622 }
1623
1624 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1625 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1626
1627 return true;
1628}
0220ab6e 1629
d683f3bc
S		 1630/* bxt clock parameters */
1631struct bxt_clk_div {
64987fc5 1632 int clock;
d683f3bc
S		 1633 uint32_t p1;
1634 uint32_t p2;
1635 uint32_t m2_int;
1636 uint32_t m2_frac;
1637 bool m2_frac_en;
1638 uint32_t n;
d683f3bc
S		 1639};
1640
1641/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1642static const struct bxt_clk_div bxt_dp_clk_val[] = {
1643 {162000, 4, 2, 32, 1677722, 1, 1},
1644 {270000, 4, 1, 27, 0, 0, 1},
1645 {540000, 2, 1, 27, 0, 0, 1},
1646 {216000, 3, 2, 32, 1677722, 1, 1},
1647 {243000, 4, 1, 24, 1258291, 1, 1},
1648 {324000, 4, 1, 32, 1677722, 1, 1},
1649 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1650};
1651
1652static bool
1653bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1654 struct intel_crtc_state *crtc_state,
96f3f1f9 1655 struct intel_encoder *intel_encoder)
d683f3bc
S		 1656{
1657 struct intel_shared_dpll *pll;
1658 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1659 int vco = 0;
1660 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1661 uint32_t lanestagger;
96f3f1f9 1662 int clock = crtc_state->port_clock;
d683f3bc
S		 1663
1664 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1665 intel_clock_t best_clock;
1666
1667 /* Calculate HDMI div */
1668 /*
1669 * FIXME: tie the following calculation into
1670 * i9xx_crtc_compute_clock
1671 */
1672 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1673 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1674 clock, pipe_name(intel_crtc->pipe));
1675 return false;
1676 }
1677
1678 clk_div.p1 = best_clock.p1;
1679 clk_div.p2 = best_clock.p2;
1680 WARN_ON(best_clock.m1 != 2);
1681 clk_div.n = best_clock.n;
1682 clk_div.m2_int = best_clock.m2 >> 22;
1683 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1684 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1685
b6dc71f3 1686 vco = best_clock.vco;
d683f3bc
S		 1687 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1688 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1689 int i;
d683f3bc 1690
64987fc5
SJ		 1691 clk_div = bxt_dp_clk_val[0];
1692 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1693 if (bxt_dp_clk_val[i].clock == clock) {
1694 clk_div = bxt_dp_clk_val[i];
1695 break;
1696 }
d683f3bc 1697 }
b6dc71f3
VK		 1698 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1699 }
1700
e6292556 1701 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1702 prop_coef = 4;
1703 int_coef = 9;
1704 gain_ctl = 3;
1705 targ_cnt = 8;
1706 } else if ((vco > 5400000 && vco < 6200000) ||
1707 (vco >= 4800000 && vco < 5400000)) {
1708 prop_coef = 5;
1709 int_coef = 11;
1710 gain_ctl = 3;
1711 targ_cnt = 9;
b6dc71f3
VK		 1712 } else if (vco == 5400000) {
1713 prop_coef = 3;
1714 int_coef = 8;
1715 gain_ctl = 1;
1716 targ_cnt = 9;
1717 } else {
1718 DRM_ERROR("Invalid VCO\n");
1719 return false;
d683f3bc
S		 1720 }
1721
dd3cd74a
ACO		 1722 memset(&crtc_state->dpll_hw_state, 0,
1723 sizeof(crtc_state->dpll_hw_state));
1724
e0681e38
VK		 1725 if (clock > 270000)
1726 lanestagger = 0x18;
1727 else if (clock > 135000)
1728 lanestagger = 0x0d;
1729 else if (clock > 67000)
1730 lanestagger = 0x07;
1731 else if (clock > 33000)
1732 lanestagger = 0x04;
1733 else
1734 lanestagger = 0x02;
1735
d683f3bc
S		 1736 crtc_state->dpll_hw_state.ebb0 =
1737 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1738 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1739 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1740 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1741
1742 if (clk_div.m2_frac_en)
1743 crtc_state->dpll_hw_state.pll3 =
1744 PORT_PLL_M2_FRAC_ENABLE;
1745
1746 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1747 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1748 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1749 PORT_PLL_GAIN_CTL(gain_ctl);
1750
1751 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1752
05712c15
ID		 1753 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1754
e6292556
VK		 1755 crtc_state->dpll_hw_state.pll10 =
1756 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1757 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1758
05712c15
ID		 1759 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1760
d683f3bc 1761 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1762 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1763
1764 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1765 if (pll == NULL) {
1766 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1767 pipe_name(intel_crtc->pipe));
1768 return false;
1769 }
1770
1771 /* shared DPLL id 0 is DPLL A */
1772 crtc_state->ddi_pll_sel = pll->id;
1773
1774 return true;
1775}
1776
0220ab6e
DL		 1777/*
1778 * Tries to find a *shared* PLL for the CRTC and store it in
1779 * intel_crtc->ddi_pll_sel.
1780 *
1781 * For private DPLLs, compute_config() should do the selection for us. This
1782 * function should be folded into compute_config() eventually.
1783 */
190f68c5
ACO		 1784bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1785 struct intel_crtc_state *crtc_state)
0220ab6e 1786{
82d35437 1787 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1788 struct intel_encoder *intel_encoder =
3165c074 1789 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1790
ef11bdb3 1791 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1792 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1793 intel_encoder);
d683f3bc
S		 1794 else if (IS_BROXTON(dev))
1795 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1796 intel_encoder);
82d35437 1797 else
190f68c5 1798 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1799 intel_encoder);
0220ab6e
DL		 1800}
1801
dae84799
PZ		 1802void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1803{
1804 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1807 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1808 int type = intel_encoder->type;
1809 uint32_t temp;
1810
0e32b39c 1811 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1812 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1813 switch (intel_crtc->config->pipe_bpp) {
dae84799 1814 case 18:
c9809791 1815 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1816 break;
1817 case 24:
c9809791 1818 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1819 break;
1820 case 30:
c9809791 1821 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1822 break;
1823 case 36:
c9809791 1824 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1825 break;
1826 default:
4e53c2e0 1827 BUG();
dae84799 1828 }
c9809791 1829 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1830 }
1831}
1832
0e32b39c
DA		 1833void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1834{
1835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1836 struct drm_device *dev = crtc->dev;
1837 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1838 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1839 uint32_t temp;
1840 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1841 if (state == true)
1842 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1843 else
1844 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1845 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1846}
1847
8228c251 1848void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1849{
1850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1851 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1852 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1853 struct drm_device *dev = crtc->dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1855 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1856 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1857 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1858 int type = intel_encoder->type;
8d9ddbcb
PZ		 1859 uint32_t temp;
1860
ad80a810
PZ		 1861 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1862 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1863 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1864
6e3c9717 1865 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1866 case 18:
ad80a810 1867 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1868 break;
1869 case 24:
ad80a810 1870 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1871 break;
1872 case 30:
ad80a810 1873 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1874 break;
1875 case 36:
ad80a810 1876 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1877 break;
1878 default:
4e53c2e0 1879 BUG();
dfcef252 1880 }
72662e10 1881
6e3c9717 1882 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1883 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1884 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1885 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1886
e6f0bfc4
PZ		 1887 if (cpu_transcoder == TRANSCODER_EDP) {
1888 switch (pipe) {
1889 case PIPE_A:
c7670b10
PZ		 1890 /* On Haswell, can only use the always-on power well for
1891 * eDP when not using the panel fitter, and when not
1892 * using motion blur mitigation (which we don't
1893 * support). */
fabf6e51 1894 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1895 (intel_crtc->config->pch_pfit.enabled ||
1896 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1897 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1898 else
1899 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1900 break;
1901 case PIPE_B:
1902 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1903 break;
1904 case PIPE_C:
1905 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1906 break;
1907 default:
1908 BUG();
1909 break;
1910 }
1911 }
1912
7739c33b 1913 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1914 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1915 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1916 else
ad80a810 1917 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1918
7739c33b 1919 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1920 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1921 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1922
1923 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1924 type == INTEL_OUTPUT_EDP) {
1925 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1926
0e32b39c
DA		 1927 if (intel_dp->is_mst) {
1928 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1929 } else
1930 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1931
90a6b7b0 1932 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1933 } else if (type == INTEL_OUTPUT_DP_MST) {
1934 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1935
1936 if (intel_dp->is_mst) {
1937 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1938 } else
1939 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1940
90a6b7b0 1941 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1942 } else {
84f44ce7
VS		 1943 WARN(1, "Invalid encoder type %d for pipe %c\n",
1944 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1945 }
1946
ad80a810 1947 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1948}
72662e10 1949
ad80a810
PZ		 1950void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1951 enum transcoder cpu_transcoder)
8d9ddbcb 1952{
f0f59a00 1953 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1954 uint32_t val = I915_READ(reg);
1955
0e32b39c 1956 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1957 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1958 I915_WRITE(reg, val);
72662e10
ED		 1959}
1960
bcbc889b
PZ		 1961bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1962{
1963 struct drm_device *dev = intel_connector->base.dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_encoder *intel_encoder = intel_connector->encoder;
1966 int type = intel_connector->base.connector_type;
1967 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1968 enum pipe pipe = 0;
1969 enum transcoder cpu_transcoder;
882244a3 1970 enum intel_display_power_domain power_domain;
bcbc889b 1971 uint32_t tmp;
d5941021 1972 bool ret;
bcbc889b 1973
882244a3 1974 power_domain = intel_display_port_power_domain(intel_encoder);
d5941021 1975 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
882244a3
PZ		 1976 return false;
1977
d5941021
ID		 1978 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1979 ret = false;
1980 goto out;
1981 }
bcbc889b
PZ		 1982
1983 if (port == PORT_A)
1984 cpu_transcoder = TRANSCODER_EDP;
1985 else
1a240d4d 1986 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1987
1988 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1989
1990 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1991 case TRANS_DDI_MODE_SELECT_HDMI:
1992 case TRANS_DDI_MODE_SELECT_DVI:
d5941021
ID		 1993 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1994 break;
bcbc889b
PZ		 1995
1996 case TRANS_DDI_MODE_SELECT_DP_SST:
d5941021
ID		 1997 ret = type == DRM_MODE_CONNECTOR_eDP ||
1998 type == DRM_MODE_CONNECTOR_DisplayPort;
1999 break;
2000
0e32b39c
DA		 2001 case TRANS_DDI_MODE_SELECT_DP_MST:
2002 /* if the transcoder is in MST state then
2003 * connector isn't connected */
d5941021
ID		 2004 ret = false;
2005 break;
bcbc889b
PZ		 2006
2007 case TRANS_DDI_MODE_SELECT_FDI:
d5941021
ID		 2008 ret = type == DRM_MODE_CONNECTOR_VGA;
2009 break;
bcbc889b
PZ		 2010
2011 default:
d5941021
ID		 2012 ret = false;
2013 break;
bcbc889b 2014 }
d5941021
ID		 2015
2016out:
2017 intel_display_power_put(dev_priv, power_domain);
2018
2019 return ret;
bcbc889b
PZ		 2020}
2021
85234cdc
DV		 2022bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2023 enum pipe *pipe)
2024{
2025 struct drm_device *dev = encoder->base.dev;
2026 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 2027 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 2028 enum intel_display_power_domain power_domain;
85234cdc
DV		 2029 u32 tmp;
2030 int i;
d5941021 2031 bool ret;
85234cdc 2032
6d129bea 2033 power_domain = intel_display_port_power_domain(encoder);
d5941021 2034 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2035 return false;
2036
d5941021
ID		 2037 ret = false;
2038
fe43d3f5 2039 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2040
2041 if (!(tmp & DDI_BUF_CTL_ENABLE))
d5941021 2042 goto out;
85234cdc 2043
ad80a810
PZ		 2044 if (port == PORT_A) {
2045 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2046
ad80a810
PZ		 2047 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2048 case TRANS_DDI_EDP_INPUT_A_ON:
2049 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2050 *pipe = PIPE_A;
2051 break;
2052 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2053 *pipe = PIPE_B;
2054 break;
2055 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2056 *pipe = PIPE_C;
2057 break;
2058 }
2059
d5941021 2060 ret = true;
ad80a810 2061
d5941021
ID		 2062 goto out;
2063 }
0e32b39c 2064
d5941021
ID		 2065 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2066 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2067
2068 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
2069 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2070 TRANS_DDI_MODE_SELECT_DP_MST)
2071 goto out;
2072
2073 *pipe = i;
2074 ret = true;
2075
2076 goto out;
85234cdc
DV		 2077 }
2078 }
2079
84f44ce7 2080 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2081
d5941021
ID		 2082out:
2083 intel_display_power_put(dev_priv, power_domain);
2084
2085 return ret;
85234cdc
DV		 2086}
2087
fc914639
PZ		 2088void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2089{
2090 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0
SS		 2091 struct drm_device *dev = crtc->dev;
2092 struct drm_i915_private *dev_priv = dev->dev_private;
fc914639
PZ		 2093 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2094 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2095 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2096
bb523fc0
PZ		 2097 if (cpu_transcoder != TRANSCODER_EDP)
2098 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2099 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2100}
2101
2102void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2103{
2104 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2105 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2106
bb523fc0
PZ		 2107 if (cpu_transcoder != TRANSCODER_EDP)
2108 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2109 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2110}
2111
f8896f5d
DW		 2112static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2113 enum port port, int type)
2114{
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116 const struct ddi_buf_trans *ddi_translations;
2117 uint8_t iboost;
75067dde 2118 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2119 int n_entries;
2120 u32 reg;
2121
75067dde
AK		 2122 /* VBT may override standard boost values */
2123 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2124 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2125
f8896f5d 2126 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2127 if (dp_iboost) {
2128 iboost = dp_iboost;
2129 } else {
2130 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
e4d4c05b 2131 iboost = ddi_translations[level].i_boost;
75067dde 2132 }
f8896f5d 2133 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2134 if (dp_iboost) {
2135 iboost = dp_iboost;
2136 } else {
2137 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
e4d4c05b 2138 iboost = ddi_translations[level].i_boost;
75067dde 2139 }
f8896f5d 2140 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2141 if (hdmi_iboost) {
2142 iboost = hdmi_iboost;
2143 } else {
2144 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
e4d4c05b 2145 iboost = ddi_translations[level].i_boost;
75067dde 2146 }
f8896f5d
DW		 2147 } else {
2148 return;
2149 }
2150
2151 /* Make sure that the requested I_boost is valid */
2152 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2153 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2154 return;
2155 }
2156
2157 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2158 reg &= ~BALANCE_LEG_MASK(port);
2159 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2160
2161 if (iboost)
2162 reg |= iboost << BALANCE_LEG_SHIFT(port);
2163 else
2164 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2165
2166 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2167}
2168
2169static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2170 enum port port, int type)
96fb9f9b
VK		 2171{
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 const struct bxt_ddi_buf_trans *ddi_translations;
2174 u32 n_entries, i;
2175 uint32_t val;
2176
d9d7000d
SJ		 2177 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2178 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2179 ddi_translations = bxt_ddi_translations_edp;
2180 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2181 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 2182 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2183 ddi_translations = bxt_ddi_translations_dp;
2184 } else if (type == INTEL_OUTPUT_HDMI) {
2185 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2186 ddi_translations = bxt_ddi_translations_hdmi;
2187 } else {
2188 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2189 type);
2190 return;
2191 }
2192
2193 /* Check if default value has to be used */
2194 if (level >= n_entries ||
2195 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2196 for (i = 0; i < n_entries; i++) {
2197 if (ddi_translations[i].default_index) {
2198 level = i;
2199 break;
2200 }
2201 }
2202 }
2203
2204 /*
2205 * While we write to the group register to program all lanes at once we
2206 * can read only lane registers and we pick lanes 0/1 for that.
2207 */
2208 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2209 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2210 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2211
2212 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2213 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2214 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2215 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2216 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2217
2218 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 2219 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 2220 if (ddi_translations[level].enable)
9c58a049
SJ		 2221 val |= SCALE_DCOMP_METHOD;
2222
2223 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2224 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2225
96fb9f9b
VK		 2226 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2227
2228 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2229 val &= ~DE_EMPHASIS;
2230 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2231 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2232
2233 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2234 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2235 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2236}
2237
f8896f5d
DW		 2238static uint32_t translate_signal_level(int signal_levels)
2239{
2240 uint32_t level;
2241
2242 switch (signal_levels) {
2243 default:
2244 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2245 signal_levels);
2246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2247 level = 0;
2248 break;
2249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2250 level = 1;
2251 break;
2252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2253 level = 2;
2254 break;
2255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2256 level = 3;
2257 break;
2258
2259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2260 level = 4;
2261 break;
2262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2263 level = 5;
2264 break;
2265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2266 level = 6;
2267 break;
2268
2269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2270 level = 7;
2271 break;
2272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2273 level = 8;
2274 break;
2275
2276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2277 level = 9;
2278 break;
2279 }
2280
2281 return level;
2282}
2283
2284uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2285{
2286 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2287 struct drm_device *dev = dport->base.base.dev;
2288 struct intel_encoder *encoder = &dport->base;
2289 uint8_t train_set = intel_dp->train_set[0];
2290 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2291 DP_TRAIN_PRE_EMPHASIS_MASK);
2292 enum port port = dport->port;
2293 uint32_t level;
2294
2295 level = translate_signal_level(signal_levels);
2296
ef11bdb3 2297 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
f8896f5d
DW		 2298 skl_ddi_set_iboost(dev, level, port, encoder->type);
2299 else if (IS_BROXTON(dev))
2300 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2301
2302 return DDI_BUF_TRANS_SELECT(level);
2303}
2304
e404ba8d
VS		 2305void intel_ddi_clk_select(struct intel_encoder *encoder,
2306 const struct intel_crtc_state *pipe_config)
6441ab5f 2307{
e404ba8d
VS		 2308 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2309 enum port port = intel_ddi_get_encoder_port(encoder);
6441ab5f 2310
e404ba8d
VS		 2311 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2312 uint32_t dpll = pipe_config->ddi_pll_sel;
efa80add
S		 2313 uint32_t val;
2314
5416d871
DL		 2315 /*
2316 * DPLL0 is used for eDP and is the only "private" DPLL (as
2317 * opposed to shared) on SKL
2318 */
e404ba8d 2319 if (encoder->type == INTEL_OUTPUT_EDP) {
5416d871
DL		 2320 WARN_ON(dpll != SKL_DPLL0);
2321
2322 val = I915_READ(DPLL_CTRL1);
2323
2324 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2325 DPLL_CTRL1_SSC(dpll) |
71cd8423 2326 DPLL_CTRL1_LINK_RATE_MASK(dpll));
e404ba8d 2327 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2328
2329 I915_WRITE(DPLL_CTRL1, val);
2330 POSTING_READ(DPLL_CTRL1);
2331 }
2332
2333 /* DDI -> PLL mapping */
efa80add
S		 2334 val = I915_READ(DPLL_CTRL2);
2335
2336 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2337 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2338 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2339 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2340
2341 I915_WRITE(DPLL_CTRL2, val);
5416d871 2342
e404ba8d
VS		 2343 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2344 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2345 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
efa80add 2346 }
e404ba8d
VS		 2347}
2348
2349static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2350{
2351 struct drm_encoder *encoder = &intel_encoder->base;
2352 struct drm_device *dev = encoder->dev;
2353 struct drm_i915_private *dev_priv = dev->dev_private;
2354 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2355 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2356 int type = intel_encoder->type;
2357 int hdmi_level;
2358
2359 if (type == INTEL_OUTPUT_EDP) {
2360 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2361 intel_edp_panel_on(intel_dp);
2362 }
2363
2364 intel_ddi_clk_select(intel_encoder, crtc->config);
c19b0669 2365
82a4d9c0 2366 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2367 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2368
901c2daf
VS		 2369 intel_dp_set_link_params(intel_dp, crtc->config);
2370
44905a27 2371 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2372
2373 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2374 intel_dp_start_link_train(intel_dp);
23f08d83 2375 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2376 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2377 } else if (type == INTEL_OUTPUT_HDMI) {
2378 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2379
96fb9f9b
VK		 2380 if (IS_BROXTON(dev)) {
2381 hdmi_level = dev_priv->vbt.
2382 ddi_port_info[port].hdmi_level_shift;
2383 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2384 INTEL_OUTPUT_HDMI);
2385 }
30cf6db8 2386 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2387 crtc->config->has_hdmi_sink,
2388 &crtc->config->base.adjusted_mode);
c19b0669 2389 }
6441ab5f
PZ		 2390}
2391
00c09d70 2392static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2393{
2394 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2395 struct drm_device *dev = encoder->dev;
2396 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2397 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2398 int type = intel_encoder->type;
2886e93f 2399 uint32_t val;
a836bdf9 2400 bool wait = false;
2886e93f
PZ		 2401
2402 val = I915_READ(DDI_BUF_CTL(port));
2403 if (val & DDI_BUF_CTL_ENABLE) {
2404 val &= ~DDI_BUF_CTL_ENABLE;
2405 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2406 wait = true;
2886e93f 2407 }
6441ab5f 2408
a836bdf9
PZ		 2409 val = I915_READ(DP_TP_CTL(port));
2410 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2411 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2412 I915_WRITE(DP_TP_CTL(port), val);
2413
2414 if (wait)
2415 intel_wait_ddi_buf_idle(dev_priv, port);
2416
76bb80ed 2417 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2418 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2419 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2420 intel_edp_panel_vdd_on(intel_dp);
4be73780 2421 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2422 }
2423
ef11bdb3 2424 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 2425 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2426 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2427 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2428 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2429}
2430
00c09d70 2431static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2432{
6547fef8 2433 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2434 struct drm_crtc *crtc = encoder->crtc;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2436 struct drm_device *dev = encoder->dev;
72662e10 2437 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2438 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2439 int type = intel_encoder->type;
72662e10 2440
6547fef8 2441 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2442 struct intel_digital_port *intel_dig_port =
2443 enc_to_dig_port(encoder);
2444
6547fef8
PZ		 2445 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2446 * are ignored so nothing special needs to be done besides
2447 * enabling the port.
2448 */
876a8cdf 2449 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2450 intel_dig_port->saved_port_bits |
2451 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2452 } else if (type == INTEL_OUTPUT_EDP) {
2453 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2454
23f08d83 2455 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2456 intel_dp_stop_link_train(intel_dp);
2457
4be73780 2458 intel_edp_backlight_on(intel_dp);
0bc12bcb 2459 intel_psr_enable(intel_dp);
c395578e 2460 intel_edp_drrs_enable(intel_dp);
6547fef8 2461 }
7b9f35a6 2462
6e3c9717 2463 if (intel_crtc->config->has_audio) {
d45a0bf5 2464 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2465 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2466 }
5ab432ef
DV		 2467}
2468
00c09d70 2469static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2470{
d6c50ff8 2471 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2472 struct drm_crtc *crtc = encoder->crtc;
2473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2474 int type = intel_encoder->type;
7b9f35a6
WX		 2475 struct drm_device *dev = encoder->dev;
2476 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2477
6e3c9717 2478 if (intel_crtc->config->has_audio) {
69bfe1a9 2479 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2480 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2481 }
2831d842 2482
d6c50ff8
PZ		 2483 if (type == INTEL_OUTPUT_EDP) {
2484 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2485
c395578e 2486 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2487 intel_psr_disable(intel_dp);
4be73780 2488 intel_edp_backlight_off(intel_dp);
d6c50ff8 2489 }
72662e10 2490}
79f689aa 2491
00490c22 2492static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
e0b01be4
DV		 2493 struct intel_shared_dpll *pll)
2494{
3e369b76 2495 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2496 POSTING_READ(WRPLL_CTL(pll->id));
2497 udelay(20);
2498}
2499
00490c22 2500static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
12030431 2501 struct intel_shared_dpll *pll)
00490c22
ML		 2502{
2503 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2504 POSTING_READ(SPLL_CTL);
2505 udelay(20);
2506}
2507
2508static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2509 struct intel_shared_dpll *pll)
12030431
DV		 2510{
2511 uint32_t val;
2512
2513 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2514 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2515 POSTING_READ(WRPLL_CTL(pll->id));
2516}
2517
00490c22
ML		 2518static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2519 struct intel_shared_dpll *pll)
2520{
2521 uint32_t val;
2522
2523 val = I915_READ(SPLL_CTL);
2524 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2525 POSTING_READ(SPLL_CTL);
2526}
2527
2528static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2529 struct intel_shared_dpll *pll,
2530 struct intel_dpll_hw_state *hw_state)
d452c5b6
DV		 2531{
2532 uint32_t val;
2533
d5941021 2534 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2535 return false;
2536
2537 val = I915_READ(WRPLL_CTL(pll->id));
2538 hw_state->wrpll = val;
2539
d5941021
ID		 2540 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2541
d452c5b6
DV		 2542 return val & WRPLL_PLL_ENABLE;
2543}
2544
00490c22
ML		 2545static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2546 struct intel_shared_dpll *pll,
2547 struct intel_dpll_hw_state *hw_state)
2548{
2549 uint32_t val;
2550
d5941021 2551 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
00490c22
ML		 2552 return false;
2553
2554 val = I915_READ(SPLL_CTL);
2555 hw_state->spll = val;
2556
d5941021
ID		 2557 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2558
00490c22
ML		 2559 return val & SPLL_PLL_ENABLE;
2560}
2561
2562
ca1381b5 2563static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2564 "WRPLL 1",
2565 "WRPLL 2",
00490c22 2566 "SPLL"
9cd86933
DV		 2567};
2568
143b307c 2569static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2570{
9cd86933
DV		 2571 int i;
2572
00490c22 2573 dev_priv->num_shared_dpll = 3;
9cd86933 2574
00490c22 2575 for (i = 0; i < 2; i++) {
9cd86933
DV		 2576 dev_priv->shared_dplls[i].id = i;
2577 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
00490c22
ML		 2578 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2579 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
d452c5b6 2580 dev_priv->shared_dplls[i].get_hw_state =
00490c22 2581 hsw_ddi_wrpll_get_hw_state;
9cd86933 2582 }
00490c22
ML		 2583
2584 /* SPLL is special, but needs to be initialized anyway.. */
2585 dev_priv->shared_dplls[i].id = i;
2586 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2587 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2588 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2589 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2590
143b307c
DL		 2591}
2592
d1a2dc78
S		 2593static const char * const skl_ddi_pll_names[] = {
2594 "DPLL 1",
2595 "DPLL 2",
2596 "DPLL 3",
2597};
2598
2599struct skl_dpll_regs {
f0f59a00 2600 i915_reg_t ctl, cfgcr1, cfgcr2;
d1a2dc78
S		 2601};
2602
2603/* this array is indexed by the *shared* pll id */
2604static const struct skl_dpll_regs skl_dpll_regs[3] = {
2605 {
2606 /* DPLL 1 */
2607 .ctl = LCPLL2_CTL,
923c1241
VS		 2608 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2609 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
d1a2dc78
S		 2610 },
2611 {
2612 /* DPLL 2 */
01403de3 2613 .ctl = WRPLL_CTL(0),
923c1241
VS		 2614 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2615 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
d1a2dc78
S		 2616 },
2617 {
2618 /* DPLL 3 */
01403de3 2619 .ctl = WRPLL_CTL(1),
923c1241
VS		 2620 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2621 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
d1a2dc78
S		 2622 },
2623};
2624
2625static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2626 struct intel_shared_dpll *pll)
2627{
2628 uint32_t val;
2629 unsigned int dpll;
2630 const struct skl_dpll_regs *regs = skl_dpll_regs;
2631
2632 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2633 dpll = pll->id + 1;
2634
2635 val = I915_READ(DPLL_CTRL1);
2636
2637 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2638 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2639 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2640
2641 I915_WRITE(DPLL_CTRL1, val);
2642 POSTING_READ(DPLL_CTRL1);
2643
2644 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2645 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2646 POSTING_READ(regs[pll->id].cfgcr1);
2647 POSTING_READ(regs[pll->id].cfgcr2);
2648
2649 /* the enable bit is always bit 31 */
2650 I915_WRITE(regs[pll->id].ctl,
2651 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2652
2653 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2654 DRM_ERROR("DPLL %d not locked\n", dpll);
2655}
2656
2657static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2658 struct intel_shared_dpll *pll)
2659{
2660 const struct skl_dpll_regs *regs = skl_dpll_regs;
2661
2662 /* the enable bit is always bit 31 */
2663 I915_WRITE(regs[pll->id].ctl,
2664 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2665 POSTING_READ(regs[pll->id].ctl);
2666}
2667
2668static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2669 struct intel_shared_dpll *pll,
2670 struct intel_dpll_hw_state *hw_state)
2671{
2672 uint32_t val;
2673 unsigned int dpll;
2674 const struct skl_dpll_regs *regs = skl_dpll_regs;
d5941021 2675 bool ret;
d1a2dc78 2676
d5941021 2677 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
d1a2dc78
S		 2678 return false;
2679
d5941021
ID		 2680 ret = false;
2681
d1a2dc78
S		 2682 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2683 dpll = pll->id + 1;
2684
2685 val = I915_READ(regs[pll->id].ctl);
2686 if (!(val & LCPLL_PLL_ENABLE))
d5941021 2687 goto out;
d1a2dc78
S		 2688
2689 val = I915_READ(DPLL_CTRL1);
2690 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2691
2692 /* avoid reading back stale values if HDMI mode is not enabled */
2693 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2694 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2695 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2696 }
d5941021 2697 ret = true;
d1a2dc78 2698
d5941021
ID		 2699out:
2700 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2701
2702 return ret;
d1a2dc78
S		 2703}
2704
2705static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2706{
2707 int i;
2708
2709 dev_priv->num_shared_dpll = 3;
2710
2711 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2712 dev_priv->shared_dplls[i].id = i;
2713 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2714 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2715 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2716 dev_priv->shared_dplls[i].get_hw_state =
2717 skl_ddi_pll_get_hw_state;
2718 }
2719}
2720
5c6706e5
VK		 2721static void broxton_phy_init(struct drm_i915_private *dev_priv,
2722 enum dpio_phy phy)
2723{
2724 enum port port;
2725 uint32_t val;
2726
2727 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2728 val |= GT_DISPLAY_POWER_ON(phy);
2729 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2730
2731 /* Considering 10ms timeout until BSpec is updated */
2732 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2733 DRM_ERROR("timeout during PHY%d power on\n", phy);
2734
2735 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2736 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2737 int lane;
2738
2739 for (lane = 0; lane < 4; lane++) {
2740 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2741 /*
2742 * Note that on CHV this flag is called UPAR, but has
2743 * the same function.
2744 */
2745 val &= ~LATENCY_OPTIM;
2746 if (lane != 1)
2747 val |= LATENCY_OPTIM;
2748
2749 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2750 }
2751 }
2752
2753 /* Program PLL Rcomp code offset */
2754 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2755 val &= ~IREF0RC_OFFSET_MASK;
2756 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2757 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2758
2759 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2760 val &= ~IREF1RC_OFFSET_MASK;
2761 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2762 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2763
2764 /* Program power gating */
2765 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2766 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2767 SUS_CLK_CONFIG;
2768 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2769
2770 if (phy == DPIO_PHY0) {
2771 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2772 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2773 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2774 }
2775
2776 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2777 val &= ~OCL2_LDOFUSE_PWR_DIS;
2778 /*
2779 * On PHY1 disable power on the second channel, since no port is
2780 * connected there. On PHY0 both channels have a port, so leave it
2781 * enabled.
2782 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2783 * power down the second channel on PHY0 as well.
2784 */
2785 if (phy == DPIO_PHY1)
2786 val |= OCL2_LDOFUSE_PWR_DIS;
2787 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2788
2789 if (phy == DPIO_PHY0) {
2790 uint32_t grc_code;
2791 /*
2792 * PHY0 isn't connected to an RCOMP resistor so copy over
2793 * the corresponding calibrated value from PHY1, and disable
2794 * the automatic calibration on PHY0.
2795 */
2796 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2797 10))
2798 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2799
2800 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2801 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2802 grc_code = val << GRC_CODE_FAST_SHIFT |
2803 val << GRC_CODE_SLOW_SHIFT |
2804 val;
2805 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2806
2807 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2808 val |= GRC_DIS | GRC_RDY_OVRD;
2809 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2810 }
2811
2812 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2813 val |= COMMON_RESET_DIS;
2814 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2815}
2816
2817void broxton_ddi_phy_init(struct drm_device *dev)
2818{
2819 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2820 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2821 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2822}
2823
2824static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2825 enum dpio_phy phy)
2826{
2827 uint32_t val;
2828
2829 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2830 val &= ~COMMON_RESET_DIS;
2831 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2832}
2833
2834void broxton_ddi_phy_uninit(struct drm_device *dev)
2835{
2836 struct drm_i915_private *dev_priv = dev->dev_private;
2837
2838 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2839 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2840
2841 /* FIXME: do this in broxton_phy_uninit per phy */
2842 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2843}
2844
dfb82408
S		 2845static const char * const bxt_ddi_pll_names[] = {
2846 "PORT PLL A",
2847 "PORT PLL B",
2848 "PORT PLL C",
2849};
2850
2851static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2852 struct intel_shared_dpll *pll)
2853{
2854 uint32_t temp;
2855 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2856
2857 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2858 temp &= ~PORT_PLL_REF_SEL;
2859 /* Non-SSC reference */
2860 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2861
2862 /* Disable 10 bit clock */
2863 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2864 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2865 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2866
2867 /* Write P1 & P2 */
2868 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2869 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2870 temp |= pll->config.hw_state.ebb0;
2871 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2872
2873 /* Write M2 integer */
2874 temp = I915_READ(BXT_PORT_PLL(port, 0));
2875 temp &= ~PORT_PLL_M2_MASK;
2876 temp |= pll->config.hw_state.pll0;
2877 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2878
2879 /* Write N */
2880 temp = I915_READ(BXT_PORT_PLL(port, 1));
2881 temp &= ~PORT_PLL_N_MASK;
2882 temp |= pll->config.hw_state.pll1;
2883 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2884
2885 /* Write M2 fraction */
2886 temp = I915_READ(BXT_PORT_PLL(port, 2));
2887 temp &= ~PORT_PLL_M2_FRAC_MASK;
2888 temp |= pll->config.hw_state.pll2;
2889 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2890
2891 /* Write M2 fraction enable */
2892 temp = I915_READ(BXT_PORT_PLL(port, 3));
2893 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2894 temp |= pll->config.hw_state.pll3;
2895 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2896
2897 /* Write coeff */
2898 temp = I915_READ(BXT_PORT_PLL(port, 6));
2899 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2900 temp &= ~PORT_PLL_INT_COEFF_MASK;
2901 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2902 temp |= pll->config.hw_state.pll6;
2903 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2904
2905 /* Write calibration val */
2906 temp = I915_READ(BXT_PORT_PLL(port, 8));
2907 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2908 temp |= pll->config.hw_state.pll8;
2909 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2910
b6dc71f3
VK		 2911 temp = I915_READ(BXT_PORT_PLL(port, 9));
2912 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2913 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2914 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2915
2916 temp = I915_READ(BXT_PORT_PLL(port, 10));
2917 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2918 temp &= ~PORT_PLL_DCO_AMP_MASK;
2919 temp |= pll->config.hw_state.pll10;
2920 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2921
2922 /* Recalibrate with new settings */
2923 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2924 temp |= PORT_PLL_RECALIBRATE;
2925 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2926 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2927 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2928 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2929
2930 /* Enable PLL */
2931 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2932 temp |= PORT_PLL_ENABLE;
2933 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2934 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2935
2936 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2937 PORT_PLL_LOCK), 200))
2938 DRM_ERROR("PLL %d not locked\n", port);
2939
2940 /*
2941 * While we write to the group register to program all lanes at once we
2942 * can read only lane registers and we pick lanes 0/1 for that.
2943 */
2944 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2945 temp &= ~LANE_STAGGER_MASK;
2946 temp &= ~LANESTAGGER_STRAP_OVRD;
2947 temp |= pll->config.hw_state.pcsdw12;
2948 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2949}
2950
2951static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2952 struct intel_shared_dpll *pll)
2953{
2954 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2955 uint32_t temp;
2956
2957 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2958 temp &= ~PORT_PLL_ENABLE;
2959 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2960 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2961}
2962
2963static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2964 struct intel_shared_dpll *pll,
2965 struct intel_dpll_hw_state *hw_state)
2966{
2967 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2968 uint32_t val;
d5941021 2969 bool ret;
dfb82408 2970
d5941021 2971 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
dfb82408
S		 2972 return false;
2973
d5941021
ID		 2974 ret = false;
2975
dfb82408
S		 2976 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2977 if (!(val & PORT_PLL_ENABLE))
d5941021 2978 goto out;
dfb82408
S		 2979
2980 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2981 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2982
05712c15
ID		 2983 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2984 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2985
dfb82408 2986 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2987 hw_state->pll0 &= PORT_PLL_M2_MASK;
2988
dfb82408 2989 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2990 hw_state->pll1 &= PORT_PLL_N_MASK;
2991
dfb82408 2992 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2993 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2994
dfb82408 2995 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2996 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2997
dfb82408 2998 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2999 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
3000 PORT_PLL_INT_COEFF_MASK |
3001 PORT_PLL_GAIN_CTL_MASK;
3002
dfb82408 3003 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 3004 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
3005
05712c15
ID		 3006 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
3007 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
3008
b6dc71f3 3009 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 3010 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
3011 PORT_PLL_DCO_AMP_MASK;
3012
dfb82408
S		 3013 /*
3014 * While we write to the group register to program all lanes at once we
3015 * can read only lane registers. We configure all lanes the same way, so
3016 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
3017 */
3018 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
b5dada82 3019 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
dfb82408
S		 3020 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
3021 hw_state->pcsdw12,
3022 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 3023 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408 3024
d5941021
ID		 3025 ret = true;
3026
3027out:
3028 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
3029
3030 return ret;
dfb82408
S		 3031}
3032
3033static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
3034{
3035 int i;
3036
3037 dev_priv->num_shared_dpll = 3;
3038
3039 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3040 dev_priv->shared_dplls[i].id = i;
3041 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
3042 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
3043 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
3044 dev_priv->shared_dplls[i].get_hw_state =
3045 bxt_ddi_pll_get_hw_state;
3046 }
3047}
3048
143b307c
DL		 3049void intel_ddi_pll_init(struct drm_device *dev)
3050{
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 uint32_t val = I915_READ(LCPLL_CTL);
3053
ef11bdb3 3054 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
d1a2dc78 3055 skl_shared_dplls_init(dev_priv);
dfb82408
S		 3056 else if (IS_BROXTON(dev))
3057 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 3058 else
3059 hsw_shared_dplls_init(dev_priv);
79f689aa 3060
ef11bdb3 3061 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
d9062ae5
DL		 3062 int cdclk_freq;
3063
3064 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 3065 dev_priv->skl_boot_cdclk = cdclk_freq;
c73666f3
SK		 3066 if (skl_sanitize_cdclk(dev_priv))
3067 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
2f693e28
DL		 3068 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
3069 DRM_ERROR("LCPLL1 is disabled\n");
f8437dd1
VK		 3070 } else if (IS_BROXTON(dev)) {
3071 broxton_init_cdclk(dev);
5c6706e5 3072 broxton_ddi_phy_init(dev);
121643c2
S		 3073 } else {
3074 /*
3075 * The LCPLL register should be turned on by the BIOS. For now
3076 * let's just check its state and print errors in case
3077 * something is wrong. Don't even try to turn it on.
3078 */
3079
3080 if (val & LCPLL_CD_SOURCE_FCLK)
3081 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 3082
121643c2
S		 3083 if (val & LCPLL_PLL_DISABLE)
3084 DRM_ERROR("LCPLL is disabled\n");
3085 }
79f689aa 3086}
c19b0669 3087
ad64217b 3088void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3089{
ad64217b
ACO		 3090 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3091 struct drm_i915_private *dev_priv =
3092 to_i915(intel_dig_port->base.base.dev);
174edf1f 3093 enum port port = intel_dig_port->port;
c19b0669 3094 uint32_t val;
f3e227df 3095 bool wait = false;
c19b0669
PZ		 3096
3097 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3098 val = I915_READ(DDI_BUF_CTL(port));
3099 if (val & DDI_BUF_CTL_ENABLE) {
3100 val &= ~DDI_BUF_CTL_ENABLE;
3101 I915_WRITE(DDI_BUF_CTL(port), val);
3102 wait = true;
3103 }
3104
3105 val = I915_READ(DP_TP_CTL(port));
3106 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3107 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3108 I915_WRITE(DP_TP_CTL(port), val);
3109 POSTING_READ(DP_TP_CTL(port));
3110
3111 if (wait)
3112 intel_wait_ddi_buf_idle(dev_priv, port);
3113 }
3114
0e32b39c 3115 val = DP_TP_CTL_ENABLE |
c19b0669 3116 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 3117 if (intel_dp->is_mst)
3118 val |= DP_TP_CTL_MODE_MST;
3119 else {
3120 val |= DP_TP_CTL_MODE_SST;
3121 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3122 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3123 }
c19b0669
PZ		 3124 I915_WRITE(DP_TP_CTL(port), val);
3125 POSTING_READ(DP_TP_CTL(port));
3126
3127 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3128 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3129 POSTING_READ(DDI_BUF_CTL(port));
3130
3131 udelay(600);
3132}
00c09d70 3133
1ad960f2
PZ		 3134void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3135{
3136 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3137 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3138 uint32_t val;
3139
3140 intel_ddi_post_disable(intel_encoder);
3141
eede3b53 3142 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3143 val &= ~FDI_RX_ENABLE;
eede3b53 3144 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3145
eede3b53 3146 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 3147 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3148 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 3149 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 3150
eede3b53 3151 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3152 val &= ~FDI_PCDCLK;
eede3b53 3153 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3154
eede3b53 3155 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3156 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 3157 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 3158}
3159
3d52ccf5
LY		 3160bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3161 struct intel_crtc *intel_crtc)
3162{
3163 u32 temp;
3164
d5941021 3165 if (intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3d52ccf5 3166 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
d5941021
ID		 3167
3168 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
3169
3d52ccf5
LY		 3170 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3171 return true;
3172 }
d5941021 3173
3d52ccf5
LY		 3174 return false;
3175}
3176
6801c18c 3177void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3178 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3179{
3180 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3181 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3182 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3183 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3184 u32 temp, flags = 0;
3185
3186 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3187 if (temp & TRANS_DDI_PHSYNC)
3188 flags |= DRM_MODE_FLAG_PHSYNC;
3189 else
3190 flags |= DRM_MODE_FLAG_NHSYNC;
3191 if (temp & TRANS_DDI_PVSYNC)
3192 flags |= DRM_MODE_FLAG_PVSYNC;
3193 else
3194 flags |= DRM_MODE_FLAG_NVSYNC;
3195
2d112de7 3196 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3197
3198 switch (temp & TRANS_DDI_BPC_MASK) {
3199 case TRANS_DDI_BPC_6:
3200 pipe_config->pipe_bpp = 18;
3201 break;
3202 case TRANS_DDI_BPC_8:
3203 pipe_config->pipe_bpp = 24;
3204 break;
3205 case TRANS_DDI_BPC_10:
3206 pipe_config->pipe_bpp = 30;
3207 break;
3208 case TRANS_DDI_BPC_12:
3209 pipe_config->pipe_bpp = 36;
3210 break;
3211 default:
3212 break;
3213 }
eb14cb74
VS		 3214
3215 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3216 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3217 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3218 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3219
cda0aaaf 3220 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 3221 pipe_config->has_infoframe = true;
cbc572a9 3222 break;
eb14cb74
VS		 3223 case TRANS_DDI_MODE_SELECT_DVI:
3224 case TRANS_DDI_MODE_SELECT_FDI:
3225 break;
3226 case TRANS_DDI_MODE_SELECT_DP_SST:
3227 case TRANS_DDI_MODE_SELECT_DP_MST:
3228 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 3229 pipe_config->lane_count =
3230 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3231 intel_dp_get_m_n(intel_crtc, pipe_config);
3232 break;
3233 default:
3234 break;
3235 }
10214420 3236
3d52ccf5
LY		 3237 pipe_config->has_audio =
3238 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 3239
10214420
DV		 3240 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3241 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3242 /*
3243 * This is a big fat ugly hack.
3244 *
3245 * Some machines in UEFI boot mode provide us a VBT that has 18
3246 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3247 * unknown we fail to light up. Yet the same BIOS boots up with
3248 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3249 * max, not what it tells us to use.
3250 *
3251 * Note: This will still be broken if the eDP panel is not lit
3252 * up by the BIOS, and thus we can't get the mode at module
3253 * load.
3254 */
3255 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3256 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3257 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3258 }
11578553 3259
22606a18 3260 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3261}
3262
00c09d70
PZ		 3263static void intel_ddi_destroy(struct drm_encoder *encoder)
3264{
3265 /* HDMI has nothing special to destroy, so we can go with this. */
3266 intel_dp_encoder_destroy(encoder);
3267}
3268
5bfe2ac0 3269static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3270 struct intel_crtc_state *pipe_config)
00c09d70 3271{
5bfe2ac0 3272 int type = encoder->type;
eccb140b 3273 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3274
5bfe2ac0 3275 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3276
eccb140b
DV		 3277 if (port == PORT_A)
3278 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3279
00c09d70 3280 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3281 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3282 else
5bfe2ac0 3283 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3284}
3285
3286static const struct drm_encoder_funcs intel_ddi_funcs = {
3287 .destroy = intel_ddi_destroy,
3288};
3289
4a28ae58
PZ		 3290static struct intel_connector *
3291intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3292{
3293 struct intel_connector *connector;
3294 enum port port = intel_dig_port->port;
3295
9bdbd0b9 3296 connector = intel_connector_alloc();
4a28ae58
PZ		 3297 if (!connector)
3298 return NULL;
3299
3300 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3301 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3302 kfree(connector);
3303 return NULL;
3304 }
3305
3306 return connector;
3307}
3308
3309static struct intel_connector *
3310intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3311{
3312 struct intel_connector *connector;
3313 enum port port = intel_dig_port->port;
3314
9bdbd0b9 3315 connector = intel_connector_alloc();
4a28ae58
PZ		 3316 if (!connector)
3317 return NULL;
3318
3319 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3320 intel_hdmi_init_connector(intel_dig_port, connector);
3321
3322 return connector;
3323}
3324
00c09d70
PZ		 3325void intel_ddi_init(struct drm_device *dev, enum port port)
3326{
876a8cdf 3327 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3328 struct intel_digital_port *intel_dig_port;
3329 struct intel_encoder *intel_encoder;
3330 struct drm_encoder *encoder;
311a2094
PZ		 3331 bool init_hdmi, init_dp;
3332
3333 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3334 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3335 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3336 if (!init_dp && !init_hdmi) {
500ea70d 3337 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3338 port_name(port));
500ea70d 3339 return;
311a2094 3340 }
00c09d70 3341
b14c5679 3342 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3343 if (!intel_dig_port)
3344 return;
3345
00c09d70
PZ		 3346 intel_encoder = &intel_dig_port->base;
3347 encoder = &intel_encoder->base;
3348
3349 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
13a3d91f 3350 DRM_MODE_ENCODER_TMDS, NULL);
00c09d70 3351
5bfe2ac0 3352 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3353 intel_encoder->enable = intel_enable_ddi;
3354 intel_encoder->pre_enable = intel_ddi_pre_enable;
3355 intel_encoder->disable = intel_disable_ddi;
3356 intel_encoder->post_disable = intel_ddi_post_disable;
3357 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3358 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3359
3360 intel_dig_port->port = port;
bcf53de4
SM		 3361 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3362 (DDI_BUF_PORT_REVERSAL |
3363 DDI_A_4_LANES);
00c09d70 3364
6c566dc9
MR		 3365 /*
3366 * Bspec says that DDI_A_4_LANES is the only supported configuration
3367 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3368 * wasn't lit up at boot. Force this bit on in our internal
3369 * configuration so that we use the proper lane count for our
3370 * calculations.
3371 */
3372 if (IS_BROXTON(dev) && port == PORT_A) {
3373 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3374 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3375 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
3376 }
3377 }
3378
00c09d70 3379 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3380 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3381 intel_encoder->cloneable = 0;
00c09d70 3382
f68d697e
CW		 3383 if (init_dp) {
3384 if (!intel_ddi_init_dp_connector(intel_dig_port))
3385 goto err;
13cf5504 3386
f68d697e 3387 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3388 /*
3389 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3390 * interrupts to check the external panel connection.
3391 */
e87a005d 3392 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 3393 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3394 else
3395 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3396 }
21a8e6a4 3397
311a2094
PZ		 3398 /* In theory we don't need the encoder->type check, but leave it just in
3399 * case we have some really bad VBTs... */
f68d697e
CW		 3400 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3401 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3402 goto err;
21a8e6a4 3403 }
f68d697e
CW		 3404
3405 return;
3406
3407err:
3408 drm_encoder_cleanup(encoder);
3409 kfree(intel_dig_port);
00c09d70 3410}
Linux kernel - Deliverables
This page took 0.459279 seconds and 5 git commands to generate.