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drm/i915: Keep sprite plane src rect in 16.16 format
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
e7457a9a 108
0e32b39c
DA		 109static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
110{
111 if (!connector->mst_port)
112 return connector->encoder;
113 else
114 return &connector->mst_port->mst_encoders[pipe]->base;
115}
116
79e53945 117typedef struct {
0206e353 118 int min, max;
79e53945
JB		 119} intel_range_t;
120
121typedef struct {
0206e353
AJ		 122 int dot_limit;
123 int p2_slow, p2_fast;
79e53945
JB		 124} intel_p2_t;
125
d4906093
ML		 126typedef struct intel_limit intel_limit_t;
127struct intel_limit {
0206e353
AJ		 128 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_p2_t p2;
d4906093 130};
79e53945 131
d2acd215
DV		 132int
133intel_pch_rawclk(struct drm_device *dev)
134{
135 struct drm_i915_private *dev_priv = dev->dev_private;
136
137 WARN_ON(!HAS_PCH_SPLIT(dev));
138
139 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
140}
141
021357ac
CW		 142static inline u32 /* units of 100MHz */
143intel_fdi_link_freq(struct drm_device *dev)
144{
8b99e68c
CW		 145 if (IS_GEN5(dev)) {
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 } else
149 return 27;
021357ac
CW		 150}
151
5d536e28 152static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 153 .dot = { .min = 25000, .max = 350000 },
9c333719 154 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 155 .n = { .min = 2, .max = 16 },
0206e353
AJ		 156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 163};
164
5d536e28
DV		 165static const intel_limit_t intel_limits_i8xx_dvo = {
166 .dot = { .min = 25000, .max = 350000 },
9c333719 167 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 168 .n = { .min = 2, .max = 16 },
5d536e28
DV		 169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 2, .max = 33 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 4, .p2_fast = 4 },
176};
177
e4b36699 178static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 179 .dot = { .min = 25000, .max = 350000 },
9c333719 180 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 181 .n = { .min = 2, .max = 16 },
0206e353
AJ		 182 .m = { .min = 96, .max = 140 },
183 .m1 = { .min = 18, .max = 26 },
184 .m2 = { .min = 6, .max = 16 },
185 .p = { .min = 4, .max = 128 },
186 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 187 .p2 = { .dot_limit = 165000,
188 .p2_slow = 14, .p2_fast = 7 },
e4b36699 189};
273e27ca 190
e4b36699 191static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 198 .p = { .min = 5, .max = 80 },
199 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 200 .p2 = { .dot_limit = 200000,
201 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 202};
203
204static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 205 .dot = { .min = 20000, .max = 400000 },
206 .vco = { .min = 1400000, .max = 2800000 },
207 .n = { .min = 1, .max = 6 },
208 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 209 .m1 = { .min = 8, .max = 18 },
210 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 211 .p = { .min = 7, .max = 98 },
212 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 213 .p2 = { .dot_limit = 112000,
214 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 215};
216
273e27ca 217
e4b36699 218static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 219 .dot = { .min = 25000, .max = 270000 },
220 .vco = { .min = 1750000, .max = 3500000},
221 .n = { .min = 1, .max = 4 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 10, .max = 30 },
226 .p1 = { .min = 1, .max = 3},
227 .p2 = { .dot_limit = 270000,
228 .p2_slow = 10,
229 .p2_fast = 10
044c7c41 230 },
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 234 .dot = { .min = 22000, .max = 400000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 4 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 16, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 5, .max = 80 },
241 .p1 = { .min = 1, .max = 8},
242 .p2 = { .dot_limit = 165000,
243 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 244};
245
246static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 247 .dot = { .min = 20000, .max = 115000 },
248 .vco = { .min = 1750000, .max = 3500000 },
249 .n = { .min = 1, .max = 3 },
250 .m = { .min = 104, .max = 138 },
251 .m1 = { .min = 17, .max = 23 },
252 .m2 = { .min = 5, .max = 11 },
253 .p = { .min = 28, .max = 112 },
254 .p1 = { .min = 2, .max = 8 },
255 .p2 = { .dot_limit = 0,
256 .p2_slow = 14, .p2_fast = 14
044c7c41 257 },
e4b36699
KP		 258};
259
260static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 261 .dot = { .min = 80000, .max = 224000 },
262 .vco = { .min = 1750000, .max = 3500000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 104, .max = 138 },
265 .m1 = { .min = 17, .max = 23 },
266 .m2 = { .min = 5, .max = 11 },
267 .p = { .min = 14, .max = 42 },
268 .p1 = { .min = 2, .max = 6 },
269 .p2 = { .dot_limit = 0,
270 .p2_slow = 7, .p2_fast = 7
044c7c41 271 },
e4b36699
KP		 272};
273
f2b115e6 274static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000},
276 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 277 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 278 .n = { .min = 3, .max = 6 },
279 .m = { .min = 2, .max = 256 },
273e27ca 280 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 5, .max = 80 },
284 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 285 .p2 = { .dot_limit = 200000,
286 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 287};
288
f2b115e6 289static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 290 .dot = { .min = 20000, .max = 400000 },
291 .vco = { .min = 1700000, .max = 3500000 },
292 .n = { .min = 3, .max = 6 },
293 .m = { .min = 2, .max = 256 },
294 .m1 = { .min = 0, .max = 0 },
295 .m2 = { .min = 0, .max = 254 },
296 .p = { .min = 7, .max = 112 },
297 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 298 .p2 = { .dot_limit = 112000,
299 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 300};
301
273e27ca
EA		 302/* Ironlake / Sandybridge
303 *
304 * We calculate clock using (register_value + 2) for N/M1/M2, so here
305 * the range value for them is (actual_value - 2).
306 */
b91ad0ec 307static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 5 },
311 .m = { .min = 79, .max = 127 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 5, .max = 80 },
315 .p1 = { .min = 1, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331};
332
333static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 3 },
337 .m = { .min = 79, .max = 127 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 14, .max = 56 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 344};
345
273e27ca 346/* LVDS 100mhz refclk limits. */
b91ad0ec 347static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 2 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 28, .max = 112 },
0206e353 355 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 358};
359
360static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 361 .dot = { .min = 25000, .max = 350000 },
362 .vco = { .min = 1760000, .max = 3510000 },
363 .n = { .min = 1, .max = 3 },
364 .m = { .min = 79, .max = 126 },
365 .m1 = { .min = 12, .max = 22 },
366 .m2 = { .min = 5, .max = 9 },
367 .p = { .min = 14, .max = 42 },
0206e353 368 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 369 .p2 = { .dot_limit = 225000,
370 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 371};
372
dc730512 373static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 374 /*
375 * These are the data rate limits (measured in fast clocks)
376 * since those are the strictest limits we have. The fast
377 * clock and actual rate limits are more relaxed, so checking
378 * them would make no difference.
379 */
380 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 381 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 382 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 383 .m1 = { .min = 2, .max = 3 },
384 .m2 = { .min = 11, .max = 156 },
b99ab663 385 .p1 = { .min = 2, .max = 3 },
5fdc9c49 386 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 387};
388
ef9348c8
CML		 389static const intel_limit_t intel_limits_chv = {
390 /*
391 * These are the data rate limits (measured in fast clocks)
392 * since those are the strictest limits we have. The fast
393 * clock and actual rate limits are more relaxed, so checking
394 * them would make no difference.
395 */
396 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 397 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 398 .n = { .min = 1, .max = 1 },
399 .m1 = { .min = 2, .max = 2 },
400 .m2 = { .min = 24 << 22, .max = 175 << 22 },
401 .p1 = { .min = 2, .max = 4 },
402 .p2 = { .p2_slow = 1, .p2_fast = 14 },
403};
404
6b4bf1c4
VS		 405static void vlv_clock(int refclk, intel_clock_t *clock)
406{
407 clock->m = clock->m1 * clock->m2;
408 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 409 if (WARN_ON(clock->n == 0 || clock->p == 0))
410 return;
fb03ac01
VS		 411 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
412 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 413}
414
e0638cdf
PZ		 415/**
416 * Returns whether any output on the specified pipe is of the specified type
417 */
4093561b 418bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 419{
409ee761 420 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 421 struct intel_encoder *encoder;
422
409ee761 423 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 424 if (encoder->type == type)
425 return true;
426
427 return false;
428}
429
d0737e1d
ACO		 430/**
431 * Returns whether any output on the specified pipe will have the specified
432 * type after a staged modeset is complete, i.e., the same as
433 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
434 * encoder->crtc.
435 */
a93e255f
ACO		 436static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
437 int type)
d0737e1d 438{
a93e255f
ACO		 439 struct drm_atomic_state *state = crtc_state->base.state;
440 struct drm_connector_state *connector_state;
d0737e1d 441 struct intel_encoder *encoder;
a93e255f
ACO		 442 int i, num_connectors = 0;
443
444 for (i = 0; i < state->num_connector; i++) {
445 if (!state->connectors[i])
446 continue;
447
448 connector_state = state->connector_states[i];
449 if (connector_state->crtc != crtc_state->base.crtc)
450 continue;
451
452 num_connectors++;
d0737e1d 453
a93e255f
ACO		 454 encoder = to_intel_encoder(connector_state->best_encoder);
455 if (encoder->type == type)
d0737e1d 456 return true;
a93e255f
ACO		 457 }
458
459 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 460
461 return false;
462}
463
a93e255f
ACO		 464static const intel_limit_t *
465intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 466{
a93e255f 467 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 468 const intel_limit_t *limit;
b91ad0ec 469
a93e255f 470 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 471 if (intel_is_dual_link_lvds(dev)) {
1b894b59 472 if (refclk == 100000)
b91ad0ec
ZW		 473 limit = &intel_limits_ironlake_dual_lvds_100m;
474 else
475 limit = &intel_limits_ironlake_dual_lvds;
476 } else {
1b894b59 477 if (refclk == 100000)
b91ad0ec
ZW		 478 limit = &intel_limits_ironlake_single_lvds_100m;
479 else
480 limit = &intel_limits_ironlake_single_lvds;
481 }
c6bb3538 482 } else
b91ad0ec 483 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 484
485 return limit;
486}
487
a93e255f
ACO		 488static const intel_limit_t *
489intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 490{
a93e255f 491 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 492 const intel_limit_t *limit;
493
a93e255f 494 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 495 if (intel_is_dual_link_lvds(dev))
e4b36699 496 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 497 else
e4b36699 498 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 499 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
500 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 501 limit = &intel_limits_g4x_hdmi;
a93e255f 502 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 503 limit = &intel_limits_g4x_sdvo;
044c7c41 504 } else /* The option is for other outputs */
e4b36699 505 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 506
507 return limit;
508}
509
a93e255f
ACO		 510static const intel_limit_t *
511intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 512{
a93e255f 513 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 514 const intel_limit_t *limit;
515
bad720ff 516 if (HAS_PCH_SPLIT(dev))
a93e255f 517 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 518 else if (IS_G4X(dev)) {
a93e255f 519 limit = intel_g4x_limit(crtc_state);
f2b115e6 520 } else if (IS_PINEVIEW(dev)) {
a93e255f 521 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 522 limit = &intel_limits_pineview_lvds;
2177832f 523 else
f2b115e6 524 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 525 } else if (IS_CHERRYVIEW(dev)) {
526 limit = &intel_limits_chv;
a0c4da24 527 } else if (IS_VALLEYVIEW(dev)) {
dc730512 528 limit = &intel_limits_vlv;
a6c45cf0 529 } else if (!IS_GEN2(dev)) {
a93e255f 530 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 531 limit = &intel_limits_i9xx_lvds;
532 else
533 limit = &intel_limits_i9xx_sdvo;
79e53945 534 } else {
a93e255f 535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 536 limit = &intel_limits_i8xx_lvds;
a93e255f 537 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 538 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 539 else
540 limit = &intel_limits_i8xx_dac;
79e53945
JB		 541 }
542 return limit;
543}
544
f2b115e6
AJ		 545/* m1 is reserved as 0 in Pineview, n is a ring counter */
546static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 547{
2177832f
SL		 548 clock->m = clock->m2 + 2;
549 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
fb03ac01
VS		 552 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
553 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 554}
555
7429e9d4
DV		 556static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
557{
558 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
559}
560
ac58c3f0 561static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 562{
7429e9d4 563 clock->m = i9xx_dpll_compute_m(clock);
79e53945 564 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 565 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
566 return;
fb03ac01
VS		 567 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
568 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 569}
570
ef9348c8
CML		 571static void chv_clock(int refclk, intel_clock_t *clock)
572{
573 clock->m = clock->m1 * clock->m2;
574 clock->p = clock->p1 * clock->p2;
575 if (WARN_ON(clock->n == 0 || clock->p == 0))
576 return;
577 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
578 clock->n << 22);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580}
581
7c04d1d9 582#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 583/**
584 * Returns whether the given set of divisors are valid for a given refclk with
585 * the given connectors.
586 */
587
1b894b59
CW		 588static bool intel_PLL_is_valid(struct drm_device *dev,
589 const intel_limit_t *limit,
590 const intel_clock_t *clock)
79e53945 591{
f01b7962
VS		 592 if (clock->n < limit->n.min || limit->n.max < clock->n)
593 INTELPllInvalid("n out of range\n");
79e53945 594 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 595 INTELPllInvalid("p1 out of range\n");
79e53945 596 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 597 INTELPllInvalid("m2 out of range\n");
79e53945 598 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 599 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 600
601 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
602 if (clock->m1 <= clock->m2)
603 INTELPllInvalid("m1 <= m2\n");
604
605 if (!IS_VALLEYVIEW(dev)) {
606 if (clock->p < limit->p.min || limit->p.max < clock->p)
607 INTELPllInvalid("p out of range\n");
608 if (clock->m < limit->m.min || limit->m.max < clock->m)
609 INTELPllInvalid("m out of range\n");
610 }
611
79e53945 612 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 613 INTELPllInvalid("vco out of range\n");
79e53945
JB		 614 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
615 * connector, etc., rather than just a single range.
616 */
617 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 618 INTELPllInvalid("dot out of range\n");
79e53945
JB		 619
620 return true;
621}
622
d4906093 623static bool
a93e255f
ACO		 624i9xx_find_best_dpll(const intel_limit_t *limit,
625 struct intel_crtc_state *crtc_state,
cec2f356
SP		 626 int target, int refclk, intel_clock_t *match_clock,
627 intel_clock_t *best_clock)
79e53945 628{
a93e255f 629 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 630 struct drm_device *dev = crtc->base.dev;
79e53945 631 intel_clock_t clock;
79e53945
JB		 632 int err = target;
633
a93e255f 634 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 635 /*
a210b028
DV		 636 * For LVDS just rely on its current settings for dual-channel.
637 * We haven't figured out how to reliably set up different
638 * single/dual channel state, if we even can.
79e53945 639 */
1974cad0 640 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
0206e353 651 memset(best_clock, 0, sizeof(*best_clock));
79e53945 652
42158660
ZY		 653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
654 clock.m1++) {
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 657 if (clock.m2 >= clock.m1)
42158660
ZY		 658 break;
659 for (clock.n = limit->n.min;
660 clock.n <= limit->n.max; clock.n++) {
661 for (clock.p1 = limit->p1.min;
662 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 663 int this_err;
664
ac58c3f0
DV		 665 i9xx_clock(refclk, &clock);
666 if (!intel_PLL_is_valid(dev, limit,
667 &clock))
668 continue;
669 if (match_clock &&
670 clock.p != match_clock->p)
671 continue;
672
673 this_err = abs(clock.dot - target);
674 if (this_err < err) {
675 *best_clock = clock;
676 err = this_err;
677 }
678 }
679 }
680 }
681 }
682
683 return (err != target);
684}
685
686static bool
a93e255f
ACO		 687pnv_find_best_dpll(const intel_limit_t *limit,
688 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
79e53945 691{
a93e255f 692 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 693 struct drm_device *dev = crtc->base.dev;
79e53945 694 intel_clock_t clock;
79e53945
JB		 695 int err = target;
696
a93e255f 697 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 698 /*
a210b028
DV		 699 * For LVDS just rely on its current settings for dual-channel.
700 * We haven't figured out how to reliably set up different
701 * single/dual channel state, if we even can.
79e53945 702 */
1974cad0 703 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 720 for (clock.n = limit->n.min;
721 clock.n <= limit->n.max; clock.n++) {
722 for (clock.p1 = limit->p1.min;
723 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 724 int this_err;
725
ac58c3f0 726 pineview_clock(refclk, &clock);
1b894b59
CW		 727 if (!intel_PLL_is_valid(dev, limit,
728 &clock))
79e53945 729 continue;
cec2f356
SP		 730 if (match_clock &&
731 clock.p != match_clock->p)
732 continue;
79e53945
JB		 733
734 this_err = abs(clock.dot - target);
735 if (this_err < err) {
736 *best_clock = clock;
737 err = this_err;
738 }
739 }
740 }
741 }
742 }
743
744 return (err != target);
745}
746
d4906093 747static bool
a93e255f
ACO		 748g4x_find_best_dpll(const intel_limit_t *limit,
749 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
d4906093 752{
a93e255f 753 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 754 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 755 intel_clock_t clock;
756 int max_n;
757 bool found;
6ba770dc
AJ		 758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 760 found = false;
761
a93e255f 762 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 763 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 764 clock.p2 = limit->p2.p2_fast;
765 else
766 clock.p2 = limit->p2.p2_slow;
767 } else {
768 if (target < limit->p2.dot_limit)
769 clock.p2 = limit->p2.p2_slow;
770 else
771 clock.p2 = limit->p2.p2_fast;
772 }
773
774 memset(best_clock, 0, sizeof(*best_clock));
775 max_n = limit->n.max;
f77f13e2 776 /* based on hardware requirement, prefer smaller n to precision */
d4906093 777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 778 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 779 for (clock.m1 = limit->m1.max;
780 clock.m1 >= limit->m1.min; clock.m1--) {
781 for (clock.m2 = limit->m2.max;
782 clock.m2 >= limit->m2.min; clock.m2--) {
783 for (clock.p1 = limit->p1.max;
784 clock.p1 >= limit->p1.min; clock.p1--) {
785 int this_err;
786
ac58c3f0 787 i9xx_clock(refclk, &clock);
1b894b59
CW		 788 if (!intel_PLL_is_valid(dev, limit,
789 &clock))
d4906093 790 continue;
1b894b59
CW		 791
792 this_err = abs(clock.dot - target);
d4906093
ML		 793 if (this_err < err_most) {
794 *best_clock = clock;
795 err_most = this_err;
796 max_n = clock.n;
797 found = true;
798 }
799 }
800 }
801 }
802 }
2c07245f
ZW		 803 return found;
804}
805
d5dd62bd
ID		 806/*
807 * Check if the calculated PLL configuration is more optimal compared to the
808 * best configuration and error found so far. Return the calculated error.
809 */
810static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
811 const intel_clock_t *calculated_clock,
812 const intel_clock_t *best_clock,
813 unsigned int best_error_ppm,
814 unsigned int *error_ppm)
815{
9ca3ba01
ID		 816 /*
817 * For CHV ignore the error and consider only the P value.
818 * Prefer a bigger P value based on HW requirements.
819 */
820 if (IS_CHERRYVIEW(dev)) {
821 *error_ppm = 0;
822
823 return calculated_clock->p > best_clock->p;
824 }
825
24be4e46
ID		 826 if (WARN_ON_ONCE(!target_freq))
827 return false;
828
d5dd62bd
ID		 829 *error_ppm = div_u64(1000000ULL *
830 abs(target_freq - calculated_clock->dot),
831 target_freq);
832 /*
833 * Prefer a better P value over a better (smaller) error if the error
834 * is small. Ensure this preference for future configurations too by
835 * setting the error to 0.
836 */
837 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
838 *error_ppm = 0;
839
840 return true;
841 }
842
843 return *error_ppm + 10 < best_error_ppm;
844}
845
a0c4da24 846static bool
a93e255f
ACO		 847vlv_find_best_dpll(const intel_limit_t *limit,
848 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 849 int target, int refclk, intel_clock_t *match_clock,
850 intel_clock_t *best_clock)
a0c4da24 851{
a93e255f 852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 853 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 854 intel_clock_t clock;
69e4f900 855 unsigned int bestppm = 1000000;
27e639bf
VS		 856 /* min update 19.2 MHz */
857 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 858 bool found = false;
a0c4da24 859
6b4bf1c4
VS		 860 target *= 5; /* fast clock */
861
862 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 863
864 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 865 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 866 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 867 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 868 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 869 clock.p = clock.p1 * clock.p2;
a0c4da24 870 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 871 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 872 unsigned int ppm;
69e4f900 873
6b4bf1c4
VS		 874 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
875 refclk * clock.m1);
876
877 vlv_clock(refclk, &clock);
43b0ac53 878
f01b7962
VS		 879 if (!intel_PLL_is_valid(dev, limit,
880 &clock))
43b0ac53
VS		 881 continue;
882
d5dd62bd
ID		 883 if (!vlv_PLL_is_optimal(dev, target,
884 &clock,
885 best_clock,
886 bestppm, &ppm))
887 continue;
6b4bf1c4 888
d5dd62bd
ID		 889 *best_clock = clock;
890 bestppm = ppm;
891 found = true;
a0c4da24
JB		 892 }
893 }
894 }
895 }
a0c4da24 896
49e497ef 897 return found;
a0c4da24 898}
a4fc5ed6 899
ef9348c8 900static bool
a93e255f
ACO		 901chv_find_best_dpll(const intel_limit_t *limit,
902 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 903 int target, int refclk, intel_clock_t *match_clock,
904 intel_clock_t *best_clock)
905{
a93e255f 906 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 907 struct drm_device *dev = crtc->base.dev;
9ca3ba01 908 unsigned int best_error_ppm;
ef9348c8
CML		 909 intel_clock_t clock;
910 uint64_t m2;
911 int found = false;
912
913 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 914 best_error_ppm = 1000000;
ef9348c8
CML		 915
916 /*
917 * Based on hardware doc, the n always set to 1, and m1 always
918 * set to 2. If requires to support 200Mhz refclk, we need to
919 * revisit this because n may not 1 anymore.
920 */
921 clock.n = 1, clock.m1 = 2;
922 target *= 5; /* fast clock */
923
924 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
925 for (clock.p2 = limit->p2.p2_fast;
926 clock.p2 >= limit->p2.p2_slow;
927 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 928 unsigned int error_ppm;
ef9348c8
CML		 929
930 clock.p = clock.p1 * clock.p2;
931
932 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
933 clock.n) << 22, refclk * clock.m1);
934
935 if (m2 > INT_MAX/clock.m1)
936 continue;
937
938 clock.m2 = m2;
939
940 chv_clock(refclk, &clock);
941
942 if (!intel_PLL_is_valid(dev, limit, &clock))
943 continue;
944
9ca3ba01
ID		 945 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
946 best_error_ppm, &error_ppm))
947 continue;
948
949 *best_clock = clock;
950 best_error_ppm = error_ppm;
951 found = true;
ef9348c8
CML		 952 }
953 }
954
955 return found;
956}
957
20ddf665
VS		 958bool intel_crtc_active(struct drm_crtc *crtc)
959{
960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
961
962 /* Be paranoid as we can arrive here with only partial
963 * state retrieved from the hardware during setup.
964 *
241bfc38 965 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 966 * as Haswell has gained clock readout/fastboot support.
967 *
66e514c1 968 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 969 * properly reconstruct framebuffers.
c3d1f436
MR		 970 *
971 * FIXME: The intel_crtc->active here should be switched to
972 * crtc->state->active once we have proper CRTC states wired up
973 * for atomic.
20ddf665 974 */
c3d1f436 975 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 976 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 977}
978
a5c961d1
PZ		 979enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
980 enum pipe pipe)
981{
982 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
6e3c9717 985 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 986}
987
fbf49ea2
VS		 988static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
989{
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u32 reg = PIPEDSL(pipe);
992 u32 line1, line2;
993 u32 line_mask;
994
995 if (IS_GEN2(dev))
996 line_mask = DSL_LINEMASK_GEN2;
997 else
998 line_mask = DSL_LINEMASK_GEN3;
999
1000 line1 = I915_READ(reg) & line_mask;
1001 mdelay(5);
1002 line2 = I915_READ(reg) & line_mask;
1003
1004 return line1 == line2;
1005}
1006
ab7ad7f6
KP		 1007/*
1008 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1009 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1010 *
1011 * After disabling a pipe, we can't wait for vblank in the usual way,
1012 * spinning on the vblank interrupt status bit, since we won't actually
1013 * see an interrupt when the pipe is disabled.
1014 *
ab7ad7f6
KP		 1015 * On Gen4 and above:
1016 * wait for the pipe register state bit to turn off
1017 *
1018 * Otherwise:
1019 * wait for the display line value to settle (it usually
1020 * ends up stopping at the start of the next frame).
58e10eb9 1021 *
9d0498a2 1022 */
575f7ab7 1023static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1024{
575f7ab7 1025 struct drm_device *dev = crtc->base.dev;
9d0498a2 1026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1028 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1029
1030 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1031 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1032
1033 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1034 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1035 100))
284637d9 1036 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1037 } else {
ab7ad7f6 1038 /* Wait for the display line to settle */
fbf49ea2 1039 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1040 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1041 }
79e53945
JB		 1042}
1043
b0ea7d37
DL		 1044/*
1045 * ibx_digital_port_connected - is the specified port connected?
1046 * @dev_priv: i915 private structure
1047 * @port: the port to test
1048 *
1049 * Returns true if @port is connected, false otherwise.
1050 */
1051bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1052 struct intel_digital_port *port)
1053{
1054 u32 bit;
1055
c36346e3 1056 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1057 switch (port->port) {
c36346e3
DL		 1058 case PORT_B:
1059 bit = SDE_PORTB_HOTPLUG;
1060 break;
1061 case PORT_C:
1062 bit = SDE_PORTC_HOTPLUG;
1063 break;
1064 case PORT_D:
1065 bit = SDE_PORTD_HOTPLUG;
1066 break;
1067 default:
1068 return true;
1069 }
1070 } else {
eba905b2 1071 switch (port->port) {
c36346e3
DL		 1072 case PORT_B:
1073 bit = SDE_PORTB_HOTPLUG_CPT;
1074 break;
1075 case PORT_C:
1076 bit = SDE_PORTC_HOTPLUG_CPT;
1077 break;
1078 case PORT_D:
1079 bit = SDE_PORTD_HOTPLUG_CPT;
1080 break;
1081 default:
1082 return true;
1083 }
b0ea7d37
DL		 1084 }
1085
1086 return I915_READ(SDEISR) & bit;
1087}
1088
b24e7179
JB		 1089static const char *state_string(bool enabled)
1090{
1091 return enabled ? "on" : "off";
1092}
1093
1094/* Only for pre-ILK configs */
55607e8a
DV		 1095void assert_pll(struct drm_i915_private *dev_priv,
1096 enum pipe pipe, bool state)
b24e7179
JB		 1097{
1098 int reg;
1099 u32 val;
1100 bool cur_state;
1101
1102 reg = DPLL(pipe);
1103 val = I915_READ(reg);
1104 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1105 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1106 "PLL state assertion failure (expected %s, current %s)\n",
1107 state_string(state), state_string(cur_state));
1108}
b24e7179 1109
23538ef1
JN		 1110/* XXX: the dsi pll is shared between MIPI DSI ports */
1111static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1112{
1113 u32 val;
1114 bool cur_state;
1115
1116 mutex_lock(&dev_priv->dpio_lock);
1117 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1118 mutex_unlock(&dev_priv->dpio_lock);
1119
1120 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1121 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1122 "DSI PLL state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1126#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1127
55607e8a 1128struct intel_shared_dpll *
e2b78267
DV		 1129intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1130{
1131 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1132
6e3c9717 1133 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1134 return NULL;
1135
6e3c9717 1136 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1137}
1138
040484af 1139/* For ILK+ */
55607e8a
DV		 1140void assert_shared_dpll(struct drm_i915_private *dev_priv,
1141 struct intel_shared_dpll *pll,
1142 bool state)
040484af 1143{
040484af 1144 bool cur_state;
5358901f 1145 struct intel_dpll_hw_state hw_state;
040484af 1146
92b27b08 1147 if (WARN (!pll,
46edb027 1148 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1149 return;
ee7b9f93 1150
5358901f 1151 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1152 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1153 "%s assertion failure (expected %s, current %s)\n",
1154 pll->name, state_string(state), state_string(cur_state));
040484af 1155}
040484af
JB		 1156
1157static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159{
1160 int reg;
1161 u32 val;
1162 bool cur_state;
ad80a810
PZ		 1163 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1164 pipe);
040484af 1165
affa9354
PZ		 1166 if (HAS_DDI(dev_priv->dev)) {
1167 /* DDI does not have a specific FDI_TX register */
ad80a810 1168 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1169 val = I915_READ(reg);
ad80a810 1170 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1171 } else {
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 cur_state = !!(val & FDI_TX_ENABLE);
1175 }
e2c719b7 1176 I915_STATE_WARN(cur_state != state,
040484af
JB		 1177 "FDI TX state assertion failure (expected %s, current %s)\n",
1178 state_string(state), state_string(cur_state));
1179}
1180#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1181#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1182
1183static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185{
1186 int reg;
1187 u32 val;
1188 bool cur_state;
1189
d63fa0dc
PZ		 1190 reg = FDI_RX_CTL(pipe);
1191 val = I915_READ(reg);
1192 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1193 I915_STATE_WARN(cur_state != state,
040484af
JB		 1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 state_string(state), state_string(cur_state));
1196}
1197#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202{
1203 int reg;
1204 u32 val;
1205
1206 /* ILK FDI PLL is always enabled */
3d13ef2e 1207 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1208 return;
1209
bf507ef7 1210 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1211 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1212 return;
1213
040484af
JB		 1214 reg = FDI_TX_CTL(pipe);
1215 val = I915_READ(reg);
e2c719b7 1216 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1217}
1218
55607e8a
DV		 1219void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
040484af
JB		 1221{
1222 int reg;
1223 u32 val;
55607e8a 1224 bool cur_state;
040484af
JB		 1225
1226 reg = FDI_RX_CTL(pipe);
1227 val = I915_READ(reg);
55607e8a 1228 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1229 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 state_string(state), state_string(cur_state));
040484af
JB		 1232}
1233
b680c37a
DV		 1234void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe)
ea0760cf 1236{
bedd4dba
JN		 1237 struct drm_device *dev = dev_priv->dev;
1238 int pp_reg;
ea0760cf
JB		 1239 u32 val;
1240 enum pipe panel_pipe = PIPE_A;
0de3b485 1241 bool locked = true;
ea0760cf 1242
bedd4dba
JN		 1243 if (WARN_ON(HAS_DDI(dev)))
1244 return;
1245
1246 if (HAS_PCH_SPLIT(dev)) {
1247 u32 port_sel;
1248
ea0760cf 1249 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1250 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1251
1252 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1253 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1254 panel_pipe = PIPE_B;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1259 panel_pipe = pipe;
ea0760cf
JB		 1260 } else {
1261 pp_reg = PP_CONTROL;
bedd4dba
JN		 1262 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1263 panel_pipe = PIPE_B;
ea0760cf
JB		 1264 }
1265
1266 val = I915_READ(pp_reg);
1267 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1268 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1269 locked = false;
1270
e2c719b7 1271 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1272 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1273 pipe_name(pipe));
ea0760cf
JB		 1274}
1275
93ce0ba6
JN		 1276static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state)
1278{
1279 struct drm_device *dev = dev_priv->dev;
1280 bool cur_state;
1281
d9d82081 1282 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1283 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1284 else
5efb3e28 1285 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1286
e2c719b7 1287 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), state_string(state), state_string(cur_state));
1290}
1291#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1293
b840d907
JB		 1294void assert_pipe(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, bool state)
b24e7179
JB		 1296{
1297 int reg;
1298 u32 val;
63d7bbe9 1299 bool cur_state;
702e7a56
PZ		 1300 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1301 pipe);
b24e7179 1302
b6b5d049
VS		 1303 /* if we need the pipe quirk it must be always on */
1304 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1305 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1306 state = true;
1307
f458ebbc 1308 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1309 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1310 cur_state = false;
1311 } else {
1312 reg = PIPECONF(cpu_transcoder);
1313 val = I915_READ(reg);
1314 cur_state = !!(val & PIPECONF_ENABLE);
1315 }
1316
e2c719b7 1317 I915_STATE_WARN(cur_state != state,
63d7bbe9 1318 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1319 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1320}
1321
931872fc
CW		 1322static void assert_plane(struct drm_i915_private *dev_priv,
1323 enum plane plane, bool state)
b24e7179
JB		 1324{
1325 int reg;
1326 u32 val;
931872fc 1327 bool cur_state;
b24e7179
JB		 1328
1329 reg = DSPCNTR(plane);
1330 val = I915_READ(reg);
931872fc 1331 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1332 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1333 "plane %c assertion failure (expected %s, current %s)\n",
1334 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1335}
1336
931872fc
CW		 1337#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1338#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1339
b24e7179
JB		 1340static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe)
1342{
653e1026 1343 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1344 int reg, i;
1345 u32 val;
1346 int cur_pipe;
1347
653e1026
VS		 1348 /* Primary planes are fixed to pipes on gen4+ */
1349 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1350 reg = DSPCNTR(pipe);
1351 val = I915_READ(reg);
e2c719b7 1352 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1353 "plane %c assertion failure, should be disabled but not\n",
1354 plane_name(pipe));
19ec1358 1355 return;
28c05794 1356 }
19ec1358 1357
b24e7179 1358 /* Need to check both planes against the pipe */
055e393f 1359 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1360 reg = DSPCNTR(i);
1361 val = I915_READ(reg);
1362 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1363 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1364 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1365 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1366 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1367 }
1368}
1369
19332d7a
JB		 1370static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe)
1372{
20674eef 1373 struct drm_device *dev = dev_priv->dev;
1fe47785 1374 int reg, sprite;
19332d7a
JB		 1375 u32 val;
1376
7feb8b88 1377 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1378 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1379 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1380 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1381 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1382 sprite, pipe_name(pipe));
1383 }
1384 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1385 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1386 reg = SPCNTR(pipe, sprite);
20674eef 1387 val = I915_READ(reg);
e2c719b7 1388 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1389 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1390 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1391 }
1392 } else if (INTEL_INFO(dev)->gen >= 7) {
1393 reg = SPRCTL(pipe);
19332d7a 1394 val = I915_READ(reg);
e2c719b7 1395 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1396 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1397 plane_name(pipe), pipe_name(pipe));
1398 } else if (INTEL_INFO(dev)->gen >= 5) {
1399 reg = DVSCNTR(pipe);
19332d7a 1400 val = I915_READ(reg);
e2c719b7 1401 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1402 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1403 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1404 }
1405}
1406
08c71e5e
VS		 1407static void assert_vblank_disabled(struct drm_crtc *crtc)
1408{
e2c719b7 1409 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1410 drm_crtc_vblank_put(crtc);
1411}
1412
89eff4be 1413static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1414{
1415 u32 val;
1416 bool enabled;
1417
e2c719b7 1418 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1419
92f2584a
JB		 1420 val = I915_READ(PCH_DREF_CONTROL);
1421 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1422 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1423 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1424}
1425
ab9412ba
DV		 1426static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe)
92f2584a
JB		 1428{
1429 int reg;
1430 u32 val;
1431 bool enabled;
1432
ab9412ba 1433 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1434 val = I915_READ(reg);
1435 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1436 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1437 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1438 pipe_name(pipe));
92f2584a
JB		 1439}
1440
4e634389
KP		 1441static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1443{
1444 if ((val & DP_PORT_EN) == 0)
1445 return false;
1446
1447 if (HAS_PCH_CPT(dev_priv->dev)) {
1448 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1449 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1450 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1451 return false;
44f37d1f
CML		 1452 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1453 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1454 return false;
f0575e92
KP		 1455 } else {
1456 if ((val & DP_PIPE_MASK) != (pipe << 30))
1457 return false;
1458 }
1459 return true;
1460}
1461
1519b995
KP		 1462static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1463 enum pipe pipe, u32 val)
1464{
dc0fa718 1465 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1466 return false;
1467
1468 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1469 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1470 return false;
44f37d1f
CML		 1471 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1472 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1473 return false;
1519b995 1474 } else {
dc0fa718 1475 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1476 return false;
1477 }
1478 return true;
1479}
1480
1481static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, u32 val)
1483{
1484 if ((val & LVDS_PORT_EN) == 0)
1485 return false;
1486
1487 if (HAS_PCH_CPT(dev_priv->dev)) {
1488 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1489 return false;
1490 } else {
1491 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1492 return false;
1493 }
1494 return true;
1495}
1496
1497static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
1500 if ((val & ADPA_DAC_ENABLE) == 0)
1501 return false;
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1504 return false;
1505 } else {
1506 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1507 return false;
1508 }
1509 return true;
1510}
1511
291906f1 1512static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1513 enum pipe pipe, int reg, u32 port_sel)
291906f1 1514{
47a05eca 1515 u32 val = I915_READ(reg);
e2c719b7 1516 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1517 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1518 reg, pipe_name(pipe));
de9a35ab 1519
e2c719b7 1520 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1521 && (val & DP_PIPEB_SELECT),
de9a35ab 1522 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1523}
1524
1525static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, int reg)
1527{
47a05eca 1528 u32 val = I915_READ(reg);
e2c719b7 1529 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1530 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1531 reg, pipe_name(pipe));
de9a35ab 1532
e2c719b7 1533 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1534 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1535 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1536}
1537
1538static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1539 enum pipe pipe)
1540{
1541 int reg;
1542 u32 val;
291906f1 1543
f0575e92
KP		 1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1545 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1546 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1547
1548 reg = PCH_ADPA;
1549 val = I915_READ(reg);
e2c719b7 1550 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1551 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1552 pipe_name(pipe));
291906f1
JB		 1553
1554 reg = PCH_LVDS;
1555 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1557 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 pipe_name(pipe));
291906f1 1559
e2debe91
PZ		 1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1561 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1562 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1563}
1564
40e9cf64
JB		 1565static void intel_init_dpio(struct drm_device *dev)
1566{
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568
1569 if (!IS_VALLEYVIEW(dev))
1570 return;
1571
a09caddd
CML		 1572 /*
1573 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1574 * CHV x1 PHY (DP/HDMI D)
1575 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1576 */
1577 if (IS_CHERRYVIEW(dev)) {
1578 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1580 } else {
1581 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1582 }
5382f5f3
JB		 1583}
1584
d288f65f 1585static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1586 const struct intel_crtc_state *pipe_config)
87442f73 1587{
426115cf
DV		 1588 struct drm_device *dev = crtc->base.dev;
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 int reg = DPLL(crtc->pipe);
d288f65f 1591 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1592
426115cf 1593 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1594
1595 /* No really, not for ILK+ */
1596 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1597
1598 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1599 if (IS_MOBILE(dev_priv->dev))
426115cf 1600 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1601
426115cf
DV		 1602 I915_WRITE(reg, dpll);
1603 POSTING_READ(reg);
1604 udelay(150);
1605
1606 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1607 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1608
d288f65f 1609 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1610 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1611
1612 /* We do this three times for luck */
426115cf 1613 I915_WRITE(reg, dpll);
87442f73
DV		 1614 POSTING_READ(reg);
1615 udelay(150); /* wait for warmup */
426115cf 1616 I915_WRITE(reg, dpll);
87442f73
DV		 1617 POSTING_READ(reg);
1618 udelay(150); /* wait for warmup */
426115cf 1619 I915_WRITE(reg, dpll);
87442f73
DV		 1620 POSTING_READ(reg);
1621 udelay(150); /* wait for warmup */
1622}
1623
d288f65f 1624static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1625 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1626{
1627 struct drm_device *dev = crtc->base.dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 int pipe = crtc->pipe;
1630 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1631 u32 tmp;
1632
1633 assert_pipe_disabled(dev_priv, crtc->pipe);
1634
1635 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1636
1637 mutex_lock(&dev_priv->dpio_lock);
1638
1639 /* Enable back the 10bit clock to display controller */
1640 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1641 tmp |= DPIO_DCLKP_EN;
1642 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1643
1644 /*
1645 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1646 */
1647 udelay(1);
1648
1649 /* Enable PLL */
d288f65f 1650 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1651
1652 /* Check PLL is locked */
a11b0703 1653 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1654 DRM_ERROR("PLL %d failed to lock\n", pipe);
1655
a11b0703 1656 /* not sure when this should be written */
d288f65f 1657 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1658 POSTING_READ(DPLL_MD(pipe));
1659
9d556c99
CML		 1660 mutex_unlock(&dev_priv->dpio_lock);
1661}
1662
1c4e0274
VS		 1663static int intel_num_dvo_pipes(struct drm_device *dev)
1664{
1665 struct intel_crtc *crtc;
1666 int count = 0;
1667
1668 for_each_intel_crtc(dev, crtc)
1669 count += crtc->active &&
409ee761 1670 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1671
1672 return count;
1673}
1674
66e3d5c0 1675static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1676{
66e3d5c0
DV		 1677 struct drm_device *dev = crtc->base.dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 int reg = DPLL(crtc->pipe);
6e3c9717 1680 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1681
66e3d5c0 1682 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1683
63d7bbe9 1684 /* No really, not for ILK+ */
3d13ef2e 1685 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1686
1687 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1688 if (IS_MOBILE(dev) && !IS_I830(dev))
1689 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1690
1c4e0274
VS		 1691 /* Enable DVO 2x clock on both PLLs if necessary */
1692 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1693 /*
1694 * It appears to be important that we don't enable this
1695 * for the current pipe before otherwise configuring the
1696 * PLL. No idea how this should be handled if multiple
1697 * DVO outputs are enabled simultaneosly.
1698 */
1699 dpll |= DPLL_DVO_2X_MODE;
1700 I915_WRITE(DPLL(!crtc->pipe),
1701 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1702 }
66e3d5c0
DV		 1703
1704 /* Wait for the clocks to stabilize. */
1705 POSTING_READ(reg);
1706 udelay(150);
1707
1708 if (INTEL_INFO(dev)->gen >= 4) {
1709 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1710 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1711 } else {
1712 /* The pixel multiplier can only be updated once the
1713 * DPLL is enabled and the clocks are stable.
1714 *
1715 * So write it again.
1716 */
1717 I915_WRITE(reg, dpll);
1718 }
63d7bbe9
JB		 1719
1720 /* We do this three times for luck */
66e3d5c0 1721 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1722 POSTING_READ(reg);
1723 udelay(150); /* wait for warmup */
66e3d5c0 1724 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1725 POSTING_READ(reg);
1726 udelay(150); /* wait for warmup */
66e3d5c0 1727 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1728 POSTING_READ(reg);
1729 udelay(150); /* wait for warmup */
1730}
1731
1732/**
50b44a44 1733 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1734 * @dev_priv: i915 private structure
1735 * @pipe: pipe PLL to disable
1736 *
1737 * Disable the PLL for @pipe, making sure the pipe is off first.
1738 *
1739 * Note! This is for pre-ILK only.
1740 */
1c4e0274 1741static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1742{
1c4e0274
VS		 1743 struct drm_device *dev = crtc->base.dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 enum pipe pipe = crtc->pipe;
1746
1747 /* Disable DVO 2x clock on both PLLs if necessary */
1748 if (IS_I830(dev) &&
409ee761 1749 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1750 intel_num_dvo_pipes(dev) == 1) {
1751 I915_WRITE(DPLL(PIPE_B),
1752 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1753 I915_WRITE(DPLL(PIPE_A),
1754 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1755 }
1756
b6b5d049
VS		 1757 /* Don't disable pipe or pipe PLLs if needed */
1758 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1759 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1760 return;
1761
1762 /* Make sure the pipe isn't still relying on us */
1763 assert_pipe_disabled(dev_priv, pipe);
1764
50b44a44
DV		 1765 I915_WRITE(DPLL(pipe), 0);
1766 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1767}
1768
f6071166
JB		 1769static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1770{
1771 u32 val = 0;
1772
1773 /* Make sure the pipe isn't still relying on us */
1774 assert_pipe_disabled(dev_priv, pipe);
1775
e5cbfbfb
ID		 1776 /*
1777 * Leave integrated clock source and reference clock enabled for pipe B.
1778 * The latter is needed for VGA hotplug / manual detection.
1779 */
f6071166 1780 if (pipe == PIPE_B)
e5cbfbfb 1781 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1782 I915_WRITE(DPLL(pipe), val);
1783 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1784
1785}
1786
1787static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1788{
d752048d 1789 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1790 u32 val;
1791
a11b0703
VS		 1792 /* Make sure the pipe isn't still relying on us */
1793 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1794
a11b0703 1795 /* Set PLL en = 0 */
d17ec4ce 1796 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1797 if (pipe != PIPE_A)
1798 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1799 I915_WRITE(DPLL(pipe), val);
1800 POSTING_READ(DPLL(pipe));
d752048d
VS		 1801
1802 mutex_lock(&dev_priv->dpio_lock);
1803
1804 /* Disable 10bit clock to display controller */
1805 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1806 val &= ~DPIO_DCLKP_EN;
1807 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1808
61407f6d
VS		 1809 /* disable left/right clock distribution */
1810 if (pipe != PIPE_B) {
1811 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1812 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1813 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1814 } else {
1815 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1816 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1817 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1818 }
1819
d752048d 1820 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1821}
1822
e4607fcf
CML		 1823void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1824 struct intel_digital_port *dport)
89b667f8
JB		 1825{
1826 u32 port_mask;
00fc31b7 1827 int dpll_reg;
89b667f8 1828
e4607fcf
CML		 1829 switch (dport->port) {
1830 case PORT_B:
89b667f8 1831 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1832 dpll_reg = DPLL(0);
e4607fcf
CML		 1833 break;
1834 case PORT_C:
89b667f8 1835 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_D:
1839 port_mask = DPLL_PORTD_READY_MASK;
1840 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1841 break;
1842 default:
1843 BUG();
1844 }
89b667f8 1845
00fc31b7 1846 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1847 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1848 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1849}
1850
b14b1055
DV		 1851static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1852{
1853 struct drm_device *dev = crtc->base.dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1856
be19f0ff
CW		 1857 if (WARN_ON(pll == NULL))
1858 return;
1859
3e369b76 1860 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1861 if (pll->active == 0) {
1862 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1863 WARN_ON(pll->on);
1864 assert_shared_dpll_disabled(dev_priv, pll);
1865
1866 pll->mode_set(dev_priv, pll);
1867 }
1868}
1869
92f2584a 1870/**
85b3894f 1871 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1872 * @dev_priv: i915 private structure
1873 * @pipe: pipe PLL to enable
1874 *
1875 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1876 * drives the transcoder clock.
1877 */
85b3894f 1878static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1879{
3d13ef2e
DL		 1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1883
87a875bb 1884 if (WARN_ON(pll == NULL))
48da64a8
CW		 1885 return;
1886
3e369b76 1887 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1888 return;
ee7b9f93 1889
74dd6928 1890 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1891 pll->name, pll->active, pll->on,
e2b78267 1892 crtc->base.base.id);
92f2584a 1893
cdbd2316
DV		 1894 if (pll->active++) {
1895 WARN_ON(!pll->on);
e9d6944e 1896 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1897 return;
1898 }
f4a091c7 1899 WARN_ON(pll->on);
ee7b9f93 1900
bd2bb1b9
PZ		 1901 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1902
46edb027 1903 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1904 pll->enable(dev_priv, pll);
ee7b9f93 1905 pll->on = true;
92f2584a
JB		 1906}
1907
f6daaec2 1908static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1909{
3d13ef2e
DL		 1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1913
92f2584a 1914 /* PCH only available on ILK+ */
3d13ef2e 1915 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1916 if (WARN_ON(pll == NULL))
ee7b9f93 1917 return;
92f2584a 1918
3e369b76 1919 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1920 return;
7a419866 1921
46edb027
DV		 1922 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1923 pll->name, pll->active, pll->on,
e2b78267 1924 crtc->base.base.id);
7a419866 1925
48da64a8 1926 if (WARN_ON(pll->active == 0)) {
e9d6944e 1927 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1928 return;
1929 }
1930
e9d6944e 1931 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1932 WARN_ON(!pll->on);
cdbd2316 1933 if (--pll->active)
7a419866 1934 return;
ee7b9f93 1935
46edb027 1936 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1937 pll->disable(dev_priv, pll);
ee7b9f93 1938 pll->on = false;
bd2bb1b9
PZ		 1939
1940 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1941}
1942
b8a4f404
PZ		 1943static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1944 enum pipe pipe)
040484af 1945{
23670b32 1946 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1947 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1949 uint32_t reg, val, pipeconf_val;
040484af
JB		 1950
1951 /* PCH only available on ILK+ */
55522f37 1952 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1953
1954 /* Make sure PCH DPLL is enabled */
e72f9fbf 1955 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1956 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1957
1958 /* FDI must be feeding us bits for PCH ports */
1959 assert_fdi_tx_enabled(dev_priv, pipe);
1960 assert_fdi_rx_enabled(dev_priv, pipe);
1961
23670b32
DV		 1962 if (HAS_PCH_CPT(dev)) {
1963 /* Workaround: Set the timing override bit before enabling the
1964 * pch transcoder. */
1965 reg = TRANS_CHICKEN2(pipe);
1966 val = I915_READ(reg);
1967 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1968 I915_WRITE(reg, val);
59c859d6 1969 }
23670b32 1970
ab9412ba 1971 reg = PCH_TRANSCONF(pipe);
040484af 1972 val = I915_READ(reg);
5f7f726d 1973 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1974
1975 if (HAS_PCH_IBX(dev_priv->dev)) {
1976 /*
1977 * make the BPC in transcoder be consistent with
1978 * that in pipeconf reg.
1979 */
dfd07d72
DV		 1980 val &= ~PIPECONF_BPC_MASK;
1981 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1982 }
5f7f726d
PZ		 1983
1984 val &= ~TRANS_INTERLACE_MASK;
1985 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1986 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1987 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1988 val |= TRANS_LEGACY_INTERLACED_ILK;
1989 else
1990 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
040484af
JB		 1994 I915_WRITE(reg, val | TRANS_ENABLE);
1995 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1996 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1997}
1998
8fb033d7 1999static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2000 enum transcoder cpu_transcoder)
040484af 2001{
8fb033d7 2002 u32 val, pipeconf_val;
8fb033d7
PZ		 2003
2004 /* PCH only available on ILK+ */
55522f37 2005 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2006
8fb033d7 2007 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2008 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2009 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2010
223a6fdf
PZ		 2011 /* Workaround: set timing override bit. */
2012 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2013 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2014 I915_WRITE(_TRANSA_CHICKEN2, val);
2015
25f3ef11 2016 val = TRANS_ENABLE;
937bb610 2017 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2018
9a76b1c6
PZ		 2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2020 PIPECONF_INTERLACED_ILK)
a35f2679 2021 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2022 else
2023 val |= TRANS_PROGRESSIVE;
2024
ab9412ba
DV		 2025 I915_WRITE(LPT_TRANSCONF, val);
2026 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2027 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2028}
2029
b8a4f404
PZ		 2030static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2031 enum pipe pipe)
040484af 2032{
23670b32
DV		 2033 struct drm_device *dev = dev_priv->dev;
2034 uint32_t reg, val;
040484af
JB		 2035
2036 /* FDI relies on the transcoder */
2037 assert_fdi_tx_disabled(dev_priv, pipe);
2038 assert_fdi_rx_disabled(dev_priv, pipe);
2039
291906f1
JB		 2040 /* Ports must be off as well */
2041 assert_pch_ports_disabled(dev_priv, pipe);
2042
ab9412ba 2043 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2044 val = I915_READ(reg);
2045 val &= ~TRANS_ENABLE;
2046 I915_WRITE(reg, val);
2047 /* wait for PCH transcoder off, transcoder state */
2048 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2049 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2050
2051 if (!HAS_PCH_IBX(dev)) {
2052 /* Workaround: Clear the timing override chicken bit again. */
2053 reg = TRANS_CHICKEN2(pipe);
2054 val = I915_READ(reg);
2055 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2056 I915_WRITE(reg, val);
2057 }
040484af
JB		 2058}
2059
ab4d966c 2060static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2061{
8fb033d7
PZ		 2062 u32 val;
2063
ab9412ba 2064 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2065 val &= ~TRANS_ENABLE;
ab9412ba 2066 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2067 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2068 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2069 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2070
2071 /* Workaround: clear timing override bit. */
2072 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2073 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2074 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2075}
2076
b24e7179 2077/**
309cfea8 2078 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2079 * @crtc: crtc responsible for the pipe
b24e7179 2080 *
0372264a 2081 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2082 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2083 */
e1fdc473 2084static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2085{
0372264a
PZ		 2086 struct drm_device *dev = crtc->base.dev;
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2089 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2090 pipe);
1a240d4d 2091 enum pipe pch_transcoder;
b24e7179
JB		 2092 int reg;
2093 u32 val;
2094
58c6eaa2 2095 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2096 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2097 assert_sprites_disabled(dev_priv, pipe);
2098
681e5811 2099 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2100 pch_transcoder = TRANSCODER_A;
2101 else
2102 pch_transcoder = pipe;
2103
b24e7179
JB		 2104 /*
2105 * A pipe without a PLL won't actually be able to drive bits from
2106 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2107 * need the check.
2108 */
2109 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2111 assert_dsi_pll_enabled(dev_priv);
2112 else
2113 assert_pll_enabled(dev_priv, pipe);
040484af 2114 else {
6e3c9717 2115 if (crtc->config->has_pch_encoder) {
040484af 2116 /* if driving the PCH, we need FDI enabled */
cc391bbb 2117 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2118 assert_fdi_tx_pll_enabled(dev_priv,
2119 (enum pipe) cpu_transcoder);
040484af
JB		 2120 }
2121 /* FIXME: assert CPU port conditions for SNB+ */
2122 }
b24e7179 2123
702e7a56 2124 reg = PIPECONF(cpu_transcoder);
b24e7179 2125 val = I915_READ(reg);
7ad25d48 2126 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2127 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2128 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2129 return;
7ad25d48 2130 }
00d70b15
CW		 2131
2132 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2133 POSTING_READ(reg);
b24e7179
JB		 2134}
2135
2136/**
309cfea8 2137 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2138 * @crtc: crtc whose pipes is to be disabled
b24e7179 2139 *
575f7ab7
VS		 2140 * Disable the pipe of @crtc, making sure that various hardware
2141 * specific requirements are met, if applicable, e.g. plane
2142 * disabled, panel fitter off, etc.
b24e7179
JB		 2143 *
2144 * Will wait until the pipe has shut down before returning.
2145 */
575f7ab7 2146static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2147{
575f7ab7 2148 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2149 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2150 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2151 int reg;
2152 u32 val;
2153
2154 /*
2155 * Make sure planes won't keep trying to pump pixels to us,
2156 * or we might hang the display.
2157 */
2158 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2159 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2160 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2161
702e7a56 2162 reg = PIPECONF(cpu_transcoder);
b24e7179 2163 val = I915_READ(reg);
00d70b15
CW		 2164 if ((val & PIPECONF_ENABLE) == 0)
2165 return;
2166
67adc644
VS		 2167 /*
2168 * Double wide has implications for planes
2169 * so best keep it disabled when not needed.
2170 */
6e3c9717 2171 if (crtc->config->double_wide)
67adc644
VS		 2172 val &= ~PIPECONF_DOUBLE_WIDE;
2173
2174 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2175 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2176 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2177 val &= ~PIPECONF_ENABLE;
2178
2179 I915_WRITE(reg, val);
2180 if ((val & PIPECONF_ENABLE) == 0)
2181 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2182}
2183
d74362c9
KP		 2184/*
2185 * Plane regs are double buffered, going from enabled->disabled needs a
2186 * trigger in order to latch. The display address reg provides this.
2187 */
1dba99f4
VS		 2188void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2189 enum plane plane)
d74362c9 2190{
3d13ef2e
DL		 2191 struct drm_device *dev = dev_priv->dev;
2192 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2193
2194 I915_WRITE(reg, I915_READ(reg));
2195 POSTING_READ(reg);
d74362c9
KP		 2196}
2197
b24e7179 2198/**
262ca2b0 2199 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2200 * @plane: plane to be enabled
2201 * @crtc: crtc for the plane
b24e7179 2202 *
fdd508a6 2203 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2204 */
fdd508a6
VS		 2205static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2206 struct drm_crtc *crtc)
b24e7179 2207{
fdd508a6
VS		 2208 struct drm_device *dev = plane->dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2211
2212 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2213 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2214
98ec7739
VS		 2215 if (intel_crtc->primary_enabled)
2216 return;
0037f71c 2217
4c445e0e 2218 intel_crtc->primary_enabled = true;
939c2fe8 2219
fdd508a6
VS		 2220 dev_priv->display.update_primary_plane(crtc, plane->fb,
2221 crtc->x, crtc->y);
33c3b0d1
VS		 2222
2223 /*
2224 * BDW signals flip done immediately if the plane
2225 * is disabled, even if the plane enable is already
2226 * armed to occur at the next vblank :(
2227 */
2228 if (IS_BROADWELL(dev))
2229 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2230}
2231
b24e7179 2232/**
262ca2b0 2233 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2234 * @plane: plane to be disabled
2235 * @crtc: crtc for the plane
b24e7179 2236 *
fdd508a6 2237 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2238 */
fdd508a6
VS		 2239static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2240 struct drm_crtc *crtc)
b24e7179 2241{
fdd508a6
VS		 2242 struct drm_device *dev = plane->dev;
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2245
32b7eeec
MR		 2246 if (WARN_ON(!intel_crtc->active))
2247 return;
b24e7179 2248
98ec7739
VS		 2249 if (!intel_crtc->primary_enabled)
2250 return;
0037f71c 2251
4c445e0e 2252 intel_crtc->primary_enabled = false;
939c2fe8 2253
fdd508a6
VS		 2254 dev_priv->display.update_primary_plane(crtc, plane->fb,
2255 crtc->x, crtc->y);
b24e7179
JB		 2256}
2257
693db184
CW		 2258static bool need_vtd_wa(struct drm_device *dev)
2259{
2260#ifdef CONFIG_INTEL_IOMMU
2261 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2262 return true;
2263#endif
2264 return false;
2265}
2266
50470bb0 2267unsigned int
6761dd31
TU		 2268intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2269 uint64_t fb_format_modifier)
a57ce0b2 2270{
6761dd31
TU		 2271 unsigned int tile_height;
2272 uint32_t pixel_bytes;
a57ce0b2 2273
b5d0e9bf
DL		 2274 switch (fb_format_modifier) {
2275 case DRM_FORMAT_MOD_NONE:
2276 tile_height = 1;
2277 break;
2278 case I915_FORMAT_MOD_X_TILED:
2279 tile_height = IS_GEN2(dev) ? 16 : 8;
2280 break;
2281 case I915_FORMAT_MOD_Y_TILED:
2282 tile_height = 32;
2283 break;
2284 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2285 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2286 switch (pixel_bytes) {
b5d0e9bf 2287 default:
6761dd31 2288 case 1:
b5d0e9bf
DL		 2289 tile_height = 64;
2290 break;
6761dd31
TU		 2291 case 2:
2292 case 4:
b5d0e9bf
DL		 2293 tile_height = 32;
2294 break;
6761dd31 2295 case 8:
b5d0e9bf
DL		 2296 tile_height = 16;
2297 break;
6761dd31 2298 case 16:
b5d0e9bf
DL		 2299 WARN_ONCE(1,
2300 "128-bit pixels are not supported for display!");
2301 tile_height = 16;
2302 break;
2303 }
2304 break;
2305 default:
2306 MISSING_CASE(fb_format_modifier);
2307 tile_height = 1;
2308 break;
2309 }
091df6cb 2310
6761dd31
TU		 2311 return tile_height;
2312}
2313
2314unsigned int
2315intel_fb_align_height(struct drm_device *dev, unsigned int height,
2316 uint32_t pixel_format, uint64_t fb_format_modifier)
2317{
2318 return ALIGN(height, intel_tile_height(dev, pixel_format,
2319 fb_format_modifier));
a57ce0b2
JB		 2320}
2321
f64b98cd
TU		 2322static int
2323intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2324 const struct drm_plane_state *plane_state)
2325{
50470bb0 2326 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2327
f64b98cd
TU		 2328 *view = i915_ggtt_view_normal;
2329
50470bb0
TU		 2330 if (!plane_state)
2331 return 0;
2332
121920fa 2333 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2334 return 0;
2335
9abc4648 2336 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2337
2338 info->height = fb->height;
2339 info->pixel_format = fb->pixel_format;
2340 info->pitch = fb->pitches[0];
2341 info->fb_modifier = fb->modifier[0];
2342
f64b98cd
TU		 2343 return 0;
2344}
2345
127bd2ac 2346int
850c4cdc
TU		 2347intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2348 struct drm_framebuffer *fb,
82bc3b2d 2349 const struct drm_plane_state *plane_state,
a4872ba6 2350 struct intel_engine_cs *pipelined)
6b95a207 2351{
850c4cdc 2352 struct drm_device *dev = fb->dev;
ce453d81 2353 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2354 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2355 struct i915_ggtt_view view;
6b95a207
KH		 2356 u32 alignment;
2357 int ret;
2358
ebcdd39e
MR		 2359 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2360
7b911adc
TU		 2361 switch (fb->modifier[0]) {
2362 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2363 if (INTEL_INFO(dev)->gen >= 9)
2364 alignment = 256 * 1024;
2365 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2366 alignment = 128 * 1024;
a6c45cf0 2367 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2368 alignment = 4 * 1024;
2369 else
2370 alignment = 64 * 1024;
6b95a207 2371 break;
7b911adc 2372 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2373 if (INTEL_INFO(dev)->gen >= 9)
2374 alignment = 256 * 1024;
2375 else {
2376 /* pin() will align the object as required by fence */
2377 alignment = 0;
2378 }
6b95a207 2379 break;
7b911adc 2380 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2381 case I915_FORMAT_MOD_Yf_TILED:
2382 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2383 "Y tiling bo slipped through, driver bug!\n"))
2384 return -EINVAL;
2385 alignment = 1 * 1024 * 1024;
2386 break;
6b95a207 2387 default:
7b911adc
TU		 2388 MISSING_CASE(fb->modifier[0]);
2389 return -EINVAL;
6b95a207
KH		 2390 }
2391
f64b98cd
TU		 2392 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2393 if (ret)
2394 return ret;
2395
693db184
CW		 2396 /* Note that the w/a also requires 64 PTE of padding following the
2397 * bo. We currently fill all unused PTE with the shadow page and so
2398 * we should always have valid PTE following the scanout preventing
2399 * the VT-d warning.
2400 */
2401 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2402 alignment = 256 * 1024;
2403
d6dd6843
PZ		 2404 /*
2405 * Global gtt pte registers are special registers which actually forward
2406 * writes to a chunk of system memory. Which means that there is no risk
2407 * that the register values disappear as soon as we call
2408 * intel_runtime_pm_put(), so it is correct to wrap only the
2409 * pin/unpin/fence and not more.
2410 */
2411 intel_runtime_pm_get(dev_priv);
2412
ce453d81 2413 dev_priv->mm.interruptible = false;
e6617330 2414 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2415 &view);
48b956c5 2416 if (ret)
ce453d81 2417 goto err_interruptible;
6b95a207
KH		 2418
2419 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2420 * fence, whereas 965+ only requires a fence if using
2421 * framebuffer compression. For simplicity, we always install
2422 * a fence as the cost is not that onerous.
2423 */
06d98131 2424 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2425 if (ret)
2426 goto err_unpin;
1690e1eb 2427
9a5a53b3 2428 i915_gem_object_pin_fence(obj);
6b95a207 2429
ce453d81 2430 dev_priv->mm.interruptible = true;
d6dd6843 2431 intel_runtime_pm_put(dev_priv);
6b95a207 2432 return 0;
48b956c5
CW		 2433
2434err_unpin:
f64b98cd 2435 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2436err_interruptible:
2437 dev_priv->mm.interruptible = true;
d6dd6843 2438 intel_runtime_pm_put(dev_priv);
48b956c5 2439 return ret;
6b95a207
KH		 2440}
2441
82bc3b2d
TU		 2442static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2443 const struct drm_plane_state *plane_state)
1690e1eb 2444{
82bc3b2d 2445 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2446 struct i915_ggtt_view view;
2447 int ret;
82bc3b2d 2448
ebcdd39e
MR		 2449 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2450
f64b98cd
TU		 2451 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2452 WARN_ONCE(ret, "Couldn't get view from plane state!");
2453
1690e1eb 2454 i915_gem_object_unpin_fence(obj);
f64b98cd 2455 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2456}
2457
c2c75131
DV		 2458/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2459 * is assumed to be a power-of-two. */
bc752862
CW		 2460unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2461 unsigned int tiling_mode,
2462 unsigned int cpp,
2463 unsigned int pitch)
c2c75131 2464{
bc752862
CW		 2465 if (tiling_mode != I915_TILING_NONE) {
2466 unsigned int tile_rows, tiles;
c2c75131 2467
bc752862
CW		 2468 tile_rows = *y / 8;
2469 *y %= 8;
c2c75131 2470
bc752862
CW		 2471 tiles = *x / (512/cpp);
2472 *x %= 512/cpp;
2473
2474 return tile_rows * pitch * 8 + tiles * 4096;
2475 } else {
2476 unsigned int offset;
2477
2478 offset = *y * pitch + *x * cpp;
2479 *y = 0;
2480 *x = (offset & 4095) / cpp;
2481 return offset & -4096;
2482 }
c2c75131
DV		 2483}
2484
b35d63fa 2485static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2486{
2487 switch (format) {
2488 case DISPPLANE_8BPP:
2489 return DRM_FORMAT_C8;
2490 case DISPPLANE_BGRX555:
2491 return DRM_FORMAT_XRGB1555;
2492 case DISPPLANE_BGRX565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case DISPPLANE_BGRX888:
2496 return DRM_FORMAT_XRGB8888;
2497 case DISPPLANE_RGBX888:
2498 return DRM_FORMAT_XBGR8888;
2499 case DISPPLANE_BGRX101010:
2500 return DRM_FORMAT_XRGB2101010;
2501 case DISPPLANE_RGBX101010:
2502 return DRM_FORMAT_XBGR2101010;
2503 }
2504}
2505
bc8d7dff
DL		 2506static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2507{
2508 switch (format) {
2509 case PLANE_CTL_FORMAT_RGB_565:
2510 return DRM_FORMAT_RGB565;
2511 default:
2512 case PLANE_CTL_FORMAT_XRGB_8888:
2513 if (rgb_order) {
2514 if (alpha)
2515 return DRM_FORMAT_ABGR8888;
2516 else
2517 return DRM_FORMAT_XBGR8888;
2518 } else {
2519 if (alpha)
2520 return DRM_FORMAT_ARGB8888;
2521 else
2522 return DRM_FORMAT_XRGB8888;
2523 }
2524 case PLANE_CTL_FORMAT_XRGB_2101010:
2525 if (rgb_order)
2526 return DRM_FORMAT_XBGR2101010;
2527 else
2528 return DRM_FORMAT_XRGB2101010;
2529 }
2530}
2531
5724dbd1 2532static bool
f6936e29
DV		 2533intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2534 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2535{
2536 struct drm_device *dev = crtc->base.dev;
2537 struct drm_i915_gem_object *obj = NULL;
2538 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2539 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2540 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2541 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2542 PAGE_SIZE);
2543
2544 size_aligned -= base_aligned;
46f297fb 2545
ff2652ea
CW		 2546 if (plane_config->size == 0)
2547 return false;
2548
f37b5c2b
DV		 2549 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2550 base_aligned,
2551 base_aligned,
2552 size_aligned);
46f297fb 2553 if (!obj)
484b41dd 2554 return false;
46f297fb 2555
49af449b
DL		 2556 obj->tiling_mode = plane_config->tiling;
2557 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2558 obj->stride = fb->pitches[0];
46f297fb 2559
6bf129df
DL		 2560 mode_cmd.pixel_format = fb->pixel_format;
2561 mode_cmd.width = fb->width;
2562 mode_cmd.height = fb->height;
2563 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2564 mode_cmd.modifier[0] = fb->modifier[0];
2565 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2566
2567 mutex_lock(&dev->struct_mutex);
6bf129df 2568 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2569 &mode_cmd, obj)) {
46f297fb
JB		 2570 DRM_DEBUG_KMS("intel fb init failed\n");
2571 goto out_unref_obj;
2572 }
46f297fb 2573 mutex_unlock(&dev->struct_mutex);
484b41dd 2574
f6936e29 2575 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2576 return true;
46f297fb
JB		 2577
2578out_unref_obj:
2579 drm_gem_object_unreference(&obj->base);
2580 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2581 return false;
2582}
2583
afd65eb4
MR		 2584/* Update plane->state->fb to match plane->fb after driver-internal updates */
2585static void
2586update_state_fb(struct drm_plane *plane)
2587{
2588 if (plane->fb == plane->state->fb)
2589 return;
2590
2591 if (plane->state->fb)
2592 drm_framebuffer_unreference(plane->state->fb);
2593 plane->state->fb = plane->fb;
2594 if (plane->state->fb)
2595 drm_framebuffer_reference(plane->state->fb);
2596}
2597
5724dbd1 2598static void
f6936e29
DV		 2599intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2600 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2601{
2602 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2603 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2604 struct drm_crtc *c;
2605 struct intel_crtc *i;
2ff8fde1 2606 struct drm_i915_gem_object *obj;
88595ac9
DV		 2607 struct drm_plane *primary = intel_crtc->base.primary;
2608 struct drm_framebuffer *fb;
484b41dd 2609
2d14030b 2610 if (!plane_config->fb)
484b41dd
JB		 2611 return;
2612
f6936e29 2613 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2614 fb = &plane_config->fb->base;
2615 goto valid_fb;
f55548b5 2616 }
484b41dd 2617
2d14030b 2618 kfree(plane_config->fb);
484b41dd
JB		 2619
2620 /*
2621 * Failed to alloc the obj, check to see if we should share
2622 * an fb with another CRTC instead
2623 */
70e1e0ec 2624 for_each_crtc(dev, c) {
484b41dd
JB		 2625 i = to_intel_crtc(c);
2626
2627 if (c == &intel_crtc->base)
2628 continue;
2629
2ff8fde1
MR		 2630 if (!i->active)
2631 continue;
2632
88595ac9
DV		 2633 fb = c->primary->fb;
2634 if (!fb)
484b41dd
JB		 2635 continue;
2636
88595ac9 2637 obj = intel_fb_obj(fb);
2ff8fde1 2638 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2639 drm_framebuffer_reference(fb);
2640 goto valid_fb;
484b41dd
JB		 2641 }
2642 }
88595ac9
DV		 2643
2644 return;
2645
2646valid_fb:
2647 obj = intel_fb_obj(fb);
2648 if (obj->tiling_mode != I915_TILING_NONE)
2649 dev_priv->preserve_bios_swizzle = true;
2650
2651 primary->fb = fb;
2652 primary->state->crtc = &intel_crtc->base;
2653 primary->crtc = &intel_crtc->base;
2654 update_state_fb(primary);
2655 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2656}
2657
29b9bde6
DV		 2658static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2659 struct drm_framebuffer *fb,
2660 int x, int y)
81255565
JB		 2661{
2662 struct drm_device *dev = crtc->dev;
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2665 struct drm_i915_gem_object *obj;
81255565 2666 int plane = intel_crtc->plane;
e506a0c6 2667 unsigned long linear_offset;
81255565 2668 u32 dspcntr;
f45651ba 2669 u32 reg = DSPCNTR(plane);
48404c1e 2670 int pixel_size;
f45651ba 2671
fdd508a6
VS		 2672 if (!intel_crtc->primary_enabled) {
2673 I915_WRITE(reg, 0);
2674 if (INTEL_INFO(dev)->gen >= 4)
2675 I915_WRITE(DSPSURF(plane), 0);
2676 else
2677 I915_WRITE(DSPADDR(plane), 0);
2678 POSTING_READ(reg);
2679 return;
2680 }
2681
c9ba6fad
VS		 2682 obj = intel_fb_obj(fb);
2683 if (WARN_ON(obj == NULL))
2684 return;
2685
2686 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2687
f45651ba
VS		 2688 dspcntr = DISPPLANE_GAMMA_ENABLE;
2689
fdd508a6 2690 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2691
2692 if (INTEL_INFO(dev)->gen < 4) {
2693 if (intel_crtc->pipe == PIPE_B)
2694 dspcntr |= DISPPLANE_SEL_PIPE_B;
2695
2696 /* pipesrc and dspsize control the size that is scaled from,
2697 * which should always be the user's requested size.
2698 */
2699 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2700 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2701 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2702 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2703 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2704 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2705 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2707 I915_WRITE(PRIMPOS(plane), 0);
2708 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2709 }
81255565 2710
57779d06
VS		 2711 switch (fb->pixel_format) {
2712 case DRM_FORMAT_C8:
81255565
JB		 2713 dspcntr |= DISPPLANE_8BPP;
2714 break;
57779d06
VS		 2715 case DRM_FORMAT_XRGB1555:
2716 case DRM_FORMAT_ARGB1555:
2717 dspcntr |= DISPPLANE_BGRX555;
81255565 2718 break;
57779d06
VS		 2719 case DRM_FORMAT_RGB565:
2720 dspcntr |= DISPPLANE_BGRX565;
2721 break;
2722 case DRM_FORMAT_XRGB8888:
2723 case DRM_FORMAT_ARGB8888:
2724 dspcntr |= DISPPLANE_BGRX888;
2725 break;
2726 case DRM_FORMAT_XBGR8888:
2727 case DRM_FORMAT_ABGR8888:
2728 dspcntr |= DISPPLANE_RGBX888;
2729 break;
2730 case DRM_FORMAT_XRGB2101010:
2731 case DRM_FORMAT_ARGB2101010:
2732 dspcntr |= DISPPLANE_BGRX101010;
2733 break;
2734 case DRM_FORMAT_XBGR2101010:
2735 case DRM_FORMAT_ABGR2101010:
2736 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2737 break;
2738 default:
baba133a 2739 BUG();
81255565 2740 }
57779d06 2741
f45651ba
VS		 2742 if (INTEL_INFO(dev)->gen >= 4 &&
2743 obj->tiling_mode != I915_TILING_NONE)
2744 dspcntr |= DISPPLANE_TILED;
81255565 2745
de1aa629
VS		 2746 if (IS_G4X(dev))
2747 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2748
b9897127 2749 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2750
c2c75131
DV		 2751 if (INTEL_INFO(dev)->gen >= 4) {
2752 intel_crtc->dspaddr_offset =
bc752862 2753 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2754 pixel_size,
bc752862 2755 fb->pitches[0]);
c2c75131
DV		 2756 linear_offset -= intel_crtc->dspaddr_offset;
2757 } else {
e506a0c6 2758 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2759 }
e506a0c6 2760
8e7d688b 2761 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2762 dspcntr |= DISPPLANE_ROTATE_180;
2763
6e3c9717
ACO		 2764 x += (intel_crtc->config->pipe_src_w - 1);
2765 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2766
2767 /* Finding the last pixel of the last line of the display
2768 data and adding to linear_offset*/
2769 linear_offset +=
6e3c9717
ACO		 2770 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2772 }
2773
2774 I915_WRITE(reg, dspcntr);
2775
01f2c773 2776 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2777 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2778 I915_WRITE(DSPSURF(plane),
2779 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2780 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2781 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2782 } else
f343c5f6 2783 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2784 POSTING_READ(reg);
17638cd6
JB		 2785}
2786
29b9bde6
DV		 2787static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2788 struct drm_framebuffer *fb,
2789 int x, int y)
17638cd6
JB		 2790{
2791 struct drm_device *dev = crtc->dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2794 struct drm_i915_gem_object *obj;
17638cd6 2795 int plane = intel_crtc->plane;
e506a0c6 2796 unsigned long linear_offset;
17638cd6 2797 u32 dspcntr;
f45651ba 2798 u32 reg = DSPCNTR(plane);
48404c1e 2799 int pixel_size;
f45651ba 2800
fdd508a6
VS		 2801 if (!intel_crtc->primary_enabled) {
2802 I915_WRITE(reg, 0);
2803 I915_WRITE(DSPSURF(plane), 0);
2804 POSTING_READ(reg);
2805 return;
2806 }
2807
c9ba6fad
VS		 2808 obj = intel_fb_obj(fb);
2809 if (WARN_ON(obj == NULL))
2810 return;
2811
2812 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2813
f45651ba
VS		 2814 dspcntr = DISPPLANE_GAMMA_ENABLE;
2815
fdd508a6 2816 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2817
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2820
57779d06
VS		 2821 switch (fb->pixel_format) {
2822 case DRM_FORMAT_C8:
17638cd6
JB		 2823 dspcntr |= DISPPLANE_8BPP;
2824 break;
57779d06
VS		 2825 case DRM_FORMAT_RGB565:
2826 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2827 break;
57779d06
VS		 2828 case DRM_FORMAT_XRGB8888:
2829 case DRM_FORMAT_ARGB8888:
2830 dspcntr |= DISPPLANE_BGRX888;
2831 break;
2832 case DRM_FORMAT_XBGR8888:
2833 case DRM_FORMAT_ABGR8888:
2834 dspcntr |= DISPPLANE_RGBX888;
2835 break;
2836 case DRM_FORMAT_XRGB2101010:
2837 case DRM_FORMAT_ARGB2101010:
2838 dspcntr |= DISPPLANE_BGRX101010;
2839 break;
2840 case DRM_FORMAT_XBGR2101010:
2841 case DRM_FORMAT_ABGR2101010:
2842 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2843 break;
2844 default:
baba133a 2845 BUG();
17638cd6
JB		 2846 }
2847
2848 if (obj->tiling_mode != I915_TILING_NONE)
2849 dspcntr |= DISPPLANE_TILED;
17638cd6 2850
f45651ba 2851 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2852 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2853
b9897127 2854 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2855 intel_crtc->dspaddr_offset =
bc752862 2856 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2857 pixel_size,
bc752862 2858 fb->pitches[0]);
c2c75131 2859 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2860 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2861 dspcntr |= DISPPLANE_ROTATE_180;
2862
2863 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2864 x += (intel_crtc->config->pipe_src_w - 1);
2865 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2866
2867 /* Finding the last pixel of the last line of the display
2868 data and adding to linear_offset*/
2869 linear_offset +=
6e3c9717
ACO		 2870 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2871 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2872 }
2873 }
2874
2875 I915_WRITE(reg, dspcntr);
17638cd6 2876
01f2c773 2877 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2878 I915_WRITE(DSPSURF(plane),
2879 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2880 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2881 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2882 } else {
2883 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2884 I915_WRITE(DSPLINOFF(plane), linear_offset);
2885 }
17638cd6 2886 POSTING_READ(reg);
17638cd6
JB		 2887}
2888
b321803d
DL		 2889u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2890 uint32_t pixel_format)
2891{
2892 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2893
2894 /*
2895 * The stride is either expressed as a multiple of 64 bytes
2896 * chunks for linear buffers or in number of tiles for tiled
2897 * buffers.
2898 */
2899 switch (fb_modifier) {
2900 case DRM_FORMAT_MOD_NONE:
2901 return 64;
2902 case I915_FORMAT_MOD_X_TILED:
2903 if (INTEL_INFO(dev)->gen == 2)
2904 return 128;
2905 return 512;
2906 case I915_FORMAT_MOD_Y_TILED:
2907 /* No need to check for old gens and Y tiling since this is
2908 * about the display engine and those will be blocked before
2909 * we get here.
2910 */
2911 return 128;
2912 case I915_FORMAT_MOD_Yf_TILED:
2913 if (bits_per_pixel == 8)
2914 return 64;
2915 else
2916 return 128;
2917 default:
2918 MISSING_CASE(fb_modifier);
2919 return 64;
2920 }
2921}
2922
121920fa
TU		 2923unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2924 struct drm_i915_gem_object *obj)
2925{
9abc4648 2926 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2927
2928 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2929 view = &i915_ggtt_view_rotated;
121920fa
TU		 2930
2931 return i915_gem_obj_ggtt_offset_view(obj, view);
2932}
2933
70d21f0e
DL		 2934static void skylake_update_primary_plane(struct drm_crtc *crtc,
2935 struct drm_framebuffer *fb,
2936 int x, int y)
2937{
2938 struct drm_device *dev = crtc->dev;
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2941 struct drm_i915_gem_object *obj;
2942 int pipe = intel_crtc->pipe;
3b7a5119
SJ		 2943 u32 plane_ctl, stride_div, stride;
2944 u32 tile_height, plane_offset, plane_size;
2945 unsigned int rotation;
2946 int x_offset, y_offset;
121920fa 2947 unsigned long surf_addr;
3b7a5119 2948 struct drm_plane *plane;
70d21f0e
DL		 2949
2950 if (!intel_crtc->primary_enabled) {
2951 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2952 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2953 POSTING_READ(PLANE_CTL(pipe, 0));
2954 return;
2955 }
2956
2957 plane_ctl = PLANE_CTL_ENABLE |
2958 PLANE_CTL_PIPE_GAMMA_ENABLE |
2959 PLANE_CTL_PIPE_CSC_ENABLE;
2960
2961 switch (fb->pixel_format) {
2962 case DRM_FORMAT_RGB565:
2963 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2964 break;
2965 case DRM_FORMAT_XRGB8888:
2966 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2967 break;
f75fb42a
JN		 2968 case DRM_FORMAT_ARGB8888:
2969 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2970 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971 break;
70d21f0e
DL		 2972 case DRM_FORMAT_XBGR8888:
2973 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2974 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2975 break;
f75fb42a
JN		 2976 case DRM_FORMAT_ABGR8888:
2977 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2978 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2979 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2980 break;
70d21f0e
DL		 2981 case DRM_FORMAT_XRGB2101010:
2982 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2983 break;
2984 case DRM_FORMAT_XBGR2101010:
2985 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2986 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2987 break;
2988 default:
2989 BUG();
2990 }
2991
30af77c4
DV		 2992 switch (fb->modifier[0]) {
2993 case DRM_FORMAT_MOD_NONE:
70d21f0e 2994 break;
30af77c4 2995 case I915_FORMAT_MOD_X_TILED:
70d21f0e 2996 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 2997 break;
2998 case I915_FORMAT_MOD_Y_TILED:
2999 plane_ctl |= PLANE_CTL_TILED_Y;
3000 break;
3001 case I915_FORMAT_MOD_Yf_TILED:
3002 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3003 break;
3004 default:
b321803d 3005 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3006 }
3007
3008 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3b7a5119
SJ		 3009
3010 plane = crtc->primary;
3011 rotation = plane->state->rotation;
3012 switch (rotation) {
3013 case BIT(DRM_ROTATE_90):
3014 plane_ctl |= PLANE_CTL_ROTATE_90;
3015 break;
3016
3017 case BIT(DRM_ROTATE_180):
1447dde0 3018 plane_ctl |= PLANE_CTL_ROTATE_180;
3b7a5119
SJ		 3019 break;
3020
3021 case BIT(DRM_ROTATE_270):
3022 plane_ctl |= PLANE_CTL_ROTATE_270;
3023 break;
3024 }
70d21f0e 3025
b321803d
DL		 3026 obj = intel_fb_obj(fb);
3027 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3028 fb->pixel_format);
3b7a5119
SJ		 3029 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3030
3031 if (intel_rotation_90_or_270(rotation)) {
3032 /* stride = Surface height in tiles */
3033 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3034 fb->modifier[0]);
3035 stride = DIV_ROUND_UP(fb->height, tile_height);
3036 x_offset = stride * tile_height - y - (plane->state->src_h >> 16);
3037 y_offset = x;
3038 plane_size = ((plane->state->src_w >> 16) - 1) << 16 |
3039 ((plane->state->src_h >> 16) - 1);
3040 } else {
3041 stride = fb->pitches[0] / stride_div;
3042 x_offset = x;
3043 y_offset = y;
3044 plane_size = ((plane->state->src_h >> 16) - 1) << 16 |
3045 ((plane->state->src_w >> 16) - 1);
3046 }
3047 plane_offset = y_offset << 16 | x_offset;
b321803d 3048
70d21f0e 3049 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e 3050 I915_WRITE(PLANE_POS(pipe, 0), 0);
3b7a5119
SJ		 3051 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3052 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3053 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
121920fa 3054 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3055
3056 POSTING_READ(PLANE_SURF(pipe, 0));
3057}
3058
17638cd6
JB		 3059/* Assume fb object is pinned & idle & fenced and just update base pointers */
3060static int
3061intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3062 int x, int y, enum mode_set_atomic state)
3063{
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3066
6b8e6ed0
CW		 3067 if (dev_priv->display.disable_fbc)
3068 dev_priv->display.disable_fbc(dev);
81255565 3069
29b9bde6
DV		 3070 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3071
3072 return 0;
81255565
JB		 3073}
3074
7514747d 3075static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3076{
96a02917
VS		 3077 struct drm_crtc *crtc;
3078
70e1e0ec 3079 for_each_crtc(dev, crtc) {
96a02917
VS		 3080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3081 enum plane plane = intel_crtc->plane;
3082
3083 intel_prepare_page_flip(dev, plane);
3084 intel_finish_page_flip_plane(dev, plane);
3085 }
7514747d
VS		 3086}
3087
3088static void intel_update_primary_planes(struct drm_device *dev)
3089{
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 struct drm_crtc *crtc;
96a02917 3092
70e1e0ec 3093 for_each_crtc(dev, crtc) {
96a02917
VS		 3094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3095
51fd371b 3096 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3097 /*
3098 * FIXME: Once we have proper support for primary planes (and
3099 * disabling them without disabling the entire crtc) allow again
66e514c1 3100 * a NULL crtc->primary->fb.
947fdaad 3101 */
f4510a27 3102 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3103 dev_priv->display.update_primary_plane(crtc,
66e514c1 3104 crtc->primary->fb,
262ca2b0
MR		 3105 crtc->x,
3106 crtc->y);
51fd371b 3107 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3108 }
3109}
3110
7514747d
VS		 3111void intel_prepare_reset(struct drm_device *dev)
3112{
f98ce92f
VS		 3113 struct drm_i915_private *dev_priv = to_i915(dev);
3114 struct intel_crtc *crtc;
3115
7514747d
VS		 3116 /* no reset support for gen2 */
3117 if (IS_GEN2(dev))
3118 return;
3119
3120 /* reset doesn't touch the display */
3121 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3122 return;
3123
3124 drm_modeset_lock_all(dev);
f98ce92f
VS		 3125
3126 /*
3127 * Disabling the crtcs gracefully seems nicer. Also the
3128 * g33 docs say we should at least disable all the planes.
3129 */
3130 for_each_intel_crtc(dev, crtc) {
3131 if (crtc->active)
3132 dev_priv->display.crtc_disable(&crtc->base);
3133 }
7514747d
VS		 3134}
3135
3136void intel_finish_reset(struct drm_device *dev)
3137{
3138 struct drm_i915_private *dev_priv = to_i915(dev);
3139
3140 /*
3141 * Flips in the rings will be nuked by the reset,
3142 * so complete all pending flips so that user space
3143 * will get its events and not get stuck.
3144 */
3145 intel_complete_page_flips(dev);
3146
3147 /* no reset support for gen2 */
3148 if (IS_GEN2(dev))
3149 return;
3150
3151 /* reset doesn't touch the display */
3152 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3153 /*
3154 * Flips in the rings have been nuked by the reset,
3155 * so update the base address of all primary
3156 * planes to the the last fb to make sure we're
3157 * showing the correct fb after a reset.
3158 */
3159 intel_update_primary_planes(dev);
3160 return;
3161 }
3162
3163 /*
3164 * The display has been reset as well,
3165 * so need a full re-initialization.
3166 */
3167 intel_runtime_pm_disable_interrupts(dev_priv);
3168 intel_runtime_pm_enable_interrupts(dev_priv);
3169
3170 intel_modeset_init_hw(dev);
3171
3172 spin_lock_irq(&dev_priv->irq_lock);
3173 if (dev_priv->display.hpd_irq_setup)
3174 dev_priv->display.hpd_irq_setup(dev);
3175 spin_unlock_irq(&dev_priv->irq_lock);
3176
3177 intel_modeset_setup_hw_state(dev, true);
3178
3179 intel_hpd_init(dev_priv);
3180
3181 drm_modeset_unlock_all(dev);
3182}
3183
14667a4b
CW		 3184static int
3185intel_finish_fb(struct drm_framebuffer *old_fb)
3186{
2ff8fde1 3187 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3188 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3189 bool was_interruptible = dev_priv->mm.interruptible;
3190 int ret;
3191
14667a4b
CW		 3192 /* Big Hammer, we also need to ensure that any pending
3193 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3194 * current scanout is retired before unpinning the old
3195 * framebuffer.
3196 *
3197 * This should only fail upon a hung GPU, in which case we
3198 * can safely continue.
3199 */
3200 dev_priv->mm.interruptible = false;
3201 ret = i915_gem_object_finish_gpu(obj);
3202 dev_priv->mm.interruptible = was_interruptible;
3203
3204 return ret;
3205}
3206
7d5e3799
CW		 3207static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3212 bool pending;
3213
3214 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3215 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3216 return false;
3217
5e2d7afc 3218 spin_lock_irq(&dev->event_lock);
7d5e3799 3219 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3220 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3221
3222 return pending;
3223}
3224
e30e8f75
GP		 3225static void intel_update_pipe_size(struct intel_crtc *crtc)
3226{
3227 struct drm_device *dev = crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 const struct drm_display_mode *adjusted_mode;
3230
3231 if (!i915.fastboot)
3232 return;
3233
3234 /*
3235 * Update pipe size and adjust fitter if needed: the reason for this is
3236 * that in compute_mode_changes we check the native mode (not the pfit
3237 * mode) to see if we can flip rather than do a full mode set. In the
3238 * fastboot case, we'll flip, but if we don't update the pipesrc and
3239 * pfit state, we'll end up with a big fb scanned out into the wrong
3240 * sized surface.
3241 *
3242 * To fix this properly, we need to hoist the checks up into
3243 * compute_mode_changes (or above), check the actual pfit state and
3244 * whether the platform allows pfit disable with pipe active, and only
3245 * then update the pipesrc and pfit state, even on the flip path.
3246 */
3247
6e3c9717 3248 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3249
3250 I915_WRITE(PIPESRC(crtc->pipe),
3251 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3252 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3253 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3254 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3255 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3256 I915_WRITE(PF_CTL(crtc->pipe), 0);
3257 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3258 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3259 }
6e3c9717
ACO		 3260 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3261 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3262}
3263
5e84e1a4
ZW		 3264static void intel_fdi_normal_train(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269 int pipe = intel_crtc->pipe;
3270 u32 reg, temp;
3271
3272 /* enable normal train */
3273 reg = FDI_TX_CTL(pipe);
3274 temp = I915_READ(reg);
61e499bf 3275 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3276 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3277 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3278 } else {
3279 temp &= ~FDI_LINK_TRAIN_NONE;
3280 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3281 }
5e84e1a4
ZW		 3282 I915_WRITE(reg, temp);
3283
3284 reg = FDI_RX_CTL(pipe);
3285 temp = I915_READ(reg);
3286 if (HAS_PCH_CPT(dev)) {
3287 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3288 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3289 } else {
3290 temp &= ~FDI_LINK_TRAIN_NONE;
3291 temp |= FDI_LINK_TRAIN_NONE;
3292 }
3293 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3294
3295 /* wait one idle pattern time */
3296 POSTING_READ(reg);
3297 udelay(1000);
357555c0
JB		 3298
3299 /* IVB wants error correction enabled */
3300 if (IS_IVYBRIDGE(dev))
3301 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3302 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3303}
3304
8db9d77b
ZW		 3305/* The FDI link training functions for ILK/Ibexpeak. */
3306static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3307{
3308 struct drm_device *dev = crtc->dev;
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3311 int pipe = intel_crtc->pipe;
5eddb70b 3312 u32 reg, temp, tries;
8db9d77b 3313
1c8562f6 3314 /* FDI needs bits from pipe first */
0fc932b8 3315 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3316
e1a44743
AJ		 3317 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3318 for train result */
5eddb70b
CW		 3319 reg = FDI_RX_IMR(pipe);
3320 temp = I915_READ(reg);
e1a44743
AJ		 3321 temp &= ~FDI_RX_SYMBOL_LOCK;
3322 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3323 I915_WRITE(reg, temp);
3324 I915_READ(reg);
e1a44743
AJ		 3325 udelay(150);
3326
8db9d77b 3327 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3328 reg = FDI_TX_CTL(pipe);
3329 temp = I915_READ(reg);
627eb5a3 3330 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3331 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3332 temp &= ~FDI_LINK_TRAIN_NONE;
3333 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3334 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3335
5eddb70b
CW		 3336 reg = FDI_RX_CTL(pipe);
3337 temp = I915_READ(reg);
8db9d77b
ZW		 3338 temp &= ~FDI_LINK_TRAIN_NONE;
3339 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3340 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3341
3342 POSTING_READ(reg);
8db9d77b
ZW		 3343 udelay(150);
3344
5b2adf89 3345 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3346 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3347 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3348 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3349
5eddb70b 3350 reg = FDI_RX_IIR(pipe);
e1a44743 3351 for (tries = 0; tries < 5; tries++) {
5eddb70b 3352 temp = I915_READ(reg);
8db9d77b
ZW		 3353 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3354
3355 if ((temp & FDI_RX_BIT_LOCK)) {
3356 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3357 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3358 break;
3359 }
8db9d77b 3360 }
e1a44743 3361 if (tries == 5)
5eddb70b 3362 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3363
3364 /* Train 2 */
5eddb70b
CW		 3365 reg = FDI_TX_CTL(pipe);
3366 temp = I915_READ(reg);
8db9d77b
ZW		 3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3369 I915_WRITE(reg, temp);
8db9d77b 3370
5eddb70b
CW		 3371 reg = FDI_RX_CTL(pipe);
3372 temp = I915_READ(reg);
8db9d77b
ZW		 3373 temp &= ~FDI_LINK_TRAIN_NONE;
3374 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3375 I915_WRITE(reg, temp);
8db9d77b 3376
5eddb70b
CW		 3377 POSTING_READ(reg);
3378 udelay(150);
8db9d77b 3379
5eddb70b 3380 reg = FDI_RX_IIR(pipe);
e1a44743 3381 for (tries = 0; tries < 5; tries++) {
5eddb70b 3382 temp = I915_READ(reg);
8db9d77b
ZW		 3383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3384
3385 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3387 DRM_DEBUG_KMS("FDI train 2 done.\n");
3388 break;
3389 }
8db9d77b 3390 }
e1a44743 3391 if (tries == 5)
5eddb70b 3392 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3393
3394 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3395
8db9d77b
ZW		 3396}
3397
0206e353 3398static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3399 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3400 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3401 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3402 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3403};
3404
3405/* The FDI link training functions for SNB/Cougarpoint. */
3406static void gen6_fdi_link_train(struct drm_crtc *crtc)
3407{
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
fa37d39e 3412 u32 reg, temp, i, retry;
8db9d77b 3413
e1a44743
AJ		 3414 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3415 for train result */
5eddb70b
CW		 3416 reg = FDI_RX_IMR(pipe);
3417 temp = I915_READ(reg);
e1a44743
AJ		 3418 temp &= ~FDI_RX_SYMBOL_LOCK;
3419 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3420 I915_WRITE(reg, temp);
3421
3422 POSTING_READ(reg);
e1a44743
AJ		 3423 udelay(150);
3424
8db9d77b 3425 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3426 reg = FDI_TX_CTL(pipe);
3427 temp = I915_READ(reg);
627eb5a3 3428 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3429 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3430 temp &= ~FDI_LINK_TRAIN_NONE;
3431 temp |= FDI_LINK_TRAIN_PATTERN_1;
3432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3433 /* SNB-B */
3434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3436
d74cf324
DV		 3437 I915_WRITE(FDI_RX_MISC(pipe),
3438 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3439
5eddb70b
CW		 3440 reg = FDI_RX_CTL(pipe);
3441 temp = I915_READ(reg);
8db9d77b
ZW		 3442 if (HAS_PCH_CPT(dev)) {
3443 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3444 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3445 } else {
3446 temp &= ~FDI_LINK_TRAIN_NONE;
3447 temp |= FDI_LINK_TRAIN_PATTERN_1;
3448 }
5eddb70b
CW		 3449 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3450
3451 POSTING_READ(reg);
8db9d77b
ZW		 3452 udelay(150);
3453
0206e353 3454 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
8db9d77b
ZW		 3457 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3458 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3459 I915_WRITE(reg, temp);
3460
3461 POSTING_READ(reg);
8db9d77b
ZW		 3462 udelay(500);
3463
fa37d39e
SP		 3464 for (retry = 0; retry < 5; retry++) {
3465 reg = FDI_RX_IIR(pipe);
3466 temp = I915_READ(reg);
3467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3468 if (temp & FDI_RX_BIT_LOCK) {
3469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3470 DRM_DEBUG_KMS("FDI train 1 done.\n");
3471 break;
3472 }
3473 udelay(50);
8db9d77b 3474 }
fa37d39e
SP		 3475 if (retry < 5)
3476 break;
8db9d77b
ZW		 3477 }
3478 if (i == 4)
5eddb70b 3479 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3480
3481 /* Train 2 */
5eddb70b
CW		 3482 reg = FDI_TX_CTL(pipe);
3483 temp = I915_READ(reg);
8db9d77b
ZW		 3484 temp &= ~FDI_LINK_TRAIN_NONE;
3485 temp |= FDI_LINK_TRAIN_PATTERN_2;
3486 if (IS_GEN6(dev)) {
3487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3488 /* SNB-B */
3489 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3490 }
5eddb70b 3491 I915_WRITE(reg, temp);
8db9d77b 3492
5eddb70b
CW		 3493 reg = FDI_RX_CTL(pipe);
3494 temp = I915_READ(reg);
8db9d77b
ZW		 3495 if (HAS_PCH_CPT(dev)) {
3496 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3497 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3498 } else {
3499 temp &= ~FDI_LINK_TRAIN_NONE;
3500 temp |= FDI_LINK_TRAIN_PATTERN_2;
3501 }
5eddb70b
CW		 3502 I915_WRITE(reg, temp);
3503
3504 POSTING_READ(reg);
8db9d77b
ZW		 3505 udelay(150);
3506
0206e353 3507 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
8db9d77b
ZW		 3510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3511 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3512 I915_WRITE(reg, temp);
3513
3514 POSTING_READ(reg);
8db9d77b
ZW		 3515 udelay(500);
3516
fa37d39e
SP		 3517 for (retry = 0; retry < 5; retry++) {
3518 reg = FDI_RX_IIR(pipe);
3519 temp = I915_READ(reg);
3520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3521 if (temp & FDI_RX_SYMBOL_LOCK) {
3522 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3523 DRM_DEBUG_KMS("FDI train 2 done.\n");
3524 break;
3525 }
3526 udelay(50);
8db9d77b 3527 }
fa37d39e
SP		 3528 if (retry < 5)
3529 break;
8db9d77b
ZW		 3530 }
3531 if (i == 4)
5eddb70b 3532 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3533
3534 DRM_DEBUG_KMS("FDI train done.\n");
3535}
3536
357555c0
JB		 3537/* Manual link training for Ivy Bridge A0 parts */
3538static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3539{
3540 struct drm_device *dev = crtc->dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543 int pipe = intel_crtc->pipe;
139ccd3f 3544 u32 reg, temp, i, j;
357555c0
JB		 3545
3546 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3547 for train result */
3548 reg = FDI_RX_IMR(pipe);
3549 temp = I915_READ(reg);
3550 temp &= ~FDI_RX_SYMBOL_LOCK;
3551 temp &= ~FDI_RX_BIT_LOCK;
3552 I915_WRITE(reg, temp);
3553
3554 POSTING_READ(reg);
3555 udelay(150);
3556
01a415fd
DV		 3557 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3558 I915_READ(FDI_RX_IIR(pipe)));
3559
139ccd3f
JB		 3560 /* Try each vswing and preemphasis setting twice before moving on */
3561 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3562 /* disable first in case we need to retry */
3563 reg = FDI_TX_CTL(pipe);
3564 temp = I915_READ(reg);
3565 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3566 temp &= ~FDI_TX_ENABLE;
3567 I915_WRITE(reg, temp);
357555c0 3568
139ccd3f
JB		 3569 reg = FDI_RX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~FDI_LINK_TRAIN_AUTO;
3572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3573 temp &= ~FDI_RX_ENABLE;
3574 I915_WRITE(reg, temp);
357555c0 3575
139ccd3f 3576 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3577 reg = FDI_TX_CTL(pipe);
3578 temp = I915_READ(reg);
139ccd3f 3579 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3580 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3581 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3583 temp |= snb_b_fdi_train_param[j/2];
3584 temp |= FDI_COMPOSITE_SYNC;
3585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3586
139ccd3f
JB		 3587 I915_WRITE(FDI_RX_MISC(pipe),
3588 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3589
139ccd3f 3590 reg = FDI_RX_CTL(pipe);
357555c0 3591 temp = I915_READ(reg);
139ccd3f
JB		 3592 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3593 temp |= FDI_COMPOSITE_SYNC;
3594 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3595
139ccd3f
JB		 3596 POSTING_READ(reg);
3597 udelay(1); /* should be 0.5us */
357555c0 3598
139ccd3f
JB		 3599 for (i = 0; i < 4; i++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3603
139ccd3f
JB		 3604 if (temp & FDI_RX_BIT_LOCK ||
3605 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3606 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3607 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3608 i);
3609 break;
3610 }
3611 udelay(1); /* should be 0.5us */
3612 }
3613 if (i == 4) {
3614 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3615 continue;
3616 }
357555c0 3617
139ccd3f 3618 /* Train 2 */
357555c0
JB		 3619 reg = FDI_TX_CTL(pipe);
3620 temp = I915_READ(reg);
139ccd3f
JB		 3621 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3622 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3623 I915_WRITE(reg, temp);
3624
3625 reg = FDI_RX_CTL(pipe);
3626 temp = I915_READ(reg);
3627 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3628 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3629 I915_WRITE(reg, temp);
3630
3631 POSTING_READ(reg);
139ccd3f 3632 udelay(2); /* should be 1.5us */
357555c0 3633
139ccd3f
JB		 3634 for (i = 0; i < 4; i++) {
3635 reg = FDI_RX_IIR(pipe);
3636 temp = I915_READ(reg);
3637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3638
139ccd3f
JB		 3639 if (temp & FDI_RX_SYMBOL_LOCK ||
3640 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3641 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3642 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3643 i);
3644 goto train_done;
3645 }
3646 udelay(2); /* should be 1.5us */
357555c0 3647 }
139ccd3f
JB		 3648 if (i == 4)
3649 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3650 }
357555c0 3651
139ccd3f 3652train_done:
357555c0
JB		 3653 DRM_DEBUG_KMS("FDI train done.\n");
3654}
3655
88cefb6c 3656static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3657{
88cefb6c 3658 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3659 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3660 int pipe = intel_crtc->pipe;
5eddb70b 3661 u32 reg, temp;
79e53945 3662
c64e311e 3663
c98e9dcf 3664 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3665 reg = FDI_RX_CTL(pipe);
3666 temp = I915_READ(reg);
627eb5a3 3667 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3668 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3669 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3670 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3671
3672 POSTING_READ(reg);
c98e9dcf
JB		 3673 udelay(200);
3674
3675 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3676 temp = I915_READ(reg);
3677 I915_WRITE(reg, temp | FDI_PCDCLK);
3678
3679 POSTING_READ(reg);
c98e9dcf
JB		 3680 udelay(200);
3681
20749730
PZ		 3682 /* Enable CPU FDI TX PLL, always on for Ironlake */
3683 reg = FDI_TX_CTL(pipe);
3684 temp = I915_READ(reg);
3685 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3686 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3687
20749730
PZ		 3688 POSTING_READ(reg);
3689 udelay(100);
6be4a607 3690 }
0e23b99d
JB		 3691}
3692
88cefb6c
DV		 3693static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3694{
3695 struct drm_device *dev = intel_crtc->base.dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 int pipe = intel_crtc->pipe;
3698 u32 reg, temp;
3699
3700 /* Switch from PCDclk to Rawclk */
3701 reg = FDI_RX_CTL(pipe);
3702 temp = I915_READ(reg);
3703 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3704
3705 /* Disable CPU FDI TX PLL */
3706 reg = FDI_TX_CTL(pipe);
3707 temp = I915_READ(reg);
3708 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3709
3710 POSTING_READ(reg);
3711 udelay(100);
3712
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3716
3717 /* Wait for the clocks to turn off. */
3718 POSTING_READ(reg);
3719 udelay(100);
3720}
3721
0fc932b8
JB		 3722static void ironlake_fdi_disable(struct drm_crtc *crtc)
3723{
3724 struct drm_device *dev = crtc->dev;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3727 int pipe = intel_crtc->pipe;
3728 u32 reg, temp;
3729
3730 /* disable CPU FDI tx and PCH FDI rx */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3734 POSTING_READ(reg);
3735
3736 reg = FDI_RX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~(0x7 << 16);
dfd07d72 3739 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3740 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3741
3742 POSTING_READ(reg);
3743 udelay(100);
3744
3745 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3746 if (HAS_PCH_IBX(dev))
6f06ce18 3747 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3748
3749 /* still set train pattern 1 */
3750 reg = FDI_TX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~FDI_LINK_TRAIN_NONE;
3753 temp |= FDI_LINK_TRAIN_PATTERN_1;
3754 I915_WRITE(reg, temp);
3755
3756 reg = FDI_RX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 if (HAS_PCH_CPT(dev)) {
3759 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3760 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3761 } else {
3762 temp &= ~FDI_LINK_TRAIN_NONE;
3763 temp |= FDI_LINK_TRAIN_PATTERN_1;
3764 }
3765 /* BPC in FDI rx is consistent with that in PIPECONF */
3766 temp &= ~(0x07 << 16);
dfd07d72 3767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3768 I915_WRITE(reg, temp);
3769
3770 POSTING_READ(reg);
3771 udelay(100);
3772}
3773
5dce5b93
CW		 3774bool intel_has_pending_fb_unpin(struct drm_device *dev)
3775{
3776 struct intel_crtc *crtc;
3777
3778 /* Note that we don't need to be called with mode_config.lock here
3779 * as our list of CRTC objects is static for the lifetime of the
3780 * device and so cannot disappear as we iterate. Similarly, we can
3781 * happily treat the predicates as racy, atomic checks as userspace
3782 * cannot claim and pin a new fb without at least acquring the
3783 * struct_mutex and so serialising with us.
3784 */
d3fcc808 3785 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3786 if (atomic_read(&crtc->unpin_work_count) == 0)
3787 continue;
3788
3789 if (crtc->unpin_work)
3790 intel_wait_for_vblank(dev, crtc->pipe);
3791
3792 return true;
3793 }
3794
3795 return false;
3796}
3797
d6bbafa1
CW		 3798static void page_flip_completed(struct intel_crtc *intel_crtc)
3799{
3800 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3801 struct intel_unpin_work *work = intel_crtc->unpin_work;
3802
3803 /* ensure that the unpin work is consistent wrt ->pending. */
3804 smp_rmb();
3805 intel_crtc->unpin_work = NULL;
3806
3807 if (work->event)
3808 drm_send_vblank_event(intel_crtc->base.dev,
3809 intel_crtc->pipe,
3810 work->event);
3811
3812 drm_crtc_vblank_put(&intel_crtc->base);
3813
3814 wake_up_all(&dev_priv->pending_flip_queue);
3815 queue_work(dev_priv->wq, &work->work);
3816
3817 trace_i915_flip_complete(intel_crtc->plane,
3818 work->pending_flip_obj);
3819}
3820
46a55d30 3821void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3822{
0f91128d 3823 struct drm_device *dev = crtc->dev;
5bb61643 3824 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3825
2c10d571 3826 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3827 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3828 !intel_crtc_has_pending_flip(crtc),
3829 60*HZ) == 0)) {
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3831
5e2d7afc 3832 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3833 if (intel_crtc->unpin_work) {
3834 WARN_ONCE(1, "Removing stuck page flip\n");
3835 page_flip_completed(intel_crtc);
3836 }
5e2d7afc 3837 spin_unlock_irq(&dev->event_lock);
9c787942 3838 }
5bb61643 3839
975d568a
CW		 3840 if (crtc->primary->fb) {
3841 mutex_lock(&dev->struct_mutex);
3842 intel_finish_fb(crtc->primary->fb);
3843 mutex_unlock(&dev->struct_mutex);
3844 }
e6c3a2a6
CW		 3845}
3846
e615efe4
ED		 3847/* Program iCLKIP clock to the desired frequency */
3848static void lpt_program_iclkip(struct drm_crtc *crtc)
3849{
3850 struct drm_device *dev = crtc->dev;
3851 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3852 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3853 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3854 u32 temp;
3855
09153000
DV		 3856 mutex_lock(&dev_priv->dpio_lock);
3857
e615efe4
ED		 3858 /* It is necessary to ungate the pixclk gate prior to programming
3859 * the divisors, and gate it back when it is done.
3860 */
3861 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3862
3863 /* Disable SSCCTL */
3864 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3865 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3866 SBI_SSCCTL_DISABLE,
3867 SBI_ICLK);
e615efe4
ED		 3868
3869 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3870 if (clock == 20000) {
e615efe4
ED		 3871 auxdiv = 1;
3872 divsel = 0x41;
3873 phaseinc = 0x20;
3874 } else {
3875 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3876 * but the adjusted_mode->crtc_clock in in KHz. To get the
3877 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3878 * convert the virtual clock precision to KHz here for higher
3879 * precision.
3880 */
3881 u32 iclk_virtual_root_freq = 172800 * 1000;
3882 u32 iclk_pi_range = 64;
3883 u32 desired_divisor, msb_divisor_value, pi_value;
3884
12d7ceed 3885 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3886 msb_divisor_value = desired_divisor / iclk_pi_range;
3887 pi_value = desired_divisor % iclk_pi_range;
3888
3889 auxdiv = 0;
3890 divsel = msb_divisor_value - 2;
3891 phaseinc = pi_value;
3892 }
3893
3894 /* This should not happen with any sane values */
3895 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3896 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3897 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3898 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3899
3900 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3901 clock,
e615efe4
ED		 3902 auxdiv,
3903 divsel,
3904 phasedir,
3905 phaseinc);
3906
3907 /* Program SSCDIVINTPHASE6 */
988d6ee8 3908 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3909 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3910 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3911 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3912 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3913 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3914 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3915 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3916
3917 /* Program SSCAUXDIV */
988d6ee8 3918 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3919 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3920 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3921 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3922
3923 /* Enable modulator and associated divider */
988d6ee8 3924 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3925 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3926 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3927
3928 /* Wait for initialization time */
3929 udelay(24);
3930
3931 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3932
3933 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3934}
3935
275f01b2
DV		 3936static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3937 enum pipe pch_transcoder)
3938{
3939 struct drm_device *dev = crtc->base.dev;
3940 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3942
3943 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3944 I915_READ(HTOTAL(cpu_transcoder)));
3945 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3946 I915_READ(HBLANK(cpu_transcoder)));
3947 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3948 I915_READ(HSYNC(cpu_transcoder)));
3949
3950 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3951 I915_READ(VTOTAL(cpu_transcoder)));
3952 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3953 I915_READ(VBLANK(cpu_transcoder)));
3954 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3955 I915_READ(VSYNC(cpu_transcoder)));
3956 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3957 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3958}
3959
003632d9 3960static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3961{
3962 struct drm_i915_private *dev_priv = dev->dev_private;
3963 uint32_t temp;
3964
3965 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3966 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3967 return;
3968
3969 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3970 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3971
003632d9
ACO		 3972 temp &= ~FDI_BC_BIFURCATION_SELECT;
3973 if (enable)
3974 temp |= FDI_BC_BIFURCATION_SELECT;
3975
3976 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 3977 I915_WRITE(SOUTH_CHICKEN1, temp);
3978 POSTING_READ(SOUTH_CHICKEN1);
3979}
3980
3981static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3982{
3983 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 3984
3985 switch (intel_crtc->pipe) {
3986 case PIPE_A:
3987 break;
3988 case PIPE_B:
6e3c9717 3989 if (intel_crtc->config->fdi_lanes > 2)
003632d9 3990 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 3991 else
003632d9 3992 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3993
3994 break;
3995 case PIPE_C:
003632d9 3996 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3997
3998 break;
3999 default:
4000 BUG();
4001 }
4002}
4003
f67a559d
JB		 4004/*
4005 * Enable PCH resources required for PCH ports:
4006 * - PCH PLLs
4007 * - FDI training & RX/TX
4008 * - update transcoder timings
4009 * - DP transcoding bits
4010 * - transcoder
4011 */
4012static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4013{
4014 struct drm_device *dev = crtc->dev;
4015 struct drm_i915_private *dev_priv = dev->dev_private;
4016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4017 int pipe = intel_crtc->pipe;
ee7b9f93 4018 u32 reg, temp;
2c07245f 4019
ab9412ba 4020 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4021
1fbc0d78
DV		 4022 if (IS_IVYBRIDGE(dev))
4023 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4024
cd986abb
DV		 4025 /* Write the TU size bits before fdi link training, so that error
4026 * detection works. */
4027 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4028 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4029
c98e9dcf 4030 /* For PCH output, training FDI link */
674cf967 4031 dev_priv->display.fdi_link_train(crtc);
2c07245f 4032
3ad8a208
DV		 4033 /* We need to program the right clock selection before writing the pixel
4034 * mutliplier into the DPLL. */
303b81e0 4035 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4036 u32 sel;
4b645f14 4037
c98e9dcf 4038 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4039 temp |= TRANS_DPLL_ENABLE(pipe);
4040 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4041 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4042 temp |= sel;
4043 else
4044 temp &= ~sel;
c98e9dcf 4045 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4046 }
5eddb70b 4047
3ad8a208
DV		 4048 /* XXX: pch pll's can be enabled any time before we enable the PCH
4049 * transcoder, and we actually should do this to not upset any PCH
4050 * transcoder that already use the clock when we share it.
4051 *
4052 * Note that enable_shared_dpll tries to do the right thing, but
4053 * get_shared_dpll unconditionally resets the pll - we need that to have
4054 * the right LVDS enable sequence. */
85b3894f 4055 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4056
d9b6cb56
JB		 4057 /* set transcoder timing, panel must allow it */
4058 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4059 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4060
303b81e0 4061 intel_fdi_normal_train(crtc);
5e84e1a4 4062
c98e9dcf 4063 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4064 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4066 reg = TRANS_DP_CTL(pipe);
4067 temp = I915_READ(reg);
4068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4069 TRANS_DP_SYNC_MASK |
4070 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4071 temp |= (TRANS_DP_OUTPUT_ENABLE |
4072 TRANS_DP_ENH_FRAMING);
9325c9f0 4073 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4074
4075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4079
4080 switch (intel_trans_dp_port_sel(crtc)) {
4081 case PCH_DP_B:
5eddb70b 4082 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4083 break;
4084 case PCH_DP_C:
5eddb70b 4085 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4086 break;
4087 case PCH_DP_D:
5eddb70b 4088 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4089 break;
4090 default:
e95d41e1 4091 BUG();
32f9d658 4092 }
2c07245f 4093
5eddb70b 4094 I915_WRITE(reg, temp);
6be4a607 4095 }
b52eb4dc 4096
b8a4f404 4097 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4098}
4099
1507e5bd
PZ		 4100static void lpt_pch_enable(struct drm_crtc *crtc)
4101{
4102 struct drm_device *dev = crtc->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4105 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4106
ab9412ba 4107 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4108
8c52b5e8 4109 lpt_program_iclkip(crtc);
1507e5bd 4110
0540e488 4111 /* Set transcoder timing. */
275f01b2 4112 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4113
937bb610 4114 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4115}
4116
716c2e55 4117void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4118{
e2b78267 4119 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4120
4121 if (pll == NULL)
4122 return;
4123
3e369b76 4124 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4125 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4126 return;
4127 }
4128
3e369b76
ACO		 4129 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4130 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4131 WARN_ON(pll->on);
4132 WARN_ON(pll->active);
4133 }
4134
6e3c9717 4135 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4136}
4137
190f68c5
ACO		 4138struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4139 struct intel_crtc_state *crtc_state)
ee7b9f93 4140{
e2b78267 4141 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4142 struct intel_shared_dpll *pll;
e2b78267 4143 enum intel_dpll_id i;
ee7b9f93 4144
98b6bd99
DV		 4145 if (HAS_PCH_IBX(dev_priv->dev)) {
4146 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4147 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4148 pll = &dev_priv->shared_dplls[i];
98b6bd99 4149
46edb027
DV		 4150 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4151 crtc->base.base.id, pll->name);
98b6bd99 4152
8bd31e67 4153 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4154
98b6bd99
DV		 4155 goto found;
4156 }
4157
e72f9fbf
DV		 4158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4159 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4160
4161 /* Only want to check enabled timings first */
8bd31e67 4162 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4163 continue;
4164
190f68c5 4165 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4166 &pll->new_config->hw_state,
4167 sizeof(pll->new_config->hw_state)) == 0) {
4168 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4169 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4170 pll->new_config->crtc_mask,
4171 pll->active);
ee7b9f93
JB		 4172 goto found;
4173 }
4174 }
4175
4176 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4177 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4178 pll = &dev_priv->shared_dplls[i];
8bd31e67 4179 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4180 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4181 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4182 goto found;
4183 }
4184 }
4185
4186 return NULL;
4187
4188found:
8bd31e67 4189 if (pll->new_config->crtc_mask == 0)
190f68c5 4190 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4191
190f68c5 4192 crtc_state->shared_dpll = i;
46edb027
DV		 4193 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4194 pipe_name(crtc->pipe));
ee7b9f93 4195
8bd31e67 4196 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4197
ee7b9f93
JB		 4198 return pll;
4199}
4200
8bd31e67
ACO		 4201/**
4202 * intel_shared_dpll_start_config - start a new PLL staged config
4203 * @dev_priv: DRM device
4204 * @clear_pipes: mask of pipes that will have their PLLs freed
4205 *
4206 * Starts a new PLL staged config, copying the current config but
4207 * releasing the references of pipes specified in clear_pipes.
4208 */
4209static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4210 unsigned clear_pipes)
4211{
4212 struct intel_shared_dpll *pll;
4213 enum intel_dpll_id i;
4214
4215 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4216 pll = &dev_priv->shared_dplls[i];
4217
4218 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4219 GFP_KERNEL);
4220 if (!pll->new_config)
4221 goto cleanup;
4222
4223 pll->new_config->crtc_mask &= ~clear_pipes;
4224 }
4225
4226 return 0;
4227
4228cleanup:
4229 while (--i >= 0) {
4230 pll = &dev_priv->shared_dplls[i];
f354d733 4231 kfree(pll->new_config);
8bd31e67
ACO		 4232 pll->new_config = NULL;
4233 }
4234
4235 return -ENOMEM;
4236}
4237
4238static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4239{
4240 struct intel_shared_dpll *pll;
4241 enum intel_dpll_id i;
4242
4243 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4244 pll = &dev_priv->shared_dplls[i];
4245
4246 WARN_ON(pll->new_config == &pll->config);
4247
4248 pll->config = *pll->new_config;
4249 kfree(pll->new_config);
4250 pll->new_config = NULL;
4251 }
4252}
4253
4254static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4255{
4256 struct intel_shared_dpll *pll;
4257 enum intel_dpll_id i;
4258
4259 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4260 pll = &dev_priv->shared_dplls[i];
4261
4262 WARN_ON(pll->new_config == &pll->config);
4263
4264 kfree(pll->new_config);
4265 pll->new_config = NULL;
4266 }
4267}
4268
a1520318 4269static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4270{
4271 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4272 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4273 u32 temp;
4274
4275 temp = I915_READ(dslreg);
4276 udelay(500);
4277 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4278 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4279 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4280 }
4281}
4282
bd2e244f
JB		 4283static void skylake_pfit_enable(struct intel_crtc *crtc)
4284{
4285 struct drm_device *dev = crtc->base.dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 int pipe = crtc->pipe;
4288
6e3c9717 4289 if (crtc->config->pch_pfit.enabled) {
bd2e244f 4290 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
6e3c9717
ACO		 4291 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4292 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
bd2e244f
JB		 4293 }
4294}
4295
b074cec8
JB		 4296static void ironlake_pfit_enable(struct intel_crtc *crtc)
4297{
4298 struct drm_device *dev = crtc->base.dev;
4299 struct drm_i915_private *dev_priv = dev->dev_private;
4300 int pipe = crtc->pipe;
4301
6e3c9717 4302 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4303 /* Force use of hard-coded filter coefficients
4304 * as some pre-programmed values are broken,
4305 * e.g. x201.
4306 */
4307 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4308 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4309 PF_PIPE_SEL_IVB(pipe));
4310 else
4311 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4312 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4313 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4314 }
4315}
4316
4a3b8769 4317static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4318{
4319 struct drm_device *dev = crtc->dev;
4320 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4321 struct drm_plane *plane;
bb53d4ae
VS		 4322 struct intel_plane *intel_plane;
4323
af2b653b
MR		 4324 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4325 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4326 if (intel_plane->pipe == pipe)
4327 intel_plane_restore(&intel_plane->base);
af2b653b 4328 }
bb53d4ae
VS		 4329}
4330
0d703d4e
MR		 4331/*
4332 * Disable a plane internally without actually modifying the plane's state.
4333 * This will allow us to easily restore the plane later by just reprogramming
4334 * its state.
4335 */
4336static void disable_plane_internal(struct drm_plane *plane)
4337{
4338 struct intel_plane *intel_plane = to_intel_plane(plane);
4339 struct drm_plane_state *state =
4340 plane->funcs->atomic_duplicate_state(plane);
4341 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4342
4343 intel_state->visible = false;
4344 intel_plane->commit_plane(plane, intel_state);
4345
4346 intel_plane_destroy_state(plane, state);
4347}
4348
4a3b8769 4349static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4350{
4351 struct drm_device *dev = crtc->dev;
4352 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4353 struct drm_plane *plane;
bb53d4ae
VS		 4354 struct intel_plane *intel_plane;
4355
af2b653b
MR		 4356 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4357 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4358 if (plane->fb && intel_plane->pipe == pipe)
4359 disable_plane_internal(plane);
af2b653b 4360 }
bb53d4ae
VS		 4361}
4362
20bc8673 4363void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4364{
cea165c3
VS		 4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4367
6e3c9717 4368 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4369 return;
4370
cea165c3
VS		 4371 /* We can only enable IPS after we enable a plane and wait for a vblank */
4372 intel_wait_for_vblank(dev, crtc->pipe);
4373
d77e4531 4374 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4375 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4376 mutex_lock(&dev_priv->rps.hw_lock);
4377 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4378 mutex_unlock(&dev_priv->rps.hw_lock);
4379 /* Quoting Art Runyan: "its not safe to expect any particular
4380 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4381 * mailbox." Moreover, the mailbox may return a bogus state,
4382 * so we need to just enable it and continue on.
2a114cc1
BW		 4383 */
4384 } else {
4385 I915_WRITE(IPS_CTL, IPS_ENABLE);
4386 /* The bit only becomes 1 in the next vblank, so this wait here
4387 * is essentially intel_wait_for_vblank. If we don't have this
4388 * and don't wait for vblanks until the end of crtc_enable, then
4389 * the HW state readout code will complain that the expected
4390 * IPS_CTL value is not the one we read. */
4391 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4392 DRM_ERROR("Timed out waiting for IPS enable\n");
4393 }
d77e4531
PZ		 4394}
4395
20bc8673 4396void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4397{
4398 struct drm_device *dev = crtc->base.dev;
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400
6e3c9717 4401 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4402 return;
4403
4404 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4405 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4406 mutex_lock(&dev_priv->rps.hw_lock);
4407 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4408 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4409 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4410 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4411 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4412 } else {
2a114cc1 4413 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4414 POSTING_READ(IPS_CTL);
4415 }
d77e4531
PZ		 4416
4417 /* We need to wait for a vblank before we can disable the plane. */
4418 intel_wait_for_vblank(dev, crtc->pipe);
4419}
4420
4421/** Loads the palette/gamma unit for the CRTC with the prepared values */
4422static void intel_crtc_load_lut(struct drm_crtc *crtc)
4423{
4424 struct drm_device *dev = crtc->dev;
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4427 enum pipe pipe = intel_crtc->pipe;
4428 int palreg = PALETTE(pipe);
4429 int i;
4430 bool reenable_ips = false;
4431
4432 /* The clocks have to be on to load the palette. */
83d65738 4433 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4434 return;
4435
4436 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4437 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4438 assert_dsi_pll_enabled(dev_priv);
4439 else
4440 assert_pll_enabled(dev_priv, pipe);
4441 }
4442
4443 /* use legacy palette for Ironlake */
7a1db49a 4444 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4445 palreg = LGC_PALETTE(pipe);
4446
4447 /* Workaround : Do not read or write the pipe palette/gamma data while
4448 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4449 */
6e3c9717 4450 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4451 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4452 GAMMA_MODE_MODE_SPLIT)) {
4453 hsw_disable_ips(intel_crtc);
4454 reenable_ips = true;
4455 }
4456
4457 for (i = 0; i < 256; i++) {
4458 I915_WRITE(palreg + 4 * i,
4459 (intel_crtc->lut_r[i] << 16) |
4460 (intel_crtc->lut_g[i] << 8) |
4461 intel_crtc->lut_b[i]);
4462 }
4463
4464 if (reenable_ips)
4465 hsw_enable_ips(intel_crtc);
4466}
4467
d3eedb1a
VS		 4468static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4469{
4470 if (!enable && intel_crtc->overlay) {
4471 struct drm_device *dev = intel_crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473
4474 mutex_lock(&dev->struct_mutex);
4475 dev_priv->mm.interruptible = false;
4476 (void) intel_overlay_switch_off(intel_crtc->overlay);
4477 dev_priv->mm.interruptible = true;
4478 mutex_unlock(&dev->struct_mutex);
4479 }
4480
4481 /* Let userspace switch the overlay on again. In most cases userspace
4482 * has to recompute where to put it anyway.
4483 */
4484}
4485
d3eedb1a 4486static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4487{
4488 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4490 int pipe = intel_crtc->pipe;
a5c4d7bc 4491
fdd508a6 4492 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4493 intel_enable_sprite_planes(crtc);
a5c4d7bc 4494 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4495 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4496
4497 hsw_enable_ips(intel_crtc);
4498
4499 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4500 intel_fbc_update(dev);
a5c4d7bc 4501 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4502
4503 /*
4504 * FIXME: Once we grow proper nuclear flip support out of this we need
4505 * to compute the mask of flip planes precisely. For the time being
4506 * consider this a flip from a NULL plane.
4507 */
4508 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4509}
4510
d3eedb1a 4511static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4512{
4513 struct drm_device *dev = crtc->dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4516 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4517
4518 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4519
e35fef21 4520 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4521 intel_fbc_disable(dev);
a5c4d7bc
VS		 4522
4523 hsw_disable_ips(intel_crtc);
4524
d3eedb1a 4525 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4526 intel_crtc_update_cursor(crtc, false);
4a3b8769 4527 intel_disable_sprite_planes(crtc);
fdd508a6 4528 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4529
f99d7069
DV		 4530 /*
4531 * FIXME: Once we grow proper nuclear flip support out of this we need
4532 * to compute the mask of flip planes precisely. For the time being
4533 * consider this a flip to a NULL plane.
4534 */
4535 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4536}
4537
f67a559d
JB		 4538static void ironlake_crtc_enable(struct drm_crtc *crtc)
4539{
4540 struct drm_device *dev = crtc->dev;
4541 struct drm_i915_private *dev_priv = dev->dev_private;
4542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4543 struct intel_encoder *encoder;
f67a559d 4544 int pipe = intel_crtc->pipe;
f67a559d 4545
83d65738 4546 WARN_ON(!crtc->state->enable);
08a48469 4547
f67a559d
JB		 4548 if (intel_crtc->active)
4549 return;
4550
6e3c9717 4551 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4552 intel_prepare_shared_dpll(intel_crtc);
4553
6e3c9717 4554 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4555 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4556
4557 intel_set_pipe_timings(intel_crtc);
4558
6e3c9717 4559 if (intel_crtc->config->has_pch_encoder) {
29407aab 4560 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4561 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4562 }
4563
4564 ironlake_set_pipeconf(crtc);
4565
f67a559d 4566 intel_crtc->active = true;
8664281b 4567
a72e4c9f
DV		 4568 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4569 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4570
f6736a1a 4571 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4572 if (encoder->pre_enable)
4573 encoder->pre_enable(encoder);
f67a559d 4574
6e3c9717 4575 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4576 /* Note: FDI PLL enabling _must_ be done before we enable the
4577 * cpu pipes, hence this is separate from all the other fdi/pch
4578 * enabling. */
88cefb6c 4579 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4580 } else {
4581 assert_fdi_tx_disabled(dev_priv, pipe);
4582 assert_fdi_rx_disabled(dev_priv, pipe);
4583 }
f67a559d 4584
b074cec8 4585 ironlake_pfit_enable(intel_crtc);
f67a559d 4586
9c54c0dd
JB		 4587 /*
4588 * On ILK+ LUT must be loaded before the pipe is running but with
4589 * clocks enabled
4590 */
4591 intel_crtc_load_lut(crtc);
4592
f37fcc2a 4593 intel_update_watermarks(crtc);
e1fdc473 4594 intel_enable_pipe(intel_crtc);
f67a559d 4595
6e3c9717 4596 if (intel_crtc->config->has_pch_encoder)
f67a559d 4597 ironlake_pch_enable(crtc);
c98e9dcf 4598
f9b61ff6
DV		 4599 assert_vblank_disabled(crtc);
4600 drm_crtc_vblank_on(crtc);
4601
fa5c73b1
DV		 4602 for_each_encoder_on_crtc(dev, crtc, encoder)
4603 encoder->enable(encoder);
61b77ddd
DV		 4604
4605 if (HAS_PCH_CPT(dev))
a1520318 4606 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4607
d3eedb1a 4608 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4609}
4610
42db64ef
PZ		 4611/* IPS only exists on ULT machines and is tied to pipe A. */
4612static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4613{
f5adf94e 4614 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4615}
4616
e4916946
PZ		 4617/*
4618 * This implements the workaround described in the "notes" section of the mode
4619 * set sequence documentation. When going from no pipes or single pipe to
4620 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4621 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4622 */
4623static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4624{
4625 struct drm_device *dev = crtc->base.dev;
4626 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4627
4628 /* We want to get the other_active_crtc only if there's only 1 other
4629 * active crtc. */
d3fcc808 4630 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4631 if (!crtc_it->active || crtc_it == crtc)
4632 continue;
4633
4634 if (other_active_crtc)
4635 return;
4636
4637 other_active_crtc = crtc_it;
4638 }
4639 if (!other_active_crtc)
4640 return;
4641
4642 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4643 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4644}
4645
4f771f10
PZ		 4646static void haswell_crtc_enable(struct drm_crtc *crtc)
4647{
4648 struct drm_device *dev = crtc->dev;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4651 struct intel_encoder *encoder;
4652 int pipe = intel_crtc->pipe;
4f771f10 4653
83d65738 4654 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4655
4656 if (intel_crtc->active)
4657 return;
4658
df8ad70c
DV		 4659 if (intel_crtc_to_shared_dpll(intel_crtc))
4660 intel_enable_shared_dpll(intel_crtc);
4661
6e3c9717 4662 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4663 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4664
4665 intel_set_pipe_timings(intel_crtc);
4666
6e3c9717
ACO		 4667 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4668 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4669 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4670 }
4671
6e3c9717 4672 if (intel_crtc->config->has_pch_encoder) {
229fca97 4673 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4674 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4675 }
4676
4677 haswell_set_pipeconf(crtc);
4678
4679 intel_set_pipe_csc(crtc);
4680
4f771f10 4681 intel_crtc->active = true;
8664281b 4682
a72e4c9f 4683 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4684 for_each_encoder_on_crtc(dev, crtc, encoder)
4685 if (encoder->pre_enable)
4686 encoder->pre_enable(encoder);
4687
6e3c9717 4688 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4689 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4690 true);
4fe9467d
ID		 4691 dev_priv->display.fdi_link_train(crtc);
4692 }
4693
1f544388 4694 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4695
bd2e244f
JB		 4696 if (IS_SKYLAKE(dev))
4697 skylake_pfit_enable(intel_crtc);
4698 else
4699 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4700
4701 /*
4702 * On ILK+ LUT must be loaded before the pipe is running but with
4703 * clocks enabled
4704 */
4705 intel_crtc_load_lut(crtc);
4706
1f544388 4707 intel_ddi_set_pipe_settings(crtc);
8228c251 4708 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4709
f37fcc2a 4710 intel_update_watermarks(crtc);
e1fdc473 4711 intel_enable_pipe(intel_crtc);
42db64ef 4712
6e3c9717 4713 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4714 lpt_pch_enable(crtc);
4f771f10 4715
6e3c9717 4716 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4717 intel_ddi_set_vc_payload_alloc(crtc, true);
4718
f9b61ff6
DV		 4719 assert_vblank_disabled(crtc);
4720 drm_crtc_vblank_on(crtc);
4721
8807e55b 4722 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4723 encoder->enable(encoder);
8807e55b
JN		 4724 intel_opregion_notify_encoder(encoder, true);
4725 }
4f771f10 4726
e4916946
PZ		 4727 /* If we change the relative order between pipe/planes enabling, we need
4728 * to change the workaround. */
4729 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4730 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4731}
4732
bd2e244f
JB		 4733static void skylake_pfit_disable(struct intel_crtc *crtc)
4734{
4735 struct drm_device *dev = crtc->base.dev;
4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737 int pipe = crtc->pipe;
4738
4739 /* To avoid upsetting the power well on haswell only disable the pfit if
4740 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4741 if (crtc->config->pch_pfit.enabled) {
bd2e244f
JB		 4742 I915_WRITE(PS_CTL(pipe), 0);
4743 I915_WRITE(PS_WIN_POS(pipe), 0);
4744 I915_WRITE(PS_WIN_SZ(pipe), 0);
4745 }
4746}
4747
3f8dce3a
DV		 4748static void ironlake_pfit_disable(struct intel_crtc *crtc)
4749{
4750 struct drm_device *dev = crtc->base.dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 int pipe = crtc->pipe;
4753
4754 /* To avoid upsetting the power well on haswell only disable the pfit if
4755 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4756 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4757 I915_WRITE(PF_CTL(pipe), 0);
4758 I915_WRITE(PF_WIN_POS(pipe), 0);
4759 I915_WRITE(PF_WIN_SZ(pipe), 0);
4760 }
4761}
4762
6be4a607
JB		 4763static void ironlake_crtc_disable(struct drm_crtc *crtc)
4764{
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4768 struct intel_encoder *encoder;
6be4a607 4769 int pipe = intel_crtc->pipe;
5eddb70b 4770 u32 reg, temp;
b52eb4dc 4771
f7abfe8b
CW		 4772 if (!intel_crtc->active)
4773 return;
4774
d3eedb1a 4775 intel_crtc_disable_planes(crtc);
a5c4d7bc 4776
ea9d758d
DV		 4777 for_each_encoder_on_crtc(dev, crtc, encoder)
4778 encoder->disable(encoder);
4779
f9b61ff6
DV		 4780 drm_crtc_vblank_off(crtc);
4781 assert_vblank_disabled(crtc);
4782
6e3c9717 4783 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4784 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4785
575f7ab7 4786 intel_disable_pipe(intel_crtc);
32f9d658 4787
3f8dce3a 4788 ironlake_pfit_disable(intel_crtc);
2c07245f 4789
bf49ec8c
DV		 4790 for_each_encoder_on_crtc(dev, crtc, encoder)
4791 if (encoder->post_disable)
4792 encoder->post_disable(encoder);
2c07245f 4793
6e3c9717 4794 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4795 ironlake_fdi_disable(crtc);
913d8d11 4796
d925c59a 4797 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4798
d925c59a
DV		 4799 if (HAS_PCH_CPT(dev)) {
4800 /* disable TRANS_DP_CTL */
4801 reg = TRANS_DP_CTL(pipe);
4802 temp = I915_READ(reg);
4803 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4804 TRANS_DP_PORT_SEL_MASK);
4805 temp |= TRANS_DP_PORT_SEL_NONE;
4806 I915_WRITE(reg, temp);
4807
4808 /* disable DPLL_SEL */
4809 temp = I915_READ(PCH_DPLL_SEL);
11887397 4810 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4811 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4812 }
e3421a18 4813
d925c59a 4814 /* disable PCH DPLL */
e72f9fbf 4815 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4816
d925c59a
DV		 4817 ironlake_fdi_pll_disable(intel_crtc);
4818 }
6b383a7f 4819
f7abfe8b 4820 intel_crtc->active = false;
46ba614c 4821 intel_update_watermarks(crtc);
d1ebd816
BW		 4822
4823 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4824 intel_fbc_update(dev);
d1ebd816 4825 mutex_unlock(&dev->struct_mutex);
6be4a607 4826}
1b3c7a47 4827
4f771f10 4828static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4829{
4f771f10
PZ		 4830 struct drm_device *dev = crtc->dev;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 4833 struct intel_encoder *encoder;
6e3c9717 4834 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 4835
4f771f10
PZ		 4836 if (!intel_crtc->active)
4837 return;
4838
d3eedb1a 4839 intel_crtc_disable_planes(crtc);
dda9a66a 4840
8807e55b
JN		 4841 for_each_encoder_on_crtc(dev, crtc, encoder) {
4842 intel_opregion_notify_encoder(encoder, false);
4f771f10 4843 encoder->disable(encoder);
8807e55b 4844 }
4f771f10 4845
f9b61ff6
DV		 4846 drm_crtc_vblank_off(crtc);
4847 assert_vblank_disabled(crtc);
4848
6e3c9717 4849 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 4850 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4851 false);
575f7ab7 4852 intel_disable_pipe(intel_crtc);
4f771f10 4853
6e3c9717 4854 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 4855 intel_ddi_set_vc_payload_alloc(crtc, false);
4856
ad80a810 4857 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 4858
bd2e244f
JB		 4859 if (IS_SKYLAKE(dev))
4860 skylake_pfit_disable(intel_crtc);
4861 else
4862 ironlake_pfit_disable(intel_crtc);
4f771f10 4863
1f544388 4864 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 4865
6e3c9717 4866 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 4867 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 4868 intel_ddi_fdi_disable(crtc);
83616634 4869 }
4f771f10 4870
97b040aa
ID		 4871 for_each_encoder_on_crtc(dev, crtc, encoder)
4872 if (encoder->post_disable)
4873 encoder->post_disable(encoder);
4874
4f771f10 4875 intel_crtc->active = false;
46ba614c 4876 intel_update_watermarks(crtc);
4f771f10
PZ		 4877
4878 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4879 intel_fbc_update(dev);
4f771f10 4880 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 4881
4882 if (intel_crtc_to_shared_dpll(intel_crtc))
4883 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 4884}
4885
ee7b9f93
JB		 4886static void ironlake_crtc_off(struct drm_crtc *crtc)
4887{
4888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 4889 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 4890}
4891
6441ab5f 4892
2dd24552
JB		 4893static void i9xx_pfit_enable(struct intel_crtc *crtc)
4894{
4895 struct drm_device *dev = crtc->base.dev;
4896 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4897 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 4898
681a8504 4899 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 4900 return;
4901
2dd24552 4902 /*
c0b03411
DV		 4903 * The panel fitter should only be adjusted whilst the pipe is disabled,
4904 * according to register description and PRM.
2dd24552 4905 */
c0b03411
DV		 4906 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4907 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 4908
b074cec8
JB		 4909 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4910 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 4911
4912 /* Border color in case we don't scale up to the full screen. Black by
4913 * default, change to something else for debugging. */
4914 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 4915}
4916
d05410f9
DA		 4917static enum intel_display_power_domain port_to_power_domain(enum port port)
4918{
4919 switch (port) {
4920 case PORT_A:
4921 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4922 case PORT_B:
4923 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4924 case PORT_C:
4925 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4926 case PORT_D:
4927 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4928 default:
4929 WARN_ON_ONCE(1);
4930 return POWER_DOMAIN_PORT_OTHER;
4931 }
4932}
4933
77d22dca
ID		 4934#define for_each_power_domain(domain, mask) \
4935 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4936 if ((1 << (domain)) & (mask))
4937
319be8ae
ID		 4938enum intel_display_power_domain
4939intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4940{
4941 struct drm_device *dev = intel_encoder->base.dev;
4942 struct intel_digital_port *intel_dig_port;
4943
4944 switch (intel_encoder->type) {
4945 case INTEL_OUTPUT_UNKNOWN:
4946 /* Only DDI platforms should ever use this output type */
4947 WARN_ON_ONCE(!HAS_DDI(dev));
4948 case INTEL_OUTPUT_DISPLAYPORT:
4949 case INTEL_OUTPUT_HDMI:
4950 case INTEL_OUTPUT_EDP:
4951 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 4952 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 4953 case INTEL_OUTPUT_DP_MST:
4954 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4955 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 4956 case INTEL_OUTPUT_ANALOG:
4957 return POWER_DOMAIN_PORT_CRT;
4958 case INTEL_OUTPUT_DSI:
4959 return POWER_DOMAIN_PORT_DSI;
4960 default:
4961 return POWER_DOMAIN_PORT_OTHER;
4962 }
4963}
4964
4965static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 4966{
319be8ae
ID		 4967 struct drm_device *dev = crtc->dev;
4968 struct intel_encoder *intel_encoder;
4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4970 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 4971 unsigned long mask;
4972 enum transcoder transcoder;
4973
4974 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4975
4976 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4977 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 4978 if (intel_crtc->config->pch_pfit.enabled ||
4979 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 4980 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4981
319be8ae
ID		 4982 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4983 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4984
77d22dca
ID		 4985 return mask;
4986}
4987
679dacd4 4988static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 4989{
679dacd4 4990 struct drm_device *dev = state->dev;
77d22dca
ID		 4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4993 struct intel_crtc *crtc;
4994
4995 /*
4996 * First get all needed power domains, then put all unneeded, to avoid
4997 * any unnecessary toggling of the power wells.
4998 */
d3fcc808 4999 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5000 enum intel_display_power_domain domain;
5001
83d65738 5002 if (!crtc->base.state->enable)
77d22dca
ID		 5003 continue;
5004
319be8ae 5005 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5006
5007 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5008 intel_display_power_get(dev_priv, domain);
5009 }
5010
50f6e502 5011 if (dev_priv->display.modeset_global_resources)
679dacd4 5012 dev_priv->display.modeset_global_resources(state);
50f6e502 5013
d3fcc808 5014 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5015 enum intel_display_power_domain domain;
5016
5017 for_each_power_domain(domain, crtc->enabled_power_domains)
5018 intel_display_power_put(dev_priv, domain);
5019
5020 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5021 }
5022
5023 intel_display_set_init_power(dev_priv, false);
5024}
5025
dfcab17e 5026/* returns HPLL frequency in kHz */
f8bf63fd 5027static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5028{
586f49dc 5029 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5030
586f49dc
JB		 5031 /* Obtain SKU information */
5032 mutex_lock(&dev_priv->dpio_lock);
5033 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5034 CCK_FUSE_HPLL_FREQ_MASK;
5035 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5036
dfcab17e 5037 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5038}
5039
f8bf63fd
VS		 5040static void vlv_update_cdclk(struct drm_device *dev)
5041{
5042 struct drm_i915_private *dev_priv = dev->dev_private;
5043
5044 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5045 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
f8bf63fd
VS		 5046 dev_priv->vlv_cdclk_freq);
5047
5048 /*
5049 * Program the gmbus_freq based on the cdclk frequency.
5050 * BSpec erroneously claims we should aim for 4MHz, but
5051 * in fact 1MHz is the correct frequency.
5052 */
6be1e3d3 5053 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
f8bf63fd
VS		 5054}
5055
30a970c6
JB		 5056/* Adjust CDclk dividers to allow high res or save power if possible */
5057static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5058{
5059 struct drm_i915_private *dev_priv = dev->dev_private;
5060 u32 val, cmd;
5061
d197b7d3 5062 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
d60c4473 5063
dfcab17e 5064 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5065 cmd = 2;
dfcab17e 5066 else if (cdclk == 266667)
30a970c6
JB		 5067 cmd = 1;
5068 else
5069 cmd = 0;
5070
5071 mutex_lock(&dev_priv->rps.hw_lock);
5072 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5073 val &= ~DSPFREQGUAR_MASK;
5074 val |= (cmd << DSPFREQGUAR_SHIFT);
5075 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5076 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5077 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5078 50)) {
5079 DRM_ERROR("timed out waiting for CDclk change\n");
5080 }
5081 mutex_unlock(&dev_priv->rps.hw_lock);
5082
dfcab17e 5083 if (cdclk == 400000) {
6bcda4f0 5084 u32 divider;
30a970c6 5085
6bcda4f0 5086 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5087
5088 mutex_lock(&dev_priv->dpio_lock);
5089 /* adjust cdclk divider */
5090 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5091 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5092 val |= divider;
5093 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5094
5095 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5096 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5097 50))
5098 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5099 mutex_unlock(&dev_priv->dpio_lock);
5100 }
5101
5102 mutex_lock(&dev_priv->dpio_lock);
5103 /* adjust self-refresh exit latency value */
5104 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5105 val &= ~0x7f;
5106
5107 /*
5108 * For high bandwidth configs, we set a higher latency in the bunit
5109 * so that the core display fetch happens in time to avoid underruns.
5110 */
dfcab17e 5111 if (cdclk == 400000)
30a970c6
JB		 5112 val |= 4500 / 250; /* 4.5 usec */
5113 else
5114 val |= 3000 / 250; /* 3.0 usec */
5115 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5116 mutex_unlock(&dev_priv->dpio_lock);
5117
f8bf63fd 5118 vlv_update_cdclk(dev);
30a970c6
JB		 5119}
5120
383c5a6a
VS		 5121static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5122{
5123 struct drm_i915_private *dev_priv = dev->dev_private;
5124 u32 val, cmd;
5125
5126 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5127
5128 switch (cdclk) {
383c5a6a
VS		 5129 case 333333:
5130 case 320000:
383c5a6a 5131 case 266667:
383c5a6a 5132 case 200000:
383c5a6a
VS		 5133 break;
5134 default:
5f77eeb0 5135 MISSING_CASE(cdclk);
383c5a6a
VS		 5136 return;
5137 }
5138
9d0d3fda
VS		 5139 /*
5140 * Specs are full of misinformation, but testing on actual
5141 * hardware has shown that we just need to write the desired
5142 * CCK divider into the Punit register.
5143 */
5144 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5145
383c5a6a
VS		 5146 mutex_lock(&dev_priv->rps.hw_lock);
5147 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5148 val &= ~DSPFREQGUAR_MASK_CHV;
5149 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5150 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5151 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5152 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5153 50)) {
5154 DRM_ERROR("timed out waiting for CDclk change\n");
5155 }
5156 mutex_unlock(&dev_priv->rps.hw_lock);
5157
5158 vlv_update_cdclk(dev);
5159}
5160
30a970c6
JB		 5161static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5162 int max_pixclk)
5163{
6bcda4f0 5164 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5165 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5166
30a970c6
JB		 5167 /*
5168 * Really only a few cases to deal with, as only 4 CDclks are supported:
5169 * 200MHz
5170 * 267MHz
29dc7ef3 5171 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5172 * 400MHz (VLV only)
5173 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5174 * of the lower bin and adjust if needed.
e37c67a1
VS		 5175 *
5176 * We seem to get an unstable or solid color picture at 200MHz.
5177 * Not sure what's wrong. For now use 200MHz only when all pipes
5178 * are off.
30a970c6 5179 */
6cca3195
VS		 5180 if (!IS_CHERRYVIEW(dev_priv) &&
5181 max_pixclk > freq_320*limit/100)
dfcab17e 5182 return 400000;
6cca3195 5183 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5184 return freq_320;
e37c67a1 5185 else if (max_pixclk > 0)
dfcab17e 5186 return 266667;
e37c67a1
VS		 5187 else
5188 return 200000;
30a970c6
JB		 5189}
5190
2f2d7aa1 5191/* compute the max pixel clock for new configuration */
304603f4 5192static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5193{
304603f4 5194 struct drm_device *dev = state->dev;
30a970c6 5195 struct intel_crtc *intel_crtc;
304603f4 5196 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5197 int max_pixclk = 0;
5198
d3fcc808 5199 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5200 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5201 if (IS_ERR(crtc_state))
5202 return PTR_ERR(crtc_state);
5203
5204 if (!crtc_state->base.enable)
5205 continue;
5206
5207 max_pixclk = max(max_pixclk,
5208 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5209 }
5210
5211 return max_pixclk;
5212}
5213
304603f4 5214static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5215 unsigned *prepare_pipes)
30a970c6 5216{
304603f4 5217 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5218 struct intel_crtc *intel_crtc;
304603f4
ACO		 5219 int max_pixclk = intel_mode_max_pixclk(state);
5220
5221 if (max_pixclk < 0)
5222 return max_pixclk;
30a970c6 5223
d60c4473
ID		 5224 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5225 dev_priv->vlv_cdclk_freq)
304603f4 5226 return 0;
30a970c6 5227
2f2d7aa1 5228 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5229 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5230 if (intel_crtc->base.state->enable)
30a970c6 5231 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5232
5233 return 0;
30a970c6
JB		 5234}
5235
1e69cd74
VS		 5236static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5237{
5238 unsigned int credits, default_credits;
5239
5240 if (IS_CHERRYVIEW(dev_priv))
5241 default_credits = PFI_CREDIT(12);
5242 else
5243 default_credits = PFI_CREDIT(8);
5244
5245 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5246 /* CHV suggested value is 31 or 63 */
5247 if (IS_CHERRYVIEW(dev_priv))
5248 credits = PFI_CREDIT_31;
5249 else
5250 credits = PFI_CREDIT(15);
5251 } else {
5252 credits = default_credits;
5253 }
5254
5255 /*
5256 * WA - write default credits before re-programming
5257 * FIXME: should we also set the resend bit here?
5258 */
5259 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5260 default_credits);
5261
5262 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5263 credits | PFI_CREDIT_RESEND);
5264
5265 /*
5266 * FIXME is this guaranteed to clear
5267 * immediately or should we poll for it?
5268 */
5269 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5270}
5271
679dacd4 5272static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5273{
679dacd4 5274 struct drm_device *dev = state->dev;
30a970c6 5275 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5276 int max_pixclk = intel_mode_max_pixclk(state);
5277 int req_cdclk;
5278
5279 /* The only reason this can fail is if we fail to add the crtc_state
5280 * to the atomic state. But that can't happen since the call to
5281 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5282 * can't have failed otherwise the mode set would be aborted) added all
5283 * the states already. */
5284 if (WARN_ON(max_pixclk < 0))
5285 return;
5286
5287 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5288
383c5a6a 5289 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
738c05c0
ID		 5290 /*
5291 * FIXME: We can end up here with all power domains off, yet
5292 * with a CDCLK frequency other than the minimum. To account
5293 * for this take the PIPE-A power domain, which covers the HW
5294 * blocks needed for the following programming. This can be
5295 * removed once it's guaranteed that we get here either with
5296 * the minimum CDCLK set, or the required power domains
5297 * enabled.
5298 */
5299 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5300
383c5a6a
VS		 5301 if (IS_CHERRYVIEW(dev))
5302 cherryview_set_cdclk(dev, req_cdclk);
5303 else
5304 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5305
1e69cd74
VS		 5306 vlv_program_pfi_credits(dev_priv);
5307
738c05c0 5308 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5309 }
30a970c6
JB		 5310}
5311
89b667f8
JB		 5312static void valleyview_crtc_enable(struct drm_crtc *crtc)
5313{
5314 struct drm_device *dev = crtc->dev;
a72e4c9f 5315 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5317 struct intel_encoder *encoder;
5318 int pipe = intel_crtc->pipe;
23538ef1 5319 bool is_dsi;
89b667f8 5320
83d65738 5321 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5322
5323 if (intel_crtc->active)
5324 return;
5325
409ee761 5326 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5327
1ae0d137
VS		 5328 if (!is_dsi) {
5329 if (IS_CHERRYVIEW(dev))
6e3c9717 5330 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5331 else
6e3c9717 5332 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5333 }
5b18e57c 5334
6e3c9717 5335 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5336 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5337
5338 intel_set_pipe_timings(intel_crtc);
5339
c14b0485
VS		 5340 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342
5343 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5344 I915_WRITE(CHV_CANVAS(pipe), 0);
5345 }
5346
5b18e57c
DV		 5347 i9xx_set_pipeconf(intel_crtc);
5348
89b667f8 5349 intel_crtc->active = true;
89b667f8 5350
a72e4c9f 5351 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5352
89b667f8
JB		 5353 for_each_encoder_on_crtc(dev, crtc, encoder)
5354 if (encoder->pre_pll_enable)
5355 encoder->pre_pll_enable(encoder);
5356
9d556c99
CML		 5357 if (!is_dsi) {
5358 if (IS_CHERRYVIEW(dev))
6e3c9717 5359 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5360 else
6e3c9717 5361 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5362 }
89b667f8
JB		 5363
5364 for_each_encoder_on_crtc(dev, crtc, encoder)
5365 if (encoder->pre_enable)
5366 encoder->pre_enable(encoder);
5367
2dd24552
JB		 5368 i9xx_pfit_enable(intel_crtc);
5369
63cbb074
VS		 5370 intel_crtc_load_lut(crtc);
5371
f37fcc2a 5372 intel_update_watermarks(crtc);
e1fdc473 5373 intel_enable_pipe(intel_crtc);
be6a6f8e 5374
4b3a9526
VS		 5375 assert_vblank_disabled(crtc);
5376 drm_crtc_vblank_on(crtc);
5377
f9b61ff6
DV		 5378 for_each_encoder_on_crtc(dev, crtc, encoder)
5379 encoder->enable(encoder);
5380
9ab0460b 5381 intel_crtc_enable_planes(crtc);
d40d9187 5382
56b80e1f 5383 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5384 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5385}
5386
f13c2ef3
DV		 5387static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5388{
5389 struct drm_device *dev = crtc->base.dev;
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391
6e3c9717
ACO		 5392 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5393 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5394}
5395
0b8765c6 5396static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5397{
5398 struct drm_device *dev = crtc->dev;
a72e4c9f 5399 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5401 struct intel_encoder *encoder;
79e53945 5402 int pipe = intel_crtc->pipe;
79e53945 5403
83d65738 5404 WARN_ON(!crtc->state->enable);
08a48469 5405
f7abfe8b
CW		 5406 if (intel_crtc->active)
5407 return;
5408
f13c2ef3
DV		 5409 i9xx_set_pll_dividers(intel_crtc);
5410
6e3c9717 5411 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5412 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5413
5414 intel_set_pipe_timings(intel_crtc);
5415
5b18e57c
DV		 5416 i9xx_set_pipeconf(intel_crtc);
5417
f7abfe8b 5418 intel_crtc->active = true;
6b383a7f 5419
4a3436e8 5420 if (!IS_GEN2(dev))
a72e4c9f 5421 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5422
9d6d9f19
MK		 5423 for_each_encoder_on_crtc(dev, crtc, encoder)
5424 if (encoder->pre_enable)
5425 encoder->pre_enable(encoder);
5426
f6736a1a
DV		 5427 i9xx_enable_pll(intel_crtc);
5428
2dd24552
JB		 5429 i9xx_pfit_enable(intel_crtc);
5430
63cbb074
VS		 5431 intel_crtc_load_lut(crtc);
5432
f37fcc2a 5433 intel_update_watermarks(crtc);
e1fdc473 5434 intel_enable_pipe(intel_crtc);
be6a6f8e 5435
4b3a9526
VS		 5436 assert_vblank_disabled(crtc);
5437 drm_crtc_vblank_on(crtc);
5438
f9b61ff6
DV		 5439 for_each_encoder_on_crtc(dev, crtc, encoder)
5440 encoder->enable(encoder);
5441
9ab0460b 5442 intel_crtc_enable_planes(crtc);
d40d9187 5443
4a3436e8
VS		 5444 /*
5445 * Gen2 reports pipe underruns whenever all planes are disabled.
5446 * So don't enable underrun reporting before at least some planes
5447 * are enabled.
5448 * FIXME: Need to fix the logic to work when we turn off all planes
5449 * but leave the pipe running.
5450 */
5451 if (IS_GEN2(dev))
a72e4c9f 5452 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5453
56b80e1f 5454 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5455 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5456}
79e53945 5457
87476d63
DV		 5458static void i9xx_pfit_disable(struct intel_crtc *crtc)
5459{
5460 struct drm_device *dev = crtc->base.dev;
5461 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5462
6e3c9717 5463 if (!crtc->config->gmch_pfit.control)
328d8e82 5464 return;
87476d63 5465
328d8e82 5466 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5467
328d8e82
DV		 5468 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5469 I915_READ(PFIT_CONTROL));
5470 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5471}
5472
0b8765c6
JB		 5473static void i9xx_crtc_disable(struct drm_crtc *crtc)
5474{
5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5478 struct intel_encoder *encoder;
0b8765c6 5479 int pipe = intel_crtc->pipe;
ef9c3aee 5480
f7abfe8b
CW		 5481 if (!intel_crtc->active)
5482 return;
5483
4a3436e8
VS		 5484 /*
5485 * Gen2 reports pipe underruns whenever all planes are disabled.
5486 * So diasble underrun reporting before all the planes get disabled.
5487 * FIXME: Need to fix the logic to work when we turn off all planes
5488 * but leave the pipe running.
5489 */
5490 if (IS_GEN2(dev))
a72e4c9f 5491 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5492
564ed191
ID		 5493 /*
5494 * Vblank time updates from the shadow to live plane control register
5495 * are blocked if the memory self-refresh mode is active at that
5496 * moment. So to make sure the plane gets truly disabled, disable
5497 * first the self-refresh mode. The self-refresh enable bit in turn
5498 * will be checked/applied by the HW only at the next frame start
5499 * event which is after the vblank start event, so we need to have a
5500 * wait-for-vblank between disabling the plane and the pipe.
5501 */
5502 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5503 intel_crtc_disable_planes(crtc);
5504
6304cd91
VS		 5505 /*
5506 * On gen2 planes are double buffered but the pipe isn't, so we must
5507 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5508 * We also need to wait on all gmch platforms because of the
5509 * self-refresh mode constraint explained above.
6304cd91 5510 */
564ed191 5511 intel_wait_for_vblank(dev, pipe);
6304cd91 5512
4b3a9526
VS		 5513 for_each_encoder_on_crtc(dev, crtc, encoder)
5514 encoder->disable(encoder);
5515
f9b61ff6
DV		 5516 drm_crtc_vblank_off(crtc);
5517 assert_vblank_disabled(crtc);
5518
575f7ab7 5519 intel_disable_pipe(intel_crtc);
24a1f16d 5520
87476d63 5521 i9xx_pfit_disable(intel_crtc);
24a1f16d 5522
89b667f8
JB		 5523 for_each_encoder_on_crtc(dev, crtc, encoder)
5524 if (encoder->post_disable)
5525 encoder->post_disable(encoder);
5526
409ee761 5527 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5528 if (IS_CHERRYVIEW(dev))
5529 chv_disable_pll(dev_priv, pipe);
5530 else if (IS_VALLEYVIEW(dev))
5531 vlv_disable_pll(dev_priv, pipe);
5532 else
1c4e0274 5533 i9xx_disable_pll(intel_crtc);
076ed3b2 5534 }
0b8765c6 5535
4a3436e8 5536 if (!IS_GEN2(dev))
a72e4c9f 5537 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5538
f7abfe8b 5539 intel_crtc->active = false;
46ba614c 5540 intel_update_watermarks(crtc);
f37fcc2a 5541
efa9624e 5542 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5543 intel_fbc_update(dev);
efa9624e 5544 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5545}
5546
ee7b9f93
JB		 5547static void i9xx_crtc_off(struct drm_crtc *crtc)
5548{
5549}
5550
b04c5bd6
BF		 5551/* Master function to enable/disable CRTC and corresponding power wells */
5552void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5553{
5554 struct drm_device *dev = crtc->dev;
5555 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5557 enum intel_display_power_domain domain;
5558 unsigned long domains;
976f8a20 5559
0e572fe7
DV		 5560 if (enable) {
5561 if (!intel_crtc->active) {
e1e9fb84
DV		 5562 domains = get_crtc_power_domains(crtc);
5563 for_each_power_domain(domain, domains)
5564 intel_display_power_get(dev_priv, domain);
5565 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5566
5567 dev_priv->display.crtc_enable(crtc);
5568 }
5569 } else {
5570 if (intel_crtc->active) {
5571 dev_priv->display.crtc_disable(crtc);
5572
e1e9fb84
DV		 5573 domains = intel_crtc->enabled_power_domains;
5574 for_each_power_domain(domain, domains)
5575 intel_display_power_put(dev_priv, domain);
5576 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5577 }
5578 }
b04c5bd6
BF		 5579}
5580
5581/**
5582 * Sets the power management mode of the pipe and plane.
5583 */
5584void intel_crtc_update_dpms(struct drm_crtc *crtc)
5585{
5586 struct drm_device *dev = crtc->dev;
5587 struct intel_encoder *intel_encoder;
5588 bool enable = false;
5589
5590 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5591 enable |= intel_encoder->connectors_active;
5592
5593 intel_crtc_control(crtc, enable);
976f8a20
DV		 5594}
5595
cdd59983
CW		 5596static void intel_crtc_disable(struct drm_crtc *crtc)
5597{
cdd59983 5598 struct drm_device *dev = crtc->dev;
976f8a20 5599 struct drm_connector *connector;
ee7b9f93 5600 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5601
976f8a20 5602 /* crtc should still be enabled when we disable it. */
83d65738 5603 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5604
5605 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5606 dev_priv->display.off(crtc);
5607
70a101f8 5608 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 5609
5610 /* Update computed state. */
5611 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5612 if (!connector->encoder || !connector->encoder->crtc)
5613 continue;
5614
5615 if (connector->encoder->crtc != crtc)
5616 continue;
5617
5618 connector->dpms = DRM_MODE_DPMS_OFF;
5619 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5620 }
5621}
5622
ea5b213a 5623void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5624{
4ef69c7a 5625 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5626
ea5b213a
CW		 5627 drm_encoder_cleanup(encoder);
5628 kfree(intel_encoder);
7e7d76c3
JB		 5629}
5630
9237329d 5631/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5632 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5633 * state of the entire output pipe. */
9237329d 5634static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5635{
5ab432ef
DV		 5636 if (mode == DRM_MODE_DPMS_ON) {
5637 encoder->connectors_active = true;
5638
b2cabb0e 5639 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5640 } else {
5641 encoder->connectors_active = false;
5642
b2cabb0e 5643 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5644 }
79e53945
JB		 5645}
5646
0a91ca29
DV		 5647/* Cross check the actual hw state with our own modeset state tracking (and it's
5648 * internal consistency). */
b980514c 5649static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5650{
0a91ca29
DV		 5651 if (connector->get_hw_state(connector)) {
5652 struct intel_encoder *encoder = connector->encoder;
5653 struct drm_crtc *crtc;
5654 bool encoder_enabled;
5655 enum pipe pipe;
5656
5657 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5658 connector->base.base.id,
c23cc417 5659 connector->base.name);
0a91ca29 5660
0e32b39c
DA		 5661 /* there is no real hw state for MST connectors */
5662 if (connector->mst_port)
5663 return;
5664
e2c719b7 5665 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5666 "wrong connector dpms state\n");
e2c719b7 5667 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5668 "active connector not linked to encoder\n");
0a91ca29 5669
36cd7444 5670 if (encoder) {
e2c719b7 5671 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5672 "encoder->connectors_active not set\n");
5673
5674 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5675 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5676 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5677 return;
0a91ca29 5678
36cd7444 5679 crtc = encoder->base.crtc;
0a91ca29 5680
83d65738
MR		 5681 I915_STATE_WARN(!crtc->state->enable,
5682 "crtc not enabled\n");
e2c719b7
RC		 5683 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5684 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5685 "encoder active on the wrong pipe\n");
5686 }
0a91ca29 5687 }
79e53945
JB		 5688}
5689
9bdbd0b9
ACO		 5690int intel_connector_init(struct intel_connector *connector)
5691{
5692 struct drm_connector_state *connector_state;
5693
5694 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
5695 if (!connector_state)
5696 return -ENOMEM;
5697
5698 connector->base.state = connector_state;
5699 return 0;
5700}
5701
5702struct intel_connector *intel_connector_alloc(void)
5703{
5704 struct intel_connector *connector;
5705
5706 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5707 if (!connector)
5708 return NULL;
5709
5710 if (intel_connector_init(connector) < 0) {
5711 kfree(connector);
5712 return NULL;
5713 }
5714
5715 return connector;
5716}
5717
5ab432ef
DV		 5718/* Even simpler default implementation, if there's really no special case to
5719 * consider. */
5720void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5721{
5ab432ef
DV		 5722 /* All the simple cases only support two dpms states. */
5723 if (mode != DRM_MODE_DPMS_ON)
5724 mode = DRM_MODE_DPMS_OFF;
d4270e57 5725
5ab432ef
DV		 5726 if (mode == connector->dpms)
5727 return;
5728
5729 connector->dpms = mode;
5730
5731 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5732 if (connector->encoder)
5733 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5734
b980514c 5735 intel_modeset_check_state(connector->dev);
79e53945
JB		 5736}
5737
f0947c37
DV		 5738/* Simple connector->get_hw_state implementation for encoders that support only
5739 * one connector and no cloning and hence the encoder state determines the state
5740 * of the connector. */
5741bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5742{
24929352 5743 enum pipe pipe = 0;
f0947c37 5744 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5745
f0947c37 5746 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5747}
5748
6d293983 5749static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 5750{
6d293983
ACO		 5751 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5752 return crtc_state->fdi_lanes;
d272ddfa
VS		 5753
5754 return 0;
5755}
5756
6d293983 5757static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5758 struct intel_crtc_state *pipe_config)
1857e1da 5759{
6d293983
ACO		 5760 struct drm_atomic_state *state = pipe_config->base.state;
5761 struct intel_crtc *other_crtc;
5762 struct intel_crtc_state *other_crtc_state;
5763
1857e1da
DV		 5764 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5765 pipe_name(pipe), pipe_config->fdi_lanes);
5766 if (pipe_config->fdi_lanes > 4) {
5767 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5768 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5769 return -EINVAL;
1857e1da
DV		 5770 }
5771
bafb6553 5772 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5773 if (pipe_config->fdi_lanes > 2) {
5774 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5775 pipe_config->fdi_lanes);
6d293983 5776 return -EINVAL;
1857e1da 5777 } else {
6d293983 5778 return 0;
1857e1da
DV		 5779 }
5780 }
5781
5782 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 5783 return 0;
1857e1da
DV		 5784
5785 /* Ivybridge 3 pipe is really complicated */
5786 switch (pipe) {
5787 case PIPE_A:
6d293983 5788 return 0;
1857e1da 5789 case PIPE_B:
6d293983
ACO		 5790 if (pipe_config->fdi_lanes <= 2)
5791 return 0;
5792
5793 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
5794 other_crtc_state =
5795 intel_atomic_get_crtc_state(state, other_crtc);
5796 if (IS_ERR(other_crtc_state))
5797 return PTR_ERR(other_crtc_state);
5798
5799 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 5800 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5801 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5802 return -EINVAL;
1857e1da 5803 }
6d293983 5804 return 0;
1857e1da 5805 case PIPE_C:
251cc67c
VS		 5806 if (pipe_config->fdi_lanes > 2) {
5807 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5808 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5809 return -EINVAL;
251cc67c 5810 }
6d293983
ACO		 5811
5812 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
5813 other_crtc_state =
5814 intel_atomic_get_crtc_state(state, other_crtc);
5815 if (IS_ERR(other_crtc_state))
5816 return PTR_ERR(other_crtc_state);
5817
5818 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 5819 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 5820 return -EINVAL;
1857e1da 5821 }
6d293983 5822 return 0;
1857e1da
DV		 5823 default:
5824 BUG();
5825 }
5826}
5827
e29c22c0
DV		 5828#define RETRY 1
5829static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 5830 struct intel_crtc_state *pipe_config)
877d48d5 5831{
1857e1da 5832 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 5833 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 5834 int lane, link_bw, fdi_dotclock, ret;
5835 bool needs_recompute = false;
877d48d5 5836
e29c22c0 5837retry:
877d48d5
DV		 5838 /* FDI is a binary signal running at ~2.7GHz, encoding
5839 * each output octet as 10 bits. The actual frequency
5840 * is stored as a divider into a 100MHz clock, and the
5841 * mode pixel clock is stored in units of 1KHz.
5842 * Hence the bw of each lane in terms of the mode signal
5843 * is:
5844 */
5845 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5846
241bfc38 5847 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 5848
2bd89a07 5849 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 5850 pipe_config->pipe_bpp);
5851
5852 pipe_config->fdi_lanes = lane;
5853
2bd89a07 5854 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 5855 link_bw, &pipe_config->fdi_m_n);
1857e1da 5856
6d293983
ACO		 5857 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5858 intel_crtc->pipe, pipe_config);
5859 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 5860 pipe_config->pipe_bpp -= 2*3;
5861 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5862 pipe_config->pipe_bpp);
5863 needs_recompute = true;
5864 pipe_config->bw_constrained = true;
5865
5866 goto retry;
5867 }
5868
5869 if (needs_recompute)
5870 return RETRY;
5871
6d293983 5872 return ret;
877d48d5
DV		 5873}
5874
42db64ef 5875static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 5876 struct intel_crtc_state *pipe_config)
42db64ef 5877{
d330a953 5878 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 5879 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 5880 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 5881}
5882
a43f6e0f 5883static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 5884 struct intel_crtc_state *pipe_config)
79e53945 5885{
a43f6e0f 5886 struct drm_device *dev = crtc->base.dev;
8bd31e67 5887 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 5888 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 5889
ad3a4479 5890 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 5891 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 5892 int clock_limit =
5893 dev_priv->display.get_display_clock_speed(dev);
5894
5895 /*
5896 * Enable pixel doubling when the dot clock
5897 * is > 90% of the (display) core speed.
5898 *
b397c96b
VS		 5899 * GDG double wide on either pipe,
5900 * otherwise pipe A only.
cf532bb2 5901 */
b397c96b 5902 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 5903 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 5904 clock_limit *= 2;
cf532bb2 5905 pipe_config->double_wide = true;
ad3a4479
VS		 5906 }
5907
241bfc38 5908 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 5909 return -EINVAL;
2c07245f 5910 }
89749350 5911
1d1d0e27
VS		 5912 /*
5913 * Pipe horizontal size must be even in:
5914 * - DVO ganged mode
5915 * - LVDS dual channel mode
5916 * - Double wide pipe
5917 */
a93e255f 5918 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 5919 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5920 pipe_config->pipe_src_w &= ~1;
5921
8693a824
DL		 5922 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5923 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 5924 */
5925 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5926 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 5927 return -EINVAL;
44f46b42 5928
bd080ee5 5929 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 5930 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 5931 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 5932 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5933 * for lvds. */
5934 pipe_config->pipe_bpp = 8*3;
5935 }
5936
f5adf94e 5937 if (HAS_IPS(dev))
a43f6e0f
DV		 5938 hsw_compute_ips_config(crtc, pipe_config);
5939
877d48d5 5940 if (pipe_config->has_pch_encoder)
a43f6e0f 5941 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 5942
e29c22c0 5943 return 0;
79e53945
JB		 5944}
5945
1652d19e
VS		 5946static int skylake_get_display_clock_speed(struct drm_device *dev)
5947{
5948 struct drm_i915_private *dev_priv = to_i915(dev);
5949 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5950 uint32_t cdctl = I915_READ(CDCLK_CTL);
5951 uint32_t linkrate;
5952
5953 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
5954 WARN(1, "LCPLL1 not enabled\n");
5955 return 24000; /* 24MHz is the cd freq with NSSC ref */
5956 }
5957
5958 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
5959 return 540000;
5960
5961 linkrate = (I915_READ(DPLL_CTRL1) &
5962 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
5963
5964 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
5965 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
5966 /* vco 8640 */
5967 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
5968 case CDCLK_FREQ_450_432:
5969 return 432000;
5970 case CDCLK_FREQ_337_308:
5971 return 308570;
5972 case CDCLK_FREQ_675_617:
5973 return 617140;
5974 default:
5975 WARN(1, "Unknown cd freq selection\n");
5976 }
5977 } else {
5978 /* vco 8100 */
5979 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
5980 case CDCLK_FREQ_450_432:
5981 return 450000;
5982 case CDCLK_FREQ_337_308:
5983 return 337500;
5984 case CDCLK_FREQ_675_617:
5985 return 675000;
5986 default:
5987 WARN(1, "Unknown cd freq selection\n");
5988 }
5989 }
5990
5991 /* error case, do as if DPLL0 isn't enabled */
5992 return 24000;
5993}
5994
5995static int broadwell_get_display_clock_speed(struct drm_device *dev)
5996{
5997 struct drm_i915_private *dev_priv = dev->dev_private;
5998 uint32_t lcpll = I915_READ(LCPLL_CTL);
5999 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6000
6001 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6002 return 800000;
6003 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6004 return 450000;
6005 else if (freq == LCPLL_CLK_FREQ_450)
6006 return 450000;
6007 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6008 return 540000;
6009 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6010 return 337500;
6011 else
6012 return 675000;
6013}
6014
6015static int haswell_get_display_clock_speed(struct drm_device *dev)
6016{
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 uint32_t lcpll = I915_READ(LCPLL_CTL);
6019 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6020
6021 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6022 return 800000;
6023 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6024 return 450000;
6025 else if (freq == LCPLL_CLK_FREQ_450)
6026 return 450000;
6027 else if (IS_HSW_ULT(dev))
6028 return 337500;
6029 else
6030 return 540000;
6031}
6032
25eb05fc
JB		 6033static int valleyview_get_display_clock_speed(struct drm_device *dev)
6034{
d197b7d3 6035 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6036 u32 val;
6037 int divider;
6038
6bcda4f0
VS		 6039 if (dev_priv->hpll_freq == 0)
6040 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6041
d197b7d3
VS		 6042 mutex_lock(&dev_priv->dpio_lock);
6043 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6044 mutex_unlock(&dev_priv->dpio_lock);
6045
6046 divider = val & DISPLAY_FREQUENCY_VALUES;
6047
7d007f40
VS		 6048 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6049 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6050 "cdclk change in progress\n");
6051
6bcda4f0 6052 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6053}
6054
b37a6434
VS		 6055static int ilk_get_display_clock_speed(struct drm_device *dev)
6056{
6057 return 450000;
6058}
6059
e70236a8
JB		 6060static int i945_get_display_clock_speed(struct drm_device *dev)
6061{
6062 return 400000;
6063}
79e53945 6064
e70236a8 6065static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6066{
e907f170 6067 return 333333;
e70236a8 6068}
79e53945 6069
e70236a8
JB		 6070static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6071{
6072 return 200000;
6073}
79e53945 6074
257a7ffc
DV		 6075static int pnv_get_display_clock_speed(struct drm_device *dev)
6076{
6077 u16 gcfgc = 0;
6078
6079 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6080
6081 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6082 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6083 return 266667;
257a7ffc 6084 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6085 return 333333;
257a7ffc 6086 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6087 return 444444;
257a7ffc
DV		 6088 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6089 return 200000;
6090 default:
6091 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6092 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6093 return 133333;
257a7ffc 6094 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6095 return 166667;
257a7ffc
DV		 6096 }
6097}
6098
e70236a8
JB		 6099static int i915gm_get_display_clock_speed(struct drm_device *dev)
6100{
6101 u16 gcfgc = 0;
79e53945 6102
e70236a8
JB		 6103 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6104
6105 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6106 return 133333;
e70236a8
JB		 6107 else {
6108 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6109 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6110 return 333333;
e70236a8
JB		 6111 default:
6112 case GC_DISPLAY_CLOCK_190_200_MHZ:
6113 return 190000;
79e53945 6114 }
e70236a8
JB		 6115 }
6116}
6117
6118static int i865_get_display_clock_speed(struct drm_device *dev)
6119{
e907f170 6120 return 266667;
e70236a8
JB		 6121}
6122
6123static int i855_get_display_clock_speed(struct drm_device *dev)
6124{
6125 u16 hpllcc = 0;
6126 /* Assume that the hardware is in the high speed state. This
6127 * should be the default.
6128 */
6129 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6130 case GC_CLOCK_133_200:
6131 case GC_CLOCK_100_200:
6132 return 200000;
6133 case GC_CLOCK_166_250:
6134 return 250000;
6135 case GC_CLOCK_100_133:
e907f170 6136 return 133333;
e70236a8 6137 }
79e53945 6138
e70236a8
JB		 6139 /* Shouldn't happen */
6140 return 0;
6141}
79e53945 6142
e70236a8
JB		 6143static int i830_get_display_clock_speed(struct drm_device *dev)
6144{
e907f170 6145 return 133333;
79e53945
JB		 6146}
6147
2c07245f 6148static void
a65851af 6149intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6150{
a65851af
VS		 6151 while (*num > DATA_LINK_M_N_MASK ||
6152 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6153 *num >>= 1;
6154 *den >>= 1;
6155 }
6156}
6157
a65851af
VS		 6158static void compute_m_n(unsigned int m, unsigned int n,
6159 uint32_t *ret_m, uint32_t *ret_n)
6160{
6161 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6162 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6163 intel_reduce_m_n_ratio(ret_m, ret_n);
6164}
6165
e69d0bc1
DV		 6166void
6167intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6168 int pixel_clock, int link_clock,
6169 struct intel_link_m_n *m_n)
2c07245f 6170{
e69d0bc1 6171 m_n->tu = 64;
a65851af
VS		 6172
6173 compute_m_n(bits_per_pixel * pixel_clock,
6174 link_clock * nlanes * 8,
6175 &m_n->gmch_m, &m_n->gmch_n);
6176
6177 compute_m_n(pixel_clock, link_clock,
6178 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6179}
6180
a7615030
CW		 6181static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6182{
d330a953
JN		 6183 if (i915.panel_use_ssc >= 0)
6184 return i915.panel_use_ssc != 0;
41aa3448 6185 return dev_priv->vbt.lvds_use_ssc
435793df 6186 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6187}
6188
a93e255f
ACO		 6189static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6190 int num_connectors)
c65d77d8 6191{
a93e255f 6192 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6193 struct drm_i915_private *dev_priv = dev->dev_private;
6194 int refclk;
6195
a93e255f
ACO		 6196 WARN_ON(!crtc_state->base.state);
6197
a0c4da24 6198 if (IS_VALLEYVIEW(dev)) {
9a0ea498 6199 refclk = 100000;
a93e255f 6200 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6201 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6202 refclk = dev_priv->vbt.lvds_ssc_freq;
6203 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6204 } else if (!IS_GEN2(dev)) {
6205 refclk = 96000;
6206 } else {
6207 refclk = 48000;
6208 }
6209
6210 return refclk;
6211}
6212
7429e9d4 6213static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6214{
7df00d7a 6215 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6216}
f47709a9 6217
7429e9d4
DV		 6218static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6219{
6220 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6221}
6222
f47709a9 6223static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6224 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6225 intel_clock_t *reduced_clock)
6226{
f47709a9 6227 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6228 u32 fp, fp2 = 0;
6229
6230 if (IS_PINEVIEW(dev)) {
190f68c5 6231 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6232 if (reduced_clock)
7429e9d4 6233 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6234 } else {
190f68c5 6235 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6236 if (reduced_clock)
7429e9d4 6237 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6238 }
6239
190f68c5 6240 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6241
f47709a9 6242 crtc->lowfreq_avail = false;
a93e255f 6243 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6244 reduced_clock) {
190f68c5 6245 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6246 crtc->lowfreq_avail = true;
a7516a05 6247 } else {
190f68c5 6248 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6249 }
6250}
6251
5e69f97f
CML		 6252static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6253 pipe)
89b667f8
JB		 6254{
6255 u32 reg_val;
6256
6257 /*
6258 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6259 * and set it to a reasonable value instead.
6260 */
ab3c759a 6261 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6262 reg_val &= 0xffffff00;
6263 reg_val |= 0x00000030;
ab3c759a 6264 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6265
ab3c759a 6266 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6267 reg_val &= 0x8cffffff;
6268 reg_val = 0x8c000000;
ab3c759a 6269 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6270
ab3c759a 6271 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6272 reg_val &= 0xffffff00;
ab3c759a 6273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6274
ab3c759a 6275 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6276 reg_val &= 0x00ffffff;
6277 reg_val |= 0xb0000000;
ab3c759a 6278 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6279}
6280
b551842d
DV		 6281static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6282 struct intel_link_m_n *m_n)
6283{
6284 struct drm_device *dev = crtc->base.dev;
6285 struct drm_i915_private *dev_priv = dev->dev_private;
6286 int pipe = crtc->pipe;
6287
e3b95f1e
DV		 6288 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6289 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6290 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6291 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6292}
6293
6294static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6295 struct intel_link_m_n *m_n,
6296 struct intel_link_m_n *m2_n2)
b551842d
DV		 6297{
6298 struct drm_device *dev = crtc->base.dev;
6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300 int pipe = crtc->pipe;
6e3c9717 6301 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6302
6303 if (INTEL_INFO(dev)->gen >= 5) {
6304 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6305 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6306 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6307 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6308 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6309 * for gen < 8) and if DRRS is supported (to make sure the
6310 * registers are not unnecessarily accessed).
6311 */
44395bfe 6312 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6313 crtc->config->has_drrs) {
f769cd24
VK		 6314 I915_WRITE(PIPE_DATA_M2(transcoder),
6315 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6316 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6317 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6318 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6319 }
b551842d 6320 } else {
e3b95f1e
DV		 6321 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6322 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6323 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6324 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6325 }
6326}
6327
fe3cd48d 6328void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6329{
fe3cd48d
R		 6330 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6331
6332 if (m_n == M1_N1) {
6333 dp_m_n = &crtc->config->dp_m_n;
6334 dp_m2_n2 = &crtc->config->dp_m2_n2;
6335 } else if (m_n == M2_N2) {
6336
6337 /*
6338 * M2_N2 registers are not supported. Hence m2_n2 divider value
6339 * needs to be programmed into M1_N1.
6340 */
6341 dp_m_n = &crtc->config->dp_m2_n2;
6342 } else {
6343 DRM_ERROR("Unsupported divider value\n");
6344 return;
6345 }
6346
6e3c9717
ACO		 6347 if (crtc->config->has_pch_encoder)
6348 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6349 else
fe3cd48d 6350 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6351}
6352
d288f65f 6353static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6354 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6355{
6356 u32 dpll, dpll_md;
6357
6358 /*
6359 * Enable DPIO clock input. We should never disable the reference
6360 * clock for pipe B, since VGA hotplug / manual detection depends
6361 * on it.
6362 */
6363 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6364 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6365 /* We should never disable this, set it here for state tracking */
6366 if (crtc->pipe == PIPE_B)
6367 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6368 dpll |= DPLL_VCO_ENABLE;
d288f65f 6369 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6370
d288f65f 6371 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6372 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6373 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6374}
6375
d288f65f 6376static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6377 const struct intel_crtc_state *pipe_config)
a0c4da24 6378{
f47709a9 6379 struct drm_device *dev = crtc->base.dev;
a0c4da24 6380 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6381 int pipe = crtc->pipe;
bdd4b6a6 6382 u32 mdiv;
a0c4da24 6383 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6384 u32 coreclk, reg_val;
a0c4da24 6385
09153000
DV		 6386 mutex_lock(&dev_priv->dpio_lock);
6387
d288f65f
VS		 6388 bestn = pipe_config->dpll.n;
6389 bestm1 = pipe_config->dpll.m1;
6390 bestm2 = pipe_config->dpll.m2;
6391 bestp1 = pipe_config->dpll.p1;
6392 bestp2 = pipe_config->dpll.p2;
a0c4da24 6393
89b667f8
JB		 6394 /* See eDP HDMI DPIO driver vbios notes doc */
6395
6396 /* PLL B needs special handling */
bdd4b6a6 6397 if (pipe == PIPE_B)
5e69f97f 6398 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6399
6400 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6401 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6402
6403 /* Disable target IRef on PLL */
ab3c759a 6404 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6405 reg_val &= 0x00ffffff;
ab3c759a 6406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6407
6408 /* Disable fast lock */
ab3c759a 6409 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6410
6411 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6412 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6413 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6414 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6415 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6416
6417 /*
6418 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6419 * but we don't support that).
6420 * Note: don't use the DAC post divider as it seems unstable.
6421 */
6422 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6423 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6424
a0c4da24 6425 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6426 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6427
89b667f8 6428 /* Set HBR and RBR LPF coefficients */
d288f65f 6429 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6430 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6431 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6432 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6433 0x009f0003);
89b667f8 6434 else
ab3c759a 6435 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6436 0x00d0000f);
6437
681a8504 6438 if (pipe_config->has_dp_encoder) {
89b667f8 6439 /* Use SSC source */
bdd4b6a6 6440 if (pipe == PIPE_A)
ab3c759a 6441 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6442 0x0df40000);
6443 else
ab3c759a 6444 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6445 0x0df70000);
6446 } else { /* HDMI or VGA */
6447 /* Use bend source */
bdd4b6a6 6448 if (pipe == PIPE_A)
ab3c759a 6449 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6450 0x0df70000);
6451 else
ab3c759a 6452 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6453 0x0df40000);
6454 }
a0c4da24 6455
ab3c759a 6456 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6457 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6459 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6460 coreclk |= 0x01000000;
ab3c759a 6461 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6462
ab3c759a 6463 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6464 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6465}
6466
d288f65f 6467static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6468 struct intel_crtc_state *pipe_config)
1ae0d137 6469{
d288f65f 6470 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6471 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6472 DPLL_VCO_ENABLE;
6473 if (crtc->pipe != PIPE_A)
d288f65f 6474 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6475
d288f65f
VS		 6476 pipe_config->dpll_hw_state.dpll_md =
6477 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6478}
6479
d288f65f 6480static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6481 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6482{
6483 struct drm_device *dev = crtc->base.dev;
6484 struct drm_i915_private *dev_priv = dev->dev_private;
6485 int pipe = crtc->pipe;
6486 int dpll_reg = DPLL(crtc->pipe);
6487 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6488 u32 loopfilter, tribuf_calcntr;
9d556c99 6489 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6490 u32 dpio_val;
9cbe40c1 6491 int vco;
9d556c99 6492
d288f65f
VS		 6493 bestn = pipe_config->dpll.n;
6494 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6495 bestm1 = pipe_config->dpll.m1;
6496 bestm2 = pipe_config->dpll.m2 >> 22;
6497 bestp1 = pipe_config->dpll.p1;
6498 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6499 vco = pipe_config->dpll.vco;
a945ce7e 6500 dpio_val = 0;
9cbe40c1 6501 loopfilter = 0;
9d556c99
CML		 6502
6503 /*
6504 * Enable Refclk and SSC
6505 */
a11b0703 6506 I915_WRITE(dpll_reg,
d288f65f 6507 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6508
6509 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6510
9d556c99
CML		 6511 /* p1 and p2 divider */
6512 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6513 5 << DPIO_CHV_S1_DIV_SHIFT |
6514 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6515 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6516 1 << DPIO_CHV_K_DIV_SHIFT);
6517
6518 /* Feedback post-divider - m2 */
6519 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6520
6521 /* Feedback refclk divider - n and m1 */
6522 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6523 DPIO_CHV_M1_DIV_BY_2 |
6524 1 << DPIO_CHV_N_DIV_SHIFT);
6525
6526 /* M2 fraction division */
a945ce7e
VP		 6527 if (bestm2_frac)
6528 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6529
6530 /* M2 fraction division enable */
a945ce7e
VP		 6531 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6532 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6533 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6534 if (bestm2_frac)
6535 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6536 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6537
de3a0fde
VP		 6538 /* Program digital lock detect threshold */
6539 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6540 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6541 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6542 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6543 if (!bestm2_frac)
6544 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6545 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6546
9d556c99 6547 /* Loop filter */
9cbe40c1
VP		 6548 if (vco == 5400000) {
6549 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6550 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6551 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6552 tribuf_calcntr = 0x9;
6553 } else if (vco <= 6200000) {
6554 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6555 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6556 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6557 tribuf_calcntr = 0x9;
6558 } else if (vco <= 6480000) {
6559 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6560 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6561 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6562 tribuf_calcntr = 0x8;
6563 } else {
6564 /* Not supported. Apply the same limits as in the max case */
6565 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6566 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6567 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6568 tribuf_calcntr = 0;
6569 }
9d556c99
CML		 6570 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6571
968040b2 6572 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6573 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6574 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6575 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6576
9d556c99
CML		 6577 /* AFC Recal */
6578 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6579 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6580 DPIO_AFC_RECAL);
6581
6582 mutex_unlock(&dev_priv->dpio_lock);
6583}
6584
d288f65f
VS		 6585/**
6586 * vlv_force_pll_on - forcibly enable just the PLL
6587 * @dev_priv: i915 private structure
6588 * @pipe: pipe PLL to enable
6589 * @dpll: PLL configuration
6590 *
6591 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6592 * in cases where we need the PLL enabled even when @pipe is not going to
6593 * be enabled.
6594 */
6595void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6596 const struct dpll *dpll)
6597{
6598 struct intel_crtc *crtc =
6599 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6600 struct intel_crtc_state pipe_config = {
a93e255f 6601 .base.crtc = &crtc->base,
d288f65f
VS		 6602 .pixel_multiplier = 1,
6603 .dpll = *dpll,
6604 };
6605
6606 if (IS_CHERRYVIEW(dev)) {
6607 chv_update_pll(crtc, &pipe_config);
6608 chv_prepare_pll(crtc, &pipe_config);
6609 chv_enable_pll(crtc, &pipe_config);
6610 } else {
6611 vlv_update_pll(crtc, &pipe_config);
6612 vlv_prepare_pll(crtc, &pipe_config);
6613 vlv_enable_pll(crtc, &pipe_config);
6614 }
6615}
6616
6617/**
6618 * vlv_force_pll_off - forcibly disable just the PLL
6619 * @dev_priv: i915 private structure
6620 * @pipe: pipe PLL to disable
6621 *
6622 * Disable the PLL for @pipe. To be used in cases where we need
6623 * the PLL enabled even when @pipe is not going to be enabled.
6624 */
6625void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6626{
6627 if (IS_CHERRYVIEW(dev))
6628 chv_disable_pll(to_i915(dev), pipe);
6629 else
6630 vlv_disable_pll(to_i915(dev), pipe);
6631}
6632
f47709a9 6633static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6634 struct intel_crtc_state *crtc_state,
f47709a9 6635 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6636 int num_connectors)
6637{
f47709a9 6638 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6639 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6640 u32 dpll;
6641 bool is_sdvo;
190f68c5 6642 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6643
190f68c5 6644 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6645
a93e255f
ACO		 6646 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6647 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6648
6649 dpll = DPLL_VGA_MODE_DIS;
6650
a93e255f 6651 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6652 dpll |= DPLLB_MODE_LVDS;
6653 else
6654 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6655
ef1b460d 6656 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6657 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6658 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6659 }
198a037f
DV		 6660
6661 if (is_sdvo)
4a33e48d 6662 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6663
190f68c5 6664 if (crtc_state->has_dp_encoder)
4a33e48d 6665 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6666
6667 /* compute bitmask from p1 value */
6668 if (IS_PINEVIEW(dev))
6669 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6670 else {
6671 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6672 if (IS_G4X(dev) && reduced_clock)
6673 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6674 }
6675 switch (clock->p2) {
6676 case 5:
6677 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6678 break;
6679 case 7:
6680 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6681 break;
6682 case 10:
6683 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6684 break;
6685 case 14:
6686 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6687 break;
6688 }
6689 if (INTEL_INFO(dev)->gen >= 4)
6690 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6691
190f68c5 6692 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6693 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 6694 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6695 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6696 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6697 else
6698 dpll |= PLL_REF_INPUT_DREFCLK;
6699
6700 dpll |= DPLL_VCO_ENABLE;
190f68c5 6701 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6702
eb1cbe48 6703 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6704 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6705 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6706 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6707 }
6708}
6709
f47709a9 6710static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6711 struct intel_crtc_state *crtc_state,
f47709a9 6712 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6713 int num_connectors)
6714{
f47709a9 6715 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6716 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6717 u32 dpll;
190f68c5 6718 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6719
190f68c5 6720 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6721
eb1cbe48
DV		 6722 dpll = DPLL_VGA_MODE_DIS;
6723
a93e255f 6724 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6725 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6726 } else {
6727 if (clock->p1 == 2)
6728 dpll |= PLL_P1_DIVIDE_BY_TWO;
6729 else
6730 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6731 if (clock->p2 == 4)
6732 dpll |= PLL_P2_DIVIDE_BY_4;
6733 }
6734
a93e255f 6735 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6736 dpll |= DPLL_DVO_2X_MODE;
6737
a93e255f 6738 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6739 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6740 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6741 else
6742 dpll |= PLL_REF_INPUT_DREFCLK;
6743
6744 dpll |= DPLL_VCO_ENABLE;
190f68c5 6745 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6746}
6747
8a654f3b 6748static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6749{
6750 struct drm_device *dev = intel_crtc->base.dev;
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6753 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6754 struct drm_display_mode *adjusted_mode =
6e3c9717 6755 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6756 uint32_t crtc_vtotal, crtc_vblank_end;
6757 int vsyncshift = 0;
4d8a62ea
DV		 6758
6759 /* We need to be careful not to changed the adjusted mode, for otherwise
6760 * the hw state checker will get angry at the mismatch. */
6761 crtc_vtotal = adjusted_mode->crtc_vtotal;
6762 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6763
609aeaca 6764 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6765 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6766 crtc_vtotal -= 1;
6767 crtc_vblank_end -= 1;
609aeaca 6768
409ee761 6769 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6770 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6771 else
6772 vsyncshift = adjusted_mode->crtc_hsync_start -
6773 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6774 if (vsyncshift < 0)
6775 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6776 }
6777
6778 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6779 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6780
fe2b8f9d 6781 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6782 (adjusted_mode->crtc_hdisplay - 1) |
6783 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6784 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6785 (adjusted_mode->crtc_hblank_start - 1) |
6786 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6787 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6788 (adjusted_mode->crtc_hsync_start - 1) |
6789 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6790
fe2b8f9d 6791 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6792 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6793 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6794 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6795 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6796 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6797 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6798 (adjusted_mode->crtc_vsync_start - 1) |
6799 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6800
b5e508d4
PZ		 6801 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6802 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6803 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6804 * bits. */
6805 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6806 (pipe == PIPE_B || pipe == PIPE_C))
6807 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6808
b0e77b9c
PZ		 6809 /* pipesrc controls the size that is scaled from, which should
6810 * always be the user's requested size.
6811 */
6812 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6813 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6814 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6815}
6816
1bd1bd80 6817static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6818 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 6819{
6820 struct drm_device *dev = crtc->base.dev;
6821 struct drm_i915_private *dev_priv = dev->dev_private;
6822 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6823 uint32_t tmp;
6824
6825 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 6826 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6827 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6828 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 6829 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6830 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6831 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 6832 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6833 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6834
6835 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 6836 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6837 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6838 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 6839 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6840 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6841 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 6842 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6843 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6844
6845 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 6846 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6847 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6848 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 6849 }
6850
6851 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 6852 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6853 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6854
2d112de7
ACO		 6855 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6856 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 6857}
6858
f6a83288 6859void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6860 struct intel_crtc_state *pipe_config)
babea61d 6861{
2d112de7
ACO		 6862 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6863 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6864 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6865 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6866
2d112de7
ACO		 6867 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6868 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6869 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6870 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6871
2d112de7 6872 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 6873
2d112de7
ACO		 6874 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6875 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 6876}
6877
84b046f3
DV		 6878static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6879{
6880 struct drm_device *dev = intel_crtc->base.dev;
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6882 uint32_t pipeconf;
6883
9f11a9e4 6884 pipeconf = 0;
84b046f3 6885
b6b5d049
VS		 6886 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6887 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6888 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 6889
6e3c9717 6890 if (intel_crtc->config->double_wide)
cf532bb2 6891 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 6892
ff9ce46e
DV		 6893 /* only g4x and later have fancy bpc/dither controls */
6894 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 6895 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 6896 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 6897 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 6898 PIPECONF_DITHER_TYPE_SP;
84b046f3 6899
6e3c9717 6900 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 6901 case 18:
6902 pipeconf |= PIPECONF_6BPC;
6903 break;
6904 case 24:
6905 pipeconf |= PIPECONF_8BPC;
6906 break;
6907 case 30:
6908 pipeconf |= PIPECONF_10BPC;
6909 break;
6910 default:
6911 /* Case prevented by intel_choose_pipe_bpp_dither. */
6912 BUG();
84b046f3
DV		 6913 }
6914 }
6915
6916 if (HAS_PIPE_CXSR(dev)) {
6917 if (intel_crtc->lowfreq_avail) {
6918 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6919 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6920 } else {
6921 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 6922 }
6923 }
6924
6e3c9717 6925 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 6926 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 6927 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 6928 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6929 else
6930 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6931 } else
84b046f3
DV		 6932 pipeconf |= PIPECONF_PROGRESSIVE;
6933
6e3c9717 6934 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 6935 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 6936
84b046f3
DV		 6937 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6938 POSTING_READ(PIPECONF(intel_crtc->pipe));
6939}
6940
190f68c5
ACO		 6941static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6942 struct intel_crtc_state *crtc_state)
79e53945 6943{
c7653199 6944 struct drm_device *dev = crtc->base.dev;
79e53945 6945 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 6946 int refclk, num_connectors = 0;
652c393a 6947 intel_clock_t clock, reduced_clock;
a16af721 6948 bool ok, has_reduced_clock = false;
e9fd1c02 6949 bool is_lvds = false, is_dsi = false;
5eddb70b 6950 struct intel_encoder *encoder;
d4906093 6951 const intel_limit_t *limit;
55bb9992
ACO		 6952 struct drm_atomic_state *state = crtc_state->base.state;
6953 struct drm_connector_state *connector_state;
6954 int i;
79e53945 6955
55bb9992
ACO		 6956 for (i = 0; i < state->num_connector; i++) {
6957 if (!state->connectors[i])
d0737e1d
ACO		 6958 continue;
6959
55bb9992
ACO		 6960 connector_state = state->connector_states[i];
6961 if (connector_state->crtc != &crtc->base)
6962 continue;
6963
6964 encoder = to_intel_encoder(connector_state->best_encoder);
6965
5eddb70b 6966 switch (encoder->type) {
79e53945
JB		 6967 case INTEL_OUTPUT_LVDS:
6968 is_lvds = true;
6969 break;
e9fd1c02
JN		 6970 case INTEL_OUTPUT_DSI:
6971 is_dsi = true;
6972 break;
6847d71b
PZ		 6973 default:
6974 break;
79e53945 6975 }
43565a06 6976
c751ce4f 6977 num_connectors++;
79e53945
JB		 6978 }
6979
f2335330 6980 if (is_dsi)
5b18e57c 6981 return 0;
f2335330 6982
190f68c5 6983 if (!crtc_state->clock_set) {
a93e255f 6984 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 6985
e9fd1c02
JN		 6986 /*
6987 * Returns a set of divisors for the desired target clock with
6988 * the given refclk, or FALSE. The returned values represent
6989 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6990 * 2) / p1 / p2.
6991 */
a93e255f
ACO		 6992 limit = intel_limit(crtc_state, refclk);
6993 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 6994 crtc_state->port_clock,
e9fd1c02 6995 refclk, NULL, &clock);
f2335330 6996 if (!ok) {
e9fd1c02
JN		 6997 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6998 return -EINVAL;
6999 }
79e53945 7000
f2335330
JN		 7001 if (is_lvds && dev_priv->lvds_downclock_avail) {
7002 /*
7003 * Ensure we match the reduced clock's P to the target
7004 * clock. If the clocks don't match, we can't switch
7005 * the display clock by using the FP0/FP1. In such case
7006 * we will disable the LVDS downclock feature.
7007 */
7008 has_reduced_clock =
a93e255f 7009 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7010 dev_priv->lvds_downclock,
7011 refclk, &clock,
7012 &reduced_clock);
7013 }
7014 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7015 crtc_state->dpll.n = clock.n;
7016 crtc_state->dpll.m1 = clock.m1;
7017 crtc_state->dpll.m2 = clock.m2;
7018 crtc_state->dpll.p1 = clock.p1;
7019 crtc_state->dpll.p2 = clock.p2;
f47709a9 7020 }
7026d4ac 7021
e9fd1c02 7022 if (IS_GEN2(dev)) {
190f68c5 7023 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7024 has_reduced_clock ? &reduced_clock : NULL,
7025 num_connectors);
9d556c99 7026 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7027 chv_update_pll(crtc, crtc_state);
e9fd1c02 7028 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7029 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7030 } else {
190f68c5 7031 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7032 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7033 num_connectors);
e9fd1c02 7034 }
79e53945 7035
c8f7a0db 7036 return 0;
f564048e
EA		 7037}
7038
2fa2fe9a 7039static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7040 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7041{
7042 struct drm_device *dev = crtc->base.dev;
7043 struct drm_i915_private *dev_priv = dev->dev_private;
7044 uint32_t tmp;
7045
dc9e7dec
VS		 7046 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7047 return;
7048
2fa2fe9a 7049 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7050 if (!(tmp & PFIT_ENABLE))
7051 return;
2fa2fe9a 7052
06922821 7053 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7054 if (INTEL_INFO(dev)->gen < 4) {
7055 if (crtc->pipe != PIPE_B)
7056 return;
2fa2fe9a
DV		 7057 } else {
7058 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7059 return;
7060 }
7061
06922821 7062 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7063 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7064 if (INTEL_INFO(dev)->gen < 5)
7065 pipe_config->gmch_pfit.lvds_border_bits =
7066 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7067}
7068
acbec814 7069static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7070 struct intel_crtc_state *pipe_config)
acbec814
JB		 7071{
7072 struct drm_device *dev = crtc->base.dev;
7073 struct drm_i915_private *dev_priv = dev->dev_private;
7074 int pipe = pipe_config->cpu_transcoder;
7075 intel_clock_t clock;
7076 u32 mdiv;
662c6ecb 7077 int refclk = 100000;
acbec814 7078
f573de5a
SK		 7079 /* In case of MIPI DPLL will not even be used */
7080 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7081 return;
7082
acbec814 7083 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7084 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7085 mutex_unlock(&dev_priv->dpio_lock);
7086
7087 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7088 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7089 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7090 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7091 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7092
f646628b 7093 vlv_clock(refclk, &clock);
acbec814 7094
f646628b
VS		 7095 /* clock.dot is the fast clock */
7096 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7097}
7098
5724dbd1
DL		 7099static void
7100i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7101 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7102{
7103 struct drm_device *dev = crtc->base.dev;
7104 struct drm_i915_private *dev_priv = dev->dev_private;
7105 u32 val, base, offset;
7106 int pipe = crtc->pipe, plane = crtc->plane;
7107 int fourcc, pixel_format;
6761dd31 7108 unsigned int aligned_height;
b113d5ee 7109 struct drm_framebuffer *fb;
1b842c89 7110 struct intel_framebuffer *intel_fb;
1ad292b5 7111
42a7b088
DL		 7112 val = I915_READ(DSPCNTR(plane));
7113 if (!(val & DISPLAY_PLANE_ENABLE))
7114 return;
7115
d9806c9f 7116 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7117 if (!intel_fb) {
1ad292b5
JB		 7118 DRM_DEBUG_KMS("failed to alloc fb\n");
7119 return;
7120 }
7121
1b842c89
DL		 7122 fb = &intel_fb->base;
7123
18c5247e
DV		 7124 if (INTEL_INFO(dev)->gen >= 4) {
7125 if (val & DISPPLANE_TILED) {
49af449b 7126 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7127 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7128 }
7129 }
1ad292b5
JB		 7130
7131 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7132 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7133 fb->pixel_format = fourcc;
7134 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7135
7136 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7137 if (plane_config->tiling)
1ad292b5
JB		 7138 offset = I915_READ(DSPTILEOFF(plane));
7139 else
7140 offset = I915_READ(DSPLINOFF(plane));
7141 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7142 } else {
7143 base = I915_READ(DSPADDR(plane));
7144 }
7145 plane_config->base = base;
7146
7147 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7148 fb->width = ((val >> 16) & 0xfff) + 1;
7149 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7150
7151 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7152 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7153
b113d5ee 7154 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7155 fb->pixel_format,
7156 fb->modifier[0]);
1ad292b5 7157
f37b5c2b 7158 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7159
2844a921
DL		 7160 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7161 pipe_name(pipe), plane, fb->width, fb->height,
7162 fb->bits_per_pixel, base, fb->pitches[0],
7163 plane_config->size);
1ad292b5 7164
2d14030b 7165 plane_config->fb = intel_fb;
1ad292b5
JB		 7166}
7167
70b23a98 7168static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7169 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7170{
7171 struct drm_device *dev = crtc->base.dev;
7172 struct drm_i915_private *dev_priv = dev->dev_private;
7173 int pipe = pipe_config->cpu_transcoder;
7174 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7175 intel_clock_t clock;
7176 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7177 int refclk = 100000;
7178
7179 mutex_lock(&dev_priv->dpio_lock);
7180 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7181 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7182 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7183 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7184 mutex_unlock(&dev_priv->dpio_lock);
7185
7186 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7187 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7188 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7189 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7190 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7191
7192 chv_clock(refclk, &clock);
7193
7194 /* clock.dot is the fast clock */
7195 pipe_config->port_clock = clock.dot / 5;
7196}
7197
0e8ffe1b 7198static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7199 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7200{
7201 struct drm_device *dev = crtc->base.dev;
7202 struct drm_i915_private *dev_priv = dev->dev_private;
7203 uint32_t tmp;
7204
f458ebbc
DV		 7205 if (!intel_display_power_is_enabled(dev_priv,
7206 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7207 return false;
7208
e143a21c 7209 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7210 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7211
0e8ffe1b
DV		 7212 tmp = I915_READ(PIPECONF(crtc->pipe));
7213 if (!(tmp & PIPECONF_ENABLE))
7214 return false;
7215
42571aef
VS		 7216 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7217 switch (tmp & PIPECONF_BPC_MASK) {
7218 case PIPECONF_6BPC:
7219 pipe_config->pipe_bpp = 18;
7220 break;
7221 case PIPECONF_8BPC:
7222 pipe_config->pipe_bpp = 24;
7223 break;
7224 case PIPECONF_10BPC:
7225 pipe_config->pipe_bpp = 30;
7226 break;
7227 default:
7228 break;
7229 }
7230 }
7231
b5a9fa09
DV		 7232 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7233 pipe_config->limited_color_range = true;
7234
282740f7
VS		 7235 if (INTEL_INFO(dev)->gen < 4)
7236 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7237
1bd1bd80
DV		 7238 intel_get_pipe_timings(crtc, pipe_config);
7239
2fa2fe9a
DV		 7240 i9xx_get_pfit_config(crtc, pipe_config);
7241
6c49f241
DV		 7242 if (INTEL_INFO(dev)->gen >= 4) {
7243 tmp = I915_READ(DPLL_MD(crtc->pipe));
7244 pipe_config->pixel_multiplier =
7245 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7246 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7247 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7248 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7249 tmp = I915_READ(DPLL(crtc->pipe));
7250 pipe_config->pixel_multiplier =
7251 ((tmp & SDVO_MULTIPLIER_MASK)
7252 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7253 } else {
7254 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7255 * port and will be fixed up in the encoder->get_config
7256 * function. */
7257 pipe_config->pixel_multiplier = 1;
7258 }
8bcc2795
DV		 7259 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7260 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7261 /*
7262 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7263 * on 830. Filter it out here so that we don't
7264 * report errors due to that.
7265 */
7266 if (IS_I830(dev))
7267 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7268
8bcc2795
DV		 7269 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7270 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7271 } else {
7272 /* Mask out read-only status bits. */
7273 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7274 DPLL_PORTC_READY_MASK |
7275 DPLL_PORTB_READY_MASK);
8bcc2795 7276 }
6c49f241 7277
70b23a98
VS		 7278 if (IS_CHERRYVIEW(dev))
7279 chv_crtc_clock_get(crtc, pipe_config);
7280 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7281 vlv_crtc_clock_get(crtc, pipe_config);
7282 else
7283 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7284
0e8ffe1b
DV		 7285 return true;
7286}
7287
dde86e2d 7288static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7289{
7290 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7291 struct intel_encoder *encoder;
74cfd7ac 7292 u32 val, final;
13d83a67 7293 bool has_lvds = false;
199e5d79 7294 bool has_cpu_edp = false;
199e5d79 7295 bool has_panel = false;
99eb6a01
KP		 7296 bool has_ck505 = false;
7297 bool can_ssc = false;
13d83a67
JB		 7298
7299 /* We need to take the global config into account */
b2784e15 7300 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7301 switch (encoder->type) {
7302 case INTEL_OUTPUT_LVDS:
7303 has_panel = true;
7304 has_lvds = true;
7305 break;
7306 case INTEL_OUTPUT_EDP:
7307 has_panel = true;
2de6905f 7308 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7309 has_cpu_edp = true;
7310 break;
6847d71b
PZ		 7311 default:
7312 break;
13d83a67
JB		 7313 }
7314 }
7315
99eb6a01 7316 if (HAS_PCH_IBX(dev)) {
41aa3448 7317 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7318 can_ssc = has_ck505;
7319 } else {
7320 has_ck505 = false;
7321 can_ssc = true;
7322 }
7323
2de6905f
ID		 7324 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7325 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7326
7327 /* Ironlake: try to setup display ref clock before DPLL
7328 * enabling. This is only under driver's control after
7329 * PCH B stepping, previous chipset stepping should be
7330 * ignoring this setting.
7331 */
74cfd7ac
CW		 7332 val = I915_READ(PCH_DREF_CONTROL);
7333
7334 /* As we must carefully and slowly disable/enable each source in turn,
7335 * compute the final state we want first and check if we need to
7336 * make any changes at all.
7337 */
7338 final = val;
7339 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7340 if (has_ck505)
7341 final |= DREF_NONSPREAD_CK505_ENABLE;
7342 else
7343 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7344
7345 final &= ~DREF_SSC_SOURCE_MASK;
7346 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7347 final &= ~DREF_SSC1_ENABLE;
7348
7349 if (has_panel) {
7350 final |= DREF_SSC_SOURCE_ENABLE;
7351
7352 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7353 final |= DREF_SSC1_ENABLE;
7354
7355 if (has_cpu_edp) {
7356 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7357 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7358 else
7359 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7360 } else
7361 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7362 } else {
7363 final |= DREF_SSC_SOURCE_DISABLE;
7364 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7365 }
7366
7367 if (final == val)
7368 return;
7369
13d83a67 7370 /* Always enable nonspread source */
74cfd7ac 7371 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7372
99eb6a01 7373 if (has_ck505)
74cfd7ac 7374 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7375 else
74cfd7ac 7376 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7377
199e5d79 7378 if (has_panel) {
74cfd7ac
CW		 7379 val &= ~DREF_SSC_SOURCE_MASK;
7380 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7381
199e5d79 7382 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7383 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7384 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7385 val |= DREF_SSC1_ENABLE;
e77166b5 7386 } else
74cfd7ac 7387 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7388
7389 /* Get SSC going before enabling the outputs */
74cfd7ac 7390 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7391 POSTING_READ(PCH_DREF_CONTROL);
7392 udelay(200);
7393
74cfd7ac 7394 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7395
7396 /* Enable CPU source on CPU attached eDP */
199e5d79 7397 if (has_cpu_edp) {
99eb6a01 7398 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7399 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7400 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7401 } else
74cfd7ac 7402 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7403 } else
74cfd7ac 7404 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7405
74cfd7ac 7406 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7407 POSTING_READ(PCH_DREF_CONTROL);
7408 udelay(200);
7409 } else {
7410 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7411
74cfd7ac 7412 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7413
7414 /* Turn off CPU output */
74cfd7ac 7415 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7416
74cfd7ac 7417 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7418 POSTING_READ(PCH_DREF_CONTROL);
7419 udelay(200);
7420
7421 /* Turn off the SSC source */
74cfd7ac
CW		 7422 val &= ~DREF_SSC_SOURCE_MASK;
7423 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7424
7425 /* Turn off SSC1 */
74cfd7ac 7426 val &= ~DREF_SSC1_ENABLE;
199e5d79 7427
74cfd7ac 7428 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7429 POSTING_READ(PCH_DREF_CONTROL);
7430 udelay(200);
7431 }
74cfd7ac
CW		 7432
7433 BUG_ON(val != final);
13d83a67
JB		 7434}
7435
f31f2d55 7436static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7437{
f31f2d55 7438 uint32_t tmp;
dde86e2d 7439
0ff066a9
PZ		 7440 tmp = I915_READ(SOUTH_CHICKEN2);
7441 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7442 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7443
0ff066a9
PZ		 7444 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7445 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7446 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7447
0ff066a9
PZ		 7448 tmp = I915_READ(SOUTH_CHICKEN2);
7449 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7450 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7451
0ff066a9
PZ		 7452 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7453 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7454 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7455}
7456
7457/* WaMPhyProgramming:hsw */
7458static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7459{
7460 uint32_t tmp;
dde86e2d
PZ		 7461
7462 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7463 tmp &= ~(0xFF << 24);
7464 tmp |= (0x12 << 24);
7465 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7466
dde86e2d
PZ		 7467 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7468 tmp |= (1 << 11);
7469 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7470
7471 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7472 tmp |= (1 << 11);
7473 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7474
dde86e2d
PZ		 7475 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7476 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7477 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7478
7479 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7480 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7481 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7482
0ff066a9
PZ		 7483 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7484 tmp &= ~(7 << 13);
7485 tmp |= (5 << 13);
7486 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7487
0ff066a9
PZ		 7488 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7489 tmp &= ~(7 << 13);
7490 tmp |= (5 << 13);
7491 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7492
7493 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7494 tmp &= ~0xFF;
7495 tmp |= 0x1C;
7496 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7497
7498 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7499 tmp &= ~0xFF;
7500 tmp |= 0x1C;
7501 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7502
7503 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7504 tmp &= ~(0xFF << 16);
7505 tmp |= (0x1C << 16);
7506 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7507
7508 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7509 tmp &= ~(0xFF << 16);
7510 tmp |= (0x1C << 16);
7511 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7512
0ff066a9
PZ		 7513 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7514 tmp |= (1 << 27);
7515 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7516
0ff066a9
PZ		 7517 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7518 tmp |= (1 << 27);
7519 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7520
0ff066a9
PZ		 7521 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7522 tmp &= ~(0xF << 28);
7523 tmp |= (4 << 28);
7524 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7525
0ff066a9
PZ		 7526 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7527 tmp &= ~(0xF << 28);
7528 tmp |= (4 << 28);
7529 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7530}
7531
2fa86a1f
PZ		 7532/* Implements 3 different sequences from BSpec chapter "Display iCLK
7533 * Programming" based on the parameters passed:
7534 * - Sequence to enable CLKOUT_DP
7535 * - Sequence to enable CLKOUT_DP without spread
7536 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7537 */
7538static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7539 bool with_fdi)
f31f2d55
PZ		 7540{
7541 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7542 uint32_t reg, tmp;
7543
7544 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7545 with_spread = true;
7546 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7547 with_fdi, "LP PCH doesn't have FDI\n"))
7548 with_fdi = false;
f31f2d55
PZ		 7549
7550 mutex_lock(&dev_priv->dpio_lock);
7551
7552 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7553 tmp &= ~SBI_SSCCTL_DISABLE;
7554 tmp |= SBI_SSCCTL_PATHALT;
7555 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7556
7557 udelay(24);
7558
2fa86a1f
PZ		 7559 if (with_spread) {
7560 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7561 tmp &= ~SBI_SSCCTL_PATHALT;
7562 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7563
2fa86a1f
PZ		 7564 if (with_fdi) {
7565 lpt_reset_fdi_mphy(dev_priv);
7566 lpt_program_fdi_mphy(dev_priv);
7567 }
7568 }
dde86e2d 7569
2fa86a1f
PZ		 7570 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7571 SBI_GEN0 : SBI_DBUFF0;
7572 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7573 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7574 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7575
7576 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7577}
7578
47701c3b
PZ		 7579/* Sequence to disable CLKOUT_DP */
7580static void lpt_disable_clkout_dp(struct drm_device *dev)
7581{
7582 struct drm_i915_private *dev_priv = dev->dev_private;
7583 uint32_t reg, tmp;
7584
7585 mutex_lock(&dev_priv->dpio_lock);
7586
7587 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7588 SBI_GEN0 : SBI_DBUFF0;
7589 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7590 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7591 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7592
7593 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7594 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7595 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7596 tmp |= SBI_SSCCTL_PATHALT;
7597 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7598 udelay(32);
7599 }
7600 tmp |= SBI_SSCCTL_DISABLE;
7601 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7602 }
7603
7604 mutex_unlock(&dev_priv->dpio_lock);
7605}
7606
bf8fa3d3
PZ		 7607static void lpt_init_pch_refclk(struct drm_device *dev)
7608{
bf8fa3d3
PZ		 7609 struct intel_encoder *encoder;
7610 bool has_vga = false;
7611
b2784e15 7612 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7613 switch (encoder->type) {
7614 case INTEL_OUTPUT_ANALOG:
7615 has_vga = true;
7616 break;
6847d71b
PZ		 7617 default:
7618 break;
bf8fa3d3
PZ		 7619 }
7620 }
7621
47701c3b
PZ		 7622 if (has_vga)
7623 lpt_enable_clkout_dp(dev, true, true);
7624 else
7625 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7626}
7627
dde86e2d
PZ		 7628/*
7629 * Initialize reference clocks when the driver loads
7630 */
7631void intel_init_pch_refclk(struct drm_device *dev)
7632{
7633 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7634 ironlake_init_pch_refclk(dev);
7635 else if (HAS_PCH_LPT(dev))
7636 lpt_init_pch_refclk(dev);
7637}
7638
55bb9992 7639static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 7640{
55bb9992 7641 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 7642 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7643 struct drm_atomic_state *state = crtc_state->base.state;
7644 struct drm_connector_state *connector_state;
d9d444cb 7645 struct intel_encoder *encoder;
55bb9992 7646 int num_connectors = 0, i;
d9d444cb
JB		 7647 bool is_lvds = false;
7648
55bb9992
ACO		 7649 for (i = 0; i < state->num_connector; i++) {
7650 if (!state->connectors[i])
d0737e1d
ACO		 7651 continue;
7652
55bb9992
ACO		 7653 connector_state = state->connector_states[i];
7654 if (connector_state->crtc != crtc_state->base.crtc)
7655 continue;
7656
7657 encoder = to_intel_encoder(connector_state->best_encoder);
7658
d9d444cb
JB		 7659 switch (encoder->type) {
7660 case INTEL_OUTPUT_LVDS:
7661 is_lvds = true;
7662 break;
6847d71b
PZ		 7663 default:
7664 break;
d9d444cb
JB		 7665 }
7666 num_connectors++;
7667 }
7668
7669 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7670 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7671 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7672 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7673 }
7674
7675 return 120000;
7676}
7677
6ff93609 7678static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7679{
c8203565 7680 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7682 int pipe = intel_crtc->pipe;
c8203565
PZ		 7683 uint32_t val;
7684
78114071 7685 val = 0;
c8203565 7686
6e3c9717 7687 switch (intel_crtc->config->pipe_bpp) {
c8203565 7688 case 18:
dfd07d72 7689 val |= PIPECONF_6BPC;
c8203565
PZ		 7690 break;
7691 case 24:
dfd07d72 7692 val |= PIPECONF_8BPC;
c8203565
PZ		 7693 break;
7694 case 30:
dfd07d72 7695 val |= PIPECONF_10BPC;
c8203565
PZ		 7696 break;
7697 case 36:
dfd07d72 7698 val |= PIPECONF_12BPC;
c8203565
PZ		 7699 break;
7700 default:
cc769b62
PZ		 7701 /* Case prevented by intel_choose_pipe_bpp_dither. */
7702 BUG();
c8203565
PZ		 7703 }
7704
6e3c9717 7705 if (intel_crtc->config->dither)
c8203565
PZ		 7706 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7707
6e3c9717 7708 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7709 val |= PIPECONF_INTERLACED_ILK;
7710 else
7711 val |= PIPECONF_PROGRESSIVE;
7712
6e3c9717 7713 if (intel_crtc->config->limited_color_range)
3685a8f3 7714 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7715
c8203565
PZ		 7716 I915_WRITE(PIPECONF(pipe), val);
7717 POSTING_READ(PIPECONF(pipe));
7718}
7719
86d3efce
VS		 7720/*
7721 * Set up the pipe CSC unit.
7722 *
7723 * Currently only full range RGB to limited range RGB conversion
7724 * is supported, but eventually this should handle various
7725 * RGB<->YCbCr scenarios as well.
7726 */
50f3b016 7727static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7728{
7729 struct drm_device *dev = crtc->dev;
7730 struct drm_i915_private *dev_priv = dev->dev_private;
7731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7732 int pipe = intel_crtc->pipe;
7733 uint16_t coeff = 0x7800; /* 1.0 */
7734
7735 /*
7736 * TODO: Check what kind of values actually come out of the pipe
7737 * with these coeff/postoff values and adjust to get the best
7738 * accuracy. Perhaps we even need to take the bpc value into
7739 * consideration.
7740 */
7741
6e3c9717 7742 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7743 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7744
7745 /*
7746 * GY/GU and RY/RU should be the other way around according
7747 * to BSpec, but reality doesn't agree. Just set them up in
7748 * a way that results in the correct picture.
7749 */
7750 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7751 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7752
7753 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7754 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7755
7756 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7757 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7758
7759 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7760 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7761 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7762
7763 if (INTEL_INFO(dev)->gen > 6) {
7764 uint16_t postoff = 0;
7765
6e3c9717 7766 if (intel_crtc->config->limited_color_range)
32cf0cb0 7767 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7768
7769 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7770 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7771 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7772
7773 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7774 } else {
7775 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7776
6e3c9717 7777 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7778 mode |= CSC_BLACK_SCREEN_OFFSET;
7779
7780 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7781 }
7782}
7783
6ff93609 7784static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7785{
756f85cf
PZ		 7786 struct drm_device *dev = crtc->dev;
7787 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7789 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7790 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7791 uint32_t val;
7792
3eff4faa 7793 val = 0;
ee2b0b38 7794
6e3c9717 7795 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7796 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7797
6e3c9717 7798 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7799 val |= PIPECONF_INTERLACED_ILK;
7800 else
7801 val |= PIPECONF_PROGRESSIVE;
7802
702e7a56
PZ		 7803 I915_WRITE(PIPECONF(cpu_transcoder), val);
7804 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7805
7806 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7807 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7808
3cdf122c 7809 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7810 val = 0;
7811
6e3c9717 7812 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7813 case 18:
7814 val |= PIPEMISC_DITHER_6_BPC;
7815 break;
7816 case 24:
7817 val |= PIPEMISC_DITHER_8_BPC;
7818 break;
7819 case 30:
7820 val |= PIPEMISC_DITHER_10_BPC;
7821 break;
7822 case 36:
7823 val |= PIPEMISC_DITHER_12_BPC;
7824 break;
7825 default:
7826 /* Case prevented by pipe_config_set_bpp. */
7827 BUG();
7828 }
7829
6e3c9717 7830 if (intel_crtc->config->dither)
756f85cf
PZ		 7831 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7832
7833 I915_WRITE(PIPEMISC(pipe), val);
7834 }
ee2b0b38
PZ		 7835}
7836
6591c6e4 7837static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 7838 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 7839 intel_clock_t *clock,
7840 bool *has_reduced_clock,
7841 intel_clock_t *reduced_clock)
7842{
7843 struct drm_device *dev = crtc->dev;
7844 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 7845 int refclk;
d4906093 7846 const intel_limit_t *limit;
a16af721 7847 bool ret, is_lvds = false;
79e53945 7848
a93e255f 7849 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 7850
55bb9992 7851 refclk = ironlake_get_refclk(crtc_state);
79e53945 7852
d4906093
ML		 7853 /*
7854 * Returns a set of divisors for the desired target clock with the given
7855 * refclk, or FALSE. The returned values represent the clock equation:
7856 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7857 */
a93e255f
ACO		 7858 limit = intel_limit(crtc_state, refclk);
7859 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7860 crtc_state->port_clock,
ee9300bb 7861 refclk, NULL, clock);
6591c6e4
PZ		 7862 if (!ret)
7863 return false;
cda4b7d3 7864
ddc9003c 7865 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 7866 /*
7867 * Ensure we match the reduced clock's P to the target clock.
7868 * If the clocks don't match, we can't switch the display clock
7869 * by using the FP0/FP1. In such case we will disable the LVDS
7870 * downclock feature.
7871 */
ee9300bb 7872 *has_reduced_clock =
a93e255f 7873 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 7874 dev_priv->lvds_downclock,
7875 refclk, clock,
7876 reduced_clock);
652c393a 7877 }
61e9653f 7878
6591c6e4
PZ		 7879 return true;
7880}
7881
d4b1931c
PZ		 7882int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7883{
7884 /*
7885 * Account for spread spectrum to avoid
7886 * oversubscribing the link. Max center spread
7887 * is 2.5%; use 5% for safety's sake.
7888 */
7889 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 7890 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 7891}
7892
7429e9d4 7893static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 7894{
7429e9d4 7895 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 7896}
7897
de13a2e3 7898static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 7899 struct intel_crtc_state *crtc_state,
7429e9d4 7900 u32 *fp,
9a7c7890 7901 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 7902{
de13a2e3 7903 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 7904 struct drm_device *dev = crtc->dev;
7905 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7906 struct drm_atomic_state *state = crtc_state->base.state;
7907 struct drm_connector_state *connector_state;
7908 struct intel_encoder *encoder;
de13a2e3 7909 uint32_t dpll;
55bb9992 7910 int factor, num_connectors = 0, i;
09ede541 7911 bool is_lvds = false, is_sdvo = false;
79e53945 7912
55bb9992
ACO		 7913 for (i = 0; i < state->num_connector; i++) {
7914 if (!state->connectors[i])
d0737e1d
ACO		 7915 continue;
7916
55bb9992
ACO		 7917 connector_state = state->connector_states[i];
7918 if (connector_state->crtc != crtc_state->base.crtc)
7919 continue;
7920
7921 encoder = to_intel_encoder(connector_state->best_encoder);
7922
7923 switch (encoder->type) {
79e53945
JB		 7924 case INTEL_OUTPUT_LVDS:
7925 is_lvds = true;
7926 break;
7927 case INTEL_OUTPUT_SDVO:
7d57382e 7928 case INTEL_OUTPUT_HDMI:
79e53945 7929 is_sdvo = true;
79e53945 7930 break;
6847d71b
PZ		 7931 default:
7932 break;
79e53945 7933 }
43565a06 7934
c751ce4f 7935 num_connectors++;
79e53945 7936 }
79e53945 7937
c1858123 7938 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 7939 factor = 21;
7940 if (is_lvds) {
7941 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 7942 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 7943 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 7944 factor = 25;
190f68c5 7945 } else if (crtc_state->sdvo_tv_clock)
8febb297 7946 factor = 20;
c1858123 7947
190f68c5 7948 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 7949 *fp |= FP_CB_TUNE;
2c07245f 7950
9a7c7890
DV		 7951 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7952 *fp2 |= FP_CB_TUNE;
7953
5eddb70b 7954 dpll = 0;
2c07245f 7955
a07d6787
EA		 7956 if (is_lvds)
7957 dpll |= DPLLB_MODE_LVDS;
7958 else
7959 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 7960
190f68c5 7961 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 7962 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 7963
7964 if (is_sdvo)
4a33e48d 7965 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 7966 if (crtc_state->has_dp_encoder)
4a33e48d 7967 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 7968
a07d6787 7969 /* compute bitmask from p1 value */
190f68c5 7970 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 7971 /* also FPA1 */
190f68c5 7972 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 7973
190f68c5 7974 switch (crtc_state->dpll.p2) {
a07d6787
EA		 7975 case 5:
7976 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7977 break;
7978 case 7:
7979 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7980 break;
7981 case 10:
7982 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7983 break;
7984 case 14:
7985 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7986 break;
79e53945
JB		 7987 }
7988
b4c09f3b 7989 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 7990 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 7991 else
7992 dpll |= PLL_REF_INPUT_DREFCLK;
7993
959e16d6 7994 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 7995}
7996
190f68c5
ACO		 7997static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7998 struct intel_crtc_state *crtc_state)
de13a2e3 7999{
c7653199 8000 struct drm_device *dev = crtc->base.dev;
de13a2e3 8001 intel_clock_t clock, reduced_clock;
cbbab5bd 8002 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8003 bool ok, has_reduced_clock = false;
8b47047b 8004 bool is_lvds = false;
e2b78267 8005 struct intel_shared_dpll *pll;
de13a2e3 8006
409ee761 8007 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8008
5dc5298b
PZ		 8009 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8010 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8011
190f68c5 8012 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8013 &has_reduced_clock, &reduced_clock);
190f68c5 8014 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8015 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8016 return -EINVAL;
79e53945 8017 }
f47709a9 8018 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8019 if (!crtc_state->clock_set) {
8020 crtc_state->dpll.n = clock.n;
8021 crtc_state->dpll.m1 = clock.m1;
8022 crtc_state->dpll.m2 = clock.m2;
8023 crtc_state->dpll.p1 = clock.p1;
8024 crtc_state->dpll.p2 = clock.p2;
f47709a9 8025 }
79e53945 8026
5dc5298b 8027 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8028 if (crtc_state->has_pch_encoder) {
8029 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8030 if (has_reduced_clock)
7429e9d4 8031 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8032
190f68c5 8033 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8034 &fp, &reduced_clock,
8035 has_reduced_clock ? &fp2 : NULL);
8036
190f68c5
ACO		 8037 crtc_state->dpll_hw_state.dpll = dpll;
8038 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8039 if (has_reduced_clock)
190f68c5 8040 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8041 else
190f68c5 8042 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8043
190f68c5 8044 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8045 if (pll == NULL) {
84f44ce7 8046 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8047 pipe_name(crtc->pipe));
4b645f14
JB		 8048 return -EINVAL;
8049 }
3fb37703 8050 }
79e53945 8051
ab585dea 8052 if (is_lvds && has_reduced_clock)
c7653199 8053 crtc->lowfreq_avail = true;
bcd644e0 8054 else
c7653199 8055 crtc->lowfreq_avail = false;
e2b78267 8056
c8f7a0db 8057 return 0;
79e53945
JB		 8058}
8059
eb14cb74
VS		 8060static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8061 struct intel_link_m_n *m_n)
8062{
8063 struct drm_device *dev = crtc->base.dev;
8064 struct drm_i915_private *dev_priv = dev->dev_private;
8065 enum pipe pipe = crtc->pipe;
8066
8067 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8068 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8069 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8070 & ~TU_SIZE_MASK;
8071 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8072 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8073 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8074}
8075
8076static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8077 enum transcoder transcoder,
b95af8be
VK		 8078 struct intel_link_m_n *m_n,
8079 struct intel_link_m_n *m2_n2)
72419203
DV		 8080{
8081 struct drm_device *dev = crtc->base.dev;
8082 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8083 enum pipe pipe = crtc->pipe;
72419203 8084
eb14cb74
VS		 8085 if (INTEL_INFO(dev)->gen >= 5) {
8086 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8087 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8088 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8089 & ~TU_SIZE_MASK;
8090 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8091 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8092 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8093 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8094 * gen < 8) and if DRRS is supported (to make sure the
8095 * registers are not unnecessarily read).
8096 */
8097 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8098 crtc->config->has_drrs) {
b95af8be
VK		 8099 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8100 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8101 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8102 & ~TU_SIZE_MASK;
8103 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8104 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8105 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8106 }
eb14cb74
VS		 8107 } else {
8108 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8109 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8110 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8111 & ~TU_SIZE_MASK;
8112 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8113 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8114 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8115 }
8116}
8117
8118void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8119 struct intel_crtc_state *pipe_config)
eb14cb74 8120{
681a8504 8121 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8122 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8123 else
8124 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8125 &pipe_config->dp_m_n,
8126 &pipe_config->dp_m2_n2);
eb14cb74 8127}
72419203 8128
eb14cb74 8129static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8130 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8131{
8132 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8133 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8134}
8135
bd2e244f 8136static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8137 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8138{
8139 struct drm_device *dev = crtc->base.dev;
8140 struct drm_i915_private *dev_priv = dev->dev_private;
8141 uint32_t tmp;
8142
8143 tmp = I915_READ(PS_CTL(crtc->pipe));
8144
8145 if (tmp & PS_ENABLE) {
8146 pipe_config->pch_pfit.enabled = true;
8147 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
8148 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
8149 }
8150}
8151
5724dbd1
DL		 8152static void
8153skylake_get_initial_plane_config(struct intel_crtc *crtc,
8154 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8155{
8156 struct drm_device *dev = crtc->base.dev;
8157 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8158 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8159 int pipe = crtc->pipe;
8160 int fourcc, pixel_format;
6761dd31 8161 unsigned int aligned_height;
bc8d7dff 8162 struct drm_framebuffer *fb;
1b842c89 8163 struct intel_framebuffer *intel_fb;
bc8d7dff 8164
d9806c9f 8165 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8166 if (!intel_fb) {
bc8d7dff
DL		 8167 DRM_DEBUG_KMS("failed to alloc fb\n");
8168 return;
8169 }
8170
1b842c89
DL		 8171 fb = &intel_fb->base;
8172
bc8d7dff 8173 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8174 if (!(val & PLANE_CTL_ENABLE))
8175 goto error;
8176
bc8d7dff
DL		 8177 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8178 fourcc = skl_format_to_fourcc(pixel_format,
8179 val & PLANE_CTL_ORDER_RGBX,
8180 val & PLANE_CTL_ALPHA_MASK);
8181 fb->pixel_format = fourcc;
8182 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8183
40f46283
DL		 8184 tiling = val & PLANE_CTL_TILED_MASK;
8185 switch (tiling) {
8186 case PLANE_CTL_TILED_LINEAR:
8187 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8188 break;
8189 case PLANE_CTL_TILED_X:
8190 plane_config->tiling = I915_TILING_X;
8191 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8192 break;
8193 case PLANE_CTL_TILED_Y:
8194 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8195 break;
8196 case PLANE_CTL_TILED_YF:
8197 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8198 break;
8199 default:
8200 MISSING_CASE(tiling);
8201 goto error;
8202 }
8203
bc8d7dff
DL		 8204 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8205 plane_config->base = base;
8206
8207 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8208
8209 val = I915_READ(PLANE_SIZE(pipe, 0));
8210 fb->height = ((val >> 16) & 0xfff) + 1;
8211 fb->width = ((val >> 0) & 0x1fff) + 1;
8212
8213 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8214 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8215 fb->pixel_format);
bc8d7dff
DL		 8216 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8217
8218 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8219 fb->pixel_format,
8220 fb->modifier[0]);
bc8d7dff 8221
f37b5c2b 8222 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8223
8224 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8225 pipe_name(pipe), fb->width, fb->height,
8226 fb->bits_per_pixel, base, fb->pitches[0],
8227 plane_config->size);
8228
2d14030b 8229 plane_config->fb = intel_fb;
bc8d7dff
DL		 8230 return;
8231
8232error:
8233 kfree(fb);
8234}
8235
2fa2fe9a 8236static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8237 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8238{
8239 struct drm_device *dev = crtc->base.dev;
8240 struct drm_i915_private *dev_priv = dev->dev_private;
8241 uint32_t tmp;
8242
8243 tmp = I915_READ(PF_CTL(crtc->pipe));
8244
8245 if (tmp & PF_ENABLE) {
fd4daa9c 8246 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8247 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8248 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8249
8250 /* We currently do not free assignements of panel fitters on
8251 * ivb/hsw (since we don't use the higher upscaling modes which
8252 * differentiates them) so just WARN about this case for now. */
8253 if (IS_GEN7(dev)) {
8254 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8255 PF_PIPE_SEL_IVB(crtc->pipe));
8256 }
2fa2fe9a 8257 }
79e53945
JB		 8258}
8259
5724dbd1
DL		 8260static void
8261ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8262 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8263{
8264 struct drm_device *dev = crtc->base.dev;
8265 struct drm_i915_private *dev_priv = dev->dev_private;
8266 u32 val, base, offset;
aeee5a49 8267 int pipe = crtc->pipe;
4c6baa59 8268 int fourcc, pixel_format;
6761dd31 8269 unsigned int aligned_height;
b113d5ee 8270 struct drm_framebuffer *fb;
1b842c89 8271 struct intel_framebuffer *intel_fb;
4c6baa59 8272
42a7b088
DL		 8273 val = I915_READ(DSPCNTR(pipe));
8274 if (!(val & DISPLAY_PLANE_ENABLE))
8275 return;
8276
d9806c9f 8277 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8278 if (!intel_fb) {
4c6baa59
JB		 8279 DRM_DEBUG_KMS("failed to alloc fb\n");
8280 return;
8281 }
8282
1b842c89
DL		 8283 fb = &intel_fb->base;
8284
18c5247e
DV		 8285 if (INTEL_INFO(dev)->gen >= 4) {
8286 if (val & DISPPLANE_TILED) {
49af449b 8287 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8288 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8289 }
8290 }
4c6baa59
JB		 8291
8292 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8293 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8294 fb->pixel_format = fourcc;
8295 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8296
aeee5a49 8297 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8298 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8299 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8300 } else {
49af449b 8301 if (plane_config->tiling)
aeee5a49 8302 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8303 else
aeee5a49 8304 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8305 }
8306 plane_config->base = base;
8307
8308 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8309 fb->width = ((val >> 16) & 0xfff) + 1;
8310 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8311
8312 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8313 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8314
b113d5ee 8315 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8316 fb->pixel_format,
8317 fb->modifier[0]);
4c6baa59 8318
f37b5c2b 8319 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8320
2844a921
DL		 8321 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8322 pipe_name(pipe), fb->width, fb->height,
8323 fb->bits_per_pixel, base, fb->pitches[0],
8324 plane_config->size);
b113d5ee 8325
2d14030b 8326 plane_config->fb = intel_fb;
4c6baa59
JB		 8327}
8328
0e8ffe1b 8329static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8330 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8331{
8332 struct drm_device *dev = crtc->base.dev;
8333 struct drm_i915_private *dev_priv = dev->dev_private;
8334 uint32_t tmp;
8335
f458ebbc
DV		 8336 if (!intel_display_power_is_enabled(dev_priv,
8337 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8338 return false;
8339
e143a21c 8340 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8341 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8342
0e8ffe1b
DV		 8343 tmp = I915_READ(PIPECONF(crtc->pipe));
8344 if (!(tmp & PIPECONF_ENABLE))
8345 return false;
8346
42571aef
VS		 8347 switch (tmp & PIPECONF_BPC_MASK) {
8348 case PIPECONF_6BPC:
8349 pipe_config->pipe_bpp = 18;
8350 break;
8351 case PIPECONF_8BPC:
8352 pipe_config->pipe_bpp = 24;
8353 break;
8354 case PIPECONF_10BPC:
8355 pipe_config->pipe_bpp = 30;
8356 break;
8357 case PIPECONF_12BPC:
8358 pipe_config->pipe_bpp = 36;
8359 break;
8360 default:
8361 break;
8362 }
8363
b5a9fa09
DV		 8364 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8365 pipe_config->limited_color_range = true;
8366
ab9412ba 8367 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8368 struct intel_shared_dpll *pll;
8369
88adfff1
DV		 8370 pipe_config->has_pch_encoder = true;
8371
627eb5a3
DV		 8372 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8373 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8374 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8375
8376 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8377
c0d43d62 8378 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8379 pipe_config->shared_dpll =
8380 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8381 } else {
8382 tmp = I915_READ(PCH_DPLL_SEL);
8383 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8384 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8385 else
8386 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8387 }
66e985c0
DV		 8388
8389 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8390
8391 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8392 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8393
8394 tmp = pipe_config->dpll_hw_state.dpll;
8395 pipe_config->pixel_multiplier =
8396 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8397 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8398
8399 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8400 } else {
8401 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8402 }
8403
1bd1bd80
DV		 8404 intel_get_pipe_timings(crtc, pipe_config);
8405
2fa2fe9a
DV		 8406 ironlake_get_pfit_config(crtc, pipe_config);
8407
0e8ffe1b
DV		 8408 return true;
8409}
8410
be256dc7
PZ		 8411static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8412{
8413 struct drm_device *dev = dev_priv->dev;
be256dc7 8414 struct intel_crtc *crtc;
be256dc7 8415
d3fcc808 8416 for_each_intel_crtc(dev, crtc)
e2c719b7 8417 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8418 pipe_name(crtc->pipe));
8419
e2c719b7
RC		 8420 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8421 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8422 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8423 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8424 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8425 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8426 "CPU PWM1 enabled\n");
c5107b87 8427 if (IS_HASWELL(dev))
e2c719b7 8428 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8429 "CPU PWM2 enabled\n");
e2c719b7 8430 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8431 "PCH PWM1 enabled\n");
e2c719b7 8432 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8433 "Utility pin enabled\n");
e2c719b7 8434 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8435
9926ada1
PZ		 8436 /*
8437 * In theory we can still leave IRQs enabled, as long as only the HPD
8438 * interrupts remain enabled. We used to check for that, but since it's
8439 * gen-specific and since we only disable LCPLL after we fully disable
8440 * the interrupts, the check below should be enough.
8441 */
e2c719b7 8442 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8443}
8444
9ccd5aeb
PZ		 8445static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8446{
8447 struct drm_device *dev = dev_priv->dev;
8448
8449 if (IS_HASWELL(dev))
8450 return I915_READ(D_COMP_HSW);
8451 else
8452 return I915_READ(D_COMP_BDW);
8453}
8454
3c4c9b81
PZ		 8455static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8456{
8457 struct drm_device *dev = dev_priv->dev;
8458
8459 if (IS_HASWELL(dev)) {
8460 mutex_lock(&dev_priv->rps.hw_lock);
8461 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8462 val))
f475dadf 8463 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8464 mutex_unlock(&dev_priv->rps.hw_lock);
8465 } else {
9ccd5aeb
PZ		 8466 I915_WRITE(D_COMP_BDW, val);
8467 POSTING_READ(D_COMP_BDW);
3c4c9b81 8468 }
be256dc7
PZ		 8469}
8470
8471/*
8472 * This function implements pieces of two sequences from BSpec:
8473 * - Sequence for display software to disable LCPLL
8474 * - Sequence for display software to allow package C8+
8475 * The steps implemented here are just the steps that actually touch the LCPLL
8476 * register. Callers should take care of disabling all the display engine
8477 * functions, doing the mode unset, fixing interrupts, etc.
8478 */
6ff58d53
PZ		 8479static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8480 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8481{
8482 uint32_t val;
8483
8484 assert_can_disable_lcpll(dev_priv);
8485
8486 val = I915_READ(LCPLL_CTL);
8487
8488 if (switch_to_fclk) {
8489 val |= LCPLL_CD_SOURCE_FCLK;
8490 I915_WRITE(LCPLL_CTL, val);
8491
8492 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8493 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8494 DRM_ERROR("Switching to FCLK failed\n");
8495
8496 val = I915_READ(LCPLL_CTL);
8497 }
8498
8499 val |= LCPLL_PLL_DISABLE;
8500 I915_WRITE(LCPLL_CTL, val);
8501 POSTING_READ(LCPLL_CTL);
8502
8503 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8504 DRM_ERROR("LCPLL still locked\n");
8505
9ccd5aeb 8506 val = hsw_read_dcomp(dev_priv);
be256dc7 8507 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8508 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8509 ndelay(100);
8510
9ccd5aeb
PZ		 8511 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8512 1))
be256dc7
PZ		 8513 DRM_ERROR("D_COMP RCOMP still in progress\n");
8514
8515 if (allow_power_down) {
8516 val = I915_READ(LCPLL_CTL);
8517 val |= LCPLL_POWER_DOWN_ALLOW;
8518 I915_WRITE(LCPLL_CTL, val);
8519 POSTING_READ(LCPLL_CTL);
8520 }
8521}
8522
8523/*
8524 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8525 * source.
8526 */
6ff58d53 8527static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8528{
8529 uint32_t val;
8530
8531 val = I915_READ(LCPLL_CTL);
8532
8533 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8534 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8535 return;
8536
a8a8bd54
PZ		 8537 /*
8538 * Make sure we're not on PC8 state before disabling PC8, otherwise
8539 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8540 */
59bad947 8541 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8542
be256dc7
PZ		 8543 if (val & LCPLL_POWER_DOWN_ALLOW) {
8544 val &= ~LCPLL_POWER_DOWN_ALLOW;
8545 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8546 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8547 }
8548
9ccd5aeb 8549 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8550 val |= D_COMP_COMP_FORCE;
8551 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8552 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8553
8554 val = I915_READ(LCPLL_CTL);
8555 val &= ~LCPLL_PLL_DISABLE;
8556 I915_WRITE(LCPLL_CTL, val);
8557
8558 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8559 DRM_ERROR("LCPLL not locked yet\n");
8560
8561 if (val & LCPLL_CD_SOURCE_FCLK) {
8562 val = I915_READ(LCPLL_CTL);
8563 val &= ~LCPLL_CD_SOURCE_FCLK;
8564 I915_WRITE(LCPLL_CTL, val);
8565
8566 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8567 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8568 DRM_ERROR("Switching back to LCPLL failed\n");
8569 }
215733fa 8570
59bad947 8571 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8572}
8573
765dab67
PZ		 8574/*
8575 * Package states C8 and deeper are really deep PC states that can only be
8576 * reached when all the devices on the system allow it, so even if the graphics
8577 * device allows PC8+, it doesn't mean the system will actually get to these
8578 * states. Our driver only allows PC8+ when going into runtime PM.
8579 *
8580 * The requirements for PC8+ are that all the outputs are disabled, the power
8581 * well is disabled and most interrupts are disabled, and these are also
8582 * requirements for runtime PM. When these conditions are met, we manually do
8583 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8584 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8585 * hang the machine.
8586 *
8587 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8588 * the state of some registers, so when we come back from PC8+ we need to
8589 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8590 * need to take care of the registers kept by RC6. Notice that this happens even
8591 * if we don't put the device in PCI D3 state (which is what currently happens
8592 * because of the runtime PM support).
8593 *
8594 * For more, read "Display Sequences for Package C8" on the hardware
8595 * documentation.
8596 */
a14cb6fc 8597void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8598{
c67a470b
PZ		 8599 struct drm_device *dev = dev_priv->dev;
8600 uint32_t val;
8601
c67a470b
PZ		 8602 DRM_DEBUG_KMS("Enabling package C8+\n");
8603
c67a470b
PZ		 8604 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8605 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8606 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8607 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8608 }
8609
8610 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8611 hsw_disable_lcpll(dev_priv, true, true);
8612}
8613
a14cb6fc 8614void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8615{
8616 struct drm_device *dev = dev_priv->dev;
8617 uint32_t val;
8618
c67a470b
PZ		 8619 DRM_DEBUG_KMS("Disabling package C8+\n");
8620
8621 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8622 lpt_init_pch_refclk(dev);
8623
8624 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8625 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8626 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8627 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8628 }
8629
8630 intel_prepare_ddi(dev);
c67a470b
PZ		 8631}
8632
190f68c5
ACO		 8633static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8634 struct intel_crtc_state *crtc_state)
09b4ddf9 8635{
190f68c5 8636 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8637 return -EINVAL;
716c2e55 8638
c7653199 8639 crtc->lowfreq_avail = false;
644cef34 8640
c8f7a0db 8641 return 0;
79e53945
JB		 8642}
8643
96b7dfb7
S		 8644static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8645 enum port port,
5cec258b 8646 struct intel_crtc_state *pipe_config)
96b7dfb7 8647{
3148ade7 8648 u32 temp, dpll_ctl1;
96b7dfb7
S		 8649
8650 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8651 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8652
8653 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8654 case SKL_DPLL0:
8655 /*
8656 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8657 * of the shared DPLL framework and thus needs to be read out
8658 * separately
8659 */
8660 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8661 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8662 break;
96b7dfb7
S		 8663 case SKL_DPLL1:
8664 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8665 break;
8666 case SKL_DPLL2:
8667 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8668 break;
8669 case SKL_DPLL3:
8670 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8671 break;
96b7dfb7
S		 8672 }
8673}
8674
7d2c8175
DL		 8675static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8676 enum port port,
5cec258b 8677 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8678{
8679 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8680
8681 switch (pipe_config->ddi_pll_sel) {
8682 case PORT_CLK_SEL_WRPLL1:
8683 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8684 break;
8685 case PORT_CLK_SEL_WRPLL2:
8686 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8687 break;
8688 }
8689}
8690
26804afd 8691static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8692 struct intel_crtc_state *pipe_config)
26804afd
DV		 8693{
8694 struct drm_device *dev = crtc->base.dev;
8695 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8696 struct intel_shared_dpll *pll;
26804afd
DV		 8697 enum port port;
8698 uint32_t tmp;
8699
8700 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8701
8702 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8703
96b7dfb7
S		 8704 if (IS_SKYLAKE(dev))
8705 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8706 else
8707 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8708
d452c5b6
DV		 8709 if (pipe_config->shared_dpll >= 0) {
8710 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8711
8712 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8713 &pipe_config->dpll_hw_state));
8714 }
8715
26804afd
DV		 8716 /*
8717 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8718 * DDI E. So just check whether this pipe is wired to DDI E and whether
8719 * the PCH transcoder is on.
8720 */
ca370455
DL		 8721 if (INTEL_INFO(dev)->gen < 9 &&
8722 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8723 pipe_config->has_pch_encoder = true;
8724
8725 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8726 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8727 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8728
8729 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8730 }
8731}
8732
0e8ffe1b 8733static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8734 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8735{
8736 struct drm_device *dev = crtc->base.dev;
8737 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8738 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8739 uint32_t tmp;
8740
f458ebbc 8741 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8742 POWER_DOMAIN_PIPE(crtc->pipe)))
8743 return false;
8744
e143a21c 8745 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8746 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8747
eccb140b
DV		 8748 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8749 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8750 enum pipe trans_edp_pipe;
8751 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8752 default:
8753 WARN(1, "unknown pipe linked to edp transcoder\n");
8754 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8755 case TRANS_DDI_EDP_INPUT_A_ON:
8756 trans_edp_pipe = PIPE_A;
8757 break;
8758 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8759 trans_edp_pipe = PIPE_B;
8760 break;
8761 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8762 trans_edp_pipe = PIPE_C;
8763 break;
8764 }
8765
8766 if (trans_edp_pipe == crtc->pipe)
8767 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8768 }
8769
f458ebbc 8770 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8771 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8772 return false;
8773
eccb140b 8774 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8775 if (!(tmp & PIPECONF_ENABLE))
8776 return false;
8777
26804afd 8778 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8779
1bd1bd80
DV		 8780 intel_get_pipe_timings(crtc, pipe_config);
8781
2fa2fe9a 8782 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8783 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8784 if (IS_SKYLAKE(dev))
8785 skylake_get_pfit_config(crtc, pipe_config);
8786 else
8787 ironlake_get_pfit_config(crtc, pipe_config);
8788 }
88adfff1 8789
e59150dc
JB		 8790 if (IS_HASWELL(dev))
8791 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8792 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8793
ebb69c95
CT		 8794 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8795 pipe_config->pixel_multiplier =
8796 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8797 } else {
8798 pipe_config->pixel_multiplier = 1;
8799 }
6c49f241 8800
0e8ffe1b
DV		 8801 return true;
8802}
8803
560b85bb
CW		 8804static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8805{
8806 struct drm_device *dev = crtc->dev;
8807 struct drm_i915_private *dev_priv = dev->dev_private;
8808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 8809 uint32_t cntl = 0, size = 0;
560b85bb 8810
dc41c154 8811 if (base) {
3dd512fb
MR		 8812 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8813 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 8814 unsigned int stride = roundup_pow_of_two(width) * 4;
8815
8816 switch (stride) {
8817 default:
8818 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8819 width, stride);
8820 stride = 256;
8821 /* fallthrough */
8822 case 256:
8823 case 512:
8824 case 1024:
8825 case 2048:
8826 break;
4b0e333e
CW		 8827 }
8828
dc41c154
VS		 8829 cntl |= CURSOR_ENABLE |
8830 CURSOR_GAMMA_ENABLE |
8831 CURSOR_FORMAT_ARGB |
8832 CURSOR_STRIDE(stride);
8833
8834 size = (height << 12) | width;
4b0e333e 8835 }
560b85bb 8836
dc41c154
VS		 8837 if (intel_crtc->cursor_cntl != 0 &&
8838 (intel_crtc->cursor_base != base ||
8839 intel_crtc->cursor_size != size ||
8840 intel_crtc->cursor_cntl != cntl)) {
8841 /* On these chipsets we can only modify the base/size/stride
8842 * whilst the cursor is disabled.
8843 */
8844 I915_WRITE(_CURACNTR, 0);
4b0e333e 8845 POSTING_READ(_CURACNTR);
dc41c154 8846 intel_crtc->cursor_cntl = 0;
4b0e333e 8847 }
560b85bb 8848
99d1f387 8849 if (intel_crtc->cursor_base != base) {
9db4a9c7 8850 I915_WRITE(_CURABASE, base);
99d1f387
VS		 8851 intel_crtc->cursor_base = base;
8852 }
4726e0b0 8853
dc41c154
VS		 8854 if (intel_crtc->cursor_size != size) {
8855 I915_WRITE(CURSIZE, size);
8856 intel_crtc->cursor_size = size;
4b0e333e 8857 }
560b85bb 8858
4b0e333e 8859 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 8860 I915_WRITE(_CURACNTR, cntl);
8861 POSTING_READ(_CURACNTR);
4b0e333e 8862 intel_crtc->cursor_cntl = cntl;
560b85bb 8863 }
560b85bb
CW		 8864}
8865
560b85bb 8866static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 8867{
8868 struct drm_device *dev = crtc->dev;
8869 struct drm_i915_private *dev_priv = dev->dev_private;
8870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8871 int pipe = intel_crtc->pipe;
4b0e333e
CW		 8872 uint32_t cntl;
8873
8874 cntl = 0;
8875 if (base) {
8876 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 8877 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 8878 case 64:
8879 cntl |= CURSOR_MODE_64_ARGB_AX;
8880 break;
8881 case 128:
8882 cntl |= CURSOR_MODE_128_ARGB_AX;
8883 break;
8884 case 256:
8885 cntl |= CURSOR_MODE_256_ARGB_AX;
8886 break;
8887 default:
3dd512fb 8888 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 8889 return;
65a21cd6 8890 }
4b0e333e 8891 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 8892
8893 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8894 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 8895 }
65a21cd6 8896
8e7d688b 8897 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 8898 cntl |= CURSOR_ROTATE_180;
8899
4b0e333e
CW		 8900 if (intel_crtc->cursor_cntl != cntl) {
8901 I915_WRITE(CURCNTR(pipe), cntl);
8902 POSTING_READ(CURCNTR(pipe));
8903 intel_crtc->cursor_cntl = cntl;
65a21cd6 8904 }
4b0e333e 8905
65a21cd6 8906 /* and commit changes on next vblank */
5efb3e28
VS		 8907 I915_WRITE(CURBASE(pipe), base);
8908 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 8909
8910 intel_crtc->cursor_base = base;
65a21cd6
JB		 8911}
8912
cda4b7d3 8913/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 8914static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8915 bool on)
cda4b7d3
CW		 8916{
8917 struct drm_device *dev = crtc->dev;
8918 struct drm_i915_private *dev_priv = dev->dev_private;
8919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8920 int pipe = intel_crtc->pipe;
3d7d6510
MR		 8921 int x = crtc->cursor_x;
8922 int y = crtc->cursor_y;
d6e4db15 8923 u32 base = 0, pos = 0;
cda4b7d3 8924
d6e4db15 8925 if (on)
cda4b7d3 8926 base = intel_crtc->cursor_addr;
cda4b7d3 8927
6e3c9717 8928 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 8929 base = 0;
8930
6e3c9717 8931 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 8932 base = 0;
8933
8934 if (x < 0) {
3dd512fb 8935 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 8936 base = 0;
8937
8938 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8939 x = -x;
8940 }
8941 pos |= x << CURSOR_X_SHIFT;
8942
8943 if (y < 0) {
3dd512fb 8944 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 8945 base = 0;
8946
8947 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8948 y = -y;
8949 }
8950 pos |= y << CURSOR_Y_SHIFT;
8951
4b0e333e 8952 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 8953 return;
8954
5efb3e28
VS		 8955 I915_WRITE(CURPOS(pipe), pos);
8956
4398ad45
VS		 8957 /* ILK+ do this automagically */
8958 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 8959 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 8960 base += (intel_crtc->base.cursor->state->crtc_h *
8961 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 8962 }
8963
8ac54669 8964 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 8965 i845_update_cursor(crtc, base);
8966 else
8967 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 8968}
8969
dc41c154
VS		 8970static bool cursor_size_ok(struct drm_device *dev,
8971 uint32_t width, uint32_t height)
8972{
8973 if (width == 0 || height == 0)
8974 return false;
8975
8976 /*
8977 * 845g/865g are special in that they are only limited by
8978 * the width of their cursors, the height is arbitrary up to
8979 * the precision of the register. Everything else requires
8980 * square cursors, limited to a few power-of-two sizes.
8981 */
8982 if (IS_845G(dev) || IS_I865G(dev)) {
8983 if ((width & 63) != 0)
8984 return false;
8985
8986 if (width > (IS_845G(dev) ? 64 : 512))
8987 return false;
8988
8989 if (height > 1023)
8990 return false;
8991 } else {
8992 switch (width | height) {
8993 case 256:
8994 case 128:
8995 if (IS_GEN2(dev))
8996 return false;
8997 case 64:
8998 break;
8999 default:
9000 return false;
9001 }
9002 }
9003
9004 return true;
9005}
9006
79e53945 9007static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9008 u16 *blue, uint32_t start, uint32_t size)
79e53945 9009{
7203425a 9010 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9012
7203425a 9013 for (i = start; i < end; i++) {
79e53945
JB		 9014 intel_crtc->lut_r[i] = red[i] >> 8;
9015 intel_crtc->lut_g[i] = green[i] >> 8;
9016 intel_crtc->lut_b[i] = blue[i] >> 8;
9017 }
9018
9019 intel_crtc_load_lut(crtc);
9020}
9021
79e53945
JB		 9022/* VESA 640x480x72Hz mode to set on the pipe */
9023static struct drm_display_mode load_detect_mode = {
9024 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9025 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9026};
9027
a8bb6818
DV		 9028struct drm_framebuffer *
9029__intel_framebuffer_create(struct drm_device *dev,
9030 struct drm_mode_fb_cmd2 *mode_cmd,
9031 struct drm_i915_gem_object *obj)
d2dff872
CW		 9032{
9033 struct intel_framebuffer *intel_fb;
9034 int ret;
9035
9036 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9037 if (!intel_fb) {
6ccb81f2 9038 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9039 return ERR_PTR(-ENOMEM);
9040 }
9041
9042 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9043 if (ret)
9044 goto err;
d2dff872
CW		 9045
9046 return &intel_fb->base;
dd4916c5 9047err:
6ccb81f2 9048 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9049 kfree(intel_fb);
9050
9051 return ERR_PTR(ret);
d2dff872
CW		 9052}
9053
b5ea642a 9054static struct drm_framebuffer *
a8bb6818
DV		 9055intel_framebuffer_create(struct drm_device *dev,
9056 struct drm_mode_fb_cmd2 *mode_cmd,
9057 struct drm_i915_gem_object *obj)
9058{
9059 struct drm_framebuffer *fb;
9060 int ret;
9061
9062 ret = i915_mutex_lock_interruptible(dev);
9063 if (ret)
9064 return ERR_PTR(ret);
9065 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9066 mutex_unlock(&dev->struct_mutex);
9067
9068 return fb;
9069}
9070
d2dff872
CW		 9071static u32
9072intel_framebuffer_pitch_for_width(int width, int bpp)
9073{
9074 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9075 return ALIGN(pitch, 64);
9076}
9077
9078static u32
9079intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9080{
9081 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9082 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9083}
9084
9085static struct drm_framebuffer *
9086intel_framebuffer_create_for_mode(struct drm_device *dev,
9087 struct drm_display_mode *mode,
9088 int depth, int bpp)
9089{
9090 struct drm_i915_gem_object *obj;
0fed39bd 9091 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9092
9093 obj = i915_gem_alloc_object(dev,
9094 intel_framebuffer_size_for_mode(mode, bpp));
9095 if (obj == NULL)
9096 return ERR_PTR(-ENOMEM);
9097
9098 mode_cmd.width = mode->hdisplay;
9099 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9100 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9101 bpp);
5ca0c34a 9102 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9103
9104 return intel_framebuffer_create(dev, &mode_cmd, obj);
9105}
9106
9107static struct drm_framebuffer *
9108mode_fits_in_fbdev(struct drm_device *dev,
9109 struct drm_display_mode *mode)
9110{
4520f53a 9111#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9112 struct drm_i915_private *dev_priv = dev->dev_private;
9113 struct drm_i915_gem_object *obj;
9114 struct drm_framebuffer *fb;
9115
4c0e5528 9116 if (!dev_priv->fbdev)
d2dff872
CW		 9117 return NULL;
9118
4c0e5528 9119 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9120 return NULL;
9121
4c0e5528
DV		 9122 obj = dev_priv->fbdev->fb->obj;
9123 BUG_ON(!obj);
9124
8bcd4553 9125 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9126 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9127 fb->bits_per_pixel))
d2dff872
CW		 9128 return NULL;
9129
01f2c773 9130 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9131 return NULL;
9132
9133 return fb;
4520f53a
DV		 9134#else
9135 return NULL;
9136#endif
d2dff872
CW		 9137}
9138
d2434ab7 9139bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9140 struct drm_display_mode *mode,
51fd371b
RC		 9141 struct intel_load_detect_pipe *old,
9142 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9143{
9144 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9145 struct intel_encoder *intel_encoder =
9146 intel_attached_encoder(connector);
79e53945 9147 struct drm_crtc *possible_crtc;
4ef69c7a 9148 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9149 struct drm_crtc *crtc = NULL;
9150 struct drm_device *dev = encoder->dev;
94352cf9 9151 struct drm_framebuffer *fb;
51fd371b 9152 struct drm_mode_config *config = &dev->mode_config;
83a57153 9153 struct drm_atomic_state *state = NULL;
944b0c76 9154 struct drm_connector_state *connector_state;
51fd371b 9155 int ret, i = -1;
79e53945 9156
d2dff872 9157 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9158 connector->base.id, connector->name,
8e329a03 9159 encoder->base.id, encoder->name);
d2dff872 9160
51fd371b
RC		 9161retry:
9162 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9163 if (ret)
9164 goto fail_unlock;
6e9f798d 9165
79e53945
JB		 9166 /*
9167 * Algorithm gets a little messy:
7a5e4805 9168 *
79e53945
JB		 9169 * - if the connector already has an assigned crtc, use it (but make
9170 * sure it's on first)
7a5e4805 9171 *
79e53945
JB		 9172 * - try to find the first unused crtc that can drive this connector,
9173 * and use that if we find one
79e53945
JB		 9174 */
9175
9176 /* See if we already have a CRTC for this connector */
9177 if (encoder->crtc) {
9178 crtc = encoder->crtc;
8261b191 9179
51fd371b 9180 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9181 if (ret)
9182 goto fail_unlock;
9183 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9184 if (ret)
9185 goto fail_unlock;
7b24056b 9186
24218aac 9187 old->dpms_mode = connector->dpms;
8261b191
CW		 9188 old->load_detect_temp = false;
9189
9190 /* Make sure the crtc and connector are running */
24218aac
DV		 9191 if (connector->dpms != DRM_MODE_DPMS_ON)
9192 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9193
7173188d 9194 return true;
79e53945
JB		 9195 }
9196
9197 /* Find an unused one (if possible) */
70e1e0ec 9198 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9199 i++;
9200 if (!(encoder->possible_crtcs & (1 << i)))
9201 continue;
83d65738 9202 if (possible_crtc->state->enable)
a459249c
VS		 9203 continue;
9204 /* This can occur when applying the pipe A quirk on resume. */
9205 if (to_intel_crtc(possible_crtc)->new_enabled)
9206 continue;
9207
9208 crtc = possible_crtc;
9209 break;
79e53945
JB		 9210 }
9211
9212 /*
9213 * If we didn't find an unused CRTC, don't use any.
9214 */
9215 if (!crtc) {
7173188d 9216 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9217 goto fail_unlock;
79e53945
JB		 9218 }
9219
51fd371b
RC		 9220 ret = drm_modeset_lock(&crtc->mutex, ctx);
9221 if (ret)
4d02e2de
DV		 9222 goto fail_unlock;
9223 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9224 if (ret)
51fd371b 9225 goto fail_unlock;
fc303101
DV		 9226 intel_encoder->new_crtc = to_intel_crtc(crtc);
9227 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9228
9229 intel_crtc = to_intel_crtc(crtc);
412b61d8 9230 intel_crtc->new_enabled = true;
24218aac 9231 old->dpms_mode = connector->dpms;
8261b191 9232 old->load_detect_temp = true;
d2dff872 9233 old->release_fb = NULL;
79e53945 9234
83a57153
ACO		 9235 state = drm_atomic_state_alloc(dev);
9236 if (!state)
9237 return false;
9238
9239 state->acquire_ctx = ctx;
9240
944b0c76
ACO		 9241 connector_state = drm_atomic_get_connector_state(state, connector);
9242 if (IS_ERR(connector_state)) {
9243 ret = PTR_ERR(connector_state);
9244 goto fail;
9245 }
9246
9247 connector_state->crtc = crtc;
9248 connector_state->best_encoder = &intel_encoder->base;
9249
6492711d
CW		 9250 if (!mode)
9251 mode = &load_detect_mode;
79e53945 9252
d2dff872
CW		 9253 /* We need a framebuffer large enough to accommodate all accesses
9254 * that the plane may generate whilst we perform load detection.
9255 * We can not rely on the fbcon either being present (we get called
9256 * during its initialisation to detect all boot displays, or it may
9257 * not even exist) or that it is large enough to satisfy the
9258 * requested mode.
9259 */
94352cf9
DV		 9260 fb = mode_fits_in_fbdev(dev, mode);
9261 if (fb == NULL) {
d2dff872 9262 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9263 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9264 old->release_fb = fb;
d2dff872
CW		 9265 } else
9266 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9267 if (IS_ERR(fb)) {
d2dff872 9268 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9269 goto fail;
79e53945 9270 }
79e53945 9271
83a57153 9272 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9273 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9274 if (old->release_fb)
9275 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9276 goto fail;
79e53945 9277 }
9128b040 9278 crtc->primary->crtc = crtc;
7173188d 9279
79e53945 9280 /* let the connector get through one full cycle before testing */
9d0498a2 9281 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9282 return true;
412b61d8
VS		 9283
9284 fail:
83d65738 9285 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9286fail_unlock:
83a57153
ACO		 9287 if (state) {
9288 drm_atomic_state_free(state);
9289 state = NULL;
9290 }
9291
51fd371b
RC		 9292 if (ret == -EDEADLK) {
9293 drm_modeset_backoff(ctx);
9294 goto retry;
9295 }
9296
412b61d8 9297 return false;
79e53945
JB		 9298}
9299
d2434ab7 9300void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9301 struct intel_load_detect_pipe *old,
9302 struct drm_modeset_acquire_ctx *ctx)
79e53945 9303{
83a57153 9304 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9305 struct intel_encoder *intel_encoder =
9306 intel_attached_encoder(connector);
4ef69c7a 9307 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9308 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9310 struct drm_atomic_state *state;
944b0c76 9311 struct drm_connector_state *connector_state;
79e53945 9312
d2dff872 9313 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9314 connector->base.id, connector->name,
8e329a03 9315 encoder->base.id, encoder->name);
d2dff872 9316
8261b191 9317 if (old->load_detect_temp) {
83a57153 9318 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9319 if (!state)
9320 goto fail;
83a57153
ACO		 9321
9322 state->acquire_ctx = ctx;
9323
944b0c76
ACO		 9324 connector_state = drm_atomic_get_connector_state(state, connector);
9325 if (IS_ERR(connector_state))
9326 goto fail;
9327
fc303101
DV		 9328 to_intel_connector(connector)->new_encoder = NULL;
9329 intel_encoder->new_crtc = NULL;
412b61d8 9330 intel_crtc->new_enabled = false;
944b0c76
ACO		 9331
9332 connector_state->best_encoder = NULL;
9333 connector_state->crtc = NULL;
9334
83a57153
ACO		 9335 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9336
9337 drm_atomic_state_free(state);
d2dff872 9338
36206361
DV		 9339 if (old->release_fb) {
9340 drm_framebuffer_unregister_private(old->release_fb);
9341 drm_framebuffer_unreference(old->release_fb);
9342 }
d2dff872 9343
0622a53c 9344 return;
79e53945
JB		 9345 }
9346
c751ce4f 9347 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9348 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9349 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9350
9351 return;
9352fail:
9353 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9354 drm_atomic_state_free(state);
79e53945
JB		 9355}
9356
da4a1efa 9357static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9358 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9359{
9360 struct drm_i915_private *dev_priv = dev->dev_private;
9361 u32 dpll = pipe_config->dpll_hw_state.dpll;
9362
9363 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9364 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9365 else if (HAS_PCH_SPLIT(dev))
9366 return 120000;
9367 else if (!IS_GEN2(dev))
9368 return 96000;
9369 else
9370 return 48000;
9371}
9372
79e53945 9373/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9374static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9375 struct intel_crtc_state *pipe_config)
79e53945 9376{
f1f644dc 9377 struct drm_device *dev = crtc->base.dev;
79e53945 9378 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9379 int pipe = pipe_config->cpu_transcoder;
293623f7 9380 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9381 u32 fp;
9382 intel_clock_t clock;
da4a1efa 9383 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9384
9385 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9386 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9387 else
293623f7 9388 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9389
9390 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9391 if (IS_PINEVIEW(dev)) {
9392 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9393 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9394 } else {
9395 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9396 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9397 }
9398
a6c45cf0 9399 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9400 if (IS_PINEVIEW(dev))
9401 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9402 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9403 else
9404 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9405 DPLL_FPA01_P1_POST_DIV_SHIFT);
9406
9407 switch (dpll & DPLL_MODE_MASK) {
9408 case DPLLB_MODE_DAC_SERIAL:
9409 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9410 5 : 10;
9411 break;
9412 case DPLLB_MODE_LVDS:
9413 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9414 7 : 14;
9415 break;
9416 default:
28c97730 9417 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9418 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9419 return;
79e53945
JB		 9420 }
9421
ac58c3f0 9422 if (IS_PINEVIEW(dev))
da4a1efa 9423 pineview_clock(refclk, &clock);
ac58c3f0 9424 else
da4a1efa 9425 i9xx_clock(refclk, &clock);
79e53945 9426 } else {
0fb58223 9427 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9428 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9429
9430 if (is_lvds) {
9431 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9432 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9433
9434 if (lvds & LVDS_CLKB_POWER_UP)
9435 clock.p2 = 7;
9436 else
9437 clock.p2 = 14;
79e53945
JB		 9438 } else {
9439 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9440 clock.p1 = 2;
9441 else {
9442 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9443 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9444 }
9445 if (dpll & PLL_P2_DIVIDE_BY_4)
9446 clock.p2 = 4;
9447 else
9448 clock.p2 = 2;
79e53945 9449 }
da4a1efa
VS		 9450
9451 i9xx_clock(refclk, &clock);
79e53945
JB		 9452 }
9453
18442d08
VS		 9454 /*
9455 * This value includes pixel_multiplier. We will use
241bfc38 9456 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9457 * encoder's get_config() function.
9458 */
9459 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9460}
9461
6878da05
VS		 9462int intel_dotclock_calculate(int link_freq,
9463 const struct intel_link_m_n *m_n)
f1f644dc 9464{
f1f644dc
JB		 9465 /*
9466 * The calculation for the data clock is:
1041a02f 9467 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9468 * But we want to avoid losing precison if possible, so:
1041a02f 9469 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9470 *
9471 * and the link clock is simpler:
1041a02f 9472 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9473 */
9474
6878da05
VS		 9475 if (!m_n->link_n)
9476 return 0;
f1f644dc 9477
6878da05
VS		 9478 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9479}
f1f644dc 9480
18442d08 9481static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9482 struct intel_crtc_state *pipe_config)
6878da05
VS		 9483{
9484 struct drm_device *dev = crtc->base.dev;
79e53945 9485
18442d08
VS		 9486 /* read out port_clock from the DPLL */
9487 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9488
f1f644dc 9489 /*
18442d08 9490 * This value does not include pixel_multiplier.
241bfc38 9491 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9492 * agree once we know their relationship in the encoder's
9493 * get_config() function.
79e53945 9494 */
2d112de7 9495 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9496 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9497 &pipe_config->fdi_m_n);
79e53945
JB		 9498}
9499
9500/** Returns the currently programmed mode of the given pipe. */
9501struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9502 struct drm_crtc *crtc)
9503{
548f245b 9504 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9506 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9507 struct drm_display_mode *mode;
5cec258b 9508 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9509 int htot = I915_READ(HTOTAL(cpu_transcoder));
9510 int hsync = I915_READ(HSYNC(cpu_transcoder));
9511 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9512 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9513 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9514
9515 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9516 if (!mode)
9517 return NULL;
9518
f1f644dc
JB		 9519 /*
9520 * Construct a pipe_config sufficient for getting the clock info
9521 * back out of crtc_clock_get.
9522 *
9523 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9524 * to use a real value here instead.
9525 */
293623f7 9526 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9527 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9528 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9529 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9530 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9531 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9532
773ae034 9533 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9534 mode->hdisplay = (htot & 0xffff) + 1;
9535 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9536 mode->hsync_start = (hsync & 0xffff) + 1;
9537 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9538 mode->vdisplay = (vtot & 0xffff) + 1;
9539 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9540 mode->vsync_start = (vsync & 0xffff) + 1;
9541 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9542
9543 drm_mode_set_name(mode);
79e53945
JB		 9544
9545 return mode;
9546}
9547
652c393a
JB		 9548static void intel_decrease_pllclock(struct drm_crtc *crtc)
9549{
9550 struct drm_device *dev = crtc->dev;
fbee40df 9551 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9553
baff296c 9554 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9555 return;
9556
9557 if (!dev_priv->lvds_downclock_avail)
9558 return;
9559
9560 /*
9561 * Since this is called by a timer, we should never get here in
9562 * the manual case.
9563 */
9564 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9565 int pipe = intel_crtc->pipe;
9566 int dpll_reg = DPLL(pipe);
9567 int dpll;
f6e5b160 9568
44d98a61 9569 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9570
8ac5a6d5 9571 assert_panel_unlocked(dev_priv, pipe);
652c393a 9572
dc257cf1 9573 dpll = I915_READ(dpll_reg);
652c393a
JB		 9574 dpll |= DISPLAY_RATE_SELECT_FPA1;
9575 I915_WRITE(dpll_reg, dpll);
9d0498a2 9576 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9577 dpll = I915_READ(dpll_reg);
9578 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9579 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9580 }
9581
9582}
9583
f047e395
CW		 9584void intel_mark_busy(struct drm_device *dev)
9585{
c67a470b
PZ		 9586 struct drm_i915_private *dev_priv = dev->dev_private;
9587
f62a0076
CW		 9588 if (dev_priv->mm.busy)
9589 return;
9590
43694d69 9591 intel_runtime_pm_get(dev_priv);
c67a470b 9592 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 9593 if (INTEL_INFO(dev)->gen >= 6)
9594 gen6_rps_busy(dev_priv);
f62a0076 9595 dev_priv->mm.busy = true;
f047e395
CW		 9596}
9597
9598void intel_mark_idle(struct drm_device *dev)
652c393a 9599{
c67a470b 9600 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9601 struct drm_crtc *crtc;
652c393a 9602
f62a0076
CW		 9603 if (!dev_priv->mm.busy)
9604 return;
9605
9606 dev_priv->mm.busy = false;
9607
70e1e0ec 9608 for_each_crtc(dev, crtc) {
f4510a27 9609 if (!crtc->primary->fb)
652c393a
JB		 9610 continue;
9611
725a5b54 9612 intel_decrease_pllclock(crtc);
652c393a 9613 }
b29c19b6 9614
3d13ef2e 9615 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9616 gen6_rps_idle(dev->dev_private);
bb4cdd53 9617
43694d69 9618 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9619}
9620
f5de6e07
ACO		 9621static void intel_crtc_set_state(struct intel_crtc *crtc,
9622 struct intel_crtc_state *crtc_state)
9623{
9624 kfree(crtc->config);
9625 crtc->config = crtc_state;
16f3f658 9626 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9627}
9628
79e53945
JB		 9629static void intel_crtc_destroy(struct drm_crtc *crtc)
9630{
9631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9632 struct drm_device *dev = crtc->dev;
9633 struct intel_unpin_work *work;
67e77c5a 9634
5e2d7afc 9635 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9636 work = intel_crtc->unpin_work;
9637 intel_crtc->unpin_work = NULL;
5e2d7afc 9638 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9639
9640 if (work) {
9641 cancel_work_sync(&work->work);
9642 kfree(work);
9643 }
79e53945 9644
f5de6e07 9645 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9646 drm_crtc_cleanup(crtc);
67e77c5a 9647
79e53945
JB		 9648 kfree(intel_crtc);
9649}
9650
6b95a207
KH		 9651static void intel_unpin_work_fn(struct work_struct *__work)
9652{
9653 struct intel_unpin_work *work =
9654 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9655 struct drm_device *dev = work->crtc->dev;
f99d7069 9656 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9657
b4a98e57 9658 mutex_lock(&dev->struct_mutex);
82bc3b2d 9659 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 9660 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 9661
7ff0ebcc 9662 intel_fbc_update(dev);
f06cc1b9
JH		 9663
9664 if (work->flip_queued_req)
146d84f0 9665 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9666 mutex_unlock(&dev->struct_mutex);
9667
f99d7069 9668 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 9669 drm_framebuffer_unreference(work->old_fb);
f99d7069 9670
b4a98e57
CW		 9671 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9672 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9673
6b95a207
KH		 9674 kfree(work);
9675}
9676
1afe3e9d 9677static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9678 struct drm_crtc *crtc)
6b95a207 9679{
6b95a207
KH		 9680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9681 struct intel_unpin_work *work;
6b95a207
KH		 9682 unsigned long flags;
9683
9684 /* Ignore early vblank irqs */
9685 if (intel_crtc == NULL)
9686 return;
9687
f326038a
DV		 9688 /*
9689 * This is called both by irq handlers and the reset code (to complete
9690 * lost pageflips) so needs the full irqsave spinlocks.
9691 */
6b95a207
KH		 9692 spin_lock_irqsave(&dev->event_lock, flags);
9693 work = intel_crtc->unpin_work;
e7d841ca
CW		 9694
9695 /* Ensure we don't miss a work->pending update ... */
9696 smp_rmb();
9697
9698 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9699 spin_unlock_irqrestore(&dev->event_lock, flags);
9700 return;
9701 }
9702
d6bbafa1 9703 page_flip_completed(intel_crtc);
0af7e4df 9704
6b95a207 9705 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9706}
9707
1afe3e9d
JB		 9708void intel_finish_page_flip(struct drm_device *dev, int pipe)
9709{
fbee40df 9710 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9711 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9712
49b14a5c 9713 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9714}
9715
9716void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9717{
fbee40df 9718 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9719 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9720
49b14a5c 9721 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9722}
9723
75f7f3ec
VS		 9724/* Is 'a' after or equal to 'b'? */
9725static bool g4x_flip_count_after_eq(u32 a, u32 b)
9726{
9727 return !((a - b) & 0x80000000);
9728}
9729
9730static bool page_flip_finished(struct intel_crtc *crtc)
9731{
9732 struct drm_device *dev = crtc->base.dev;
9733 struct drm_i915_private *dev_priv = dev->dev_private;
9734
bdfa7542
VS		 9735 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9736 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9737 return true;
9738
75f7f3ec
VS		 9739 /*
9740 * The relevant registers doen't exist on pre-ctg.
9741 * As the flip done interrupt doesn't trigger for mmio
9742 * flips on gmch platforms, a flip count check isn't
9743 * really needed there. But since ctg has the registers,
9744 * include it in the check anyway.
9745 */
9746 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9747 return true;
9748
9749 /*
9750 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9751 * used the same base address. In that case the mmio flip might
9752 * have completed, but the CS hasn't even executed the flip yet.
9753 *
9754 * A flip count check isn't enough as the CS might have updated
9755 * the base address just after start of vblank, but before we
9756 * managed to process the interrupt. This means we'd complete the
9757 * CS flip too soon.
9758 *
9759 * Combining both checks should get us a good enough result. It may
9760 * still happen that the CS flip has been executed, but has not
9761 * yet actually completed. But in case the base address is the same
9762 * anyway, we don't really care.
9763 */
9764 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9765 crtc->unpin_work->gtt_offset &&
9766 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9767 crtc->unpin_work->flip_count);
9768}
9769
6b95a207
KH		 9770void intel_prepare_page_flip(struct drm_device *dev, int plane)
9771{
fbee40df 9772 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9773 struct intel_crtc *intel_crtc =
9774 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9775 unsigned long flags;
9776
f326038a
DV		 9777
9778 /*
9779 * This is called both by irq handlers and the reset code (to complete
9780 * lost pageflips) so needs the full irqsave spinlocks.
9781 *
9782 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9783 * generate a page-flip completion irq, i.e. every modeset
9784 * is also accompanied by a spurious intel_prepare_page_flip().
9785 */
6b95a207 9786 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9787 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9788 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9789 spin_unlock_irqrestore(&dev->event_lock, flags);
9790}
9791
eba905b2 9792static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9793{
9794 /* Ensure that the work item is consistent when activating it ... */
9795 smp_wmb();
9796 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9797 /* and that it is marked active as soon as the irq could fire. */
9798 smp_wmb();
9799}
9800
8c9f3aaf
JB		 9801static int intel_gen2_queue_flip(struct drm_device *dev,
9802 struct drm_crtc *crtc,
9803 struct drm_framebuffer *fb,
ed8d1975 9804 struct drm_i915_gem_object *obj,
a4872ba6 9805 struct intel_engine_cs *ring,
ed8d1975 9806 uint32_t flags)
8c9f3aaf 9807{
8c9f3aaf 9808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9809 u32 flip_mask;
9810 int ret;
9811
6d90c952 9812 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9813 if (ret)
4fa62c89 9814 return ret;
8c9f3aaf
JB		 9815
9816 /* Can't queue multiple flips, so wait for the previous
9817 * one to finish before executing the next.
9818 */
9819 if (intel_crtc->plane)
9820 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9821 else
9822 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9823 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9824 intel_ring_emit(ring, MI_NOOP);
9825 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9826 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9827 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9828 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 9829 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 9830
9831 intel_mark_page_flip_active(intel_crtc);
09246732 9832 __intel_ring_advance(ring);
83d4092b 9833 return 0;
8c9f3aaf
JB		 9834}
9835
9836static int intel_gen3_queue_flip(struct drm_device *dev,
9837 struct drm_crtc *crtc,
9838 struct drm_framebuffer *fb,
ed8d1975 9839 struct drm_i915_gem_object *obj,
a4872ba6 9840 struct intel_engine_cs *ring,
ed8d1975 9841 uint32_t flags)
8c9f3aaf 9842{
8c9f3aaf 9843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9844 u32 flip_mask;
9845 int ret;
9846
6d90c952 9847 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9848 if (ret)
4fa62c89 9849 return ret;
8c9f3aaf
JB		 9850
9851 if (intel_crtc->plane)
9852 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9853 else
9854 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9855 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9856 intel_ring_emit(ring, MI_NOOP);
9857 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9858 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9859 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9860 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 9861 intel_ring_emit(ring, MI_NOOP);
9862
e7d841ca 9863 intel_mark_page_flip_active(intel_crtc);
09246732 9864 __intel_ring_advance(ring);
83d4092b 9865 return 0;
8c9f3aaf
JB		 9866}
9867
9868static int intel_gen4_queue_flip(struct drm_device *dev,
9869 struct drm_crtc *crtc,
9870 struct drm_framebuffer *fb,
ed8d1975 9871 struct drm_i915_gem_object *obj,
a4872ba6 9872 struct intel_engine_cs *ring,
ed8d1975 9873 uint32_t flags)
8c9f3aaf
JB		 9874{
9875 struct drm_i915_private *dev_priv = dev->dev_private;
9876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9877 uint32_t pf, pipesrc;
9878 int ret;
9879
6d90c952 9880 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9881 if (ret)
4fa62c89 9882 return ret;
8c9f3aaf
JB		 9883
9884 /* i965+ uses the linear or tiled offsets from the
9885 * Display Registers (which do not change across a page-flip)
9886 * so we need only reprogram the base address.
9887 */
6d90c952
DV		 9888 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9889 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9890 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9891 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 9892 obj->tiling_mode);
8c9f3aaf
JB		 9893
9894 /* XXX Enabling the panel-fitter across page-flip is so far
9895 * untested on non-native modes, so ignore it for now.
9896 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9897 */
9898 pf = 0;
9899 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9900 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9901
9902 intel_mark_page_flip_active(intel_crtc);
09246732 9903 __intel_ring_advance(ring);
83d4092b 9904 return 0;
8c9f3aaf
JB		 9905}
9906
9907static int intel_gen6_queue_flip(struct drm_device *dev,
9908 struct drm_crtc *crtc,
9909 struct drm_framebuffer *fb,
ed8d1975 9910 struct drm_i915_gem_object *obj,
a4872ba6 9911 struct intel_engine_cs *ring,
ed8d1975 9912 uint32_t flags)
8c9f3aaf
JB		 9913{
9914 struct drm_i915_private *dev_priv = dev->dev_private;
9915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9916 uint32_t pf, pipesrc;
9917 int ret;
9918
6d90c952 9919 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9920 if (ret)
4fa62c89 9921 return ret;
8c9f3aaf 9922
6d90c952
DV		 9923 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9924 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9925 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 9926 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 9927
dc257cf1
DV		 9928 /* Contrary to the suggestions in the documentation,
9929 * "Enable Panel Fitter" does not seem to be required when page
9930 * flipping with a non-native mode, and worse causes a normal
9931 * modeset to fail.
9932 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9933 */
9934 pf = 0;
8c9f3aaf 9935 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9936 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9937
9938 intel_mark_page_flip_active(intel_crtc);
09246732 9939 __intel_ring_advance(ring);
83d4092b 9940 return 0;
8c9f3aaf
JB		 9941}
9942
7c9017e5
JB		 9943static int intel_gen7_queue_flip(struct drm_device *dev,
9944 struct drm_crtc *crtc,
9945 struct drm_framebuffer *fb,
ed8d1975 9946 struct drm_i915_gem_object *obj,
a4872ba6 9947 struct intel_engine_cs *ring,
ed8d1975 9948 uint32_t flags)
7c9017e5 9949{
7c9017e5 9950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 9951 uint32_t plane_bit = 0;
ffe74d75
CW		 9952 int len, ret;
9953
eba905b2 9954 switch (intel_crtc->plane) {
cb05d8de
DV		 9955 case PLANE_A:
9956 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9957 break;
9958 case PLANE_B:
9959 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9960 break;
9961 case PLANE_C:
9962 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9963 break;
9964 default:
9965 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 9966 return -ENODEV;
cb05d8de
DV		 9967 }
9968
ffe74d75 9969 len = 4;
f476828a 9970 if (ring->id == RCS) {
ffe74d75 9971 len += 6;
f476828a
DL		 9972 /*
9973 * On Gen 8, SRM is now taking an extra dword to accommodate
9974 * 48bits addresses, and we need a NOOP for the batch size to
9975 * stay even.
9976 */
9977 if (IS_GEN8(dev))
9978 len += 2;
9979 }
ffe74d75 9980
f66fab8e
VS		 9981 /*
9982 * BSpec MI_DISPLAY_FLIP for IVB:
9983 * "The full packet must be contained within the same cache line."
9984 *
9985 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9986 * cacheline, if we ever start emitting more commands before
9987 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9988 * then do the cacheline alignment, and finally emit the
9989 * MI_DISPLAY_FLIP.
9990 */
9991 ret = intel_ring_cacheline_align(ring);
9992 if (ret)
4fa62c89 9993 return ret;
f66fab8e 9994
ffe74d75 9995 ret = intel_ring_begin(ring, len);
7c9017e5 9996 if (ret)
4fa62c89 9997 return ret;
7c9017e5 9998
ffe74d75
CW		 9999 /* Unmask the flip-done completion message. Note that the bspec says that
10000 * we should do this for both the BCS and RCS, and that we must not unmask
10001 * more than one flip event at any time (or ensure that one flip message
10002 * can be sent by waiting for flip-done prior to queueing new flips).
10003 * Experimentation says that BCS works despite DERRMR masking all
10004 * flip-done completion events and that unmasking all planes at once
10005 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10006 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10007 */
10008 if (ring->id == RCS) {
10009 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10010 intel_ring_emit(ring, DERRMR);
10011 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10012 DERRMR_PIPEB_PRI_FLIP_DONE |
10013 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10014 if (IS_GEN8(dev))
10015 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10016 MI_SRM_LRM_GLOBAL_GTT);
10017 else
10018 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10019 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10020 intel_ring_emit(ring, DERRMR);
10021 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10022 if (IS_GEN8(dev)) {
10023 intel_ring_emit(ring, 0);
10024 intel_ring_emit(ring, MI_NOOP);
10025 }
ffe74d75
CW		 10026 }
10027
cb05d8de 10028 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10029 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10030 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10031 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10032
10033 intel_mark_page_flip_active(intel_crtc);
09246732 10034 __intel_ring_advance(ring);
83d4092b 10035 return 0;
7c9017e5
JB		 10036}
10037
84c33a64
SG		 10038static bool use_mmio_flip(struct intel_engine_cs *ring,
10039 struct drm_i915_gem_object *obj)
10040{
10041 /*
10042 * This is not being used for older platforms, because
10043 * non-availability of flip done interrupt forces us to use
10044 * CS flips. Older platforms derive flip done using some clever
10045 * tricks involving the flip_pending status bits and vblank irqs.
10046 * So using MMIO flips there would disrupt this mechanism.
10047 */
10048
8e09bf83
CW		 10049 if (ring == NULL)
10050 return true;
10051
84c33a64
SG		 10052 if (INTEL_INFO(ring->dev)->gen < 5)
10053 return false;
10054
10055 if (i915.use_mmio_flip < 0)
10056 return false;
10057 else if (i915.use_mmio_flip > 0)
10058 return true;
14bf993e
OM		 10059 else if (i915.enable_execlists)
10060 return true;
84c33a64 10061 else
41c52415 10062 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10063}
10064
ff944564
DL		 10065static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10066{
10067 struct drm_device *dev = intel_crtc->base.dev;
10068 struct drm_i915_private *dev_priv = dev->dev_private;
10069 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10070 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10071 struct drm_i915_gem_object *obj = intel_fb->obj;
10072 const enum pipe pipe = intel_crtc->pipe;
10073 u32 ctl, stride;
10074
10075 ctl = I915_READ(PLANE_CTL(pipe, 0));
10076 ctl &= ~PLANE_CTL_TILED_MASK;
10077 if (obj->tiling_mode == I915_TILING_X)
10078 ctl |= PLANE_CTL_TILED_X;
10079
10080 /*
10081 * The stride is either expressed as a multiple of 64 bytes chunks for
10082 * linear buffers or in number of tiles for tiled buffers.
10083 */
10084 stride = fb->pitches[0] >> 6;
10085 if (obj->tiling_mode == I915_TILING_X)
10086 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
10087
10088 /*
10089 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10090 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10091 */
10092 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10093 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10094
10095 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10096 POSTING_READ(PLANE_SURF(pipe, 0));
10097}
10098
10099static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10100{
10101 struct drm_device *dev = intel_crtc->base.dev;
10102 struct drm_i915_private *dev_priv = dev->dev_private;
10103 struct intel_framebuffer *intel_fb =
10104 to_intel_framebuffer(intel_crtc->base.primary->fb);
10105 struct drm_i915_gem_object *obj = intel_fb->obj;
10106 u32 dspcntr;
10107 u32 reg;
10108
84c33a64
SG		 10109 reg = DSPCNTR(intel_crtc->plane);
10110 dspcntr = I915_READ(reg);
10111
c5d97472
DL		 10112 if (obj->tiling_mode != I915_TILING_NONE)
10113 dspcntr |= DISPPLANE_TILED;
10114 else
10115 dspcntr &= ~DISPPLANE_TILED;
10116
84c33a64
SG		 10117 I915_WRITE(reg, dspcntr);
10118
10119 I915_WRITE(DSPSURF(intel_crtc->plane),
10120 intel_crtc->unpin_work->gtt_offset);
10121 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10122
ff944564
DL		 10123}
10124
10125/*
10126 * XXX: This is the temporary way to update the plane registers until we get
10127 * around to using the usual plane update functions for MMIO flips
10128 */
10129static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10130{
10131 struct drm_device *dev = intel_crtc->base.dev;
10132 bool atomic_update;
10133 u32 start_vbl_count;
10134
10135 intel_mark_page_flip_active(intel_crtc);
10136
10137 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10138
10139 if (INTEL_INFO(dev)->gen >= 9)
10140 skl_do_mmio_flip(intel_crtc);
10141 else
10142 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10143 ilk_do_mmio_flip(intel_crtc);
10144
9362c7c5
ACO		 10145 if (atomic_update)
10146 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10147}
10148
9362c7c5 10149static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10150{
cc8c4cc2 10151 struct intel_crtc *crtc =
9362c7c5 10152 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10153 struct intel_mmio_flip *mmio_flip;
84c33a64 10154
cc8c4cc2
JH		 10155 mmio_flip = &crtc->mmio_flip;
10156 if (mmio_flip->req)
9c654818
JH		 10157 WARN_ON(__i915_wait_request(mmio_flip->req,
10158 crtc->reset_counter,
10159 false, NULL, NULL) != 0);
84c33a64 10160
cc8c4cc2
JH		 10161 intel_do_mmio_flip(crtc);
10162 if (mmio_flip->req) {
10163 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10164 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10165 mutex_unlock(&crtc->base.dev->struct_mutex);
10166 }
84c33a64
SG		 10167}
10168
10169static int intel_queue_mmio_flip(struct drm_device *dev,
10170 struct drm_crtc *crtc,
10171 struct drm_framebuffer *fb,
10172 struct drm_i915_gem_object *obj,
10173 struct intel_engine_cs *ring,
10174 uint32_t flags)
10175{
84c33a64 10176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10177
cc8c4cc2
JH		 10178 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10179 obj->last_write_req);
536f5b5e
ACO		 10180
10181 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10182
84c33a64
SG		 10183 return 0;
10184}
10185
8c9f3aaf
JB		 10186static int intel_default_queue_flip(struct drm_device *dev,
10187 struct drm_crtc *crtc,
10188 struct drm_framebuffer *fb,
ed8d1975 10189 struct drm_i915_gem_object *obj,
a4872ba6 10190 struct intel_engine_cs *ring,
ed8d1975 10191 uint32_t flags)
8c9f3aaf
JB		 10192{
10193 return -ENODEV;
10194}
10195
d6bbafa1
CW		 10196static bool __intel_pageflip_stall_check(struct drm_device *dev,
10197 struct drm_crtc *crtc)
10198{
10199 struct drm_i915_private *dev_priv = dev->dev_private;
10200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10201 struct intel_unpin_work *work = intel_crtc->unpin_work;
10202 u32 addr;
10203
10204 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10205 return true;
10206
10207 if (!work->enable_stall_check)
10208 return false;
10209
10210 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10211 if (work->flip_queued_req &&
10212 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10213 return false;
10214
1e3feefd 10215 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10216 }
10217
1e3feefd 10218 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10219 return false;
10220
10221 /* Potential stall - if we see that the flip has happened,
10222 * assume a missed interrupt. */
10223 if (INTEL_INFO(dev)->gen >= 4)
10224 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10225 else
10226 addr = I915_READ(DSPADDR(intel_crtc->plane));
10227
10228 /* There is a potential issue here with a false positive after a flip
10229 * to the same address. We could address this by checking for a
10230 * non-incrementing frame counter.
10231 */
10232 return addr == work->gtt_offset;
10233}
10234
10235void intel_check_page_flip(struct drm_device *dev, int pipe)
10236{
10237 struct drm_i915_private *dev_priv = dev->dev_private;
10238 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10240 struct intel_unpin_work *work;
f326038a 10241
6c51d46f 10242 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10243
10244 if (crtc == NULL)
10245 return;
10246
f326038a 10247 spin_lock(&dev->event_lock);
6ad790c0
CW		 10248 work = intel_crtc->unpin_work;
10249 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10250 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10251 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10252 page_flip_completed(intel_crtc);
6ad790c0 10253 work = NULL;
d6bbafa1 10254 }
6ad790c0
CW		 10255 if (work != NULL &&
10256 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10257 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10258 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10259}
10260
6b95a207
KH		 10261static int intel_crtc_page_flip(struct drm_crtc *crtc,
10262 struct drm_framebuffer *fb,
ed8d1975
KP		 10263 struct drm_pending_vblank_event *event,
10264 uint32_t page_flip_flags)
6b95a207
KH		 10265{
10266 struct drm_device *dev = crtc->dev;
10267 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10268 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10269 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10271 struct drm_plane *primary = crtc->primary;
a071fa00 10272 enum pipe pipe = intel_crtc->pipe;
6b95a207 10273 struct intel_unpin_work *work;
a4872ba6 10274 struct intel_engine_cs *ring;
cf5d8a46 10275 bool mmio_flip;
52e68630 10276 int ret;
6b95a207 10277
2ff8fde1
MR		 10278 /*
10279 * drm_mode_page_flip_ioctl() should already catch this, but double
10280 * check to be safe. In the future we may enable pageflipping from
10281 * a disabled primary plane.
10282 */
10283 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10284 return -EBUSY;
10285
e6a595d2 10286 /* Can't change pixel format via MI display flips. */
f4510a27 10287 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10288 return -EINVAL;
10289
10290 /*
10291 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10292 * Note that pitch changes could also affect these register.
10293 */
10294 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10295 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10296 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10297 return -EINVAL;
10298
f900db47
CW		 10299 if (i915_terminally_wedged(&dev_priv->gpu_error))
10300 goto out_hang;
10301
b14c5679 10302 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10303 if (work == NULL)
10304 return -ENOMEM;
10305
6b95a207 10306 work->event = event;
b4a98e57 10307 work->crtc = crtc;
ab8d6675 10308 work->old_fb = old_fb;
6b95a207
KH		 10309 INIT_WORK(&work->work, intel_unpin_work_fn);
10310
87b6b101 10311 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10312 if (ret)
10313 goto free_work;
10314
6b95a207 10315 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10316 spin_lock_irq(&dev->event_lock);
6b95a207 10317 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10318 /* Before declaring the flip queue wedged, check if
10319 * the hardware completed the operation behind our backs.
10320 */
10321 if (__intel_pageflip_stall_check(dev, crtc)) {
10322 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10323 page_flip_completed(intel_crtc);
10324 } else {
10325 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10326 spin_unlock_irq(&dev->event_lock);
468f0b44 10327
d6bbafa1
CW		 10328 drm_crtc_vblank_put(crtc);
10329 kfree(work);
10330 return -EBUSY;
10331 }
6b95a207
KH		 10332 }
10333 intel_crtc->unpin_work = work;
5e2d7afc 10334 spin_unlock_irq(&dev->event_lock);
6b95a207 10335
b4a98e57
CW		 10336 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10337 flush_workqueue(dev_priv->wq);
10338
75dfca80 10339 /* Reference the objects for the scheduled work. */
ab8d6675 10340 drm_framebuffer_reference(work->old_fb);
05394f39 10341 drm_gem_object_reference(&obj->base);
6b95a207 10342
f4510a27 10343 crtc->primary->fb = fb;
afd65eb4 10344 update_state_fb(crtc->primary);
1ed1f968 10345
e1f99ce6 10346 work->pending_flip_obj = obj;
e1f99ce6 10347
89ed88ba
CW		 10348 ret = i915_mutex_lock_interruptible(dev);
10349 if (ret)
10350 goto cleanup;
10351
b4a98e57 10352 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10353 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10354
75f7f3ec 10355 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10356 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10357
4fa62c89
VS		 10358 if (IS_VALLEYVIEW(dev)) {
10359 ring = &dev_priv->ring[BCS];
ab8d6675 10360 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10361 /* vlv: DISPLAY_FLIP fails to change tiling */
10362 ring = NULL;
48bf5b2d 10363 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10364 ring = &dev_priv->ring[BCS];
4fa62c89 10365 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10366 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10367 if (ring == NULL || ring->id != RCS)
10368 ring = &dev_priv->ring[BCS];
10369 } else {
10370 ring = &dev_priv->ring[RCS];
10371 }
10372
cf5d8a46
CW		 10373 mmio_flip = use_mmio_flip(ring, obj);
10374
10375 /* When using CS flips, we want to emit semaphores between rings.
10376 * However, when using mmio flips we will create a task to do the
10377 * synchronisation, so all we want here is to pin the framebuffer
10378 * into the display plane and skip any waits.
10379 */
82bc3b2d 10380 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10381 crtc->primary->state,
10382 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10383 if (ret)
10384 goto cleanup_pending;
6b95a207 10385
121920fa
TU		 10386 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10387 + intel_crtc->dspaddr_offset;
4fa62c89 10388
cf5d8a46 10389 if (mmio_flip) {
84c33a64
SG		 10390 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10391 page_flip_flags);
d6bbafa1
CW		 10392 if (ret)
10393 goto cleanup_unpin;
10394
f06cc1b9
JH		 10395 i915_gem_request_assign(&work->flip_queued_req,
10396 obj->last_write_req);
d6bbafa1 10397 } else {
84c33a64 10398 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10399 page_flip_flags);
10400 if (ret)
10401 goto cleanup_unpin;
10402
f06cc1b9
JH		 10403 i915_gem_request_assign(&work->flip_queued_req,
10404 intel_ring_get_request(ring));
d6bbafa1
CW		 10405 }
10406
1e3feefd 10407 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10408 work->enable_stall_check = true;
4fa62c89 10409
ab8d6675 10410 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10411 INTEL_FRONTBUFFER_PRIMARY(pipe));
10412
7ff0ebcc 10413 intel_fbc_disable(dev);
f99d7069 10414 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10415 mutex_unlock(&dev->struct_mutex);
10416
e5510fac
JB		 10417 trace_i915_flip_request(intel_crtc->plane, obj);
10418
6b95a207 10419 return 0;
96b099fd 10420
4fa62c89 10421cleanup_unpin:
82bc3b2d 10422 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10423cleanup_pending:
b4a98e57 10424 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10425 mutex_unlock(&dev->struct_mutex);
10426cleanup:
f4510a27 10427 crtc->primary->fb = old_fb;
afd65eb4 10428 update_state_fb(crtc->primary);
89ed88ba
CW		 10429
10430 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10431 drm_framebuffer_unreference(work->old_fb);
96b099fd 10432
5e2d7afc 10433 spin_lock_irq(&dev->event_lock);
96b099fd 10434 intel_crtc->unpin_work = NULL;
5e2d7afc 10435 spin_unlock_irq(&dev->event_lock);
96b099fd 10436
87b6b101 10437 drm_crtc_vblank_put(crtc);
7317c75e 10438free_work:
96b099fd
CW		 10439 kfree(work);
10440
f900db47
CW		 10441 if (ret == -EIO) {
10442out_hang:
53a366b9 10443 ret = intel_plane_restore(primary);
f0d3dad3 10444 if (ret == 0 && event) {
5e2d7afc 10445 spin_lock_irq(&dev->event_lock);
a071fa00 10446 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10447 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10448 }
f900db47 10449 }
96b099fd 10450 return ret;
6b95a207
KH		 10451}
10452
f6e5b160 10453static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10454 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10455 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10456 .atomic_begin = intel_begin_crtc_commit,
10457 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10458};
10459
9a935856
DV		 10460/**
10461 * intel_modeset_update_staged_output_state
10462 *
10463 * Updates the staged output configuration state, e.g. after we've read out the
10464 * current hw state.
10465 */
10466static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10467{
7668851f 10468 struct intel_crtc *crtc;
9a935856
DV		 10469 struct intel_encoder *encoder;
10470 struct intel_connector *connector;
f6e5b160 10471
3a3371ff 10472 for_each_intel_connector(dev, connector) {
9a935856
DV		 10473 connector->new_encoder =
10474 to_intel_encoder(connector->base.encoder);
10475 }
f6e5b160 10476
b2784e15 10477 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10478 encoder->new_crtc =
10479 to_intel_crtc(encoder->base.crtc);
10480 }
7668851f 10481
d3fcc808 10482 for_each_intel_crtc(dev, crtc) {
83d65738 10483 crtc->new_enabled = crtc->base.state->enable;
7668851f 10484 }
f6e5b160
CW		 10485}
10486
d29b2f9d
ACO		 10487/* Transitional helper to copy current connector/encoder state to
10488 * connector->state. This is needed so that code that is partially
10489 * converted to atomic does the right thing.
10490 */
10491static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10492{
10493 struct intel_connector *connector;
10494
10495 for_each_intel_connector(dev, connector) {
10496 if (connector->base.encoder) {
10497 connector->base.state->best_encoder =
10498 connector->base.encoder;
10499 connector->base.state->crtc =
10500 connector->base.encoder->crtc;
10501 } else {
10502 connector->base.state->best_encoder = NULL;
10503 connector->base.state->crtc = NULL;
10504 }
10505 }
10506}
10507
9a935856
DV		 10508/**
10509 * intel_modeset_commit_output_state
10510 *
10511 * This function copies the stage display pipe configuration to the real one.
10512 */
10513static void intel_modeset_commit_output_state(struct drm_device *dev)
10514{
7668851f 10515 struct intel_crtc *crtc;
9a935856
DV		 10516 struct intel_encoder *encoder;
10517 struct intel_connector *connector;
f6e5b160 10518
3a3371ff 10519 for_each_intel_connector(dev, connector) {
9a935856
DV		 10520 connector->base.encoder = &connector->new_encoder->base;
10521 }
f6e5b160 10522
b2784e15 10523 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10524 encoder->base.crtc = &encoder->new_crtc->base;
10525 }
7668851f 10526
d3fcc808 10527 for_each_intel_crtc(dev, crtc) {
83d65738 10528 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10529 crtc->base.enabled = crtc->new_enabled;
10530 }
d29b2f9d
ACO		 10531
10532 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 10533}
10534
050f7aeb 10535static void
eba905b2 10536connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10537 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10538{
10539 int bpp = pipe_config->pipe_bpp;
10540
10541 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10542 connector->base.base.id,
c23cc417 10543 connector->base.name);
050f7aeb
DV		 10544
10545 /* Don't use an invalid EDID bpc value */
10546 if (connector->base.display_info.bpc &&
10547 connector->base.display_info.bpc * 3 < bpp) {
10548 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10549 bpp, connector->base.display_info.bpc*3);
10550 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10551 }
10552
10553 /* Clamp bpp to 8 on screens without EDID 1.4 */
10554 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10555 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10556 bpp);
10557 pipe_config->pipe_bpp = 24;
10558 }
10559}
10560
4e53c2e0 10561static int
050f7aeb
DV		 10562compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10563 struct drm_framebuffer *fb,
5cec258b 10564 struct intel_crtc_state *pipe_config)
4e53c2e0 10565{
050f7aeb 10566 struct drm_device *dev = crtc->base.dev;
1486017f 10567 struct drm_atomic_state *state;
050f7aeb 10568 struct intel_connector *connector;
1486017f 10569 int bpp, i;
4e53c2e0 10570
d42264b1
DV		 10571 switch (fb->pixel_format) {
10572 case DRM_FORMAT_C8:
4e53c2e0
DV		 10573 bpp = 8*3; /* since we go through a colormap */
10574 break;
d42264b1
DV		 10575 case DRM_FORMAT_XRGB1555:
10576 case DRM_FORMAT_ARGB1555:
10577 /* checked in intel_framebuffer_init already */
10578 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10579 return -EINVAL;
10580 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10581 bpp = 6*3; /* min is 18bpp */
10582 break;
d42264b1
DV		 10583 case DRM_FORMAT_XBGR8888:
10584 case DRM_FORMAT_ABGR8888:
10585 /* checked in intel_framebuffer_init already */
10586 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10587 return -EINVAL;
10588 case DRM_FORMAT_XRGB8888:
10589 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10590 bpp = 8*3;
10591 break;
d42264b1
DV		 10592 case DRM_FORMAT_XRGB2101010:
10593 case DRM_FORMAT_ARGB2101010:
10594 case DRM_FORMAT_XBGR2101010:
10595 case DRM_FORMAT_ABGR2101010:
10596 /* checked in intel_framebuffer_init already */
10597 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10598 return -EINVAL;
4e53c2e0
DV		 10599 bpp = 10*3;
10600 break;
baba133a 10601 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10602 default:
10603 DRM_DEBUG_KMS("unsupported depth\n");
10604 return -EINVAL;
10605 }
10606
4e53c2e0
DV		 10607 pipe_config->pipe_bpp = bpp;
10608
1486017f
ACO		 10609 state = pipe_config->base.state;
10610
4e53c2e0 10611 /* Clamp display bpp to EDID value */
1486017f
ACO		 10612 for (i = 0; i < state->num_connector; i++) {
10613 if (!state->connectors[i])
10614 continue;
10615
10616 connector = to_intel_connector(state->connectors[i]);
10617 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 10618 continue;
10619
050f7aeb 10620 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10621 }
10622
10623 return bpp;
10624}
10625
644db711
DV		 10626static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10627{
10628 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10629 "type: 0x%x flags: 0x%x\n",
1342830c 10630 mode->crtc_clock,
644db711
DV		 10631 mode->crtc_hdisplay, mode->crtc_hsync_start,
10632 mode->crtc_hsync_end, mode->crtc_htotal,
10633 mode->crtc_vdisplay, mode->crtc_vsync_start,
10634 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10635}
10636
c0b03411 10637static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10638 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10639 const char *context)
10640{
10641 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10642 context, pipe_name(crtc->pipe));
10643
10644 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10645 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10646 pipe_config->pipe_bpp, pipe_config->dither);
10647 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10648 pipe_config->has_pch_encoder,
10649 pipe_config->fdi_lanes,
10650 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10651 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10652 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10653 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10654 pipe_config->has_dp_encoder,
10655 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10656 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10657 pipe_config->dp_m_n.tu);
b95af8be
VK		 10658
10659 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10660 pipe_config->has_dp_encoder,
10661 pipe_config->dp_m2_n2.gmch_m,
10662 pipe_config->dp_m2_n2.gmch_n,
10663 pipe_config->dp_m2_n2.link_m,
10664 pipe_config->dp_m2_n2.link_n,
10665 pipe_config->dp_m2_n2.tu);
10666
55072d19
DV		 10667 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10668 pipe_config->has_audio,
10669 pipe_config->has_infoframe);
10670
c0b03411 10671 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10672 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10673 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10674 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10675 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10676 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10677 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10678 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 10679 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10680 pipe_config->gmch_pfit.control,
10681 pipe_config->gmch_pfit.pgm_ratios,
10682 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10683 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10684 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10685 pipe_config->pch_pfit.size,
10686 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10687 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10688 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 10689}
10690
bc079e8b
VS		 10691static bool encoders_cloneable(const struct intel_encoder *a,
10692 const struct intel_encoder *b)
accfc0c5 10693{
bc079e8b
VS		 10694 /* masks could be asymmetric, so check both ways */
10695 return a == b || (a->cloneable & (1 << b->type) &&
10696 b->cloneable & (1 << a->type));
10697}
10698
98a221da
ACO		 10699static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10700 struct intel_crtc *crtc,
bc079e8b
VS		 10701 struct intel_encoder *encoder)
10702{
bc079e8b 10703 struct intel_encoder *source_encoder;
98a221da
ACO		 10704 struct drm_connector_state *connector_state;
10705 int i;
10706
10707 for (i = 0; i < state->num_connector; i++) {
10708 if (!state->connectors[i])
10709 continue;
bc079e8b 10710
98a221da
ACO		 10711 connector_state = state->connector_states[i];
10712 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 10713 continue;
10714
98a221da
ACO		 10715 source_encoder =
10716 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 10717 if (!encoders_cloneable(encoder, source_encoder))
10718 return false;
10719 }
10720
10721 return true;
10722}
10723
98a221da
ACO		 10724static bool check_encoder_cloning(struct drm_atomic_state *state,
10725 struct intel_crtc *crtc)
bc079e8b 10726{
accfc0c5 10727 struct intel_encoder *encoder;
98a221da
ACO		 10728 struct drm_connector_state *connector_state;
10729 int i;
accfc0c5 10730
98a221da
ACO		 10731 for (i = 0; i < state->num_connector; i++) {
10732 if (!state->connectors[i])
accfc0c5
DV		 10733 continue;
10734
98a221da
ACO		 10735 connector_state = state->connector_states[i];
10736 if (connector_state->crtc != &crtc->base)
10737 continue;
10738
10739 encoder = to_intel_encoder(connector_state->best_encoder);
10740 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 10741 return false;
accfc0c5
DV		 10742 }
10743
bc079e8b 10744 return true;
accfc0c5
DV		 10745}
10746
5448a00d 10747static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 10748{
5448a00d
ACO		 10749 struct drm_device *dev = state->dev;
10750 struct intel_encoder *encoder;
10751 struct drm_connector_state *connector_state;
00f0b378 10752 unsigned int used_ports = 0;
5448a00d 10753 int i;
00f0b378
VS		 10754
10755 /*
10756 * Walk the connector list instead of the encoder
10757 * list to detect the problem on ddi platforms
10758 * where there's just one encoder per digital port.
10759 */
5448a00d
ACO		 10760 for (i = 0; i < state->num_connector; i++) {
10761 if (!state->connectors[i])
10762 continue;
00f0b378 10763
5448a00d
ACO		 10764 connector_state = state->connector_states[i];
10765 if (!connector_state->best_encoder)
00f0b378
VS		 10766 continue;
10767
5448a00d
ACO		 10768 encoder = to_intel_encoder(connector_state->best_encoder);
10769
10770 WARN_ON(!connector_state->crtc);
00f0b378
VS		 10771
10772 switch (encoder->type) {
10773 unsigned int port_mask;
10774 case INTEL_OUTPUT_UNKNOWN:
10775 if (WARN_ON(!HAS_DDI(dev)))
10776 break;
10777 case INTEL_OUTPUT_DISPLAYPORT:
10778 case INTEL_OUTPUT_HDMI:
10779 case INTEL_OUTPUT_EDP:
10780 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10781
10782 /* the same port mustn't appear more than once */
10783 if (used_ports & port_mask)
10784 return false;
10785
10786 used_ports |= port_mask;
10787 default:
10788 break;
10789 }
10790 }
10791
10792 return true;
10793}
10794
83a57153
ACO		 10795static void
10796clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10797{
10798 struct drm_crtc_state tmp_state;
10799
10800 /* Clear only the intel specific part of the crtc state */
10801 tmp_state = crtc_state->base;
10802 memset(crtc_state, 0, sizeof *crtc_state);
10803 crtc_state->base = tmp_state;
10804}
10805
5cec258b 10806static struct intel_crtc_state *
b8cecdf5 10807intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 10808 struct drm_framebuffer *fb,
83a57153
ACO		 10809 struct drm_display_mode *mode,
10810 struct drm_atomic_state *state)
ee7b9f93 10811{
7758a113 10812 struct intel_encoder *encoder;
0b901879
ACO		 10813 struct intel_connector *connector;
10814 struct drm_connector_state *connector_state;
5cec258b 10815 struct intel_crtc_state *pipe_config;
e29c22c0 10816 int plane_bpp, ret = -EINVAL;
0b901879 10817 int i;
e29c22c0 10818 bool retry = true;
ee7b9f93 10819
98a221da 10820 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5
DV		 10821 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10822 return ERR_PTR(-EINVAL);
10823 }
10824
5448a00d 10825 if (!check_digital_port_conflicts(state)) {
00f0b378
VS		 10826 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10827 return ERR_PTR(-EINVAL);
10828 }
10829
83a57153
ACO		 10830 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10831 if (IS_ERR(pipe_config))
10832 return pipe_config;
10833
10834 clear_intel_crtc_state(pipe_config);
7758a113 10835
07878248 10836 pipe_config->base.crtc = crtc;
2d112de7
ACO		 10837 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10838 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 10839
e143a21c
DV		 10840 pipe_config->cpu_transcoder =
10841 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 10842 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 10843
2960bc9c
ID		 10844 /*
10845 * Sanitize sync polarity flags based on requested ones. If neither
10846 * positive or negative polarity is requested, treat this as meaning
10847 * negative polarity.
10848 */
2d112de7 10849 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10850 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 10851 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 10852
2d112de7 10853 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10854 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 10855 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 10856
050f7aeb
DV		 10857 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10858 * plane pixel format and any sink constraints into account. Returns the
10859 * source plane bpp so that dithering can be selected on mismatches
10860 * after encoders and crtc also have had their say. */
10861 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10862 fb, pipe_config);
4e53c2e0
DV		 10863 if (plane_bpp < 0)
10864 goto fail;
10865
e41a56be
VS		 10866 /*
10867 * Determine the real pipe dimensions. Note that stereo modes can
10868 * increase the actual pipe size due to the frame doubling and
10869 * insertion of additional space for blanks between the frame. This
10870 * is stored in the crtc timings. We use the requested mode to do this
10871 * computation to clearly distinguish it from the adjusted mode, which
10872 * can be changed by the connectors in the below retry loop.
10873 */
2d112de7 10874 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 10875 &pipe_config->pipe_src_w,
10876 &pipe_config->pipe_src_h);
e41a56be 10877
e29c22c0 10878encoder_retry:
ef1b460d 10879 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 10880 pipe_config->port_clock = 0;
ef1b460d 10881 pipe_config->pixel_multiplier = 1;
ff9a6750 10882
135c81b8 10883 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 10884 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10885 CRTC_STEREO_DOUBLE);
135c81b8 10886
7758a113
DV		 10887 /* Pass our mode to the connectors and the CRTC to give them a chance to
10888 * adjust it according to limitations or connector properties, and also
10889 * a chance to reject the mode entirely.
47f1c6c9 10890 */
0b901879
ACO		 10891 for (i = 0; i < state->num_connector; i++) {
10892 connector = to_intel_connector(state->connectors[i]);
10893 if (!connector)
10894 continue;
47f1c6c9 10895
0b901879
ACO		 10896 connector_state = state->connector_states[i];
10897 if (connector_state->crtc != crtc)
7758a113 10898 continue;
7ae89233 10899
0b901879
ACO		 10900 encoder = to_intel_encoder(connector_state->best_encoder);
10901
efea6e8e
DV		 10902 if (!(encoder->compute_config(encoder, pipe_config))) {
10903 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 10904 goto fail;
10905 }
ee7b9f93 10906 }
47f1c6c9 10907
ff9a6750
DV		 10908 /* Set default port clock if not overwritten by the encoder. Needs to be
10909 * done afterwards in case the encoder adjusts the mode. */
10910 if (!pipe_config->port_clock)
2d112de7 10911 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 10912 * pipe_config->pixel_multiplier;
ff9a6750 10913
a43f6e0f 10914 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 10915 if (ret < 0) {
7758a113
DV		 10916 DRM_DEBUG_KMS("CRTC fixup failed\n");
10917 goto fail;
ee7b9f93 10918 }
e29c22c0
DV		 10919
10920 if (ret == RETRY) {
10921 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10922 ret = -EINVAL;
10923 goto fail;
10924 }
10925
10926 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10927 retry = false;
10928 goto encoder_retry;
10929 }
10930
4e53c2e0
DV		 10931 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10932 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10933 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10934
b8cecdf5 10935 return pipe_config;
7758a113 10936fail:
e29c22c0 10937 return ERR_PTR(ret);
ee7b9f93 10938}
47f1c6c9 10939
e2e1ed41
DV		 10940/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10941 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10942static void
10943intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10944 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 10945{
10946 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 10947 struct drm_device *dev = crtc->dev;
10948 struct intel_encoder *encoder;
10949 struct intel_connector *connector;
10950 struct drm_crtc *tmp_crtc;
79e53945 10951
e2e1ed41 10952 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 10953
e2e1ed41
DV		 10954 /* Check which crtcs have changed outputs connected to them, these need
10955 * to be part of the prepare_pipes mask. We don't (yet) support global
10956 * modeset across multiple crtcs, so modeset_pipes will only have one
10957 * bit set at most. */
3a3371ff 10958 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 10959 if (connector->base.encoder == &connector->new_encoder->base)
10960 continue;
79e53945 10961
e2e1ed41
DV		 10962 if (connector->base.encoder) {
10963 tmp_crtc = connector->base.encoder->crtc;
10964
10965 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10966 }
10967
10968 if (connector->new_encoder)
10969 *prepare_pipes |=
10970 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 10971 }
10972
b2784e15 10973 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 10974 if (encoder->base.crtc == &encoder->new_crtc->base)
10975 continue;
10976
10977 if (encoder->base.crtc) {
10978 tmp_crtc = encoder->base.crtc;
10979
10980 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10981 }
10982
10983 if (encoder->new_crtc)
10984 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 10985 }
10986
7668851f 10987 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 10988 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10989 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 10990 continue;
7e7d76c3 10991
7668851f 10992 if (!intel_crtc->new_enabled)
e2e1ed41 10993 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 10994 else
10995 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 10996 }
10997
e2e1ed41
DV		 10998
10999 /* set_mode is also used to update properties on life display pipes. */
11000 intel_crtc = to_intel_crtc(crtc);
7668851f 11001 if (intel_crtc->new_enabled)
e2e1ed41
DV		 11002 *prepare_pipes |= 1 << intel_crtc->pipe;
11003
b6c5164d
DV		 11004 /*
11005 * For simplicity do a full modeset on any pipe where the output routing
11006 * changed. We could be more clever, but that would require us to be
11007 * more careful with calling the relevant encoder->mode_set functions.
11008 */
e2e1ed41
DV		 11009 if (*prepare_pipes)
11010 *modeset_pipes = *prepare_pipes;
11011
11012 /* ... and mask these out. */
11013 *modeset_pipes &= ~(*disable_pipes);
11014 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 11015
11016 /*
11017 * HACK: We don't (yet) fully support global modesets. intel_set_config
11018 * obies this rule, but the modeset restore mode of
11019 * intel_modeset_setup_hw_state does not.
11020 */
11021 *modeset_pipes &= 1 << intel_crtc->pipe;
11022 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 11023
11024 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11025 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 11026}
79e53945 11027
ea9d758d 11028static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11029{
ea9d758d 11030 struct drm_encoder *encoder;
f6e5b160 11031 struct drm_device *dev = crtc->dev;
f6e5b160 11032
ea9d758d
DV		 11033 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11034 if (encoder->crtc == crtc)
11035 return true;
11036
11037 return false;
11038}
11039
11040static void
11041intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
11042{
ba41c0de 11043 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 11044 struct intel_encoder *intel_encoder;
11045 struct intel_crtc *intel_crtc;
11046 struct drm_connector *connector;
11047
ba41c0de
DV		 11048 intel_shared_dpll_commit(dev_priv);
11049
b2784e15 11050 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11051 if (!intel_encoder->base.crtc)
11052 continue;
11053
11054 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
11055
11056 if (prepare_pipes & (1 << intel_crtc->pipe))
11057 intel_encoder->connectors_active = false;
11058 }
11059
11060 intel_modeset_commit_output_state(dev);
11061
7668851f 11062 /* Double check state. */
d3fcc808 11063 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11064 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
ea9d758d
DV		 11065 }
11066
11067 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11068 if (!connector->encoder || !connector->encoder->crtc)
11069 continue;
11070
11071 intel_crtc = to_intel_crtc(connector->encoder->crtc);
11072
11073 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 11074 struct drm_property *dpms_property =
11075 dev->mode_config.dpms_property;
11076
ea9d758d 11077 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11078 drm_object_property_set_value(&connector->base,
68d34720
DV		 11079 dpms_property,
11080 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11081
11082 intel_encoder = to_intel_encoder(connector->encoder);
11083 intel_encoder->connectors_active = true;
11084 }
11085 }
11086
11087}
11088
3bd26263 11089static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11090{
3bd26263 11091 int diff;
f1f644dc
JB		 11092
11093 if (clock1 == clock2)
11094 return true;
11095
11096 if (!clock1 || !clock2)
11097 return false;
11098
11099 diff = abs(clock1 - clock2);
11100
11101 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11102 return true;
11103
11104 return false;
11105}
11106
25c5b266
DV		 11107#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11108 list_for_each_entry((intel_crtc), \
11109 &(dev)->mode_config.crtc_list, \
11110 base.head) \
0973f18f 11111 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11112
0e8ffe1b 11113static bool
2fa2fe9a 11114intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11115 struct intel_crtc_state *current_config,
11116 struct intel_crtc_state *pipe_config)
0e8ffe1b 11117{
66e985c0
DV		 11118#define PIPE_CONF_CHECK_X(name) \
11119 if (current_config->name != pipe_config->name) { \
11120 DRM_ERROR("mismatch in " #name " " \
11121 "(expected 0x%08x, found 0x%08x)\n", \
11122 current_config->name, \
11123 pipe_config->name); \
11124 return false; \
11125 }
11126
08a24034
DV		 11127#define PIPE_CONF_CHECK_I(name) \
11128 if (current_config->name != pipe_config->name) { \
11129 DRM_ERROR("mismatch in " #name " " \
11130 "(expected %i, found %i)\n", \
11131 current_config->name, \
11132 pipe_config->name); \
11133 return false; \
88adfff1
DV		 11134 }
11135
b95af8be
VK		 11136/* This is required for BDW+ where there is only one set of registers for
11137 * switching between high and low RR.
11138 * This macro can be used whenever a comparison has to be made between one
11139 * hw state and multiple sw state variables.
11140 */
11141#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11142 if ((current_config->name != pipe_config->name) && \
11143 (current_config->alt_name != pipe_config->name)) { \
11144 DRM_ERROR("mismatch in " #name " " \
11145 "(expected %i or %i, found %i)\n", \
11146 current_config->name, \
11147 current_config->alt_name, \
11148 pipe_config->name); \
11149 return false; \
11150 }
11151
1bd1bd80
DV		 11152#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11153 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11154 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11155 "(expected %i, found %i)\n", \
11156 current_config->name & (mask), \
11157 pipe_config->name & (mask)); \
11158 return false; \
11159 }
11160
5e550656
VS		 11161#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11162 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11163 DRM_ERROR("mismatch in " #name " " \
11164 "(expected %i, found %i)\n", \
11165 current_config->name, \
11166 pipe_config->name); \
11167 return false; \
11168 }
11169
bb760063
DV		 11170#define PIPE_CONF_QUIRK(quirk) \
11171 ((current_config->quirks | pipe_config->quirks) & (quirk))
11172
eccb140b
DV		 11173 PIPE_CONF_CHECK_I(cpu_transcoder);
11174
08a24034
DV		 11175 PIPE_CONF_CHECK_I(has_pch_encoder);
11176 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11177 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11178 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11179 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11180 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11181 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11182
eb14cb74 11183 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11184
11185 if (INTEL_INFO(dev)->gen < 8) {
11186 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11187 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11188 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11189 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11190 PIPE_CONF_CHECK_I(dp_m_n.tu);
11191
11192 if (current_config->has_drrs) {
11193 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11194 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11195 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11196 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11197 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11198 }
11199 } else {
11200 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11201 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11202 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11203 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11204 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11205 }
eb14cb74 11206
2d112de7
ACO		 11207 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11208 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11209 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11210 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11211 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11212 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11213
2d112de7
ACO		 11214 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11215 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11216 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11217 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11218 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11219 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11220
c93f54cf 11221 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11222 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11223 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11224 IS_VALLEYVIEW(dev))
11225 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11226 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11227
9ed109a7
DV		 11228 PIPE_CONF_CHECK_I(has_audio);
11229
2d112de7 11230 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11231 DRM_MODE_FLAG_INTERLACE);
11232
bb760063 11233 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11234 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11235 DRM_MODE_FLAG_PHSYNC);
2d112de7 11236 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11237 DRM_MODE_FLAG_NHSYNC);
2d112de7 11238 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11239 DRM_MODE_FLAG_PVSYNC);
2d112de7 11240 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11241 DRM_MODE_FLAG_NVSYNC);
11242 }
045ac3b5 11243
37327abd
VS		 11244 PIPE_CONF_CHECK_I(pipe_src_w);
11245 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11246
9953599b
DV		 11247 /*
11248 * FIXME: BIOS likes to set up a cloned config with lvds+external
11249 * screen. Since we don't yet re-compute the pipe config when moving
11250 * just the lvds port away to another pipe the sw tracking won't match.
11251 *
11252 * Proper atomic modesets with recomputed global state will fix this.
11253 * Until then just don't check gmch state for inherited modes.
11254 */
11255 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11256 PIPE_CONF_CHECK_I(gmch_pfit.control);
11257 /* pfit ratios are autocomputed by the hw on gen4+ */
11258 if (INTEL_INFO(dev)->gen < 4)
11259 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11260 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11261 }
11262
fd4daa9c
CW		 11263 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11264 if (current_config->pch_pfit.enabled) {
11265 PIPE_CONF_CHECK_I(pch_pfit.pos);
11266 PIPE_CONF_CHECK_I(pch_pfit.size);
11267 }
2fa2fe9a 11268
e59150dc
JB		 11269 /* BDW+ don't expose a synchronous way to read the state */
11270 if (IS_HASWELL(dev))
11271 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11272
282740f7
VS		 11273 PIPE_CONF_CHECK_I(double_wide);
11274
26804afd
DV		 11275 PIPE_CONF_CHECK_X(ddi_pll_sel);
11276
c0d43d62 11277 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11278 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11279 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11280 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11281 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11282 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11283 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11284 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11285 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11286
42571aef
VS		 11287 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11288 PIPE_CONF_CHECK_I(pipe_bpp);
11289
2d112de7 11290 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11291 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11292
66e985c0 11293#undef PIPE_CONF_CHECK_X
08a24034 11294#undef PIPE_CONF_CHECK_I
b95af8be 11295#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11296#undef PIPE_CONF_CHECK_FLAGS
5e550656 11297#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11298#undef PIPE_CONF_QUIRK
88adfff1 11299
0e8ffe1b
DV		 11300 return true;
11301}
11302
08db6652
DL		 11303static void check_wm_state(struct drm_device *dev)
11304{
11305 struct drm_i915_private *dev_priv = dev->dev_private;
11306 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11307 struct intel_crtc *intel_crtc;
11308 int plane;
11309
11310 if (INTEL_INFO(dev)->gen < 9)
11311 return;
11312
11313 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11314 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11315
11316 for_each_intel_crtc(dev, intel_crtc) {
11317 struct skl_ddb_entry *hw_entry, *sw_entry;
11318 const enum pipe pipe = intel_crtc->pipe;
11319
11320 if (!intel_crtc->active)
11321 continue;
11322
11323 /* planes */
dd740780 11324 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11325 hw_entry = &hw_ddb.plane[pipe][plane];
11326 sw_entry = &sw_ddb->plane[pipe][plane];
11327
11328 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11329 continue;
11330
11331 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11332 "(expected (%u,%u), found (%u,%u))\n",
11333 pipe_name(pipe), plane + 1,
11334 sw_entry->start, sw_entry->end,
11335 hw_entry->start, hw_entry->end);
11336 }
11337
11338 /* cursor */
11339 hw_entry = &hw_ddb.cursor[pipe];
11340 sw_entry = &sw_ddb->cursor[pipe];
11341
11342 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11343 continue;
11344
11345 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11346 "(expected (%u,%u), found (%u,%u))\n",
11347 pipe_name(pipe),
11348 sw_entry->start, sw_entry->end,
11349 hw_entry->start, hw_entry->end);
11350 }
11351}
11352
91d1b4bd
DV		 11353static void
11354check_connector_state(struct drm_device *dev)
8af6cf88 11355{
8af6cf88
DV		 11356 struct intel_connector *connector;
11357
3a3371ff 11358 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11359 /* This also checks the encoder/connector hw state with the
11360 * ->get_hw_state callbacks. */
11361 intel_connector_check_state(connector);
11362
e2c719b7 11363 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11364 "connector's staged encoder doesn't match current encoder\n");
11365 }
91d1b4bd
DV		 11366}
11367
11368static void
11369check_encoder_state(struct drm_device *dev)
11370{
11371 struct intel_encoder *encoder;
11372 struct intel_connector *connector;
8af6cf88 11373
b2784e15 11374 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11375 bool enabled = false;
11376 bool active = false;
11377 enum pipe pipe, tracked_pipe;
11378
11379 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11380 encoder->base.base.id,
8e329a03 11381 encoder->base.name);
8af6cf88 11382
e2c719b7 11383 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11384 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11385 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11386 "encoder's active_connectors set, but no crtc\n");
11387
3a3371ff 11388 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11389 if (connector->base.encoder != &encoder->base)
11390 continue;
11391 enabled = true;
11392 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11393 active = true;
11394 }
0e32b39c
DA		 11395 /*
11396 * for MST connectors if we unplug the connector is gone
11397 * away but the encoder is still connected to a crtc
11398 * until a modeset happens in response to the hotplug.
11399 */
11400 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11401 continue;
11402
e2c719b7 11403 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11404 "encoder's enabled state mismatch "
11405 "(expected %i, found %i)\n",
11406 !!encoder->base.crtc, enabled);
e2c719b7 11407 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11408 "active encoder with no crtc\n");
11409
e2c719b7 11410 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11411 "encoder's computed active state doesn't match tracked active state "
11412 "(expected %i, found %i)\n", active, encoder->connectors_active);
11413
11414 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11415 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11416 "encoder's hw state doesn't match sw tracking "
11417 "(expected %i, found %i)\n",
11418 encoder->connectors_active, active);
11419
11420 if (!encoder->base.crtc)
11421 continue;
11422
11423 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11424 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11425 "active encoder's pipe doesn't match"
11426 "(expected %i, found %i)\n",
11427 tracked_pipe, pipe);
11428
11429 }
91d1b4bd
DV		 11430}
11431
11432static void
11433check_crtc_state(struct drm_device *dev)
11434{
fbee40df 11435 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11436 struct intel_crtc *crtc;
11437 struct intel_encoder *encoder;
5cec258b 11438 struct intel_crtc_state pipe_config;
8af6cf88 11439
d3fcc808 11440 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11441 bool enabled = false;
11442 bool active = false;
11443
045ac3b5
JB		 11444 memset(&pipe_config, 0, sizeof(pipe_config));
11445
8af6cf88
DV		 11446 DRM_DEBUG_KMS("[CRTC:%d]\n",
11447 crtc->base.base.id);
11448
83d65738 11449 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11450 "active crtc, but not enabled in sw tracking\n");
11451
b2784e15 11452 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11453 if (encoder->base.crtc != &crtc->base)
11454 continue;
11455 enabled = true;
11456 if (encoder->connectors_active)
11457 active = true;
11458 }
6c49f241 11459
e2c719b7 11460 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11461 "crtc's computed active state doesn't match tracked active state "
11462 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11463 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11464 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11465 "(expected %i, found %i)\n", enabled,
11466 crtc->base.state->enable);
8af6cf88 11467
0e8ffe1b
DV		 11468 active = dev_priv->display.get_pipe_config(crtc,
11469 &pipe_config);
d62cf62a 11470
b6b5d049
VS		 11471 /* hw state is inconsistent with the pipe quirk */
11472 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11473 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11474 active = crtc->active;
11475
b2784e15 11476 for_each_intel_encoder(dev, encoder) {
3eaba51c 11477 enum pipe pipe;
6c49f241
DV		 11478 if (encoder->base.crtc != &crtc->base)
11479 continue;
1d37b689 11480 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11481 encoder->get_config(encoder, &pipe_config);
11482 }
11483
e2c719b7 11484 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11485 "crtc active state doesn't match with hw state "
11486 "(expected %i, found %i)\n", crtc->active, active);
11487
c0b03411 11488 if (active &&
6e3c9717 11489 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11490 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11491 intel_dump_pipe_config(crtc, &pipe_config,
11492 "[hw state]");
6e3c9717 11493 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11494 "[sw state]");
11495 }
8af6cf88
DV		 11496 }
11497}
11498
91d1b4bd
DV		 11499static void
11500check_shared_dpll_state(struct drm_device *dev)
11501{
fbee40df 11502 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11503 struct intel_crtc *crtc;
11504 struct intel_dpll_hw_state dpll_hw_state;
11505 int i;
5358901f
DV		 11506
11507 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11508 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11509 int enabled_crtcs = 0, active_crtcs = 0;
11510 bool active;
11511
11512 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11513
11514 DRM_DEBUG_KMS("%s\n", pll->name);
11515
11516 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11517
e2c719b7 11518 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11519 "more active pll users than references: %i vs %i\n",
3e369b76 11520 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11521 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11522 "pll in active use but not on in sw tracking\n");
e2c719b7 11523 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11524 "pll in on but not on in use in sw tracking\n");
e2c719b7 11525 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11526 "pll on state mismatch (expected %i, found %i)\n",
11527 pll->on, active);
11528
d3fcc808 11529 for_each_intel_crtc(dev, crtc) {
83d65738 11530 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11531 enabled_crtcs++;
11532 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11533 active_crtcs++;
11534 }
e2c719b7 11535 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11536 "pll active crtcs mismatch (expected %i, found %i)\n",
11537 pll->active, active_crtcs);
e2c719b7 11538 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11539 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11540 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11541
e2c719b7 11542 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11543 sizeof(dpll_hw_state)),
11544 "pll hw state mismatch\n");
5358901f 11545 }
8af6cf88
DV		 11546}
11547
91d1b4bd
DV		 11548void
11549intel_modeset_check_state(struct drm_device *dev)
11550{
08db6652 11551 check_wm_state(dev);
91d1b4bd
DV		 11552 check_connector_state(dev);
11553 check_encoder_state(dev);
11554 check_crtc_state(dev);
11555 check_shared_dpll_state(dev);
11556}
11557
5cec258b 11558void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11559 int dotclock)
11560{
11561 /*
11562 * FDI already provided one idea for the dotclock.
11563 * Yell if the encoder disagrees.
11564 */
2d112de7 11565 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11566 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11567 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11568}
11569
80715b2f
VS		 11570static void update_scanline_offset(struct intel_crtc *crtc)
11571{
11572 struct drm_device *dev = crtc->base.dev;
11573
11574 /*
11575 * The scanline counter increments at the leading edge of hsync.
11576 *
11577 * On most platforms it starts counting from vtotal-1 on the
11578 * first active line. That means the scanline counter value is
11579 * always one less than what we would expect. Ie. just after
11580 * start of vblank, which also occurs at start of hsync (on the
11581 * last active line), the scanline counter will read vblank_start-1.
11582 *
11583 * On gen2 the scanline counter starts counting from 1 instead
11584 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11585 * to keep the value positive), instead of adding one.
11586 *
11587 * On HSW+ the behaviour of the scanline counter depends on the output
11588 * type. For DP ports it behaves like most other platforms, but on HDMI
11589 * there's an extra 1 line difference. So we need to add two instead of
11590 * one to the value.
11591 */
11592 if (IS_GEN2(dev)) {
6e3c9717 11593 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11594 int vtotal;
11595
11596 vtotal = mode->crtc_vtotal;
11597 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11598 vtotal /= 2;
11599
11600 crtc->scanline_offset = vtotal - 1;
11601 } else if (HAS_DDI(dev) &&
409ee761 11602 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11603 crtc->scanline_offset = 2;
11604 } else
11605 crtc->scanline_offset = 1;
11606}
11607
5cec258b 11608static struct intel_crtc_state *
7f27126e
JB		 11609intel_modeset_compute_config(struct drm_crtc *crtc,
11610 struct drm_display_mode *mode,
11611 struct drm_framebuffer *fb,
83a57153 11612 struct drm_atomic_state *state,
7f27126e
JB		 11613 unsigned *modeset_pipes,
11614 unsigned *prepare_pipes,
11615 unsigned *disable_pipes)
11616{
db7542dd 11617 struct drm_device *dev = crtc->dev;
5cec258b 11618 struct intel_crtc_state *pipe_config = NULL;
db7542dd 11619 struct intel_crtc *intel_crtc;
0b901879
ACO		 11620 int ret = 0;
11621
11622 ret = drm_atomic_add_affected_connectors(state, crtc);
11623 if (ret)
11624 return ERR_PTR(ret);
7f27126e
JB		 11625
11626 intel_modeset_affected_pipes(crtc, modeset_pipes,
11627 prepare_pipes, disable_pipes);
11628
db7542dd
ACO		 11629 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11630 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11631 if (IS_ERR(pipe_config))
11632 return pipe_config;
11633
11634 pipe_config->base.enable = false;
11635 }
7f27126e
JB		 11636
11637 /*
11638 * Note this needs changes when we start tracking multiple modes
11639 * and crtcs. At that point we'll need to compute the whole config
11640 * (i.e. one pipe_config for each crtc) rather than just the one
11641 * for this crtc.
11642 */
db7542dd
ACO		 11643 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11644 /* FIXME: For now we still expect modeset_pipes has at most
11645 * one bit set. */
11646 if (WARN_ON(&intel_crtc->base != crtc))
11647 continue;
83a57153 11648
db7542dd
ACO		 11649 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11650 if (IS_ERR(pipe_config))
11651 return pipe_config;
7f27126e 11652
304603f4
ACO		 11653 pipe_config->base.enable = true;
11654
db7542dd
ACO		 11655 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11656 "[modeset]");
11657 }
11658
11659 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 11660}
11661
225da59b 11662static int __intel_set_mode_setup_plls(struct drm_atomic_state *state,
ed6739ef
ACO		 11663 unsigned modeset_pipes,
11664 unsigned disable_pipes)
11665{
225da59b 11666 struct drm_device *dev = state->dev;
ed6739ef
ACO		 11667 struct drm_i915_private *dev_priv = to_i915(dev);
11668 unsigned clear_pipes = modeset_pipes | disable_pipes;
11669 struct intel_crtc *intel_crtc;
11670 int ret = 0;
11671
11672 if (!dev_priv->display.crtc_compute_clock)
11673 return 0;
11674
11675 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11676 if (ret)
11677 goto done;
11678
11679 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
225da59b
ACO		 11680 struct intel_crtc_state *crtc_state =
11681 intel_atomic_get_crtc_state(state, intel_crtc);
11682
11683 /* Modeset pipes should have a new state by now */
11684 if (WARN_ON(IS_ERR(crtc_state)))
11685 continue;
11686
ed6739ef 11687 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
225da59b 11688 crtc_state);
ed6739ef
ACO		 11689 if (ret) {
11690 intel_shared_dpll_abort_config(dev_priv);
11691 goto done;
11692 }
11693 }
11694
11695done:
11696 return ret;
11697}
11698
f30da187
DV		 11699static int __intel_set_mode(struct drm_crtc *crtc,
11700 struct drm_display_mode *mode,
7f27126e 11701 int x, int y, struct drm_framebuffer *fb,
5cec258b 11702 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11703 unsigned modeset_pipes,
11704 unsigned prepare_pipes,
11705 unsigned disable_pipes)
a6778b3c
DV		 11706{
11707 struct drm_device *dev = crtc->dev;
fbee40df 11708 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11709 struct drm_display_mode *saved_mode;
304603f4 11710 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 11711 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 11712 struct intel_crtc *intel_crtc;
c0c36b94 11713 int ret = 0;
a6778b3c 11714
4b4b9238 11715 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11716 if (!saved_mode)
11717 return -ENOMEM;
a6778b3c 11718
83a57153
ACO		 11719 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11720 if (!crtc_state_copy) {
11721 ret = -ENOMEM;
11722 goto done;
11723 }
11724
3ac18232 11725 *saved_mode = crtc->mode;
a6778b3c 11726
30a970c6
JB		 11727 /*
11728 * See if the config requires any additional preparation, e.g.
11729 * to adjust global state with pipes off. We need to do this
11730 * here so we can get the modeset_pipe updated config for the new
11731 * mode set on this crtc. For other crtcs we need to use the
11732 * adjusted_mode bits in the crtc directly.
11733 */
c164f833 11734 if (IS_VALLEYVIEW(dev)) {
304603f4
ACO		 11735 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
11736 if (ret)
11737 goto done;
30a970c6 11738
c164f833
VS		 11739 /* may have added more to prepare_pipes than we should */
11740 prepare_pipes &= ~disable_pipes;
11741 }
11742
225da59b 11743 ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
ed6739ef
ACO		 11744 if (ret)
11745 goto done;
8bd31e67 11746
460da916
DV		 11747 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11748 intel_crtc_disable(&intel_crtc->base);
11749
ea9d758d 11750 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 11751 if (intel_crtc->base.state->enable)
ea9d758d
DV		 11752 dev_priv->display.crtc_disable(&intel_crtc->base);
11753 }
a6778b3c 11754
6c4c86f5
DV		 11755 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11756 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 11757 *
11758 * Note we'll need to fix this up when we start tracking multiple
11759 * pipes; here we assume a single modeset_pipe and only track the
11760 * single crtc and mode.
f6e5b160 11761 */
b8cecdf5 11762 if (modeset_pipes) {
25c5b266 11763 crtc->mode = *mode;
b8cecdf5
DV		 11764 /* mode_set/enable/disable functions rely on a correct pipe
11765 * config. */
f5de6e07 11766 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 11767
11768 /*
11769 * Calculate and store various constants which
11770 * are later needed by vblank and swap-completion
11771 * timestamping. They are derived from true hwmode.
11772 */
11773 drm_calc_timestamping_constants(crtc,
2d112de7 11774 &pipe_config->base.adjusted_mode);
b8cecdf5 11775 }
7758a113 11776
ea9d758d
DV		 11777 /* Only after disabling all output pipelines that will be changed can we
11778 * update the the output configuration. */
11779 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 11780
304603f4 11781 modeset_update_crtc_power_domains(state);
47fab737 11782
25c5b266 11783 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 11784 struct drm_plane *primary = intel_crtc->base.primary;
11785 int vdisplay, hdisplay;
4c10794f 11786
455a6808 11787 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
70a101f8
MR		 11788 ret = drm_plane_helper_update(primary, &intel_crtc->base,
11789 fb, 0, 0,
11790 hdisplay, vdisplay,
11791 x << 16, y << 16,
11792 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 11793 }
11794
11795 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 11796 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11797 update_scanline_offset(intel_crtc);
11798
25c5b266 11799 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 11800 }
a6778b3c 11801
a6778b3c
DV		 11802 /* FIXME: add subpixel order */
11803done:
83d65738 11804 if (ret && crtc->state->enable)
3ac18232 11805 crtc->mode = *saved_mode;
a6778b3c 11806
83a57153
ACO		 11807 if (ret == 0 && pipe_config) {
11808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11809
11810 /* The pipe_config will be freed with the atomic state, so
11811 * make a copy. */
11812 memcpy(crtc_state_copy, intel_crtc->config,
11813 sizeof *crtc_state_copy);
11814 intel_crtc->config = crtc_state_copy;
11815 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 11816 } else {
11817 kfree(crtc_state_copy);
11818 }
11819
3ac18232 11820 kfree(saved_mode);
a6778b3c 11821 return ret;
f6e5b160
CW		 11822}
11823
7f27126e
JB		 11824static int intel_set_mode_pipes(struct drm_crtc *crtc,
11825 struct drm_display_mode *mode,
11826 int x, int y, struct drm_framebuffer *fb,
5cec258b 11827 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11828 unsigned modeset_pipes,
11829 unsigned prepare_pipes,
11830 unsigned disable_pipes)
f30da187
DV		 11831{
11832 int ret;
11833
7f27126e
JB		 11834 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11835 prepare_pipes, disable_pipes);
f30da187
DV		 11836
11837 if (ret == 0)
11838 intel_modeset_check_state(crtc->dev);
11839
11840 return ret;
11841}
11842
7f27126e
JB		 11843static int intel_set_mode(struct drm_crtc *crtc,
11844 struct drm_display_mode *mode,
83a57153
ACO		 11845 int x, int y, struct drm_framebuffer *fb,
11846 struct drm_atomic_state *state)
7f27126e 11847{
5cec258b 11848 struct intel_crtc_state *pipe_config;
7f27126e 11849 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 11850 int ret = 0;
7f27126e 11851
83a57153 11852 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
7f27126e
JB		 11853 &modeset_pipes,
11854 &prepare_pipes,
11855 &disable_pipes);
11856
83a57153
ACO		 11857 if (IS_ERR(pipe_config)) {
11858 ret = PTR_ERR(pipe_config);
11859 goto out;
11860 }
11861
11862 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11863 modeset_pipes, prepare_pipes,
11864 disable_pipes);
11865 if (ret)
11866 goto out;
7f27126e 11867
83a57153
ACO		 11868out:
11869 return ret;
7f27126e
JB		 11870}
11871
c0c36b94
CW		 11872void intel_crtc_restore_mode(struct drm_crtc *crtc)
11873{
83a57153
ACO		 11874 struct drm_device *dev = crtc->dev;
11875 struct drm_atomic_state *state;
11876 struct intel_encoder *encoder;
11877 struct intel_connector *connector;
11878 struct drm_connector_state *connector_state;
11879
11880 state = drm_atomic_state_alloc(dev);
11881 if (!state) {
11882 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11883 crtc->base.id);
11884 return;
11885 }
11886
11887 state->acquire_ctx = dev->mode_config.acquire_ctx;
11888
11889 /* The force restore path in the HW readout code relies on the staged
11890 * config still keeping the user requested config while the actual
11891 * state has been overwritten by the configuration read from HW. We
11892 * need to copy the staged config to the atomic state, otherwise the
11893 * mode set will just reapply the state the HW is already in. */
11894 for_each_intel_encoder(dev, encoder) {
11895 if (&encoder->new_crtc->base != crtc)
11896 continue;
11897
11898 for_each_intel_connector(dev, connector) {
11899 if (connector->new_encoder != encoder)
11900 continue;
11901
11902 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11903 if (IS_ERR(connector_state)) {
11904 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11905 connector->base.base.id,
11906 connector->base.name,
11907 PTR_ERR(connector_state));
11908 continue;
11909 }
11910
11911 connector_state->crtc = crtc;
11912 connector_state->best_encoder = &encoder->base;
11913 }
11914 }
11915
11916 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11917 state);
11918
11919 drm_atomic_state_free(state);
c0c36b94
CW		 11920}
11921
25c5b266
DV		 11922#undef for_each_intel_crtc_masked
11923
d9e55608
DV		 11924static void intel_set_config_free(struct intel_set_config *config)
11925{
11926 if (!config)
11927 return;
11928
1aa4b628
DV		 11929 kfree(config->save_connector_encoders);
11930 kfree(config->save_encoder_crtcs);
7668851f 11931 kfree(config->save_crtc_enabled);
d9e55608
DV		 11932 kfree(config);
11933}
11934
85f9eb71
DV		 11935static int intel_set_config_save_state(struct drm_device *dev,
11936 struct intel_set_config *config)
11937{
7668851f 11938 struct drm_crtc *crtc;
85f9eb71
DV		 11939 struct drm_encoder *encoder;
11940 struct drm_connector *connector;
11941 int count;
11942
7668851f
VS		 11943 config->save_crtc_enabled =
11944 kcalloc(dev->mode_config.num_crtc,
11945 sizeof(bool), GFP_KERNEL);
11946 if (!config->save_crtc_enabled)
11947 return -ENOMEM;
11948
1aa4b628
DV		 11949 config->save_encoder_crtcs =
11950 kcalloc(dev->mode_config.num_encoder,
11951 sizeof(struct drm_crtc *), GFP_KERNEL);
11952 if (!config->save_encoder_crtcs)
85f9eb71
DV		 11953 return -ENOMEM;
11954
1aa4b628
DV		 11955 config->save_connector_encoders =
11956 kcalloc(dev->mode_config.num_connector,
11957 sizeof(struct drm_encoder *), GFP_KERNEL);
11958 if (!config->save_connector_encoders)
85f9eb71
DV		 11959 return -ENOMEM;
11960
11961 /* Copy data. Note that driver private data is not affected.
11962 * Should anything bad happen only the expected state is
11963 * restored, not the drivers personal bookkeeping.
11964 */
7668851f 11965 count = 0;
70e1e0ec 11966 for_each_crtc(dev, crtc) {
83d65738 11967 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 11968 }
11969
85f9eb71
DV		 11970 count = 0;
11971 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 11972 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 11973 }
11974
11975 count = 0;
11976 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 11977 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 11978 }
11979
11980 return 0;
11981}
11982
11983static void intel_set_config_restore_state(struct drm_device *dev,
11984 struct intel_set_config *config)
11985{
7668851f 11986 struct intel_crtc *crtc;
9a935856
DV		 11987 struct intel_encoder *encoder;
11988 struct intel_connector *connector;
85f9eb71
DV		 11989 int count;
11990
7668851f 11991 count = 0;
d3fcc808 11992 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 11993 crtc->new_enabled = config->save_crtc_enabled[count++];
11994 }
11995
85f9eb71 11996 count = 0;
b2784e15 11997 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11998 encoder->new_crtc =
11999 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 12000 }
12001
12002 count = 0;
3a3371ff 12003 for_each_intel_connector(dev, connector) {
9a935856
DV		 12004 connector->new_encoder =
12005 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 12006 }
12007}
12008
e3de42b6 12009static bool
2e57f47d 12010is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12011{
12012 int i;
12013
2e57f47d
CW		 12014 if (set->num_connectors == 0)
12015 return false;
12016
12017 if (WARN_ON(set->connectors == NULL))
12018 return false;
12019
12020 for (i = 0; i < set->num_connectors; i++)
12021 if (set->connectors[i]->encoder &&
12022 set->connectors[i]->encoder->crtc == set->crtc &&
12023 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12024 return true;
12025
12026 return false;
12027}
12028
5e2b584e
DV		 12029static void
12030intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12031 struct intel_set_config *config)
12032{
12033
12034 /* We should be able to check here if the fb has the same properties
12035 * and then just flip_or_move it */
2e57f47d
CW		 12036 if (is_crtc_connector_off(set)) {
12037 config->mode_changed = true;
f4510a27 12038 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12039 /*
12040 * If we have no fb, we can only flip as long as the crtc is
12041 * active, otherwise we need a full mode set. The crtc may
12042 * be active if we've only disabled the primary plane, or
12043 * in fastboot situations.
12044 */
f4510a27 12045 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12046 struct intel_crtc *intel_crtc =
12047 to_intel_crtc(set->crtc);
12048
3b150f08 12049 if (intel_crtc->active) {
319d9827
JB		 12050 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12051 config->fb_changed = true;
12052 } else {
12053 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12054 config->mode_changed = true;
12055 }
5e2b584e
DV		 12056 } else if (set->fb == NULL) {
12057 config->mode_changed = true;
72f4901e 12058 } else if (set->fb->pixel_format !=
f4510a27 12059 set->crtc->primary->fb->pixel_format) {
5e2b584e 12060 config->mode_changed = true;
e3de42b6 12061 } else {
5e2b584e 12062 config->fb_changed = true;
e3de42b6 12063 }
5e2b584e
DV		 12064 }
12065
835c5873 12066 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 12067 config->fb_changed = true;
12068
12069 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12070 DRM_DEBUG_KMS("modes are different, full mode set\n");
12071 drm_mode_debug_printmodeline(&set->crtc->mode);
12072 drm_mode_debug_printmodeline(set->mode);
12073 config->mode_changed = true;
12074 }
a1d95703
CW		 12075
12076 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12077 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12078}
12079
2e431051 12080static int
9a935856
DV		 12081intel_modeset_stage_output_state(struct drm_device *dev,
12082 struct drm_mode_set *set,
944b0c76
ACO		 12083 struct intel_set_config *config,
12084 struct drm_atomic_state *state)
50f56119 12085{
9a935856 12086 struct intel_connector *connector;
944b0c76 12087 struct drm_connector_state *connector_state;
9a935856 12088 struct intel_encoder *encoder;
7668851f 12089 struct intel_crtc *crtc;
f3f08572 12090 int ro;
50f56119 12091
9abdda74 12092 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12093 * of connectors. For paranoia, double-check this. */
12094 WARN_ON(!set->fb && (set->num_connectors != 0));
12095 WARN_ON(set->fb && (set->num_connectors == 0));
12096
3a3371ff 12097 for_each_intel_connector(dev, connector) {
9a935856
DV		 12098 /* Otherwise traverse passed in connector list and get encoders
12099 * for them. */
50f56119 12100 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12101 if (set->connectors[ro] == &connector->base) {
0e32b39c 12102 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12103 break;
12104 }
12105 }
12106
9a935856
DV		 12107 /* If we disable the crtc, disable all its connectors. Also, if
12108 * the connector is on the changing crtc but not on the new
12109 * connector list, disable it. */
12110 if ((!set->fb || ro == set->num_connectors) &&
12111 connector->base.encoder &&
12112 connector->base.encoder->crtc == set->crtc) {
12113 connector->new_encoder = NULL;
12114
12115 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12116 connector->base.base.id,
c23cc417 12117 connector->base.name);
9a935856
DV		 12118 }
12119
12120
12121 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12122 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12123 connector->base.base.id,
12124 connector->base.name);
5e2b584e 12125 config->mode_changed = true;
50f56119
DV		 12126 }
12127 }
9a935856 12128 /* connector->new_encoder is now updated for all connectors. */
50f56119 12129
9a935856 12130 /* Update crtc of enabled connectors. */
3a3371ff 12131 for_each_intel_connector(dev, connector) {
7668851f
VS		 12132 struct drm_crtc *new_crtc;
12133
9a935856 12134 if (!connector->new_encoder)
50f56119
DV		 12135 continue;
12136
9a935856 12137 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12138
12139 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12140 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12141 new_crtc = set->crtc;
12142 }
12143
12144 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12145 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12146 new_crtc)) {
5e2b584e 12147 return -EINVAL;
50f56119 12148 }
0e32b39c 12149 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12150
944b0c76
ACO		 12151 connector_state =
12152 drm_atomic_get_connector_state(state, &connector->base);
12153 if (IS_ERR(connector_state))
12154 return PTR_ERR(connector_state);
12155
12156 connector_state->crtc = new_crtc;
12157 connector_state->best_encoder = &connector->new_encoder->base;
12158
9a935856
DV		 12159 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12160 connector->base.base.id,
c23cc417 12161 connector->base.name,
9a935856
DV		 12162 new_crtc->base.id);
12163 }
12164
12165 /* Check for any encoders that needs to be disabled. */
b2784e15 12166 for_each_intel_encoder(dev, encoder) {
5a65f358 12167 int num_connectors = 0;
3a3371ff 12168 for_each_intel_connector(dev, connector) {
9a935856
DV		 12169 if (connector->new_encoder == encoder) {
12170 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12171 num_connectors++;
9a935856
DV		 12172 }
12173 }
5a65f358
PZ		 12174
12175 if (num_connectors == 0)
12176 encoder->new_crtc = NULL;
12177 else if (num_connectors > 1)
12178 return -EINVAL;
12179
9a935856
DV		 12180 /* Only now check for crtc changes so we don't miss encoders
12181 * that will be disabled. */
12182 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12183 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12184 encoder->base.base.id,
12185 encoder->base.name);
5e2b584e 12186 config->mode_changed = true;
50f56119
DV		 12187 }
12188 }
9a935856 12189 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12190 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12191 connector_state =
12192 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12193 if (IS_ERR(connector_state))
12194 return PTR_ERR(connector_state);
944b0c76
ACO		 12195
12196 if (connector->new_encoder) {
0e32b39c
DA		 12197 if (connector->new_encoder != connector->encoder)
12198 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12199 } else {
12200 connector_state->crtc = NULL;
f61cccf3 12201 connector_state->best_encoder = NULL;
944b0c76 12202 }
0e32b39c 12203 }
d3fcc808 12204 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12205 crtc->new_enabled = false;
12206
b2784e15 12207 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12208 if (encoder->new_crtc == crtc) {
12209 crtc->new_enabled = true;
12210 break;
12211 }
12212 }
12213
83d65738 12214 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12215 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12216 crtc->base.base.id,
7668851f
VS		 12217 crtc->new_enabled ? "en" : "dis");
12218 config->mode_changed = true;
12219 }
12220 }
12221
2e431051
DV		 12222 return 0;
12223}
12224
7d00a1f5
VS		 12225static void disable_crtc_nofb(struct intel_crtc *crtc)
12226{
12227 struct drm_device *dev = crtc->base.dev;
12228 struct intel_encoder *encoder;
12229 struct intel_connector *connector;
12230
12231 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12232 pipe_name(crtc->pipe));
12233
3a3371ff 12234 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12235 if (connector->new_encoder &&
12236 connector->new_encoder->new_crtc == crtc)
12237 connector->new_encoder = NULL;
12238 }
12239
b2784e15 12240 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12241 if (encoder->new_crtc == crtc)
12242 encoder->new_crtc = NULL;
12243 }
12244
12245 crtc->new_enabled = false;
12246}
12247
2e431051
DV		 12248static int intel_crtc_set_config(struct drm_mode_set *set)
12249{
12250 struct drm_device *dev;
2e431051 12251 struct drm_mode_set save_set;
83a57153 12252 struct drm_atomic_state *state = NULL;
2e431051 12253 struct intel_set_config *config;
5cec258b 12254 struct intel_crtc_state *pipe_config;
50f52756 12255 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12256 int ret;
2e431051 12257
8d3e375e
DV		 12258 BUG_ON(!set);
12259 BUG_ON(!set->crtc);
12260 BUG_ON(!set->crtc->helper_private);
2e431051 12261
7e53f3a4
DV		 12262 /* Enforce sane interface api - has been abused by the fb helper. */
12263 BUG_ON(!set->mode && set->fb);
12264 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12265
2e431051
DV		 12266 if (set->fb) {
12267 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12268 set->crtc->base.id, set->fb->base.id,
12269 (int)set->num_connectors, set->x, set->y);
12270 } else {
12271 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12272 }
12273
12274 dev = set->crtc->dev;
12275
12276 ret = -ENOMEM;
12277 config = kzalloc(sizeof(*config), GFP_KERNEL);
12278 if (!config)
12279 goto out_config;
12280
12281 ret = intel_set_config_save_state(dev, config);
12282 if (ret)
12283 goto out_config;
12284
12285 save_set.crtc = set->crtc;
12286 save_set.mode = &set->crtc->mode;
12287 save_set.x = set->crtc->x;
12288 save_set.y = set->crtc->y;
f4510a27 12289 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12290
12291 /* Compute whether we need a full modeset, only an fb base update or no
12292 * change at all. In the future we might also check whether only the
12293 * mode changed, e.g. for LVDS where we only change the panel fitter in
12294 * such cases. */
12295 intel_set_config_compute_mode_changes(set, config);
12296
83a57153
ACO		 12297 state = drm_atomic_state_alloc(dev);
12298 if (!state) {
12299 ret = -ENOMEM;
12300 goto out_config;
12301 }
12302
12303 state->acquire_ctx = dev->mode_config.acquire_ctx;
12304
944b0c76 12305 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12306 if (ret)
12307 goto fail;
12308
50f52756 12309 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
83a57153 12310 set->fb, state,
50f52756
JB		 12311 &modeset_pipes,
12312 &prepare_pipes,
12313 &disable_pipes);
20664591 12314 if (IS_ERR(pipe_config)) {
6ac0483b 12315 ret = PTR_ERR(pipe_config);
50f52756 12316 goto fail;
20664591 12317 } else if (pipe_config) {
b9950a13 12318 if (pipe_config->has_audio !=
6e3c9717 12319 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12320 config->mode_changed = true;
12321
af15d2ce
JB		 12322 /*
12323 * Note we have an issue here with infoframes: current code
12324 * only updates them on the full mode set path per hw
12325 * requirements. So here we should be checking for any
12326 * required changes and forcing a mode set.
12327 */
20664591 12328 }
50f52756 12329
1f9954d0
JB		 12330 intel_update_pipe_size(to_intel_crtc(set->crtc));
12331
5e2b584e 12332 if (config->mode_changed) {
50f52756
JB		 12333 ret = intel_set_mode_pipes(set->crtc, set->mode,
12334 set->x, set->y, set->fb, pipe_config,
12335 modeset_pipes, prepare_pipes,
12336 disable_pipes);
5e2b584e 12337 } else if (config->fb_changed) {
3b150f08 12338 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12339 struct drm_plane *primary = set->crtc->primary;
12340 int vdisplay, hdisplay;
3b150f08 12341
455a6808 12342 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12343 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12344 0, 0, hdisplay, vdisplay,
12345 set->x << 16, set->y << 16,
12346 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12347
12348 /*
12349 * We need to make sure the primary plane is re-enabled if it
12350 * has previously been turned off.
12351 */
12352 if (!intel_crtc->primary_enabled && ret == 0) {
12353 WARN_ON(!intel_crtc->active);
fdd508a6 12354 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12355 }
12356
7ca51a3a
JB		 12357 /*
12358 * In the fastboot case this may be our only check of the
12359 * state after boot. It would be better to only do it on
12360 * the first update, but we don't have a nice way of doing that
12361 * (and really, set_config isn't used much for high freq page
12362 * flipping, so increasing its cost here shouldn't be a big
12363 * deal).
12364 */
d330a953 12365 if (i915.fastboot && ret == 0)
7ca51a3a 12366 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12367 }
12368
2d05eae1 12369 if (ret) {
bf67dfeb
DV		 12370 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12371 set->crtc->base.id, ret);
50f56119 12372fail:
2d05eae1 12373 intel_set_config_restore_state(dev, config);
50f56119 12374
83a57153
ACO		 12375 drm_atomic_state_clear(state);
12376
7d00a1f5
VS		 12377 /*
12378 * HACK: if the pipe was on, but we didn't have a framebuffer,
12379 * force the pipe off to avoid oopsing in the modeset code
12380 * due to fb==NULL. This should only happen during boot since
12381 * we don't yet reconstruct the FB from the hardware state.
12382 */
12383 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12384 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12385
2d05eae1
CW		 12386 /* Try to restore the config */
12387 if (config->mode_changed &&
12388 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12389 save_set.x, save_set.y, save_set.fb,
12390 state))
2d05eae1
CW		 12391 DRM_ERROR("failed to restore config after modeset failure\n");
12392 }
50f56119 12393
d9e55608 12394out_config:
83a57153
ACO		 12395 if (state)
12396 drm_atomic_state_free(state);
12397
d9e55608 12398 intel_set_config_free(config);
50f56119
DV		 12399 return ret;
12400}
f6e5b160
CW		 12401
12402static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12403 .gamma_set = intel_crtc_gamma_set,
50f56119 12404 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12405 .destroy = intel_crtc_destroy,
12406 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12407 .atomic_duplicate_state = intel_crtc_duplicate_state,
12408 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12409};
12410
5358901f
DV		 12411static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12412 struct intel_shared_dpll *pll,
12413 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12414{
5358901f 12415 uint32_t val;
ee7b9f93 12416
f458ebbc 12417 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12418 return false;
12419
5358901f 12420 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12421 hw_state->dpll = val;
12422 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12423 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12424
12425 return val & DPLL_VCO_ENABLE;
12426}
12427
15bdd4cf
DV		 12428static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12429 struct intel_shared_dpll *pll)
12430{
3e369b76
ACO		 12431 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12432 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12433}
12434
e7b903d2
DV		 12435static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12436 struct intel_shared_dpll *pll)
12437{
e7b903d2 12438 /* PCH refclock must be enabled first */
89eff4be 12439 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12440
3e369b76 12441 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12442
12443 /* Wait for the clocks to stabilize. */
12444 POSTING_READ(PCH_DPLL(pll->id));
12445 udelay(150);
12446
12447 /* The pixel multiplier can only be updated once the
12448 * DPLL is enabled and the clocks are stable.
12449 *
12450 * So write it again.
12451 */
3e369b76 12452 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12453 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12454 udelay(200);
12455}
12456
12457static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12458 struct intel_shared_dpll *pll)
12459{
12460 struct drm_device *dev = dev_priv->dev;
12461 struct intel_crtc *crtc;
e7b903d2
DV		 12462
12463 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12464 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12465 if (intel_crtc_to_shared_dpll(crtc) == pll)
12466 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12467 }
12468
15bdd4cf
DV		 12469 I915_WRITE(PCH_DPLL(pll->id), 0);
12470 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12471 udelay(200);
12472}
12473
46edb027
DV		 12474static char *ibx_pch_dpll_names[] = {
12475 "PCH DPLL A",
12476 "PCH DPLL B",
12477};
12478
7c74ade1 12479static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12480{
e7b903d2 12481 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12482 int i;
12483
7c74ade1 12484 dev_priv->num_shared_dpll = 2;
ee7b9f93 12485
e72f9fbf 12486 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12487 dev_priv->shared_dplls[i].id = i;
12488 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12489 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12490 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12491 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12492 dev_priv->shared_dplls[i].get_hw_state =
12493 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12494 }
12495}
12496
7c74ade1
DV		 12497static void intel_shared_dpll_init(struct drm_device *dev)
12498{
e7b903d2 12499 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12500
9cd86933
DV		 12501 if (HAS_DDI(dev))
12502 intel_ddi_pll_init(dev);
12503 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12504 ibx_pch_dpll_init(dev);
12505 else
12506 dev_priv->num_shared_dpll = 0;
12507
12508 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12509}
12510
1fc0a8f7
TU		 12511/**
12512 * intel_wm_need_update - Check whether watermarks need updating
12513 * @plane: drm plane
12514 * @state: new plane state
12515 *
12516 * Check current plane state versus the new one to determine whether
12517 * watermarks need to be recalculated.
12518 *
12519 * Returns true or false.
12520 */
12521bool intel_wm_need_update(struct drm_plane *plane,
12522 struct drm_plane_state *state)
12523{
12524 /* Update watermarks on tiling changes. */
12525 if (!plane->state->fb || !state->fb ||
12526 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12527 plane->state->rotation != state->rotation)
12528 return true;
12529
12530 return false;
12531}
12532
6beb8c23
MR		 12533/**
12534 * intel_prepare_plane_fb - Prepare fb for usage on plane
12535 * @plane: drm plane to prepare for
12536 * @fb: framebuffer to prepare for presentation
12537 *
12538 * Prepares a framebuffer for usage on a display plane. Generally this
12539 * involves pinning the underlying object and updating the frontbuffer tracking
12540 * bits. Some older platforms need special physical address handling for
12541 * cursor planes.
12542 *
12543 * Returns 0 on success, negative error code on failure.
12544 */
12545int
12546intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12547 struct drm_framebuffer *fb,
12548 const struct drm_plane_state *new_state)
465c120c
MR		 12549{
12550 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12551 struct intel_plane *intel_plane = to_intel_plane(plane);
12552 enum pipe pipe = intel_plane->pipe;
12553 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12554 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12555 unsigned frontbuffer_bits = 0;
12556 int ret = 0;
465c120c 12557
ea2c67bb 12558 if (!obj)
465c120c
MR		 12559 return 0;
12560
6beb8c23
MR		 12561 switch (plane->type) {
12562 case DRM_PLANE_TYPE_PRIMARY:
12563 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12564 break;
12565 case DRM_PLANE_TYPE_CURSOR:
12566 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12567 break;
12568 case DRM_PLANE_TYPE_OVERLAY:
12569 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12570 break;
12571 }
465c120c 12572
6beb8c23 12573 mutex_lock(&dev->struct_mutex);
465c120c 12574
6beb8c23
MR		 12575 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12576 INTEL_INFO(dev)->cursor_needs_physical) {
12577 int align = IS_I830(dev) ? 16 * 1024 : 256;
12578 ret = i915_gem_object_attach_phys(obj, align);
12579 if (ret)
12580 DRM_DEBUG_KMS("failed to attach phys object\n");
12581 } else {
82bc3b2d 12582 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12583 }
465c120c 12584
6beb8c23
MR		 12585 if (ret == 0)
12586 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12587
4c34574f 12588 mutex_unlock(&dev->struct_mutex);
465c120c 12589
6beb8c23
MR		 12590 return ret;
12591}
12592
38f3ce3a
MR		 12593/**
12594 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12595 * @plane: drm plane to clean up for
12596 * @fb: old framebuffer that was on plane
12597 *
12598 * Cleans up a framebuffer that has just been removed from a plane.
12599 */
12600void
12601intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12602 struct drm_framebuffer *fb,
12603 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12604{
12605 struct drm_device *dev = plane->dev;
12606 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12607
12608 if (WARN_ON(!obj))
12609 return;
12610
12611 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12612 !INTEL_INFO(dev)->cursor_needs_physical) {
12613 mutex_lock(&dev->struct_mutex);
82bc3b2d 12614 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12615 mutex_unlock(&dev->struct_mutex);
12616 }
465c120c
MR		 12617}
12618
12619static int
3c692a41
GP		 12620intel_check_primary_plane(struct drm_plane *plane,
12621 struct intel_plane_state *state)
12622{
32b7eeec
MR		 12623 struct drm_device *dev = plane->dev;
12624 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 12625 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12626 struct intel_crtc *intel_crtc;
2b875c22 12627 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 12628 struct drm_rect *dest = &state->dst;
12629 struct drm_rect *src = &state->src;
12630 const struct drm_rect *clip = &state->clip;
d8106366 12631 bool can_position = false;
465c120c
MR		 12632 int ret;
12633
ea2c67bb
MR		 12634 crtc = crtc ? crtc : plane->crtc;
12635 intel_crtc = to_intel_crtc(crtc);
12636
d8106366
SJ		 12637 if (INTEL_INFO(dev)->gen >= 9)
12638 can_position = true;
12639
c59cb179
MR		 12640 ret = drm_plane_helper_check_update(plane, crtc, fb,
12641 src, dest, clip,
12642 DRM_PLANE_HELPER_NO_SCALING,
12643 DRM_PLANE_HELPER_NO_SCALING,
d8106366
SJ		 12644 can_position, true,
12645 &state->visible);
c59cb179
MR		 12646 if (ret)
12647 return ret;
465c120c 12648
32b7eeec
MR		 12649 if (intel_crtc->active) {
12650 intel_crtc->atomic.wait_for_flips = true;
12651
12652 /*
12653 * FBC does not work on some platforms for rotated
12654 * planes, so disable it when rotation is not 0 and
12655 * update it when rotation is set back to 0.
12656 *
12657 * FIXME: This is redundant with the fbc update done in
12658 * the primary plane enable function except that that
12659 * one is done too late. We eventually need to unify
12660 * this.
12661 */
12662 if (intel_crtc->primary_enabled &&
12663 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 12664 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 12665 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 12666 intel_crtc->atomic.disable_fbc = true;
12667 }
12668
12669 if (state->visible) {
12670 /*
12671 * BDW signals flip done immediately if the plane
12672 * is disabled, even if the plane enable is already
12673 * armed to occur at the next vblank :(
12674 */
12675 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12676 intel_crtc->atomic.wait_vblank = true;
12677 }
12678
12679 intel_crtc->atomic.fb_bits |=
12680 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12681
12682 intel_crtc->atomic.update_fbc = true;
0fda6568 12683
1fc0a8f7 12684 if (intel_wm_need_update(plane, &state->base))
0fda6568 12685 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12686 }
12687
14af293f
GP		 12688 return 0;
12689}
12690
12691static void
12692intel_commit_primary_plane(struct drm_plane *plane,
12693 struct intel_plane_state *state)
12694{
2b875c22
MR		 12695 struct drm_crtc *crtc = state->base.crtc;
12696 struct drm_framebuffer *fb = state->base.fb;
12697 struct drm_device *dev = plane->dev;
14af293f 12698 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12699 struct intel_crtc *intel_crtc;
14af293f
GP		 12700 struct drm_rect *src = &state->src;
12701
ea2c67bb
MR		 12702 crtc = crtc ? crtc : plane->crtc;
12703 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12704
12705 plane->fb = fb;
9dc806fc
MR		 12706 crtc->x = src->x1 >> 16;
12707 crtc->y = src->y1 >> 16;
ccc759dc 12708
ccc759dc 12709 if (intel_crtc->active) {
ccc759dc 12710 if (state->visible) {
ccc759dc
GP		 12711 /* FIXME: kill this fastboot hack */
12712 intel_update_pipe_size(intel_crtc);
465c120c 12713
ccc759dc 12714 intel_crtc->primary_enabled = true;
465c120c 12715
ccc759dc
GP		 12716 dev_priv->display.update_primary_plane(crtc, plane->fb,
12717 crtc->x, crtc->y);
ccc759dc
GP		 12718 } else {
12719 /*
12720 * If clipping results in a non-visible primary plane,
12721 * we'll disable the primary plane. Note that this is
12722 * a bit different than what happens if userspace
12723 * explicitly disables the plane by passing fb=0
12724 * because plane->fb still gets set and pinned.
12725 */
12726 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12727 }
ccc759dc 12728 }
465c120c
MR		 12729}
12730
32b7eeec 12731static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12732{
32b7eeec 12733 struct drm_device *dev = crtc->dev;
140fd38d 12734 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12736 struct intel_plane *intel_plane;
12737 struct drm_plane *p;
12738 unsigned fb_bits = 0;
12739
12740 /* Track fb's for any planes being disabled */
12741 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12742 intel_plane = to_intel_plane(p);
12743
12744 if (intel_crtc->atomic.disabled_planes &
12745 (1 << drm_plane_index(p))) {
12746 switch (p->type) {
12747 case DRM_PLANE_TYPE_PRIMARY:
12748 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12749 break;
12750 case DRM_PLANE_TYPE_CURSOR:
12751 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12752 break;
12753 case DRM_PLANE_TYPE_OVERLAY:
12754 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12755 break;
12756 }
3c692a41 12757
ea2c67bb
MR		 12758 mutex_lock(&dev->struct_mutex);
12759 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12760 mutex_unlock(&dev->struct_mutex);
12761 }
12762 }
3c692a41 12763
32b7eeec
MR		 12764 if (intel_crtc->atomic.wait_for_flips)
12765 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 12766
32b7eeec
MR		 12767 if (intel_crtc->atomic.disable_fbc)
12768 intel_fbc_disable(dev);
3c692a41 12769
32b7eeec
MR		 12770 if (intel_crtc->atomic.pre_disable_primary)
12771 intel_pre_disable_primary(crtc);
3c692a41 12772
32b7eeec
MR		 12773 if (intel_crtc->atomic.update_wm)
12774 intel_update_watermarks(crtc);
3c692a41 12775
32b7eeec 12776 intel_runtime_pm_get(dev_priv);
3c692a41 12777
c34c9ee4
MR		 12778 /* Perform vblank evasion around commit operation */
12779 if (intel_crtc->active)
12780 intel_crtc->atomic.evade =
12781 intel_pipe_update_start(intel_crtc,
12782 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 12783}
12784
12785static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12786{
12787 struct drm_device *dev = crtc->dev;
12788 struct drm_i915_private *dev_priv = dev->dev_private;
12789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12790 struct drm_plane *p;
12791
c34c9ee4
MR		 12792 if (intel_crtc->atomic.evade)
12793 intel_pipe_update_end(intel_crtc,
12794 intel_crtc->atomic.start_vbl_count);
3c692a41 12795
140fd38d 12796 intel_runtime_pm_put(dev_priv);
3c692a41 12797
32b7eeec
MR		 12798 if (intel_crtc->atomic.wait_vblank)
12799 intel_wait_for_vblank(dev, intel_crtc->pipe);
12800
12801 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12802
12803 if (intel_crtc->atomic.update_fbc) {
ccc759dc 12804 mutex_lock(&dev->struct_mutex);
7ff0ebcc 12805 intel_fbc_update(dev);
ccc759dc 12806 mutex_unlock(&dev->struct_mutex);
38f3ce3a 12807 }
3c692a41 12808
32b7eeec
MR		 12809 if (intel_crtc->atomic.post_enable_primary)
12810 intel_post_enable_primary(crtc);
3c692a41 12811
32b7eeec
MR		 12812 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12813 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12814 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12815 false, false);
12816
12817 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 12818}
12819
cf4c7c12 12820/**
4a3b8769
MR		 12821 * intel_plane_destroy - destroy a plane
12822 * @plane: plane to destroy
cf4c7c12 12823 *
4a3b8769
MR		 12824 * Common destruction function for all types of planes (primary, cursor,
12825 * sprite).
cf4c7c12 12826 */
4a3b8769 12827void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 12828{
12829 struct intel_plane *intel_plane = to_intel_plane(plane);
12830 drm_plane_cleanup(plane);
12831 kfree(intel_plane);
12832}
12833
65a3fea0 12834const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 12835 .update_plane = drm_atomic_helper_update_plane,
12836 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 12837 .destroy = intel_plane_destroy,
c196e1d6 12838 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 12839 .atomic_get_property = intel_plane_atomic_get_property,
12840 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 12841 .atomic_duplicate_state = intel_plane_duplicate_state,
12842 .atomic_destroy_state = intel_plane_destroy_state,
12843
465c120c
MR		 12844};
12845
12846static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12847 int pipe)
12848{
12849 struct intel_plane *primary;
8e7d688b 12850 struct intel_plane_state *state;
465c120c
MR		 12851 const uint32_t *intel_primary_formats;
12852 int num_formats;
12853
12854 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12855 if (primary == NULL)
12856 return NULL;
12857
8e7d688b
MR		 12858 state = intel_create_plane_state(&primary->base);
12859 if (!state) {
ea2c67bb
MR		 12860 kfree(primary);
12861 return NULL;
12862 }
8e7d688b 12863 primary->base.state = &state->base;
ea2c67bb 12864
465c120c
MR		 12865 primary->can_scale = false;
12866 primary->max_downscale = 1;
549e2bfb 12867 state->scaler_id = -1;
465c120c
MR		 12868 primary->pipe = pipe;
12869 primary->plane = pipe;
c59cb179
MR		 12870 primary->check_plane = intel_check_primary_plane;
12871 primary->commit_plane = intel_commit_primary_plane;
08e221fb 12872 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 12873 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12874 primary->plane = !pipe;
12875
12876 if (INTEL_INFO(dev)->gen <= 3) {
12877 intel_primary_formats = intel_primary_formats_gen2;
12878 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12879 } else {
12880 intel_primary_formats = intel_primary_formats_gen4;
12881 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12882 }
12883
12884 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 12885 &intel_plane_funcs,
465c120c
MR		 12886 intel_primary_formats, num_formats,
12887 DRM_PLANE_TYPE_PRIMARY);
48404c1e 12888
3b7a5119
SJ		 12889 if (INTEL_INFO(dev)->gen >= 4)
12890 intel_create_rotation_property(dev, primary);
48404c1e 12891
ea2c67bb
MR		 12892 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12893
465c120c
MR		 12894 return &primary->base;
12895}
12896
3b7a5119
SJ		 12897void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
12898{
12899 if (!dev->mode_config.rotation_property) {
12900 unsigned long flags = BIT(DRM_ROTATE_0) |
12901 BIT(DRM_ROTATE_180);
12902
12903 if (INTEL_INFO(dev)->gen >= 9)
12904 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
12905
12906 dev->mode_config.rotation_property =
12907 drm_mode_create_rotation_property(dev, flags);
12908 }
12909 if (dev->mode_config.rotation_property)
12910 drm_object_attach_property(&plane->base.base,
12911 dev->mode_config.rotation_property,
12912 plane->base.state->rotation);
12913}
12914
3d7d6510 12915static int
852e787c
GP		 12916intel_check_cursor_plane(struct drm_plane *plane,
12917 struct intel_plane_state *state)
3d7d6510 12918{
2b875c22 12919 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12920 struct drm_device *dev = plane->dev;
2b875c22 12921 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 12922 struct drm_rect *dest = &state->dst;
12923 struct drm_rect *src = &state->src;
12924 const struct drm_rect *clip = &state->clip;
757f9a3e 12925 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 12926 struct intel_crtc *intel_crtc;
757f9a3e
GP		 12927 unsigned stride;
12928 int ret;
3d7d6510 12929
ea2c67bb
MR		 12930 crtc = crtc ? crtc : plane->crtc;
12931 intel_crtc = to_intel_crtc(crtc);
12932
757f9a3e 12933 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 12934 src, dest, clip,
3d7d6510
MR		 12935 DRM_PLANE_HELPER_NO_SCALING,
12936 DRM_PLANE_HELPER_NO_SCALING,
852e787c 12937 true, true, &state->visible);
757f9a3e
GP		 12938 if (ret)
12939 return ret;
12940
12941
12942 /* if we want to turn off the cursor ignore width and height */
12943 if (!obj)
32b7eeec 12944 goto finish;
757f9a3e 12945
757f9a3e 12946 /* Check for which cursor types we support */
ea2c67bb
MR		 12947 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12948 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12949 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 12950 return -EINVAL;
12951 }
12952
ea2c67bb
MR		 12953 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12954 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 12955 DRM_DEBUG_KMS("buffer is too small\n");
12956 return -ENOMEM;
12957 }
12958
3a656b54 12959 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 12960 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12961 ret = -EINVAL;
12962 }
757f9a3e 12963
32b7eeec
MR		 12964finish:
12965 if (intel_crtc->active) {
3749f463 12966 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 12967 intel_crtc->atomic.update_wm = true;
12968
12969 intel_crtc->atomic.fb_bits |=
12970 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12971 }
12972
757f9a3e 12973 return ret;
852e787c 12974}
3d7d6510 12975
f4a2cf29 12976static void
852e787c
GP		 12977intel_commit_cursor_plane(struct drm_plane *plane,
12978 struct intel_plane_state *state)
12979{
2b875c22 12980 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 12981 struct drm_device *dev = plane->dev;
12982 struct intel_crtc *intel_crtc;
2b875c22 12983 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 12984 uint32_t addr;
852e787c 12985
ea2c67bb
MR		 12986 crtc = crtc ? crtc : plane->crtc;
12987 intel_crtc = to_intel_crtc(crtc);
12988
2b875c22 12989 plane->fb = state->base.fb;
ea2c67bb
MR		 12990 crtc->cursor_x = state->base.crtc_x;
12991 crtc->cursor_y = state->base.crtc_y;
12992
a912f12f
GP		 12993 if (intel_crtc->cursor_bo == obj)
12994 goto update;
4ed91096 12995
f4a2cf29 12996 if (!obj)
a912f12f 12997 addr = 0;
f4a2cf29 12998 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 12999 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13000 else
a912f12f 13001 addr = obj->phys_handle->busaddr;
852e787c 13002
a912f12f
GP		 13003 intel_crtc->cursor_addr = addr;
13004 intel_crtc->cursor_bo = obj;
13005update:
852e787c 13006
32b7eeec 13007 if (intel_crtc->active)
a912f12f 13008 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13009}
13010
3d7d6510
MR		 13011static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13012 int pipe)
13013{
13014 struct intel_plane *cursor;
8e7d688b 13015 struct intel_plane_state *state;
3d7d6510
MR		 13016
13017 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13018 if (cursor == NULL)
13019 return NULL;
13020
8e7d688b
MR		 13021 state = intel_create_plane_state(&cursor->base);
13022 if (!state) {
ea2c67bb
MR		 13023 kfree(cursor);
13024 return NULL;
13025 }
8e7d688b 13026 cursor->base.state = &state->base;
ea2c67bb 13027
3d7d6510
MR		 13028 cursor->can_scale = false;
13029 cursor->max_downscale = 1;
13030 cursor->pipe = pipe;
13031 cursor->plane = pipe;
549e2bfb 13032 state->scaler_id = -1;
c59cb179
MR		 13033 cursor->check_plane = intel_check_cursor_plane;
13034 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 13035
13036 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13037 &intel_plane_funcs,
3d7d6510
MR		 13038 intel_cursor_formats,
13039 ARRAY_SIZE(intel_cursor_formats),
13040 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13041
13042 if (INTEL_INFO(dev)->gen >= 4) {
13043 if (!dev->mode_config.rotation_property)
13044 dev->mode_config.rotation_property =
13045 drm_mode_create_rotation_property(dev,
13046 BIT(DRM_ROTATE_0) |
13047 BIT(DRM_ROTATE_180));
13048 if (dev->mode_config.rotation_property)
13049 drm_object_attach_property(&cursor->base.base,
13050 dev->mode_config.rotation_property,
8e7d688b 13051 state->base.rotation);
4398ad45
VS		 13052 }
13053
ea2c67bb
MR		 13054 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13055
3d7d6510
MR		 13056 return &cursor->base;
13057}
13058
549e2bfb
CK		 13059static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13060 struct intel_crtc_state *crtc_state)
13061{
13062 int i;
13063 struct intel_scaler *intel_scaler;
13064 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13065
13066 for (i = 0; i < intel_crtc->num_scalers; i++) {
13067 intel_scaler = &scaler_state->scalers[i];
13068 intel_scaler->in_use = 0;
13069 intel_scaler->id = i;
13070
13071 intel_scaler->mode = PS_SCALER_MODE_DYN;
13072 }
13073
13074 scaler_state->scaler_id = -1;
13075}
13076
b358d0a6 13077static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13078{
fbee40df 13079 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13080 struct intel_crtc *intel_crtc;
f5de6e07 13081 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13082 struct drm_plane *primary = NULL;
13083 struct drm_plane *cursor = NULL;
465c120c 13084 int i, ret;
79e53945 13085
955382f3 13086 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13087 if (intel_crtc == NULL)
13088 return;
13089
f5de6e07
ACO		 13090 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13091 if (!crtc_state)
13092 goto fail;
13093 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13094 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13095
549e2bfb
CK		 13096 /* initialize shared scalers */
13097 if (INTEL_INFO(dev)->gen >= 9) {
13098 if (pipe == PIPE_C)
13099 intel_crtc->num_scalers = 1;
13100 else
13101 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13102
13103 skl_init_scalers(dev, intel_crtc, crtc_state);
13104 }
13105
465c120c 13106 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13107 if (!primary)
13108 goto fail;
13109
13110 cursor = intel_cursor_plane_create(dev, pipe);
13111 if (!cursor)
13112 goto fail;
13113
465c120c 13114 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13115 cursor, &intel_crtc_funcs);
13116 if (ret)
13117 goto fail;
79e53945
JB		 13118
13119 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13120 for (i = 0; i < 256; i++) {
13121 intel_crtc->lut_r[i] = i;
13122 intel_crtc->lut_g[i] = i;
13123 intel_crtc->lut_b[i] = i;
13124 }
13125
1f1c2e24
VS		 13126 /*
13127 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13128 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13129 */
80824003
JB		 13130 intel_crtc->pipe = pipe;
13131 intel_crtc->plane = pipe;
3a77c4c4 13132 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13133 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13134 intel_crtc->plane = !pipe;
80824003
JB		 13135 }
13136
4b0e333e
CW		 13137 intel_crtc->cursor_base = ~0;
13138 intel_crtc->cursor_cntl = ~0;
dc41c154 13139 intel_crtc->cursor_size = ~0;
8d7849db 13140
22fd0fab
JB		 13141 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13142 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13143 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13144 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13145
9362c7c5
ACO		 13146 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13147
79e53945 13148 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13149
13150 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13151 return;
13152
13153fail:
13154 if (primary)
13155 drm_plane_cleanup(primary);
13156 if (cursor)
13157 drm_plane_cleanup(cursor);
f5de6e07 13158 kfree(crtc_state);
3d7d6510 13159 kfree(intel_crtc);
79e53945
JB		 13160}
13161
752aa88a
JB		 13162enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13163{
13164 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13165 struct drm_device *dev = connector->base.dev;
752aa88a 13166
51fd371b 13167 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13168
d3babd3f 13169 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13170 return INVALID_PIPE;
13171
13172 return to_intel_crtc(encoder->crtc)->pipe;
13173}
13174
08d7b3d1 13175int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13176 struct drm_file *file)
08d7b3d1 13177{
08d7b3d1 13178 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13179 struct drm_crtc *drmmode_crtc;
c05422d5 13180 struct intel_crtc *crtc;
08d7b3d1 13181
7707e653 13182 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13183
7707e653 13184 if (!drmmode_crtc) {
08d7b3d1 13185 DRM_ERROR("no such CRTC id\n");
3f2c2057 13186 return -ENOENT;
08d7b3d1
CW		 13187 }
13188
7707e653 13189 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13190 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13191
c05422d5 13192 return 0;
08d7b3d1
CW		 13193}
13194
66a9278e 13195static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13196{
66a9278e
DV		 13197 struct drm_device *dev = encoder->base.dev;
13198 struct intel_encoder *source_encoder;
79e53945 13199 int index_mask = 0;
79e53945
JB		 13200 int entry = 0;
13201
b2784e15 13202 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13203 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13204 index_mask |= (1 << entry);
13205
79e53945
JB		 13206 entry++;
13207 }
4ef69c7a 13208
79e53945
JB		 13209 return index_mask;
13210}
13211
4d302442
CW		 13212static bool has_edp_a(struct drm_device *dev)
13213{
13214 struct drm_i915_private *dev_priv = dev->dev_private;
13215
13216 if (!IS_MOBILE(dev))
13217 return false;
13218
13219 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13220 return false;
13221
e3589908 13222 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13223 return false;
13224
13225 return true;
13226}
13227
84b4e042
JB		 13228static bool intel_crt_present(struct drm_device *dev)
13229{
13230 struct drm_i915_private *dev_priv = dev->dev_private;
13231
884497ed
DL		 13232 if (INTEL_INFO(dev)->gen >= 9)
13233 return false;
13234
cf404ce4 13235 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13236 return false;
13237
13238 if (IS_CHERRYVIEW(dev))
13239 return false;
13240
13241 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13242 return false;
13243
13244 return true;
13245}
13246
79e53945
JB		 13247static void intel_setup_outputs(struct drm_device *dev)
13248{
725e30ad 13249 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13250 struct intel_encoder *encoder;
cb0953d7 13251 bool dpd_is_edp = false;
79e53945 13252
c9093354 13253 intel_lvds_init(dev);
79e53945 13254
84b4e042 13255 if (intel_crt_present(dev))
79935fca 13256 intel_crt_init(dev);
cb0953d7 13257
affa9354 13258 if (HAS_DDI(dev)) {
0e72a5b5
ED		 13259 int found;
13260
de31facd
JB		 13261 /*
13262 * Haswell uses DDI functions to detect digital outputs.
13263 * On SKL pre-D0 the strap isn't connected, so we assume
13264 * it's there.
13265 */
0e72a5b5 13266 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13267 /* WaIgnoreDDIAStrap: skl */
13268 if (found ||
13269 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13270 intel_ddi_init(dev, PORT_A);
13271
13272 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13273 * register */
13274 found = I915_READ(SFUSE_STRAP);
13275
13276 if (found & SFUSE_STRAP_DDIB_DETECTED)
13277 intel_ddi_init(dev, PORT_B);
13278 if (found & SFUSE_STRAP_DDIC_DETECTED)
13279 intel_ddi_init(dev, PORT_C);
13280 if (found & SFUSE_STRAP_DDID_DETECTED)
13281 intel_ddi_init(dev, PORT_D);
13282 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13283 int found;
5d8a7752 13284 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13285
13286 if (has_edp_a(dev))
13287 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13288
dc0fa718 13289 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13290 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13291 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13292 if (!found)
e2debe91 13293 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13294 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13295 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13296 }
13297
dc0fa718 13298 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13299 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13300
dc0fa718 13301 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13302 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13303
5eb08b69 13304 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13305 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13306
270b3042 13307 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13308 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13309 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13310 /*
13311 * The DP_DETECTED bit is the latched state of the DDC
13312 * SDA pin at boot. However since eDP doesn't require DDC
13313 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13314 * eDP ports may have been muxed to an alternate function.
13315 * Thus we can't rely on the DP_DETECTED bit alone to detect
13316 * eDP ports. Consult the VBT as well as DP_DETECTED to
13317 * detect eDP ports.
13318 */
d2182a66
VS		 13319 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13320 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13321 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13322 PORT_B);
e17ac6db
VS		 13323 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13324 intel_dp_is_edp(dev, PORT_B))
13325 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13326
d2182a66
VS		 13327 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13328 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13329 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13330 PORT_C);
e17ac6db
VS		 13331 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13332 intel_dp_is_edp(dev, PORT_C))
13333 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13334
9418c1f1 13335 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13336 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13337 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13338 PORT_D);
e17ac6db
VS		 13339 /* eDP not supported on port D, so don't check VBT */
13340 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13341 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13342 }
13343
3cfca973 13344 intel_dsi_init(dev);
103a196f 13345 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13346 bool found = false;
7d57382e 13347
e2debe91 13348 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13349 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13350 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13351 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13352 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13353 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13354 }
27185ae1 13355
e7281eab 13356 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13357 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13358 }
13520b05
KH		 13359
13360 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13361
e2debe91 13362 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13363 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13364 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13365 }
27185ae1 13366
e2debe91 13367 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13368
b01f2c3a
JB		 13369 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13370 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13371 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13372 }
e7281eab 13373 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13374 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13375 }
27185ae1 13376
b01f2c3a 13377 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13378 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13379 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13380 } else if (IS_GEN2(dev))
79e53945
JB		 13381 intel_dvo_init(dev);
13382
103a196f 13383 if (SUPPORTS_TV(dev))
79e53945
JB		 13384 intel_tv_init(dev);
13385
0bc12bcb 13386 intel_psr_init(dev);
7c8f8a70 13387
b2784e15 13388 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13389 encoder->base.possible_crtcs = encoder->crtc_mask;
13390 encoder->base.possible_clones =
66a9278e 13391 intel_encoder_clones(encoder);
79e53945 13392 }
47356eb6 13393
dde86e2d 13394 intel_init_pch_refclk(dev);
270b3042
DV		 13395
13396 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13397}
13398
13399static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13400{
60a5ca01 13401 struct drm_device *dev = fb->dev;
79e53945 13402 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13403
ef2d633e 13404 drm_framebuffer_cleanup(fb);
60a5ca01 13405 mutex_lock(&dev->struct_mutex);
ef2d633e 13406 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13407 drm_gem_object_unreference(&intel_fb->obj->base);
13408 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13409 kfree(intel_fb);
13410}
13411
13412static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13413 struct drm_file *file,
79e53945
JB		 13414 unsigned int *handle)
13415{
13416 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13417 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13418
05394f39 13419 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13420}
13421
13422static const struct drm_framebuffer_funcs intel_fb_funcs = {
13423 .destroy = intel_user_framebuffer_destroy,
13424 .create_handle = intel_user_framebuffer_create_handle,
13425};
13426
b321803d
DL		 13427static
13428u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13429 uint32_t pixel_format)
13430{
13431 u32 gen = INTEL_INFO(dev)->gen;
13432
13433 if (gen >= 9) {
13434 /* "The stride in bytes must not exceed the of the size of 8K
13435 * pixels and 32K bytes."
13436 */
13437 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13438 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13439 return 32*1024;
13440 } else if (gen >= 4) {
13441 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13442 return 16*1024;
13443 else
13444 return 32*1024;
13445 } else if (gen >= 3) {
13446 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13447 return 8*1024;
13448 else
13449 return 16*1024;
13450 } else {
13451 /* XXX DSPC is limited to 4k tiled */
13452 return 8*1024;
13453 }
13454}
13455
b5ea642a
DV		 13456static int intel_framebuffer_init(struct drm_device *dev,
13457 struct intel_framebuffer *intel_fb,
13458 struct drm_mode_fb_cmd2 *mode_cmd,
13459 struct drm_i915_gem_object *obj)
79e53945 13460{
6761dd31 13461 unsigned int aligned_height;
79e53945 13462 int ret;
b321803d 13463 u32 pitch_limit, stride_alignment;
79e53945 13464
dd4916c5
DV		 13465 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13466
2a80eada
DV		 13467 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13468 /* Enforce that fb modifier and tiling mode match, but only for
13469 * X-tiled. This is needed for FBC. */
13470 if (!!(obj->tiling_mode == I915_TILING_X) !=
13471 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13472 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13473 return -EINVAL;
13474 }
13475 } else {
13476 if (obj->tiling_mode == I915_TILING_X)
13477 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13478 else if (obj->tiling_mode == I915_TILING_Y) {
13479 DRM_DEBUG("No Y tiling for legacy addfb\n");
13480 return -EINVAL;
13481 }
13482 }
13483
9a8f0a12
TU		 13484 /* Passed in modifier sanity checking. */
13485 switch (mode_cmd->modifier[0]) {
13486 case I915_FORMAT_MOD_Y_TILED:
13487 case I915_FORMAT_MOD_Yf_TILED:
13488 if (INTEL_INFO(dev)->gen < 9) {
13489 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13490 mode_cmd->modifier[0]);
13491 return -EINVAL;
13492 }
13493 case DRM_FORMAT_MOD_NONE:
13494 case I915_FORMAT_MOD_X_TILED:
13495 break;
13496 default:
c0f40428
JB		 13497 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13498 mode_cmd->modifier[0]);
57cd6508 13499 return -EINVAL;
c16ed4be 13500 }
57cd6508 13501
b321803d
DL		 13502 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13503 mode_cmd->pixel_format);
13504 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13505 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13506 mode_cmd->pitches[0], stride_alignment);
57cd6508 13507 return -EINVAL;
c16ed4be 13508 }
57cd6508 13509
b321803d
DL		 13510 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13511 mode_cmd->pixel_format);
a35cdaa0 13512 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13513 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13514 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13515 "tiled" : "linear",
a35cdaa0 13516 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13517 return -EINVAL;
c16ed4be 13518 }
5d7bd705 13519
2a80eada 13520 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13521 mode_cmd->pitches[0] != obj->stride) {
13522 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13523 mode_cmd->pitches[0], obj->stride);
5d7bd705 13524 return -EINVAL;
c16ed4be 13525 }
5d7bd705 13526
57779d06 13527 /* Reject formats not supported by any plane early. */
308e5bcb 13528 switch (mode_cmd->pixel_format) {
57779d06 13529 case DRM_FORMAT_C8:
04b3924d
VS		 13530 case DRM_FORMAT_RGB565:
13531 case DRM_FORMAT_XRGB8888:
13532 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13533 break;
13534 case DRM_FORMAT_XRGB1555:
13535 case DRM_FORMAT_ARGB1555:
c16ed4be 13536 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13537 DRM_DEBUG("unsupported pixel format: %s\n",
13538 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13539 return -EINVAL;
c16ed4be 13540 }
57779d06
VS		 13541 break;
13542 case DRM_FORMAT_XBGR8888:
13543 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13544 case DRM_FORMAT_XRGB2101010:
13545 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13546 case DRM_FORMAT_XBGR2101010:
13547 case DRM_FORMAT_ABGR2101010:
c16ed4be 13548 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13549 DRM_DEBUG("unsupported pixel format: %s\n",
13550 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13551 return -EINVAL;
c16ed4be 13552 }
b5626747 13553 break;
04b3924d
VS		 13554 case DRM_FORMAT_YUYV:
13555 case DRM_FORMAT_UYVY:
13556 case DRM_FORMAT_YVYU:
13557 case DRM_FORMAT_VYUY:
c16ed4be 13558 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13559 DRM_DEBUG("unsupported pixel format: %s\n",
13560 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13561 return -EINVAL;
c16ed4be 13562 }
57cd6508
CW		 13563 break;
13564 default:
4ee62c76
VS		 13565 DRM_DEBUG("unsupported pixel format: %s\n",
13566 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13567 return -EINVAL;
13568 }
13569
90f9a336
VS		 13570 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13571 if (mode_cmd->offsets[0] != 0)
13572 return -EINVAL;
13573
ec2c981e 13574 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 13575 mode_cmd->pixel_format,
13576 mode_cmd->modifier[0]);
53155c0a
DV		 13577 /* FIXME drm helper for size checks (especially planar formats)? */
13578 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13579 return -EINVAL;
13580
c7d73f6a
DV		 13581 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13582 intel_fb->obj = obj;
80075d49 13583 intel_fb->obj->framebuffer_references++;
c7d73f6a 13584
79e53945
JB		 13585 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13586 if (ret) {
13587 DRM_ERROR("framebuffer init failed %d\n", ret);
13588 return ret;
13589 }
13590
79e53945
JB		 13591 return 0;
13592}
13593
79e53945
JB		 13594static struct drm_framebuffer *
13595intel_user_framebuffer_create(struct drm_device *dev,
13596 struct drm_file *filp,
308e5bcb 13597 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 13598{
05394f39 13599 struct drm_i915_gem_object *obj;
79e53945 13600
308e5bcb
JB		 13601 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13602 mode_cmd->handles[0]));
c8725226 13603 if (&obj->base == NULL)
cce13ff7 13604 return ERR_PTR(-ENOENT);
79e53945 13605
d2dff872 13606 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 13607}
13608
4520f53a 13609#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 13610static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 13611{
13612}
13613#endif
13614
79e53945 13615static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 13616 .fb_create = intel_user_framebuffer_create,
0632fef6 13617 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 13618 .atomic_check = intel_atomic_check,
13619 .atomic_commit = intel_atomic_commit,
79e53945
JB		 13620};
13621
e70236a8
JB		 13622/* Set up chip specific display functions */
13623static void intel_init_display(struct drm_device *dev)
13624{
13625 struct drm_i915_private *dev_priv = dev->dev_private;
13626
ee9300bb
DV		 13627 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13628 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 13629 else if (IS_CHERRYVIEW(dev))
13630 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 13631 else if (IS_VALLEYVIEW(dev))
13632 dev_priv->display.find_dpll = vlv_find_best_dpll;
13633 else if (IS_PINEVIEW(dev))
13634 dev_priv->display.find_dpll = pnv_find_best_dpll;
13635 else
13636 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13637
bc8d7dff
DL		 13638 if (INTEL_INFO(dev)->gen >= 9) {
13639 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13640 dev_priv->display.get_initial_plane_config =
13641 skylake_get_initial_plane_config;
bc8d7dff
DL		 13642 dev_priv->display.crtc_compute_clock =
13643 haswell_crtc_compute_clock;
13644 dev_priv->display.crtc_enable = haswell_crtc_enable;
13645 dev_priv->display.crtc_disable = haswell_crtc_disable;
13646 dev_priv->display.off = ironlake_crtc_off;
13647 dev_priv->display.update_primary_plane =
13648 skylake_update_primary_plane;
13649 } else if (HAS_DDI(dev)) {
0e8ffe1b 13650 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13651 dev_priv->display.get_initial_plane_config =
13652 ironlake_get_initial_plane_config;
797d0259
ACO		 13653 dev_priv->display.crtc_compute_clock =
13654 haswell_crtc_compute_clock;
4f771f10
PZ		 13655 dev_priv->display.crtc_enable = haswell_crtc_enable;
13656 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 13657 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 13658 dev_priv->display.update_primary_plane =
13659 ironlake_update_primary_plane;
09b4ddf9 13660 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 13661 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 13662 dev_priv->display.get_initial_plane_config =
13663 ironlake_get_initial_plane_config;
3fb37703
ACO		 13664 dev_priv->display.crtc_compute_clock =
13665 ironlake_crtc_compute_clock;
76e5a89c
DV		 13666 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13667 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 13668 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 13669 dev_priv->display.update_primary_plane =
13670 ironlake_update_primary_plane;
89b667f8
JB		 13671 } else if (IS_VALLEYVIEW(dev)) {
13672 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13673 dev_priv->display.get_initial_plane_config =
13674 i9xx_get_initial_plane_config;
d6dfee7a 13675 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13676 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13677 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13678 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13679 dev_priv->display.update_primary_plane =
13680 i9xx_update_primary_plane;
f564048e 13681 } else {
0e8ffe1b 13682 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13683 dev_priv->display.get_initial_plane_config =
13684 i9xx_get_initial_plane_config;
d6dfee7a 13685 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13686 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13687 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13688 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13689 dev_priv->display.update_primary_plane =
13690 i9xx_update_primary_plane;
f564048e 13691 }
e70236a8 13692
e70236a8 13693 /* Returns the core display clock speed */
1652d19e
VS		 13694 if (IS_SKYLAKE(dev))
13695 dev_priv->display.get_display_clock_speed =
13696 skylake_get_display_clock_speed;
13697 else if (IS_BROADWELL(dev))
13698 dev_priv->display.get_display_clock_speed =
13699 broadwell_get_display_clock_speed;
13700 else if (IS_HASWELL(dev))
13701 dev_priv->display.get_display_clock_speed =
13702 haswell_get_display_clock_speed;
13703 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 13704 dev_priv->display.get_display_clock_speed =
13705 valleyview_get_display_clock_speed;
b37a6434
VS		 13706 else if (IS_GEN5(dev))
13707 dev_priv->display.get_display_clock_speed =
13708 ilk_get_display_clock_speed;
a7c66cd8
VS		 13709 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
13710 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13711 dev_priv->display.get_display_clock_speed =
13712 i945_get_display_clock_speed;
13713 else if (IS_I915G(dev))
13714 dev_priv->display.get_display_clock_speed =
13715 i915_get_display_clock_speed;
257a7ffc 13716 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13717 dev_priv->display.get_display_clock_speed =
13718 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13719 else if (IS_PINEVIEW(dev))
13720 dev_priv->display.get_display_clock_speed =
13721 pnv_get_display_clock_speed;
e70236a8
JB		 13722 else if (IS_I915GM(dev))
13723 dev_priv->display.get_display_clock_speed =
13724 i915gm_get_display_clock_speed;
13725 else if (IS_I865G(dev))
13726 dev_priv->display.get_display_clock_speed =
13727 i865_get_display_clock_speed;
f0f8a9ce 13728 else if (IS_I85X(dev))
e70236a8
JB		 13729 dev_priv->display.get_display_clock_speed =
13730 i855_get_display_clock_speed;
13731 else /* 852, 830 */
13732 dev_priv->display.get_display_clock_speed =
13733 i830_get_display_clock_speed;
13734
7c10a2b5 13735 if (IS_GEN5(dev)) {
3bb11b53 13736 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13737 } else if (IS_GEN6(dev)) {
13738 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 13739 } else if (IS_IVYBRIDGE(dev)) {
13740 /* FIXME: detect B0+ stepping and use auto training */
13741 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 13742 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 13743 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 13744 } else if (IS_VALLEYVIEW(dev)) {
13745 dev_priv->display.modeset_global_resources =
13746 valleyview_modeset_global_resources;
e70236a8 13747 }
8c9f3aaf 13748
8c9f3aaf
JB		 13749 switch (INTEL_INFO(dev)->gen) {
13750 case 2:
13751 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13752 break;
13753
13754 case 3:
13755 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13756 break;
13757
13758 case 4:
13759 case 5:
13760 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13761 break;
13762
13763 case 6:
13764 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13765 break;
7c9017e5 13766 case 7:
4e0bbc31 13767 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 13768 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13769 break;
830c81db 13770 case 9:
ba343e02
TU		 13771 /* Drop through - unsupported since execlist only. */
13772 default:
13773 /* Default just returns -ENODEV to indicate unsupported */
13774 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 13775 }
7bd688cd
JN		 13776
13777 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 13778
13779 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 13780}
13781
b690e96c
JB		 13782/*
13783 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13784 * resume, or other times. This quirk makes sure that's the case for
13785 * affected systems.
13786 */
0206e353 13787static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 13788{
13789 struct drm_i915_private *dev_priv = dev->dev_private;
13790
13791 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 13792 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 13793}
13794
b6b5d049
VS		 13795static void quirk_pipeb_force(struct drm_device *dev)
13796{
13797 struct drm_i915_private *dev_priv = dev->dev_private;
13798
13799 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13800 DRM_INFO("applying pipe b force quirk\n");
13801}
13802
435793df
KP		 13803/*
13804 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13805 */
13806static void quirk_ssc_force_disable(struct drm_device *dev)
13807{
13808 struct drm_i915_private *dev_priv = dev->dev_private;
13809 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 13810 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 13811}
13812
4dca20ef 13813/*
5a15ab5b
CE		 13814 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13815 * brightness value
4dca20ef
CE		 13816 */
13817static void quirk_invert_brightness(struct drm_device *dev)
13818{
13819 struct drm_i915_private *dev_priv = dev->dev_private;
13820 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 13821 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 13822}
13823
9c72cc6f
SD		 13824/* Some VBT's incorrectly indicate no backlight is present */
13825static void quirk_backlight_present(struct drm_device *dev)
13826{
13827 struct drm_i915_private *dev_priv = dev->dev_private;
13828 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13829 DRM_INFO("applying backlight present quirk\n");
13830}
13831
b690e96c
JB		 13832struct intel_quirk {
13833 int device;
13834 int subsystem_vendor;
13835 int subsystem_device;
13836 void (*hook)(struct drm_device *dev);
13837};
13838
5f85f176
EE		 13839/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13840struct intel_dmi_quirk {
13841 void (*hook)(struct drm_device *dev);
13842 const struct dmi_system_id (*dmi_id_list)[];
13843};
13844
13845static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13846{
13847 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13848 return 1;
13849}
13850
13851static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13852 {
13853 .dmi_id_list = &(const struct dmi_system_id[]) {
13854 {
13855 .callback = intel_dmi_reverse_brightness,
13856 .ident = "NCR Corporation",
13857 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13858 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13859 },
13860 },
13861 { } /* terminating entry */
13862 },
13863 .hook = quirk_invert_brightness,
13864 },
13865};
13866
c43b5634 13867static struct intel_quirk intel_quirks[] = {
b690e96c 13868 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 13869 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 13870
b690e96c
JB		 13871 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13872 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13873
b690e96c
JB		 13874 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13875 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13876
5f080c0f
VS		 13877 /* 830 needs to leave pipe A & dpll A up */
13878 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13879
b6b5d049
VS		 13880 /* 830 needs to leave pipe B & dpll B up */
13881 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13882
435793df
KP		 13883 /* Lenovo U160 cannot use SSC on LVDS */
13884 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 13885
13886 /* Sony Vaio Y cannot use SSC on LVDS */
13887 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 13888
be505f64
AH		 13889 /* Acer Aspire 5734Z must invert backlight brightness */
13890 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13891
13892 /* Acer/eMachines G725 */
13893 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13894
13895 /* Acer/eMachines e725 */
13896 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13897
13898 /* Acer/Packard Bell NCL20 */
13899 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13900
13901 /* Acer Aspire 4736Z */
13902 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 13903
13904 /* Acer Aspire 5336 */
13905 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 13906
13907 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13908 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 13909
dfb3d47b
SD		 13910 /* Acer C720 Chromebook (Core i3 4005U) */
13911 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13912
b2a9601c 13913 /* Apple Macbook 2,1 (Core 2 T7400) */
13914 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13915
d4967d8c
SD		 13916 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13917 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 13918
13919 /* HP Chromebook 14 (Celeron 2955U) */
13920 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 13921
13922 /* Dell Chromebook 11 */
13923 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 13924};
13925
13926static void intel_init_quirks(struct drm_device *dev)
13927{
13928 struct pci_dev *d = dev->pdev;
13929 int i;
13930
13931 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13932 struct intel_quirk *q = &intel_quirks[i];
13933
13934 if (d->device == q->device &&
13935 (d->subsystem_vendor == q->subsystem_vendor ||
13936 q->subsystem_vendor == PCI_ANY_ID) &&
13937 (d->subsystem_device == q->subsystem_device ||
13938 q->subsystem_device == PCI_ANY_ID))
13939 q->hook(dev);
13940 }
5f85f176
EE		 13941 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13942 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13943 intel_dmi_quirks[i].hook(dev);
13944 }
b690e96c
JB		 13945}
13946
9cce37f4
JB		 13947/* Disable the VGA plane that we never use */
13948static void i915_disable_vga(struct drm_device *dev)
13949{
13950 struct drm_i915_private *dev_priv = dev->dev_private;
13951 u8 sr1;
766aa1c4 13952 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 13953
2b37c616 13954 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 13955 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 13956 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 13957 sr1 = inb(VGA_SR_DATA);
13958 outb(sr1 | 1<<5, VGA_SR_DATA);
13959 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13960 udelay(300);
13961
01f5a626 13962 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 13963 POSTING_READ(vga_reg);
13964}
13965
f817586c
DV		 13966void intel_modeset_init_hw(struct drm_device *dev)
13967{
a8f78b58
ED		 13968 intel_prepare_ddi(dev);
13969
f8bf63fd
VS		 13970 if (IS_VALLEYVIEW(dev))
13971 vlv_update_cdclk(dev);
13972
f817586c
DV		 13973 intel_init_clock_gating(dev);
13974
8090c6b9 13975 intel_enable_gt_powersave(dev);
f817586c
DV		 13976}
13977
79e53945
JB		 13978void intel_modeset_init(struct drm_device *dev)
13979{
652c393a 13980 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 13981 int sprite, ret;
8cc87b75 13982 enum pipe pipe;
46f297fb 13983 struct intel_crtc *crtc;
79e53945
JB		 13984
13985 drm_mode_config_init(dev);
13986
13987 dev->mode_config.min_width = 0;
13988 dev->mode_config.min_height = 0;
13989
019d96cb
DA		 13990 dev->mode_config.preferred_depth = 24;
13991 dev->mode_config.prefer_shadow = 1;
13992
25bab385
TU		 13993 dev->mode_config.allow_fb_modifiers = true;
13994
e6ecefaa 13995 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 13996
b690e96c
JB		 13997 intel_init_quirks(dev);
13998
1fa61106
ED		 13999 intel_init_pm(dev);
14000
e3c74757
BW		 14001 if (INTEL_INFO(dev)->num_pipes == 0)
14002 return;
14003
e70236a8 14004 intel_init_display(dev);
7c10a2b5 14005 intel_init_audio(dev);
e70236a8 14006
a6c45cf0
CW		 14007 if (IS_GEN2(dev)) {
14008 dev->mode_config.max_width = 2048;
14009 dev->mode_config.max_height = 2048;
14010 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14011 dev->mode_config.max_width = 4096;
14012 dev->mode_config.max_height = 4096;
79e53945 14013 } else {
a6c45cf0
CW		 14014 dev->mode_config.max_width = 8192;
14015 dev->mode_config.max_height = 8192;
79e53945 14016 }
068be561 14017
dc41c154
VS		 14018 if (IS_845G(dev) || IS_I865G(dev)) {
14019 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14020 dev->mode_config.cursor_height = 1023;
14021 } else if (IS_GEN2(dev)) {
068be561
DL		 14022 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14023 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14024 } else {
14025 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14026 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14027 }
14028
5d4545ae 14029 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14030
28c97730 14031 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14032 INTEL_INFO(dev)->num_pipes,
14033 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14034
055e393f 14035 for_each_pipe(dev_priv, pipe) {
8cc87b75 14036 intel_crtc_init(dev, pipe);
3bdcfc0c 14037 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14038 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14039 if (ret)
06da8da2 14040 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14041 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14042 }
79e53945
JB		 14043 }
14044
f42bb70d
JB		 14045 intel_init_dpio(dev);
14046
e72f9fbf 14047 intel_shared_dpll_init(dev);
ee7b9f93 14048
9cce37f4
JB		 14049 /* Just disable it once at startup */
14050 i915_disable_vga(dev);
79e53945 14051 intel_setup_outputs(dev);
11be49eb
CW		 14052
14053 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14054 intel_fbc_disable(dev);
fa9fa083 14055
6e9f798d 14056 drm_modeset_lock_all(dev);
fa9fa083 14057 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14058 drm_modeset_unlock_all(dev);
46f297fb 14059
d3fcc808 14060 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14061 if (!crtc->active)
14062 continue;
14063
46f297fb 14064 /*
46f297fb
JB		 14065 * Note that reserving the BIOS fb up front prevents us
14066 * from stuffing other stolen allocations like the ring
14067 * on top. This prevents some ugliness at boot time, and
14068 * can even allow for smooth boot transitions if the BIOS
14069 * fb is large enough for the active pipe configuration.
14070 */
5724dbd1
DL		 14071 if (dev_priv->display.get_initial_plane_config) {
14072 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14073 &crtc->plane_config);
14074 /*
14075 * If the fb is shared between multiple heads, we'll
14076 * just get the first one.
14077 */
f6936e29 14078 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14079 }
46f297fb 14080 }
2c7111db
CW		 14081}
14082
7fad798e
DV		 14083static void intel_enable_pipe_a(struct drm_device *dev)
14084{
14085 struct intel_connector *connector;
14086 struct drm_connector *crt = NULL;
14087 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14088 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14089
14090 /* We can't just switch on the pipe A, we need to set things up with a
14091 * proper mode and output configuration. As a gross hack, enable pipe A
14092 * by enabling the load detect pipe once. */
3a3371ff 14093 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14094 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14095 crt = &connector->base;
14096 break;
14097 }
14098 }
14099
14100 if (!crt)
14101 return;
14102
208bf9fd 14103 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14104 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14105}
14106
fa555837
DV		 14107static bool
14108intel_check_plane_mapping(struct intel_crtc *crtc)
14109{
7eb552ae
BW		 14110 struct drm_device *dev = crtc->base.dev;
14111 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14112 u32 reg, val;
14113
7eb552ae 14114 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14115 return true;
14116
14117 reg = DSPCNTR(!crtc->plane);
14118 val = I915_READ(reg);
14119
14120 if ((val & DISPLAY_PLANE_ENABLE) &&
14121 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14122 return false;
14123
14124 return true;
14125}
14126
24929352
DV		 14127static void intel_sanitize_crtc(struct intel_crtc *crtc)
14128{
14129 struct drm_device *dev = crtc->base.dev;
14130 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14131 u32 reg;
24929352 14132
24929352 14133 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14134 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14135 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14136
d3eaf884 14137 /* restore vblank interrupts to correct state */
9625604c 14138 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14139 if (crtc->active) {
14140 update_scanline_offset(crtc);
9625604c
DV		 14141 drm_crtc_vblank_on(&crtc->base);
14142 }
d3eaf884 14143
24929352 14144 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14145 * disable the crtc (and hence change the state) if it is wrong. Note
14146 * that gen4+ has a fixed plane -> pipe mapping. */
14147 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14148 struct intel_connector *connector;
14149 bool plane;
14150
24929352
DV		 14151 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14152 crtc->base.base.id);
14153
14154 /* Pipe has the wrong plane attached and the plane is active.
14155 * Temporarily change the plane mapping and disable everything
14156 * ... */
14157 plane = crtc->plane;
14158 crtc->plane = !plane;
9c8958bc 14159 crtc->primary_enabled = true;
24929352
DV		 14160 dev_priv->display.crtc_disable(&crtc->base);
14161 crtc->plane = plane;
14162
14163 /* ... and break all links. */
3a3371ff 14164 for_each_intel_connector(dev, connector) {
24929352
DV		 14165 if (connector->encoder->base.crtc != &crtc->base)
14166 continue;
14167
7f1950fb
EE		 14168 connector->base.dpms = DRM_MODE_DPMS_OFF;
14169 connector->base.encoder = NULL;
24929352 14170 }
7f1950fb
EE		 14171 /* multiple connectors may have the same encoder:
14172 * handle them and break crtc link separately */
3a3371ff 14173 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14174 if (connector->encoder->base.crtc == &crtc->base) {
14175 connector->encoder->base.crtc = NULL;
14176 connector->encoder->connectors_active = false;
14177 }
24929352
DV		 14178
14179 WARN_ON(crtc->active);
83d65738 14180 crtc->base.state->enable = false;
24929352
DV		 14181 crtc->base.enabled = false;
14182 }
24929352 14183
7fad798e
DV		 14184 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14185 crtc->pipe == PIPE_A && !crtc->active) {
14186 /* BIOS forgot to enable pipe A, this mostly happens after
14187 * resume. Force-enable the pipe to fix this, the update_dpms
14188 * call below we restore the pipe to the right state, but leave
14189 * the required bits on. */
14190 intel_enable_pipe_a(dev);
14191 }
14192
24929352
DV		 14193 /* Adjust the state of the output pipe according to whether we
14194 * have active connectors/encoders. */
14195 intel_crtc_update_dpms(&crtc->base);
14196
83d65738 14197 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14198 struct intel_encoder *encoder;
14199
14200 /* This can happen either due to bugs in the get_hw_state
14201 * functions or because the pipe is force-enabled due to the
14202 * pipe A quirk. */
14203 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14204 crtc->base.base.id,
83d65738 14205 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14206 crtc->active ? "enabled" : "disabled");
14207
83d65738 14208 crtc->base.state->enable = crtc->active;
24929352
DV		 14209 crtc->base.enabled = crtc->active;
14210
14211 /* Because we only establish the connector -> encoder ->
14212 * crtc links if something is active, this means the
14213 * crtc is now deactivated. Break the links. connector
14214 * -> encoder links are only establish when things are
14215 * actually up, hence no need to break them. */
14216 WARN_ON(crtc->active);
14217
14218 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14219 WARN_ON(encoder->connectors_active);
14220 encoder->base.crtc = NULL;
14221 }
14222 }
c5ab3bc0 14223
a3ed6aad 14224 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14225 /*
14226 * We start out with underrun reporting disabled to avoid races.
14227 * For correct bookkeeping mark this on active crtcs.
14228 *
c5ab3bc0
DV		 14229 * Also on gmch platforms we dont have any hardware bits to
14230 * disable the underrun reporting. Which means we need to start
14231 * out with underrun reporting disabled also on inactive pipes,
14232 * since otherwise we'll complain about the garbage we read when
14233 * e.g. coming up after runtime pm.
14234 *
4cc31489
DV		 14235 * No protection against concurrent access is required - at
14236 * worst a fifo underrun happens which also sets this to false.
14237 */
14238 crtc->cpu_fifo_underrun_disabled = true;
14239 crtc->pch_fifo_underrun_disabled = true;
14240 }
24929352
DV		 14241}
14242
14243static void intel_sanitize_encoder(struct intel_encoder *encoder)
14244{
14245 struct intel_connector *connector;
14246 struct drm_device *dev = encoder->base.dev;
14247
14248 /* We need to check both for a crtc link (meaning that the
14249 * encoder is active and trying to read from a pipe) and the
14250 * pipe itself being active. */
14251 bool has_active_crtc = encoder->base.crtc &&
14252 to_intel_crtc(encoder->base.crtc)->active;
14253
14254 if (encoder->connectors_active && !has_active_crtc) {
14255 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14256 encoder->base.base.id,
8e329a03 14257 encoder->base.name);
24929352
DV		 14258
14259 /* Connector is active, but has no active pipe. This is
14260 * fallout from our resume register restoring. Disable
14261 * the encoder manually again. */
14262 if (encoder->base.crtc) {
14263 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14264 encoder->base.base.id,
8e329a03 14265 encoder->base.name);
24929352 14266 encoder->disable(encoder);
a62d1497
VS		 14267 if (encoder->post_disable)
14268 encoder->post_disable(encoder);
24929352 14269 }
7f1950fb
EE		 14270 encoder->base.crtc = NULL;
14271 encoder->connectors_active = false;
24929352
DV		 14272
14273 /* Inconsistent output/port/pipe state happens presumably due to
14274 * a bug in one of the get_hw_state functions. Or someplace else
14275 * in our code, like the register restore mess on resume. Clamp
14276 * things to off as a safer default. */
3a3371ff 14277 for_each_intel_connector(dev, connector) {
24929352
DV		 14278 if (connector->encoder != encoder)
14279 continue;
7f1950fb
EE		 14280 connector->base.dpms = DRM_MODE_DPMS_OFF;
14281 connector->base.encoder = NULL;
24929352
DV		 14282 }
14283 }
14284 /* Enabled encoders without active connectors will be fixed in
14285 * the crtc fixup. */
14286}
14287
04098753 14288void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14289{
14290 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14291 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14292
04098753
ID		 14293 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14294 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14295 i915_disable_vga(dev);
14296 }
14297}
14298
14299void i915_redisable_vga(struct drm_device *dev)
14300{
14301 struct drm_i915_private *dev_priv = dev->dev_private;
14302
8dc8a27c
PZ		 14303 /* This function can be called both from intel_modeset_setup_hw_state or
14304 * at a very early point in our resume sequence, where the power well
14305 * structures are not yet restored. Since this function is at a very
14306 * paranoid "someone might have enabled VGA while we were not looking"
14307 * level, just check if the power well is enabled instead of trying to
14308 * follow the "don't touch the power well if we don't need it" policy
14309 * the rest of the driver uses. */
f458ebbc 14310 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14311 return;
14312
04098753 14313 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14314}
14315
98ec7739
VS		 14316static bool primary_get_hw_state(struct intel_crtc *crtc)
14317{
14318 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14319
14320 if (!crtc->active)
14321 return false;
14322
14323 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14324}
14325
30e984df 14326static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14327{
14328 struct drm_i915_private *dev_priv = dev->dev_private;
14329 enum pipe pipe;
24929352
DV		 14330 struct intel_crtc *crtc;
14331 struct intel_encoder *encoder;
14332 struct intel_connector *connector;
5358901f 14333 int i;
24929352 14334
d3fcc808 14335 for_each_intel_crtc(dev, crtc) {
6e3c9717 14336 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14337
6e3c9717 14338 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14339
0e8ffe1b 14340 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14341 crtc->config);
24929352 14342
83d65738 14343 crtc->base.state->enable = crtc->active;
24929352 14344 crtc->base.enabled = crtc->active;
98ec7739 14345 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14346
14347 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14348 crtc->base.base.id,
14349 crtc->active ? "enabled" : "disabled");
14350 }
14351
5358901f
DV		 14352 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14353 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14354
3e369b76
ACO		 14355 pll->on = pll->get_hw_state(dev_priv, pll,
14356 &pll->config.hw_state);
5358901f 14357 pll->active = 0;
3e369b76 14358 pll->config.crtc_mask = 0;
d3fcc808 14359 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14360 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14361 pll->active++;
3e369b76 14362 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14363 }
5358901f 14364 }
5358901f 14365
1e6f2ddc 14366 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14367 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14368
3e369b76 14369 if (pll->config.crtc_mask)
bd2bb1b9 14370 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14371 }
14372
b2784e15 14373 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14374 pipe = 0;
14375
14376 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14377 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14378 encoder->base.crtc = &crtc->base;
6e3c9717 14379 encoder->get_config(encoder, crtc->config);
24929352
DV		 14380 } else {
14381 encoder->base.crtc = NULL;
14382 }
14383
14384 encoder->connectors_active = false;
6f2bcceb 14385 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14386 encoder->base.base.id,
8e329a03 14387 encoder->base.name,
24929352 14388 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14389 pipe_name(pipe));
24929352
DV		 14390 }
14391
3a3371ff 14392 for_each_intel_connector(dev, connector) {
24929352
DV		 14393 if (connector->get_hw_state(connector)) {
14394 connector->base.dpms = DRM_MODE_DPMS_ON;
14395 connector->encoder->connectors_active = true;
14396 connector->base.encoder = &connector->encoder->base;
14397 } else {
14398 connector->base.dpms = DRM_MODE_DPMS_OFF;
14399 connector->base.encoder = NULL;
14400 }
14401 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14402 connector->base.base.id,
c23cc417 14403 connector->base.name,
24929352
DV		 14404 connector->base.encoder ? "enabled" : "disabled");
14405 }
30e984df
DV		 14406}
14407
14408/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14409 * and i915 state tracking structures. */
14410void intel_modeset_setup_hw_state(struct drm_device *dev,
14411 bool force_restore)
14412{
14413 struct drm_i915_private *dev_priv = dev->dev_private;
14414 enum pipe pipe;
30e984df
DV		 14415 struct intel_crtc *crtc;
14416 struct intel_encoder *encoder;
35c95375 14417 int i;
30e984df
DV		 14418
14419 intel_modeset_readout_hw_state(dev);
24929352 14420
babea61d
JB		 14421 /*
14422 * Now that we have the config, copy it to each CRTC struct
14423 * Note that this could go away if we move to using crtc_config
14424 * checking everywhere.
14425 */
d3fcc808 14426 for_each_intel_crtc(dev, crtc) {
d330a953 14427 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14428 intel_mode_from_pipe_config(&crtc->base.mode,
14429 crtc->config);
babea61d
JB		 14430 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14431 crtc->base.base.id);
14432 drm_mode_debug_printmodeline(&crtc->base.mode);
14433 }
14434 }
14435
24929352 14436 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14437 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14438 intel_sanitize_encoder(encoder);
14439 }
14440
055e393f 14441 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14442 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14443 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14444 intel_dump_pipe_config(crtc, crtc->config,
14445 "[setup_hw_state]");
24929352 14446 }
9a935856 14447
d29b2f9d
ACO		 14448 intel_modeset_update_connector_atomic_state(dev);
14449
35c95375
DV		 14450 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14451 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14452
14453 if (!pll->on || pll->active)
14454 continue;
14455
14456 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14457
14458 pll->disable(dev_priv, pll);
14459 pll->on = false;
14460 }
14461
3078999f
PB		 14462 if (IS_GEN9(dev))
14463 skl_wm_get_hw_state(dev);
14464 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14465 ilk_wm_get_hw_state(dev);
14466
45e2b5f6 14467 if (force_restore) {
7d0bc1ea
VS		 14468 i915_redisable_vga(dev);
14469
f30da187
DV		 14470 /*
14471 * We need to use raw interfaces for restoring state to avoid
14472 * checking (bogus) intermediate states.
14473 */
055e393f 14474 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14475 struct drm_crtc *crtc =
14476 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14477
83a57153 14478 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14479 }
14480 } else {
14481 intel_modeset_update_staged_output_state(dev);
14482 }
8af6cf88
DV		 14483
14484 intel_modeset_check_state(dev);
2c7111db
CW		 14485}
14486
14487void intel_modeset_gem_init(struct drm_device *dev)
14488{
92122789 14489 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14490 struct drm_crtc *c;
2ff8fde1 14491 struct drm_i915_gem_object *obj;
484b41dd 14492
ae48434c
ID		 14493 mutex_lock(&dev->struct_mutex);
14494 intel_init_gt_powersave(dev);
14495 mutex_unlock(&dev->struct_mutex);
14496
92122789
JB		 14497 /*
14498 * There may be no VBT; and if the BIOS enabled SSC we can
14499 * just keep using it to avoid unnecessary flicker. Whereas if the
14500 * BIOS isn't using it, don't assume it will work even if the VBT
14501 * indicates as much.
14502 */
14503 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14504 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14505 DREF_SSC1_ENABLE);
14506
1833b134 14507 intel_modeset_init_hw(dev);
02e792fb
DV		 14508
14509 intel_setup_overlay(dev);
484b41dd
JB		 14510
14511 /*
14512 * Make sure any fbs we allocated at startup are properly
14513 * pinned & fenced. When we do the allocation it's too early
14514 * for this.
14515 */
14516 mutex_lock(&dev->struct_mutex);
70e1e0ec 14517 for_each_crtc(dev, c) {
2ff8fde1
MR		 14518 obj = intel_fb_obj(c->primary->fb);
14519 if (obj == NULL)
484b41dd
JB		 14520 continue;
14521
850c4cdc
TU		 14522 if (intel_pin_and_fence_fb_obj(c->primary,
14523 c->primary->fb,
82bc3b2d 14524 c->primary->state,
850c4cdc 14525 NULL)) {
484b41dd
JB		 14526 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14527 to_intel_crtc(c)->pipe);
66e514c1
DA		 14528 drm_framebuffer_unreference(c->primary->fb);
14529 c->primary->fb = NULL;
afd65eb4 14530 update_state_fb(c->primary);
484b41dd
JB		 14531 }
14532 }
14533 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 14534
14535 intel_backlight_register(dev);
79e53945
JB		 14536}
14537
4932e2c3
ID		 14538void intel_connector_unregister(struct intel_connector *intel_connector)
14539{
14540 struct drm_connector *connector = &intel_connector->base;
14541
14542 intel_panel_destroy_backlight(connector);
34ea3d38 14543 drm_connector_unregister(connector);
4932e2c3
ID		 14544}
14545
79e53945
JB		 14546void intel_modeset_cleanup(struct drm_device *dev)
14547{
652c393a 14548 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14549 struct drm_connector *connector;
652c393a 14550
2eb5252e
ID		 14551 intel_disable_gt_powersave(dev);
14552
0962c3c9
VS		 14553 intel_backlight_unregister(dev);
14554
fd0c0642
DV		 14555 /*
14556 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14557 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14558 * experience fancy races otherwise.
14559 */
2aeb7d3a 14560 intel_irq_uninstall(dev_priv);
eb21b92b 14561
fd0c0642
DV		 14562 /*
14563 * Due to the hpd irq storm handling the hotplug work can re-arm the
14564 * poll handlers. Hence disable polling after hpd handling is shut down.
14565 */
f87ea761 14566 drm_kms_helper_poll_fini(dev);
fd0c0642 14567
652c393a
JB		 14568 mutex_lock(&dev->struct_mutex);
14569
723bfd70
JB		 14570 intel_unregister_dsm_handler();
14571
7ff0ebcc 14572 intel_fbc_disable(dev);
e70236a8 14573
69341a5e
KH		 14574 mutex_unlock(&dev->struct_mutex);
14575
1630fe75
CW		 14576 /* flush any delayed tasks or pending work */
14577 flush_scheduled_work();
14578
db31af1d
JN		 14579 /* destroy the backlight and sysfs files before encoders/connectors */
14580 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 14581 struct intel_connector *intel_connector;
14582
14583 intel_connector = to_intel_connector(connector);
14584 intel_connector->unregister(intel_connector);
db31af1d 14585 }
d9255d57 14586
79e53945 14587 drm_mode_config_cleanup(dev);
4d7bb011
DV		 14588
14589 intel_cleanup_overlay(dev);
ae48434c
ID		 14590
14591 mutex_lock(&dev->struct_mutex);
14592 intel_cleanup_gt_powersave(dev);
14593 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14594}
14595
f1c79df3
ZW		 14596/*
14597 * Return which encoder is currently attached for connector.
14598 */
df0e9248 14599struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 14600{
df0e9248
CW		 14601 return &intel_attached_encoder(connector)->base;
14602}
f1c79df3 14603
df0e9248
CW		 14604void intel_connector_attach_encoder(struct intel_connector *connector,
14605 struct intel_encoder *encoder)
14606{
14607 connector->encoder = encoder;
14608 drm_mode_connector_attach_encoder(&connector->base,
14609 &encoder->base);
79e53945 14610}
28d52043
DA		 14611
14612/*
14613 * set vga decode state - true == enable VGA decode
14614 */
14615int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14616{
14617 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 14618 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 14619 u16 gmch_ctrl;
14620
75fa041d
CW		 14621 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14622 DRM_ERROR("failed to read control word\n");
14623 return -EIO;
14624 }
14625
c0cc8a55
CW		 14626 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14627 return 0;
14628
28d52043
DA		 14629 if (state)
14630 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14631 else
14632 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 14633
14634 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14635 DRM_ERROR("failed to write control word\n");
14636 return -EIO;
14637 }
14638
28d52043
DA		 14639 return 0;
14640}
c4a1d9e4 14641
c4a1d9e4 14642struct intel_display_error_state {
ff57f1b0
PZ		 14643
14644 u32 power_well_driver;
14645
63b66e5b
CW		 14646 int num_transcoders;
14647
c4a1d9e4
CW		 14648 struct intel_cursor_error_state {
14649 u32 control;
14650 u32 position;
14651 u32 base;
14652 u32 size;
52331309 14653 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 14654
14655 struct intel_pipe_error_state {
ddf9c536 14656 bool power_domain_on;
c4a1d9e4 14657 u32 source;
f301b1e1 14658 u32 stat;
52331309 14659 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 14660
14661 struct intel_plane_error_state {
14662 u32 control;
14663 u32 stride;
14664 u32 size;
14665 u32 pos;
14666 u32 addr;
14667 u32 surface;
14668 u32 tile_offset;
52331309 14669 } plane[I915_MAX_PIPES];
63b66e5b
CW		 14670
14671 struct intel_transcoder_error_state {
ddf9c536 14672 bool power_domain_on;
63b66e5b
CW		 14673 enum transcoder cpu_transcoder;
14674
14675 u32 conf;
14676
14677 u32 htotal;
14678 u32 hblank;
14679 u32 hsync;
14680 u32 vtotal;
14681 u32 vblank;
14682 u32 vsync;
14683 } transcoder[4];
c4a1d9e4
CW		 14684};
14685
14686struct intel_display_error_state *
14687intel_display_capture_error_state(struct drm_device *dev)
14688{
fbee40df 14689 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14690 struct intel_display_error_state *error;
63b66e5b
CW		 14691 int transcoders[] = {
14692 TRANSCODER_A,
14693 TRANSCODER_B,
14694 TRANSCODER_C,
14695 TRANSCODER_EDP,
14696 };
c4a1d9e4
CW		 14697 int i;
14698
63b66e5b
CW		 14699 if (INTEL_INFO(dev)->num_pipes == 0)
14700 return NULL;
14701
9d1cb914 14702 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14703 if (error == NULL)
14704 return NULL;
14705
190be112 14706 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14707 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14708
055e393f 14709 for_each_pipe(dev_priv, i) {
ddf9c536 14710 error->pipe[i].power_domain_on =
f458ebbc
DV		 14711 __intel_display_power_is_enabled(dev_priv,
14712 POWER_DOMAIN_PIPE(i));
ddf9c536 14713 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14714 continue;
14715
5efb3e28
VS		 14716 error->cursor[i].control = I915_READ(CURCNTR(i));
14717 error->cursor[i].position = I915_READ(CURPOS(i));
14718 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14719
14720 error->plane[i].control = I915_READ(DSPCNTR(i));
14721 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14722 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14723 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14724 error->plane[i].pos = I915_READ(DSPPOS(i));
14725 }
ca291363
PZ		 14726 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14727 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14728 if (INTEL_INFO(dev)->gen >= 4) {
14729 error->plane[i].surface = I915_READ(DSPSURF(i));
14730 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14731 }
14732
c4a1d9e4 14733 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14734
3abfce77 14735 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14736 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14737 }
14738
14739 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14740 if (HAS_DDI(dev_priv->dev))
14741 error->num_transcoders++; /* Account for eDP. */
14742
14743 for (i = 0; i < error->num_transcoders; i++) {
14744 enum transcoder cpu_transcoder = transcoders[i];
14745
ddf9c536 14746 error->transcoder[i].power_domain_on =
f458ebbc 14747 __intel_display_power_is_enabled(dev_priv,
38cc1daf 14748 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 14749 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 14750 continue;
14751
63b66e5b
CW		 14752 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14753
14754 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14755 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14756 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14757 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14758 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14759 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14760 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 14761 }
14762
14763 return error;
14764}
14765
edc3d884
MK		 14766#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14767
c4a1d9e4 14768void
edc3d884 14769intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 14770 struct drm_device *dev,
14771 struct intel_display_error_state *error)
14772{
055e393f 14773 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 14774 int i;
14775
63b66e5b
CW		 14776 if (!error)
14777 return;
14778
edc3d884 14779 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 14780 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 14781 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 14782 error->power_well_driver);
055e393f 14783 for_each_pipe(dev_priv, i) {
edc3d884 14784 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 14785 err_printf(m, " Power: %s\n",
14786 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 14787 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 14788 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 14789
14790 err_printf(m, "Plane [%d]:\n", i);
14791 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14792 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 14793 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 14794 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14795 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 14796 }
4b71a570 14797 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 14798 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 14799 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 14800 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14801 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 14802 }
14803
edc3d884
MK		 14804 err_printf(m, "Cursor [%d]:\n", i);
14805 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14806 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14807 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 14808 }
63b66e5b
CW		 14809
14810 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 14811 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 14812 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 14813 err_printf(m, " Power: %s\n",
14814 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 14815 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14816 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14817 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14818 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14819 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14820 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14821 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14822 }
c4a1d9e4 14823}
e2fcdaa9
VS		 14824
14825void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14826{
14827 struct intel_crtc *crtc;
14828
14829 for_each_intel_crtc(dev, crtc) {
14830 struct intel_unpin_work *work;
e2fcdaa9 14831
5e2d7afc 14832 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 14833
14834 work = crtc->unpin_work;
14835
14836 if (work && work->event &&
14837 work->event->base.file_priv == file) {
14838 kfree(work->event);
14839 work->event = NULL;
14840 }
14841
5e2d7afc 14842 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 14843 }
14844}
Linux kernel - Deliverables
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